| /linux-2.6.39/drivers/scsi/aacraid/ |
| D | aacraid.h | 650 #define sa_readw(AEP, CSR) readl(&((AEP)->regs.sa->CSR)) argument
651 #define sa_readl(AEP, CSR) readl(&((AEP)->regs.sa->CSR)) argument
652 #define sa_writew(AEP, CSR, value) writew(value, &((AEP)->regs.sa->CSR)) argument
653 #define sa_writel(AEP, CSR, value) writel(value, &((AEP)->regs.sa->CSR)) argument
712 #define rx_readb(AEP, CSR) readb(&((AEP)->regs.rx->CSR)) argument
713 #define rx_readl(AEP, CSR) readl(&((AEP)->regs.rx->CSR)) argument
714 #define rx_writeb(AEP, CSR, value) writeb(value, &((AEP)->regs.rx->CSR)) argument
715 #define rx_writel(AEP, CSR, value) writel(value, &((AEP)->regs.rx->CSR)) argument
730 #define rkt_readb(AEP, CSR) readb(&((AEP)->regs.rkt->CSR)) argument
731 #define rkt_readl(AEP, CSR) readl(&((AEP)->regs.rkt->CSR)) argument
[all …]
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| /linux-2.6.39/drivers/i2c/busses/ |
| D | i2c-nuc900.c | 36 #define CSR 0x00 macro
117 tmp = readl(i2c->regs + CSR); in nuc900_i2c_disable_irq()
118 writel(tmp & ~IRQEN, i2c->regs + CSR); in nuc900_i2c_disable_irq()
125 tmp = readl(i2c->regs + CSR); in nuc900_i2c_enable_irq()
126 writel(tmp | IRQEN, i2c->regs + CSR); in nuc900_i2c_enable_irq()
361 status = readl(i2c->regs + CSR); in nuc900_i2c_irq()
362 writel(status | IRQFLAG, i2c->regs + CSR); in nuc900_i2c_irq()
397 ((readl(i2c->regs + CSR) & I2CBUSY) == 0)) { in nuc900_i2c_set_master()
456 iicstat = readl(i2c->regs + CSR); in nuc900_i2c_doxfer()
462 iicstat = readl(i2c->regs + CSR); in nuc900_i2c_doxfer()
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| /linux-2.6.39/arch/arm/mach-msm/ |
| D | io.c | 44 MSM_CHIP_DEVICE(CSR, MSM7X00),
77 MSM_CHIP_DEVICE(CSR, QSD8X50),
136 MSM_CHIP_DEVICE(CSR, MSM7X30),
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| /linux-2.6.39/drivers/dma/ |
| D | txx9dmac.c | 312 channel64_readl(dc, CSR)); in txx9dmac_dump_regs()
324 channel32_readl(dc, CSR)); in txx9dmac_dump_regs()
356 if (channel_readl(dc, CSR) & TXX9_DMA_CSR_XFACT) { in txx9dmac_dostart()
366 channel64_writel(dc, CSR, 0xffffffff); in txx9dmac_dostart()
387 channel32_writel(dc, CSR, 0xffffffff); in txx9dmac_dostart()
524 desc->SAIR, desc->DAIR, desc->CCR, desc->CSR); in txx9dmac_dump_desc()
537 d->SAIR, d->DAIR, d->CCR, d->CSR); in txx9dmac_dump_desc()
563 channel_writel(dc, CSR, errors); in txx9dmac_handle_error()
589 csr = channel64_readl(dc, CSR); in txx9dmac_scan_descriptors()
590 channel64_writel(dc, CSR, csr); in txx9dmac_scan_descriptors()
[all …]
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| D | txx9dmac.h | 81 TXX9_DMA_REG32(CSR); /* Channel Status Register */
91 u32 CSR; member
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| /linux-2.6.39/drivers/net/qlge/ |
| D | qlge_mpi.c | 8 tmp = ql_read32(qdev, CSR); in ql_unpause_mpi_risc()
12 ql_write32(qdev, CSR, CSR_CMD_CLR_PAUSE); in ql_unpause_mpi_risc()
22 ql_write32(qdev, CSR, CSR_CMD_SET_PAUSE); in ql_pause_mpi_risc()
24 tmp = ql_read32(qdev, CSR); in ql_pause_mpi_risc()
39 ql_write32(qdev, CSR, CSR_CMD_SET_RST); in ql_hard_reset_mpi_risc()
41 tmp = ql_read32(qdev, CSR); in ql_hard_reset_mpi_risc()
43 ql_write32(qdev, CSR, CSR_CMD_CLR_RST); in ql_hard_reset_mpi_risc()
174 if (ql_read32(qdev, CSR) & CSR_HRI) in ql_exec_mb_cmd()
193 ql_write32(qdev, CSR, CSR_CMD_SET_H2R_INT); in ql_exec_mb_cmd()
516 ql_write32(qdev, CSR, CSR_CMD_CLR_R2PCI_INT); in ql_mpi_handler()
[all …]
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| D | qlge.h | 801 CSR = 0x14, enumerator
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| D | qlge_dbg.c | 1489 DUMP_REG(qdev, CSR); in ql_dump_regs()
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| /linux-2.6.39/drivers/staging/vme/ |
| D | TODO | 23 CR/CSR Buffer
26 The VME API provides no functions to access the buffer mapped into the CR/CSR
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| /linux-2.6.39/arch/arm/mach-omap1/ |
| D | dma.c | 65 [CSR] = 0x06,
233 l = dma_read(CSR, lch); in omap1_clear_dma()
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| /linux-2.6.39/arch/arm/plat-omap/ |
| D | dma.c | 570 status = p->dma_read(CSR, lch); in omap_enable_channel_irq()
572 p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, lch); in omap_enable_channel_irq()
741 p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, free_ch); in omap_request_dma()
772 p->dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR, lch); in omap_free_dma()
1785 csr = p->dma_read(CSR, ch); in omap1_dma_handle_ch()
1838 u32 status = p->dma_read(CSR, ch); in omap2_dma_handle_ch()
1876 p->dma_write(status, CSR, ch); in omap2_dma_handle_ch()
1895 status = p->dma_read(CSR, ch); in omap2_dma_handle_ch()
1896 p->dma_write(status, CSR, ch); in omap2_dma_handle_ch()
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| /linux-2.6.39/Documentation/rapidio/ |
| D | rapidio.txt | 112 device by writing into the Host Device ID Lock CSR. It does this to ensure that
118 is written into the device's Base Device ID CSR.
135 into device's Component Tag CSR. That unique value is used by the error
147 in the system, it sets the Master Enable bit in the Port General Control CSR
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| /linux-2.6.39/drivers/staging/ath6kl/ |
| D | Kconfig | 74 bool "CSR BC06"
76 CSR BT (3 Wire PTA)
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| /linux-2.6.39/arch/arm/mach-omap2/ |
| D | dma.c | 66 [CSR] = 0x8c,
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| /linux-2.6.39/Documentation/arm/ |
| D | IXP4xx | 39 require the use of Intel's proprietary CSR softare:
140 the CSR or a WiFi card and a ramdisk that BOOTPs and then does
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| /linux-2.6.39/arch/arm/plat-omap/include/plat/ |
| D | dma.h | 325 CSDP, CCR, CICR, CSR, enumerator
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| /linux-2.6.39/drivers/net/tokenring/ |
| D | smctr.c | 698 outb((tp->trc_mask | CSR_CLRTINT), dev->base_addr + CSR); in smctr_clear_int()
833 outb(tp->trc_mask, ioaddr + CSR); in smctr_disable_adapter_ctrl_store()
845 outb(tp->trc_mask, ioaddr + CSR); in smctr_disable_bic_int()
882 outb(tp->trc_mask, ioaddr + CSR); in smctr_enable_adapter_ctrl_store()
911 outb(tp->trc_mask, ioaddr + CSR); in smctr_enable_bic_int()
918 outb(tp->trc_mask, ioaddr + CSR); in smctr_enable_bic_int()
4314 outb(tp->trc_mask | CSR_CLRTINT | CSR_CLRCBUSY, ioaddr + CSR); in smctr_reset_adapter()
5141 outb((tp->trc_mask | CSR_CA), ioaddr + CSR); in smctr_set_ctrl_attention()
5142 outb(tp->trc_mask, ioaddr + CSR); in smctr_set_ctrl_attention()
5621 r = inb(ioaddr + CSR); in smctr_wait_while_cbusy()
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| D | smctr.h | 741 #define CSR 0x10 macro
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| /linux-2.6.39/arch/blackfin/include/asm/ |
| D | bfin_can.h | 116 #define CSR 0x0040 /* CAN Suspend Mode Request */ macro
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| /linux-2.6.39/Documentation/networking/ |
| D | stmmac.txt | 124 - clk_csr: CSR Clock range selection.
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| /linux-2.6.39/drivers/bluetooth/ |
| D | Kconfig | 56 USB Bluetooth devices based on CSR BlueCore chip, including PCMCIA and
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| /linux-2.6.39/drivers/mmc/host/ |
| D | Kconfig | 543 the Cypress Astoria chip with firmware compliant with CSR's
546 CSR boards with this device include: USB<>SDIO (M1985v2),
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| /linux-2.6.39/drivers/tty/serial/ |
| D | sc26xx.c | 478 WRITE_SC_PORT(port, CSR, csr); in sc26xx_set_termios()
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| /linux-2.6.39/Documentation/frv/ |
| D | features.txt | 83 0xFC200000 - 0xFC2FFFFF CS3# MB93493 CSR area (DAV daughter board)
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| D | mmu-layout.txt | 52 FC200000 - FC2FFFFF L-BUS CS3# MB93493 CSR area (DAV daughter board)
|