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Searched refs:CORE_MOD (Results 1 – 19 of 19) sorted by relevance

/linux-2.6.39/arch/arm/mach-omap2/
Dclock2430_data.c488 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
513 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
515 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
544 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
577 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
579 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
594 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
740 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
750 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
753 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
[all …]
Dclock2420_data.c542 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
567 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
569 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
598 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
632 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
634 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
649 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
752 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
762 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
765 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
[all …]
Dpm24xx.c82 f1 = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1); in omap2_fclks_active()
83 f2 = omap2_cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2); in omap2_fclks_active()
108 omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1); in omap2_enter_full_retention()
109 omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2); in omap2_enter_full_retention()
170 omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1); in omap2_enter_full_retention()
171 omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP24XX_PM_WKST2); in omap2_enter_full_retention()
193 l = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1); in omap2_i2c_active()
204 l = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1); in omap2_allow_mpu_retention()
210 l = omap2_cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2); in omap2_allow_mpu_retention()
233 omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, PM_WKST1); in omap2_enter_mpu_retention()
[all …]
Dcm2xxx_3xxx.c346 omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1); in omap3_cm_save_context()
348 omap2_cm_read_mod_reg(CORE_MOD, OMAP3430ES2_CM_FCLKEN3); in omap3_cm_save_context()
362 omap2_cm_read_mod_reg(CORE_MOD, CM_ICLKEN1); in omap3_cm_save_context()
364 omap2_cm_read_mod_reg(CORE_MOD, CM_ICLKEN2); in omap3_cm_save_context()
366 omap2_cm_read_mod_reg(CORE_MOD, CM_ICLKEN3); in omap3_cm_save_context()
388 omap2_cm_read_mod_reg(CORE_MOD, OMAP2_CM_CLKSTCTRL); in omap3_cm_save_context()
403 omap2_cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE1); in omap3_cm_save_context()
405 omap2_cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE2); in omap3_cm_save_context()
407 omap2_cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE3); in omap3_cm_save_context()
474 omap2_cm_write_mod_reg(cm_context.core_cm_fclken1, CORE_MOD, in omap3_cm_restore_context()
[all …]
Dclock3xxx_data.c712 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1152 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1169 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1321 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1331 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1341 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
1351 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
1368 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
1370 .clksel_reg = OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL),
1382 .enable_reg = OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
[all …]
Domap_hwmod_2430_data.c551 .module_offs = CORE_MOD,
601 .module_offs = CORE_MOD,
651 .module_offs = CORE_MOD,
701 .module_offs = CORE_MOD,
751 .module_offs = CORE_MOD,
801 .module_offs = CORE_MOD,
851 .module_offs = CORE_MOD,
901 .module_offs = CORE_MOD,
951 .module_offs = CORE_MOD,
1001 .module_offs = CORE_MOD,
[all …]
Domap_hwmod_2420_data.c450 .module_offs = CORE_MOD,
500 .module_offs = CORE_MOD,
550 .module_offs = CORE_MOD,
600 .module_offs = CORE_MOD,
651 .module_offs = CORE_MOD,
701 .module_offs = CORE_MOD,
751 .module_offs = CORE_MOD,
801 .module_offs = CORE_MOD,
851 .module_offs = CORE_MOD,
901 .module_offs = CORE_MOD,
[all …]
Dpm-debug.c89 DUMP_CM_MOD_REG(CORE_MOD, CM_FCLKEN1); in omap2_pm_dump()
91 DUMP_CM_MOD_REG(CORE_MOD, OMAP24XX_CM_FCLKEN2); in omap2_pm_dump()
98 DUMP_CM_MOD_REG(CORE_MOD, CM_ICLKEN1); in omap2_pm_dump()
99 DUMP_CM_MOD_REG(CORE_MOD, CM_ICLKEN2); in omap2_pm_dump()
103 DUMP_PRM_MOD_REG(CORE_MOD, OMAP2_PM_PWSTST); in omap2_pm_dump()
121 DUMP_PRM_MOD_REG(CORE_MOD, PM_WKST1); in omap2_pm_dump()
123 DUMP_PRM_MOD_REG(CORE_MOD, OMAP24XX_PM_WKST2); in omap2_pm_dump()
215 { "CORE", MOD_CM, CORE_MOD, 0, 0x4c },
229 { "CORE", MOD_PRM, CORE_MOD, 0x58, 0xf8 },
Dpm34xx.c248 c += prcm_clear_mod_irqs(CORE_MOD, 1); in _prcm_int_handle_wakeup()
251 c += prcm_clear_mod_irqs(CORE_MOD, 3); in _prcm_int_handle_wakeup()
687 CORE_MOD, OMAP2_RM_RSTCTRL); in omap3_d2d_idle()
688 omap2_prm_write_mod_reg(0, CORE_MOD, OMAP2_RM_RSTCTRL); in omap3_d2d_idle()
752 omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1); in prcm_setup_regs()
753 omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3); in prcm_setup_regs()
758 omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP2_RM_RSTST); in prcm_setup_regs()
Dclkt2xxx_virt_prcm_set.c145 tmp = omap2_cm_read_mod_reg(CORE_MOD, CM_CLKSEL1) & OMAP24XX_CLKSEL_DSS2_MASK; in omap2_select_table_rate()
146 omap2_cm_write_mod_reg(prcm->cm_clksel1_core | tmp, CORE_MOD, in omap2_select_table_rate()
Dpowerdomains3xxx_data.c85 .prcm_offs = CORE_MOD,
105 .prcm_offs = CORE_MOD,
Dclock2430.c48 *idlest_reg = OMAP2430_CM_REGADDR(CORE_MOD, CM_IDLEST); in omap2430_clk_i2chs_find_idlest()
Domap_hwmod_3xxx_data.c1101 .module_offs = CORE_MOD,
1151 .module_offs = CORE_MOD,
1336 .module_offs = CORE_MOD,
1373 .module_offs = CORE_MOD,
1901 .module_offs = CORE_MOD,
1943 .module_offs = CORE_MOD,
1985 .module_offs = CORE_MOD,
2428 .module_offs = CORE_MOD,
2512 .module_offs = CORE_MOD,
2754 .module_offs = CORE_MOD,
[all …]
Dserial.c490 u32 mod = (uart->num > 1) ? OMAP3430_PER_MOD : CORE_MOD; in omap_uart_idle_init()
536 uart->wk_en = OMAP2430_PRM_REGADDR(CORE_MOD, wk_en); in omap_uart_idle_init()
537 uart->wk_st = OMAP2430_PRM_REGADDR(CORE_MOD, wk_st); in omap_uart_idle_init()
539 uart->wk_en = OMAP2420_PRM_REGADDR(CORE_MOD, wk_en); in omap_uart_idle_init()
540 uart->wk_st = OMAP2420_PRM_REGADDR(CORE_MOD, wk_st); in omap_uart_idle_init()
Dpowerdomains2xxx_data.c60 .prcm_offs = CORE_MOD,
Dsram34xx.S299 .word OMAP34XX_CM_REGADDR(CORE_MOD, CM_IDLEST)
301 .word OMAP34XX_CM_REGADDR(CORE_MOD, CM_ICLKEN1)
Dprcm-common.h27 #define CORE_MOD 0x200 macro
Dsleep34xx.S41 #define PM_PREPWSTST_CORE_P OMAP3430_PRM_BASE + CORE_MOD +\
44 #define CM_IDLEST1_CORE_V OMAP34XX_CM_REGADDR(CORE_MOD, CM_IDLEST1)
Dcontrol.c314 omap2_cm_read_mod_reg(CORE_MOD, CM_CLKSEL); in omap3_save_scratchpad_contents()