Home
last modified time | relevance | path

Searched refs:BIT0 (Results 1 – 25 of 42) sorted by relevance

12

/linux-2.6.39/drivers/scsi/
Dtmscsim.h191 #define BIT0 0x00000001 macro
194 #define UNIT_ALLOCATED BIT0
200 #define DASD_SUPPORT BIT0
206 #define SRB_WAIT BIT0
223 #define SRB_OK BIT0
231 #define RESET_DEV BIT0
236 #define ABORT_DEV_ BIT0
245 #define AUTO_REQSENSE BIT0
278 #define SYNC_ENABLE BIT0
333 #define PARITY_CHK_ BIT0
[all …]
Ddc395x.h75 #define BIT0 0x00000001 macro
78 #define UNIT_ALLOCATED BIT0
84 #define DASD_SUPPORT BIT0
120 #define RESET_DEV BIT0
125 #define ABORT_DEV_ BIT0
128 #define SRB_OK BIT0
142 #define AUTO_REQSENSE BIT0
173 #define SYNC_NEGO_ENABLE BIT0
629 #define MORE2_DRV BIT0
/linux-2.6.39/drivers/staging/vt6655/
D80211hdr.h38 #define BIT0 0x00000001 macro
164 #define WLAN_GET_FC_PRVER(n) ((((unsigned short)(n) >> 8) & (BIT0 | BIT1))
177 #define WLAN_GET_SEQ_FRGNUM(n) (((unsigned short)(n) >> 8) & (BIT0|BIT1|BIT2|BIT3))
178 #define WLAN_GET_SEQ_SEQNUM(n) ((((unsigned short)(n) >> 8) & (~(BIT0|BIT1|BIT2|BIT3))) >> 4)
182 #define WLAN_GET_CAP_INFO_ESS(n) (((n) >> 8) & BIT0)
199 #define WLAN_GET_FC_PRVER(n) (((unsigned short)(n)) & (BIT0 | BIT1))
213 #define WLAN_GET_SEQ_FRGNUM(n) (((unsigned short)(n)) & (BIT0|BIT1|BIT2|BIT3))
214 #define WLAN_GET_SEQ_SEQNUM(n) ((((unsigned short)(n)) & (~(BIT0|BIT1|BIT2|BIT3))) >> 4)
218 #define WLAN_GET_CAP_INFO_ESS(n) ((n) & BIT0)
266 #define WLAN_GET_ERP_NONERP_PRESENT(n) ((n) & BIT0)
[all …]
Dhostap.h36 #define WLAN_RATE_1M BIT0
Dbaseband.c2170 MACvRegBitsOn(dwIoBase, MAC_REG_PAPEDELAY, BIT0); in BBbVT3253Init()
2203 MACvRegBitsOn(dwIoBase, MAC_REG_PAPEDELAY, BIT0); in BBbVT3253Init()
2524 byOrgData |= BIT0; in BBvPowerSaveModeON()
2546 byOrgData &= ~(BIT0); in BBvPowerSaveModeOFF()
Dbssdb.h55 #define WLAN_STA_AUTH BIT0
/linux-2.6.39/drivers/staging/vt6656/
D80211hdr.h36 #define BIT0 0x00000001 macro
160 #define WLAN_GET_FC_PRVER(n) ((((WORD)(n) >> 8) & (BIT0 | BIT1))
174 #define WLAN_GET_SEQ_FRGNUM(n) (((WORD)(n) >> 8) & (BIT0|BIT1|BIT2|BIT3))
176 & (~(BIT0|BIT1|BIT2|BIT3))) >> 4)
179 #define WLAN_GET_CAP_INFO_ESS(n) (((n) >> 8) & BIT0)
195 #define WLAN_GET_FC_PRVER(n) (((WORD)(n)) & (BIT0 | BIT1))
208 #define WLAN_GET_SEQ_FRGNUM(n) (((WORD)(n)) & (BIT0|BIT1|BIT2|BIT3))
209 #define WLAN_GET_SEQ_SEQNUM(n) ((((WORD)(n)) & (~(BIT0|BIT1|BIT2|BIT3))) >> 4)
212 #define WLAN_GET_CAP_INFO_ESS(n) ((n) & BIT0)
257 #define WLAN_GET_ERP_NONERP_PRESENT(n) ((n) & BIT0)
[all …]
Dhostap.h36 #define WLAN_RATE_1M BIT0
Dbssdb.h56 #define WLAN_STA_AUTH BIT0
/linux-2.6.39/drivers/video/via/
Ddvi.c74 viafb_write_reg_mask(SR2A, VIASR, 0x03, BIT0 + BIT1); in viafb_tmds_trasmitter_identify()
81 viafb_write_reg_mask(SR2A, VIASR, 0x03, BIT0 + BIT1); in viafb_tmds_trasmitter_identify()
494 BIT0 + BIT1 + BIT2); in dvi_patch_skew_dvp0()
497 BIT0 + BIT1 + BIT2); in dvi_patch_skew_dvp0()
504 BIT0 + BIT1 + BIT2 + BIT3); in dvi_patch_skew_dvp0()
522 viafb_write_reg_mask(CR99, VIACR, 0x03, BIT0 + BIT1); in dvi_patch_skew_dvp_low()
529 BIT0 + BIT1 + BIT2 + BIT3); in dvi_patch_skew_dvp_low()
536 BIT0 + BIT1 + BIT2 + BIT3); in dvi_patch_skew_dvp_low()
554 viafb_write_reg_mask(CR6B, VIACR, 0x01, BIT0); in viafb_dvi_enable()
555 viafb_write_reg_mask(CR6C, VIACR, 0x21, BIT0 + BIT5); in viafb_dvi_enable()
[all …]
Dvia_utility.c166 viafb_write_reg_mask(SR1A, VIASR, 0x0, BIT0); in viafb_set_gamma_table()
183 viafb_write_reg_mask(SR1A, VIASR, 0x01, BIT0); in viafb_set_gamma_table()
221 viafb_write_reg_mask(SR1A, VIASR, 0x0, BIT0); in viafb_get_gamma_table()
Dlcd.c370 viafb_write_reg_mask(CR79, VIACR, 0x07, BIT0 + BIT1 + BIT2); in load_lcd_scaling()
548 BIT0 + BIT1 + BIT2 + BIT3); in lcd_patch_skew()
603 BIT0 + BIT1 + BIT2); in viafb_lcd_set_mode()
625 viafb_write_reg_mask(CR6A, VIACR, 0x01, BIT0); in viafb_lcd_set_mode()
691 viafb_write_reg_mask(CRD2, VIACR, 0x00, BIT0 + BIT1); in integrated_lvds_enable()
693 viafb_write_reg_mask(CRD2, VIACR, 0x03, BIT0 + BIT1); in integrated_lvds_enable()
700 viafb_write_reg_mask(CR91, VIACR, 0, BIT0); in integrated_lvds_enable()
709 viafb_write_reg_mask(CRD3, VIACR, 0, BIT0); in integrated_lvds_enable()
785 BIT7 + BIT2 + BIT1 + BIT0); in set_lcd_output_path()
884 bdithering = BIT0; in fill_lcd_format()
[all …]
Dhw.c699 viafb_write_reg_mask(CR47, VIACR, 0, BIT0); in viafb_unlock_crt()
1176 viafb_write_reg_mask(CR33, VIACR, 0x06, BIT0 + BIT1 + BIT2); in load_fix_bit_crtc_reg()
1217 reg_mask = reg_mask | (BIT0 << j); in viafb_load_reg()
1218 get_bit = (timing_value & (BIT0 << bit_num)); in viafb_load_reg()
2258 viafb_write_reg_mask(SR1A, VIASR, 0x00, BIT0); in viafb_init_dac()
2272 viafb_write_reg_mask(SR1A, VIASR, 0x01, BIT0); in viafb_init_dac()
2279 viafb_write_reg_mask(SR1A, VIASR, 0x00, BIT0); in viafb_init_dac()
/linux-2.6.39/drivers/staging/rtl8192e/
Dr8192E_hw.h167 #define RCR_FILTER_MASK (BIT0|BIT1|BIT2|BIT3|BIT5|BIT12|BIT18|BIT19|BIT20|BIT21|BIT22|BIT23)
185 #define RCR_AAP BIT0 // Accept all unicast packet
240 #define SCR_TxUseDK BIT0 //Force Tx Use Default Key
270 #define IMR_ROK BIT0 // Receive DMA OK Interrupt
273 #define TPPoll_BKQ BIT0 // BK queue polling
320 #define AcmHw_HwEn BIT0
328 #define AcmFw_BeqStatus BIT0
383 #define BW_OPMODE_11J BIT0
406 #define RRSR_1M BIT0
/linux-2.6.39/drivers/staging/rtl8192u/
Dr8192U_hw.h160 #define RCR_AAP BIT0 // Accept all unicast packet
183 #define SCR_TxUseDK BIT0 //Force Tx Use Default Key
229 #define AcmHw_HwEn BIT0
284 #define BW_OPMODE_11J BIT0
307 #define RRSR_1M BIT0
/linux-2.6.39/drivers/staging/keucr/
Dsmilecc.c45 #define BIT0 0x01 macro
158 b=BIT0;
167 if (d&BIT0) ++i; // Count number of 1 bit
/linux-2.6.39/arch/arm/mach-integrator/include/mach/
Dbits.h26 #define BIT0 0x00000001 macro
/linux-2.6.39/drivers/staging/rtl8192u/ieee80211/
Drtl819x_Qos.h4 #define BIT0 0x00000001 macro
395 #define GET_VO_UAPSD(_apsd) ((_apsd) & BIT0)
396 #define SET_VO_UAPSD(_apsd) ((_apsd) |= BIT0)
/linux-2.6.39/drivers/staging/rtl8192e/ieee80211/
Drtl819x_Qos.h4 #define BIT0 0x00000001 macro
395 #define GET_VO_UAPSD(_apsd) ((_apsd) & BIT0)
396 #define SET_VO_UAPSD(_apsd) ((_apsd) |= BIT0)
/linux-2.6.39/drivers/tty/
Dsynclink_gt.c216 …a).status = cpu_to_le16((b) ? (le16_to_cpu((a).status) | BIT0) : (le16_to_cpu((a).status) & ~BIT0))
223 #define desc_abort(a) (le16_to_cpu((a).status) & BIT0)
385 #define MASK_FRAMING BIT0
427 #define IRQ_MASTER BIT0
1885 if ((status = *(p+1) & (BIT1 + BIT0))) { in rx_async()
1888 else if (status & BIT0) in rx_async()
1895 else if (status & BIT0) in rx_async()
2112 if (status & BIT0) { in ri_change()
3903 if (!(rd_reg32(info, RDCSR) & BIT0)) in rdma_reset()
3916 if (!(rd_reg32(info, TDCSR) & BIT0)) in tdma_reset()
[all …]
Dsynclinkmp.c420 #define RXRDYE BIT0
432 #define BRKE BIT0
433 #define IDLD BIT0
2172 while((status = read_reg(info,CST0)) & BIT0) in isr_rxrdy()
2588 if (status & BIT0 << shift) in synclinkmp_interrupt()
2597 if (dmastatus & BIT0 << shift) in synclinkmp_interrupt()
4031 write_reg(info, MD2, (unsigned char)(read_reg(info, MD2) | (BIT1 + BIT0))); in enable_loopback()
4034 info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2)); in enable_loopback()
4049 write_reg(info, MD2, (unsigned char)(read_reg(info, MD2) & ~(BIT1 + BIT0))); in enable_loopback()
4419 RegValue |= BIT0; in async_mode()
[all …]
/linux-2.6.39/drivers/staging/wlags49_h2/
Dhcfdef.h89 #define BIT0 0x0001
358 #define HREG_DMA_CTRL_TX_MODE_SINGLE_PACKET BIT0 // mode 1
/linux-2.6.39/include/linux/
Dsynclink.h18 #define BIT0 0x0001 macro
/linux-2.6.39/drivers/net/
Dcs89x0.h463 #define BIT0 1 macro
/linux-2.6.39/drivers/staging/rtl8187se/
Dr8180_hw.h24 #define BIT0 0x00000001 macro

12