Lines Matching refs:BIT0
74 viafb_write_reg_mask(SR2A, VIASR, 0x03, BIT0 + BIT1); in viafb_tmds_trasmitter_identify()
81 viafb_write_reg_mask(SR2A, VIASR, 0x03, BIT0 + BIT1); in viafb_tmds_trasmitter_identify()
494 BIT0 + BIT1 + BIT2); in dvi_patch_skew_dvp0()
497 BIT0 + BIT1 + BIT2); in dvi_patch_skew_dvp0()
504 BIT0 + BIT1 + BIT2 + BIT3); in dvi_patch_skew_dvp0()
522 viafb_write_reg_mask(CR99, VIACR, 0x03, BIT0 + BIT1); in dvi_patch_skew_dvp_low()
529 BIT0 + BIT1 + BIT2 + BIT3); in dvi_patch_skew_dvp_low()
536 BIT0 + BIT1 + BIT2 + BIT3); in dvi_patch_skew_dvp_low()
554 viafb_write_reg_mask(CR6B, VIACR, 0x01, BIT0); in viafb_dvi_enable()
555 viafb_write_reg_mask(CR6C, VIACR, 0x21, BIT0 + BIT5); in viafb_dvi_enable()
567 viafb_write_reg_mask(CR93, VIACR, 0x21, BIT0 + BIT5); in viafb_dvi_enable()
580 viafb_write_reg_mask(CR88, VIACR, 0x00, BIT6 + BIT0); in viafb_dvi_enable()
621 viafb_write_reg_mask(CR79, VIACR, 0x00, BIT0); in viafb_dvi_enable()