Home
last modified time | relevance | path

Searched refs:writereg (Results 1 – 19 of 19) sorted by relevance

/linux-2.4.37.9/drivers/net/
Dmac89x0.c166 writereg(struct net_device *dev, int portno, int value) in writereg() function
302 writereg(dev, PP_SelfCTL, readreg(dev, PP_SelfCTL) | POWER_ON_RESET);
329 writereg(dev, PP_BusCTL, readreg(dev, PP_BusCTL) & ~ENABLE_IRQ); in net_open()
337 writereg(dev, PP_CS8900_ISAINT, 0); in net_open()
339 writereg(dev, PP_CS8920_ISAINT, 0); in net_open()
343 writereg(dev, PP_IA+i*2, dev->dev_addr[i*2] | (dev->dev_addr[i*2+1] << 8)); in net_open()
346 writereg(dev, PP_LineCTL, readreg(dev, PP_LineCTL) | SERIAL_RX_ON | SERIAL_TX_ON); in net_open()
350 writereg(dev, PP_RxCTL, DEF_RX_ACCEPT); in net_open()
354 writereg(dev, PP_RxCFG, lp->curr_rx_cfg); in net_open()
356 writereg(dev, PP_TxCFG, TX_LOST_CRS_ENBL | TX_SQE_ERROR_ENBL | TX_OK_ENBL | in net_open()
[all …]
Ddeclance.c290 static inline void writereg(volatile unsigned short *regptr, short value) in writereg() function
307 writereg(&ll->rap, LE_CSR1); in load_csrs()
308 writereg(&ll->rdp, (leptr & 0xFFFF)); in load_csrs()
309 writereg(&ll->rap, LE_CSR2); in load_csrs()
310 writereg(&ll->rdp, leptr >> 16); in load_csrs()
311 writereg(&ll->rap, LE_CSR3); in load_csrs()
312 writereg(&ll->rdp, lp->busmaster_regval); in load_csrs()
315 writereg(&ll->rap, LE_CSR0); in load_csrs()
509 writereg(&ll->rap, LE_CSR0); in init_restart_lance()
510 writereg(&ll->rdp, LE_C0_INIT); in init_restart_lance()
[all …]
Dcs89x0.c311 writereg(struct net_device *dev, int portno, int value) in writereg() function
351 writereg(dev, PP_EECMD, (off + i) | EEPROM_READ_CMD); in get_eeprom_data()
756 writereg(dev, PP_CS8900_ISADMA, dma-5); in write_dma()
758 writereg(dev, PP_CS8920_ISADMA, dma); in write_dma()
881 writereg(dev, PP_SelfCTL, readreg(dev, PP_SelfCTL) | POWER_ON_RESET); in reset_chip()
919 writereg(dev, PP_SelfCTL, selfcontrol); in control_dc_dc()
946 writereg(dev, PP_LineCTL, lp->linectl &~ AUI_ONLY); in detect_tp()
970 writereg(dev, PP_TestCTL, readreg(dev, PP_TestCTL) | FDX_8900); in detect_tp()
987 writereg(dev, PP_AutoNegCTL, lp->auto_neg_cnf & AUTO_NEG_MASK); in detect_tp()
1016 writereg(dev, PP_LineCTL, readreg(dev, PP_LineCTL) | SERIAL_TX_ON); in send_test_pkt()
[all …]
Dni65.c165 #define writereg(val,reg) {outw(reg,PORT+L_ADDRREG);inw(PORT+L_ADDRREG); \
172 #define writedatareg(val) { writereg(val,CSR0); }
175 #define writereg(val,reg) {outw(reg,PORT+L_ADDRREG);outw(val,PORT+L_DATAREG);} macro
177 #define writedatareg(val) { writereg(val,CSR0); }
248 writereg(CSR0_STOP | CSR0_CLRALL,CSR0); /* STOP */ in ni65_set_performance()
257 writereg( (csr80 & 0x3fff) ,80); /* FIFO watermarks */ in ni65_set_performance()
459 writereg(CSR0_INIT|CSR0_INEA,CSR0); /* trigger interrupt */ in ni65_probe1()
505 writereg(CSR0_CLRALL|CSR0_STOP,CSR0); in ni65_init_lance()
516 writereg(0,CSR3); /* busmaster/no word-swap */ in ni65_init_lance()
518 writereg(pib & 0xffff,CSR1); in ni65_init_lance()
[all …]
/linux-2.4.37.9/drivers/isdn/hisax/
Dasuscom.c71 writereg(unsigned int ale, unsigned int adr, u_char off, u_char data) in writereg() function
101 writereg(cs->hw.asus.adr, cs->hw.asus.isac, offset, value); in WriteISAC()
125 writereg(cs->hw.asus.adr, cs->hw.asus.isac, offset|0x80, value); in WriteISAC_IPAC()
150 writereg(cs->hw.asus.adr, in WriteHSCX()
160 #define WRITEHSCX(cs, nr, reg, data) writereg(cs->hw.asus.adr, \
201 writereg(cs->hw.asus.adr, cs->hw.asus.hscx, HSCX_MASK, 0xFF); in asuscom_interrupt()
202 writereg(cs->hw.asus.adr, cs->hw.asus.hscx, HSCX_MASK + 0x40, 0xFF); in asuscom_interrupt()
203 writereg(cs->hw.asus.adr, cs->hw.asus.isac, ISAC_MASK, 0xFF); in asuscom_interrupt()
204 writereg(cs->hw.asus.adr, cs->hw.asus.isac, ISAC_MASK, 0x0); in asuscom_interrupt()
205 writereg(cs->hw.asus.adr, cs->hw.asus.hscx, HSCX_MASK, 0x0); in asuscom_interrupt()
[all …]
Dsedlbauer.c146 writereg(unsigned int ale, unsigned int adr, u_char off, u_char data) in writereg() function
176 writereg(cs->hw.sedl.adr, cs->hw.sedl.isac, offset, value); in WriteISAC()
200 writereg(cs->hw.sedl.adr, cs->hw.sedl.isac, offset|0x80, value); in WriteISAC_IPAC()
225 writereg(cs->hw.sedl.adr, in WriteHSCX()
249 writereg(cs->hw.sedl.adr, cs->hw.sedl.hscx, offset, value); in WriteISAR()
263 #define WRITEHSCX(cs, nr, reg, data) writereg(cs->hw.sedl.adr, \
312 writereg(cs->hw.sedl.adr, cs->hw.sedl.hscx, HSCX_MASK, 0xFF); in sedlbauer_interrupt()
313 writereg(cs->hw.sedl.adr, cs->hw.sedl.hscx, HSCX_MASK + 0x40, 0xFF); in sedlbauer_interrupt()
314 writereg(cs->hw.sedl.adr, cs->hw.sedl.isac, ISAC_MASK, 0xFF); in sedlbauer_interrupt()
315 writereg(cs->hw.sedl.adr, cs->hw.sedl.isac, ISAC_MASK, 0x0); in sedlbauer_interrupt()
[all …]
Dmic.c60 writereg(unsigned int ale, unsigned int adr, u_char off, u_char data) in writereg() function
90 writereg(cs->hw.mic.adr, cs->hw.mic.isac, offset, value); in WriteISAC()
115 writereg(cs->hw.mic.adr, in WriteHSCX()
125 #define WRITEHSCX(cs, nr, reg, data) writereg(cs->hw.mic.adr, \
166 writereg(cs->hw.mic.adr, cs->hw.mic.hscx, HSCX_MASK, 0xFF); in mic_interrupt()
167 writereg(cs->hw.mic.adr, cs->hw.mic.hscx, HSCX_MASK + 0x40, 0xFF); in mic_interrupt()
168 writereg(cs->hw.mic.adr, cs->hw.mic.isac, ISAC_MASK, 0xFF); in mic_interrupt()
169 writereg(cs->hw.mic.adr, cs->hw.mic.isac, ISAC_MASK, 0x0); in mic_interrupt()
170 writereg(cs->hw.mic.adr, cs->hw.mic.hscx, HSCX_MASK, 0x0); in mic_interrupt()
171 writereg(cs->hw.mic.adr, cs->hw.mic.hscx, HSCX_MASK + 0x40, 0x0); in mic_interrupt()
Ds0box.c24 writereg(unsigned int padr, signed int addr, u_char off, u_char val) { in writereg() function
115 writereg(cs->hw.teles3.cfg_reg, cs->hw.teles3.isac, offset, value); in WriteISAC()
139 writereg(cs->hw.teles3.cfg_reg, cs->hw.teles3.hscx[hscx], offset, value); in WriteHSCX()
147 #define WRITEHSCX(cs, nr, reg, data) writereg(cs->hw.teles3.cfg_reg, cs->hw.teles3.hscx[nr], reg, d…
188 writereg(cs->hw.teles3.cfg_reg, cs->hw.teles3.hscx[0], HSCX_MASK, 0xFF); in s0box_interrupt()
189 writereg(cs->hw.teles3.cfg_reg, cs->hw.teles3.hscx[1], HSCX_MASK, 0xFF); in s0box_interrupt()
190 writereg(cs->hw.teles3.cfg_reg, cs->hw.teles3.isac, ISAC_MASK, 0xFF); in s0box_interrupt()
191 writereg(cs->hw.teles3.cfg_reg, cs->hw.teles3.isac, ISAC_MASK, 0x0); in s0box_interrupt()
192 writereg(cs->hw.teles3.cfg_reg, cs->hw.teles3.hscx[0], HSCX_MASK, 0x0); in s0box_interrupt()
193 writereg(cs->hw.teles3.cfg_reg, cs->hw.teles3.hscx[1], HSCX_MASK, 0x0); in s0box_interrupt()
Dsaphir.c60 writereg(unsigned int ale, unsigned int adr, u_char off, u_char data) in writereg() function
90 writereg(cs->hw.saphir.ale, cs->hw.saphir.isac, offset, value); in WriteISAC()
115 writereg(cs->hw.saphir.ale, cs->hw.saphir.hscx, in WriteHSCX()
121 #define WRITEHSCX(cs, nr, reg, data) writereg(cs->hw.saphir.ale, \
167 writereg(cs->hw.saphir.ale, cs->hw.saphir.hscx, HSCX_MASK, 0xFF); in saphir_interrupt()
168 writereg(cs->hw.saphir.ale, cs->hw.saphir.hscx, HSCX_MASK + 0x40, 0xFF); in saphir_interrupt()
169 writereg(cs->hw.saphir.ale, cs->hw.saphir.isac, ISAC_MASK, 0xFF); in saphir_interrupt()
170 writereg(cs->hw.saphir.ale, cs->hw.saphir.isac, ISAC_MASK, 0); in saphir_interrupt()
171 writereg(cs->hw.saphir.ale, cs->hw.saphir.hscx, HSCX_MASK, 0); in saphir_interrupt()
172 writereg(cs->hw.saphir.ale, cs->hw.saphir.hscx, HSCX_MASK + 0x40, 0); in saphir_interrupt()
Dix1_micro.c68 writereg(unsigned int ale, unsigned int adr, u_char off, u_char data) in writereg() function
98 writereg(cs->hw.ix1.isac_ale, cs->hw.ix1.isac, offset, value); in WriteISAC()
123 writereg(cs->hw.ix1.hscx_ale, in WriteHSCX()
129 #define WRITEHSCX(cs, nr, reg, data) writereg(cs->hw.ix1.hscx_ale, \
170 writereg(cs->hw.ix1.hscx_ale, cs->hw.ix1.hscx, HSCX_MASK, 0xFF); in ix1micro_interrupt()
171 writereg(cs->hw.ix1.hscx_ale, cs->hw.ix1.hscx, HSCX_MASK + 0x40, 0xFF); in ix1micro_interrupt()
172 writereg(cs->hw.ix1.isac_ale, cs->hw.ix1.isac, ISAC_MASK, 0xFF); in ix1micro_interrupt()
173 writereg(cs->hw.ix1.isac_ale, cs->hw.ix1.isac, ISAC_MASK, 0); in ix1micro_interrupt()
174 writereg(cs->hw.ix1.hscx_ale, cs->hw.ix1.hscx, HSCX_MASK, 0); in ix1micro_interrupt()
175 writereg(cs->hw.ix1.hscx_ale, cs->hw.ix1.hscx, HSCX_MASK + 0x40, 0); in ix1micro_interrupt()
Davm_a1.c37 writereg(unsigned int adr, u_char off, u_char data) in writereg() function
66 writereg(cs->hw.avm.isac, offset, value); in WriteISAC()
90 writereg(cs->hw.avm.hscx[hscx], offset, value); in WriteHSCX()
98 #define WRITEHSCX(cs, nr, reg, data) writereg(cs->hw.avm.hscx[nr], reg, data)
131 writereg(cs->hw.avm.hscx[0], HSCX_MASK, 0xFF); in avm_a1_interrupt()
132 writereg(cs->hw.avm.hscx[1], HSCX_MASK, 0xFF); in avm_a1_interrupt()
133 writereg(cs->hw.avm.isac, ISAC_MASK, 0xFF); in avm_a1_interrupt()
134 writereg(cs->hw.avm.isac, ISAC_MASK, 0x0); in avm_a1_interrupt()
135 writereg(cs->hw.avm.hscx[0], HSCX_MASK, 0x0); in avm_a1_interrupt()
136 writereg(cs->hw.avm.hscx[1], HSCX_MASK, 0x0); in avm_a1_interrupt()
Dbkm_a8.c71 writereg(unsigned int ale, unsigned int adr, u_char off, u_char data) in writereg() function
102 writereg(cs->hw.ax.base, cs->hw.ax.data_adr, offset | 0x80, value); in WriteISAC()
127 writereg(cs->hw.ax.base, cs->hw.ax.data_adr, offset + (hscx ? 0x40 : 0), value); in WriteHSCX()
135 writereg(cs->hw.ax.base, cs->hw.ax.data_adr, IPAC_MASK, in set_ipac_active()
145 #define WRITEHSCX(cs, nr, reg, data) writereg(cs->hw.ax.base, \
201 writereg(cs->hw.ax.base, cs->hw.ax.data_adr, IPAC_MASK, 0xFF); in bkm_interrupt_ipac()
202 writereg(cs->hw.ax.base, cs->hw.ax.data_adr, IPAC_MASK, 0xC0); in bkm_interrupt_ipac()
412 writereg(pci_ioaddr5, pci_ioaddr5 + 4, in setup_sct_quadro()
414 writereg(pci_ioaddr4 + 0x08, pci_ioaddr4 + 0x0c, in setup_sct_quadro()
416 writereg(pci_ioaddr3 + 0x10, pci_ioaddr3 + 0x14, in setup_sct_quadro()
[all …]
Dniccy.c75 writereg(unsigned int ale, unsigned int adr, u_char off, u_char data) in writereg() function
105 writereg(cs->hw.niccy.isac_ale, cs->hw.niccy.isac, offset, value); in WriteISAC()
130 writereg(cs->hw.niccy.hscx_ale, in WriteHSCX()
136 #define WRITEHSCX(cs, nr, reg, data) writereg(cs->hw.niccy.hscx_ale, \
184 writereg(cs->hw.niccy.hscx_ale, cs->hw.niccy.hscx, HSCX_MASK, 0xFF); in niccy_interrupt()
185 writereg(cs->hw.niccy.hscx_ale, cs->hw.niccy.hscx, HSCX_MASK + 0x40, 0xFF); in niccy_interrupt()
186 writereg(cs->hw.niccy.isac_ale, cs->hw.niccy.isac, ISAC_MASK, 0xFF); in niccy_interrupt()
187 writereg(cs->hw.niccy.isac_ale, cs->hw.niccy.isac, ISAC_MASK, 0); in niccy_interrupt()
188 writereg(cs->hw.niccy.hscx_ale, cs->hw.niccy.hscx, HSCX_MASK, 0); in niccy_interrupt()
189 writereg(cs->hw.niccy.hscx_ale, cs->hw.niccy.hscx, HSCX_MASK + 0x40, 0); in niccy_interrupt()
Delsa.c170 writereg(unsigned int ale, unsigned int adr, u_char off, u_char data) in writereg() function
200 writereg(cs->hw.elsa.ale, cs->hw.elsa.isac, offset, value); in WriteISAC()
224 writereg(cs->hw.elsa.ale, cs->hw.elsa.isac, offset|0x80, value); in WriteISAC_IPAC()
249 writereg(cs->hw.elsa.ale, in WriteHSCX()
297 #define WRITEHSCX(cs, nr, reg, data) writereg(cs->hw.elsa.ale, \
360 writereg(cs->hw.elsa.ale, cs->hw.elsa.hscx, HSCX_MASK, 0xFF); in elsa_interrupt()
361 writereg(cs->hw.elsa.ale, cs->hw.elsa.hscx, HSCX_MASK + 0x40, 0xFF); in elsa_interrupt()
362 writereg(cs->hw.elsa.ale, cs->hw.elsa.isac, ISAC_MASK, 0xFF); in elsa_interrupt()
382 writereg(cs->hw.elsa.ale, cs->hw.elsa.hscx, HSCX_MASK, 0x0); in elsa_interrupt()
383 writereg(cs->hw.elsa.ale, cs->hw.elsa.hscx, HSCX_MASK + 0x40, 0x0); in elsa_interrupt()
[all …]
Dteles3.c37 writereg(unsigned int adr, u_char off, u_char data) in writereg() function
66 writereg(cs->hw.teles3.isac, offset, value); in WriteISAC()
90 writereg(cs->hw.teles3.hscx[hscx], offset, value); in WriteHSCX()
98 #define WRITEHSCX(cs, nr, reg, data) writereg(cs->hw.teles3.hscx[nr], reg, data)
139 writereg(cs->hw.teles3.hscx[0], HSCX_MASK, 0xFF); in teles3_interrupt()
140 writereg(cs->hw.teles3.hscx[1], HSCX_MASK, 0xFF); in teles3_interrupt()
141 writereg(cs->hw.teles3.isac, ISAC_MASK, 0xFF); in teles3_interrupt()
142 writereg(cs->hw.teles3.isac, ISAC_MASK, 0x0); in teles3_interrupt()
143 writereg(cs->hw.teles3.hscx[0], HSCX_MASK, 0x0); in teles3_interrupt()
144 writereg(cs->hw.teles3.hscx[1], HSCX_MASK, 0x0); in teles3_interrupt()
Ddiva.c110 writereg(unsigned int ale, unsigned int adr, u_char off, u_char data) in writereg() function
156 writereg(cs->hw.diva.isac_adr, cs->hw.diva.isac, offset, value); in WriteISAC()
180 writereg(cs->hw.diva.isac_adr, cs->hw.diva.isac, offset|0x80, value); in WriteISAC_IPAC()
205 writereg(cs->hw.diva.hscx_adr, in WriteHSCX()
294 #define WRITEHSCX(cs, nr, reg, data) writereg(cs->hw.diva.hscx_adr, \
327 writereg(cs->hw.diva.hscx_adr, cs->hw.diva.hscx, HSCX_MASK, 0xFF); in diva_interrupt()
328 writereg(cs->hw.diva.hscx_adr, cs->hw.diva.hscx, HSCX_MASK + 0x40, 0xFF); in diva_interrupt()
329 writereg(cs->hw.diva.isac_adr, cs->hw.diva.isac, ISAC_MASK, 0xFF); in diva_interrupt()
330 writereg(cs->hw.diva.isac_adr, cs->hw.diva.isac, ISAC_MASK, 0x0); in diva_interrupt()
331 writereg(cs->hw.diva.hscx_adr, cs->hw.diva.hscx, HSCX_MASK, 0x0); in diva_interrupt()
[all …]
Dbkm_a4t.c59 writereg(unsigned int ale, unsigned long adr, u_char off, u_char data) in writereg() function
80 writereg(ale, adr, off, *data++); in writefifo()
95 writereg(cs->hw.ax.isac_ale, cs->hw.ax.isac_adr, offset, value); in WriteISAC()
119 …writereg(cs->hw.ax.jade_ale, cs->hw.ax.jade_adr, offset + (jade == -1 ? 0 : (jade ? 0xC0 : 0x80)),… in WriteJADE()
128 #define WRITEJADE(cs, nr, reg, data) writereg(cs->hw.ax.jade_ale,\
Dteleint.c72 writereg(unsigned int ale, unsigned int adr, u_char off, u_char data) in writereg() function
127 writereg(cs->hw.hfc.addr | 1, cs->hw.hfc.addr, offset, value); in WriteISAC()
191 writereg(cs->hw.hfc.addr | 1, cs->hw.hfc.addr, ISAC_MASK, 0xFF); in TeleInt_interrupt()
192 writereg(cs->hw.hfc.addr | 1, cs->hw.hfc.addr, ISAC_MASK, 0x0); in TeleInt_interrupt()
Dgazel.c54 writereg(unsigned int adr, u_short off, u_char data) in writereg() function
141 writereg(cs->hw.gazel.isac, off2, value); in WriteISAC()
236 writereg(cs->hw.gazel.hscx[hscx], off2, value); in WriteHSCX()
368 writereg(addr, 0, 0); in reset_gazel()
370 writereg(addr, 0, 1); in reset_gazel()