71 writereg(unsigned int ale, unsigned int adr, u_char off, u_char data)  in writereg()  function
102 	writereg(cs->hw.ax.base, cs->hw.ax.data_adr, offset | 0x80, value);  in WriteISAC()
127 	writereg(cs->hw.ax.base, cs->hw.ax.data_adr, offset + (hscx ? 0x40 : 0), value);  in WriteHSCX()
135 	writereg(cs->hw.ax.base, cs->hw.ax.data_adr, IPAC_MASK,  in set_ipac_active()
145 #define WRITEHSCX(cs, nr, reg, data) writereg(cs->hw.ax.base, \
201 	writereg(cs->hw.ax.base, cs->hw.ax.data_adr, IPAC_MASK, 0xFF);  in bkm_interrupt_ipac()
202 	writereg(cs->hw.ax.base, cs->hw.ax.data_adr, IPAC_MASK, 0xC0);  in bkm_interrupt_ipac()
412 			writereg(pci_ioaddr5, pci_ioaddr5 + 4,  in setup_sct_quadro()
414 			writereg(pci_ioaddr4 + 0x08, pci_ioaddr4 + 0x0c,  in setup_sct_quadro()
416 			writereg(pci_ioaddr3 + 0x10, pci_ioaddr3 + 0x14,  in setup_sct_quadro()
418 			writereg(pci_ioaddr2 + 0x20, pci_ioaddr2 + 0x24,  in setup_sct_quadro()