Home
last modified time | relevance | path

Searched refs:mfdcr (Results 1 – 22 of 22) sorted by relevance

/linux-2.4.37.9/arch/ppc/kernel/
Dppc4xx_dma.c39 return (mfdcr(DCRN_DMASR)); in ppc4xx_get_dma_status()
144 control = mfdcr(DCRN_DMACR0); in ppc4xx_enable_dma()
147 control = mfdcr(DCRN_DMACR1); in ppc4xx_enable_dma()
150 control = mfdcr(DCRN_DMACR2); in ppc4xx_enable_dma()
153 control = mfdcr(DCRN_DMACR3); in ppc4xx_enable_dma()
245 control = mfdcr(DCRN_DMACR0); in ppc4xx_disable_dma()
250 control = mfdcr(DCRN_DMACR1); in ppc4xx_disable_dma()
255 control = mfdcr(DCRN_DMACR2); in ppc4xx_disable_dma()
260 control = mfdcr(DCRN_DMACR3); in ppc4xx_disable_dma()
377 count = mfdcr(DCRN_DMACT0); in ppc4xx_get_dma_residue()
[all …]
Dibm440gx_common.c107 mtdcr(DCRN_SRAM0_DPC, mfdcr(DCRN_SRAM0_DPC) & ~SRAM_DPC_ENABLE); in ibm440gx_l2c_enable()
108 mtdcr(DCRN_SRAM0_SB0CR, mfdcr(DCRN_SRAM0_SB0CR) & ~SRAM_SBCR_BU_MASK); in ibm440gx_l2c_enable()
109 mtdcr(DCRN_SRAM0_SB1CR, mfdcr(DCRN_SRAM0_SB1CR) & ~SRAM_SBCR_BU_MASK); in ibm440gx_l2c_enable()
110 mtdcr(DCRN_SRAM0_SB2CR, mfdcr(DCRN_SRAM0_SB2CR) & ~SRAM_SBCR_BU_MASK); in ibm440gx_l2c_enable()
111 mtdcr(DCRN_SRAM0_SB3CR, mfdcr(DCRN_SRAM0_SB3CR) & ~SRAM_SBCR_BU_MASK); in ibm440gx_l2c_enable()
114 r = mfdcr(DCRN_L2C0_CFG) & ~(L2C_CFG_ICU | L2C_CFG_DCU | L2C_CFG_SS_MASK); in ibm440gx_l2c_enable()
122 while (!(mfdcr(DCRN_L2C0_SR) & L2C_SR_CC)) ; in ibm440gx_l2c_enable()
128 r = mfdcr(DCRN_L2C0_SNP0) & ~(L2C_SNP_BA_MASK | L2C_SNP_SSR_MASK); in ibm440gx_l2c_enable()
132 r = mfdcr(DCRN_L2C0_SNP1) & ~(L2C_SNP_BA_MASK | L2C_SNP_SSR_MASK); in ibm440gx_l2c_enable()
139 r = mfdcr(DCRN_L2C0_CFG); in ibm440gx_l2c_enable()
[all …]
Dppc4xx_pic.c87 bits = mfdcr(DCRN_EXISR) & mfdcr(DCRN_EXIER); in ppc403_pic_get_irq()
162 if ((mfdcr(DCRN_UIC_TR(UIC0)) & (1 << (31 - bit))) == 0) in ppc405_uic_enable()
174 if ((mfdcr(DCRN_UIC_TR(UIC1)) & (1 << (31 - bit))) == 0) in ppc405_uic_enable()
254 tr_bits = mfdcr(DCRN_UIC_TR(UIC0)); in ppc405_uic_end()
257 tr_bits = mfdcr(DCRN_UIC_TR(UIC1)); in ppc405_uic_end()
316 bits = mfdcr(DCRN_UIC_MSR(UIC0)); in ppc405_pic_get_irq()
320 bits = mfdcr(DCRN_UIC_MSR(UIC1)); in ppc405_pic_get_irq()
379 printk("Pol %x ", mfdcr(DCRN_UIC_PR(UIC0))); in ppc4xx_extpic_init()
380 printk("Level %x\n", mfdcr(DCRN_UIC_TR(UIC0))); in ppc4xx_extpic_init()
391 printk("Pol %x ", mfdcr(DCRN_UIC_PR(UIC1))); in ppc4xx_extpic_init()
[all …]
Dppc4xx_sgdma.c176 sg_command = mfdcr(DCRN_ASGC); in ppc4xx_enable_dma_sgl()
218 sg_command = mfdcr(DCRN_ASGC); in ppc4xx_disable_dma_sgl()
266 sgl_addr = (ppc_sgl_t *) bus_to_virt(mfdcr(DCRN_ASG0)); in ppc4xx_get_dma_sgl_residue()
267 count_left = mfdcr(DCRN_DMACT0); in ppc4xx_get_dma_sgl_residue()
270 sgl_addr = (ppc_sgl_t *) bus_to_virt(mfdcr(DCRN_ASG1)); in ppc4xx_get_dma_sgl_residue()
271 count_left = mfdcr(DCRN_DMACT1); in ppc4xx_get_dma_sgl_residue()
274 sgl_addr = (ppc_sgl_t *) bus_to_virt(mfdcr(DCRN_ASG2)); in ppc4xx_get_dma_sgl_residue()
275 count_left = mfdcr(DCRN_DMACT2); in ppc4xx_get_dma_sgl_residue()
278 sgl_addr = (ppc_sgl_t *) bus_to_virt(mfdcr(DCRN_ASG3)); in ppc4xx_get_dma_sgl_residue()
279 count_left = mfdcr(DCRN_DMACT3); in ppc4xx_get_dma_sgl_residue()
[all …]
Dppc4xx_stbdma.c83 map = mfdcr(DCRN_DMAS1); in ppc4xx_map_dma_port()
88 map = mfdcr(DCRN_DMAS2); in ppc4xx_map_dma_port()
114 map = mfdcr(DCRN_DMAS1); in ppc4xx_disable_dma_port()
119 map = mfdcr(DCRN_DMAS2); in ppc4xx_disable_dma_port()
Dibm440gp_common.c31 u32 cpc0_sys0 = mfdcr(DCRN_CPC0_SYS0); in ibm440gp_get_clocks()
32 u32 cpc0_cr0 = mfdcr(DCRN_CPC0_CR0); in ibm440gp_get_clocks()
Dprocess.c274 mfdcr(DCRN_PLB0_BEAR), mfdcr(DCRN_PLB0_ACR), in show_regs()
275 mfdcr(DCRN_PLB0_BESR)); in show_regs()
279 mfdcr(DCRN_POB0_BEAR), mfdcr(DCRN_POB0_BESR0), in show_regs()
280 mfdcr(DCRN_POB0_BESR1)); in show_regs()
Dhead_4xx.S211 mfdcr r4,DCRN_POB0_BEAR
212 mfdcr r4,DCRN_POB0_BESR0
213 mfdcr r4,DCRN_POB0_BESR1
217 mfdcr r4,DCRN_PLB0_ACR
218 mfdcr r4,DCRN_PLB0_BEAR
219 mfdcr r4,DCRN_PLB0_BESR
Docp.c488 mtdcr(DCRN_CPMFR, mfdcr(DCRN_CPMFR) | bits); in ppc4xx_cpm_fr()
490 mtdcr(DCRN_CPMFR, mfdcr(DCRN_CPMFR) & ~bits); in ppc4xx_cpm_fr()
Dppc405_pci.c123 if ((mfdcr(DCRN_CHPSR) & PSR_PCI_ARBIT_EN) == 0) { in ppc4xx_find_bridges()
Dppc4xx_setup.c244 mtdcr(DCRN_CHCR1, mfdcr(DCRN_CHCR1) & ~CHR1_CETE); in ppc4xx_calibrate_decr()
/linux-2.4.37.9/include/asm-ppc/
Docp.h171 mtdcr(DCRN_CPMFR, mfdcr(DCRN_CPMFR) | odev->def->pm); in ocp_force_power_off()
177 mtdcr(DCRN_CPMFR, mfdcr(DCRN_CPMFR) & ~odev->def->pm); in ocp_force_power_on()
Dibm4xx.h47 mfdcr(base##_CFGDATA); \
Dibm44x.h107 mfdcr(DCRN_CPR_CONFIG_DATA);})
148 mfdcr(DCRN_SDR_CONFIG_DATA);})
Dprocessor.h737 #define mfdcr(rn) ({unsigned int rval; \ macro
/linux-2.4.37.9/arch/ppc/boot/simple/
Dmisc-44x.c29 while (mfdcr(DCRN_MALCR(DCRN_MAL_BASE)) & MALCR_MMSR) {}; /* wait for reset */ in load_kernel()
Dembed_config.c671 while (mfdcr(DCRN_MALCR(DCRN_MAL_BASE)) & MALCR_MMSR) {}; /* wait for the reset */ in embed_config()
/linux-2.4.37.9/drivers/net/ibm_emac/
Dibm_ocp_debug.c177 plb_error = mfdcr(DCRN_PLB0_BESR); in emac_serr_dump_0()
181 plb_addr = mfdcr(DCRN_PLB0_BEAR); in emac_serr_dump_0()
Dibm_ocp_mal.h81 x = mfdcr(dcrn(base)); \
/linux-2.4.37.9/arch/ppc/platforms/
Dcpci405.c78 uart_div = ((mfdcr(DCRN_CHCR_BASE) & CHR0_UDIV) >> 1) + 1; in cpci405_early_serial_map()
Docotea.c374 bank_config = mfdcr(DCRN_SDRAM0_CFGDATA); in ocotea_find_end_of_memory()
Debony.c451 bank_config = mfdcr(DCRN_SDRAM0_CFGDATA); in ebony_find_end_of_memory()