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Searched refs:SMP_CACHE_BYTES (Results 1 – 25 of 50) sorted by relevance

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/linux-2.4.37.9/include/linux/
Dcache.h11 #ifndef SMP_CACHE_BYTES
12 #define SMP_CACHE_BYTES L1_CACHE_BYTES macro
16 #define ____cacheline_aligned __attribute__((__aligned__(SMP_CACHE_BYTES)))
32 __attribute__((__aligned__(SMP_CACHE_BYTES), \
Dbootmem.h39 __alloc_bootmem((x), SMP_CACHE_BYTES, __pa(MAX_DMA_ADDRESS))
41 __alloc_bootmem((x), SMP_CACHE_BYTES, 0)
54 __alloc_bootmem_node((pgdat), (x), SMP_CACHE_BYTES, __pa(MAX_DMA_ADDRESS))
Dbrlock.h44 …(((sizeof(brlock_read_lock_t)*__BR_END + SMP_CACHE_BYTES-1) & ~(SMP_CACHE_BYTES-1)) / sizeof(brloc…
50 } __attribute__ ((__aligned__(SMP_CACHE_BYTES)));
Dspinlock.h167 char fill_up[(SMP_CACHE_BYTES)];
168 } spinlock_cacheline_t __attribute__ ((aligned(SMP_CACHE_BYTES)));
Dskbuff.h37 #define SKB_DATA_ALIGN(X) (((X) + (SMP_CACHE_BYTES-1)) & ~(SMP_CACHE_BYTES-1))
38 …ORDER(X,ORDER) (((PAGE_SIZE<<(ORDER)) - (X) - sizeof(struct skb_shared_info))&~(SMP_CACHE_BYTES-1))
Dinterrupt.h135 } __attribute__ ((__aligned__(SMP_CACHE_BYTES)));
/linux-2.4.37.9/include/asm-sparc64/
Dcache.h13 #define SMP_CACHE_BYTES (1 << SMP_CACHE_BYTES_SHIFT) /* L2 cache line size. */ macro
16 #define __cacheline_aligned __attribute__((__aligned__(SMP_CACHE_BYTES)))
19 __attribute__((__aligned__(SMP_CACHE_BYTES), \
/linux-2.4.37.9/include/asm-sparc/
Dcache.h16 #define SMP_CACHE_BYTES 32 macro
19 #define __cacheline_aligned __attribute__((__aligned__(SMP_CACHE_BYTES)))
22 __attribute__((__aligned__(SMP_CACHE_BYTES), \
/linux-2.4.37.9/include/asm-ia64/
Dcache.h17 # define SMP_CACHE_BYTES L1_CACHE_BYTES macro
25 # define SMP_CACHE_BYTES (1 << 3) macro
/linux-2.4.37.9/include/asm-ia64/sn/
Dpda.h66 #define CACHE_ALIGN(x) (((x) + SMP_CACHE_BYTES-1) & ~(SMP_CACHE_BYTES-1))
/linux-2.4.37.9/include/asm-mips/
Dcache.h21 #define SMP_CACHE_BYTES L1_CACHE_BYTES macro
Dprocessor.h72 } __attribute__((aligned(SMP_CACHE_BYTES)));
/linux-2.4.37.9/include/asm-mips64/
Dcache.h21 #define SMP_CACHE_BYTES L1_CACHE_BYTES macro
/linux-2.4.37.9/include/asm-alpha/
Dcache.h22 #define SMP_CACHE_BYTES L1_CACHE_BYTES macro
/linux-2.4.37.9/include/asm-arm/
Dcache.h9 #define SMP_CACHE_BYTES L1_CACHE_BYTES macro
/linux-2.4.37.9/include/asm-parisc/
Dcache.h27 #define SMP_CACHE_BYTES L1_CACHE_BYTES macro
/linux-2.4.37.9/arch/sparc64/kernel/
Dsetup.c497 if ((i == SMP_CACHE_BYTES) || (i == (2 * SMP_CACHE_BYTES))) { in setup_arch()
499 irqsz_patchme[0] |= ((i == SMP_CACHE_BYTES) ? SMP_CACHE_BYTES_SHIFT : \ in setup_arch()
Dsmp.c46 volatile int __cpu_number_map[NR_CPUS] __attribute__ ((aligned (SMP_CACHE_BYTES)));
47 volatile int __cpu_logical_map[NR_CPUS] __attribute__ ((aligned (SMP_CACHE_BYTES)));
195 #define SLAVE (SMP_CACHE_BYTES/sizeof(unsigned long))
/linux-2.4.37.9/include/asm-ppc/
Dcache.h27 #define SMP_CACHE_BYTES L1_CACHE_BYTES macro
/linux-2.4.37.9/arch/mips64/mm/
Dpg-sb1.c164 static dmadscr_t page_descr[NR_CPUS] __attribute__((aligned(SMP_CACHE_BYTES)));
/linux-2.4.37.9/arch/mips/mm/
Dpg-sb1.c164 static dmadscr_t page_descr[NR_CPUS] __attribute__((aligned(SMP_CACHE_BYTES)));
/linux-2.4.37.9/arch/sparc/mm/
Dinit.c100 ctx_list_pool = __alloc_bootmem(numctx * sizeof(struct ctx_list), SMP_CACHE_BYTES, 0UL); in sparc_context_init()
426 __alloc_bootmem(i << 2, SMP_CACHE_BYTES, 0UL); in mem_init()
/linux-2.4.37.9/drivers/net/
Dsb1250-mac.c149 #define NUMCACHEBLKS(x) (((x)+SMP_CACHE_BYTES-1)/SMP_CACHE_BYTES)
942 sb_new = dev_alloc_skb(ENET_PACKET_SIZE + SMP_CACHE_BYTES * 2 + ETHER_ALIGN); in sbdma_add_rcvbuffer()
949 sbdma_align_skb(sb_new, SMP_CACHE_BYTES, ETHER_ALIGN); in sbdma_add_rcvbuffer()
1058 ncb = NUMCACHEBLKS(length+(phys & (SMP_CACHE_BYTES - 1))); in sbdma_add_txbuffer()
2390 sc->sbm_buffersize = ENET_PACKET_SIZE + SMP_CACHE_BYTES * 2 + ETHER_ALIGN; in sbmac_init()
Dacenic.h660 __attribute__ ((aligned (SMP_CACHE_BYTES)));
699 __attribute__ ((aligned (SMP_CACHE_BYTES)));;
/linux-2.4.37.9/arch/ia64/
Dvmlinux.lds.S142 . = ALIGN(SMP_CACHE_BYTES);

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