Home
last modified time | relevance | path

Searched refs:NCR5380_read (Results 1 – 22 of 22) sorted by relevance

/linux-2.4.37.9/drivers/scsi/
Dmac_NCR5380.c583 data = NCR5380_read(CURRENT_SCSI_DATA_REG); in NCR5380_print()
584 status = NCR5380_read(STATUS_REG); in NCR5380_print()
585 mr = NCR5380_read(MODE_REG); in NCR5380_print()
586 icr = NCR5380_read(INITIATOR_COMMAND_REG); in NCR5380_print()
587 basr = NCR5380_read(BUS_AND_STATUS_REG); in NCR5380_print()
629 status = NCR5380_read(STATUS_REG); in NCR5380_print_phase()
1225 if ((((NCR5380_read(BUS_AND_STATUS_REG)) & in NCR5380_dma_complete()
1228 saved_data = NCR5380_read(INPUT_DATA_REG); in NCR5380_dma_complete()
1236 HOSTNO, NCR5380_read(BUS_AND_STATUS_REG), in NCR5380_dma_complete()
1237 NCR5380_read(STATUS_REG)); in NCR5380_dma_complete()
[all …]
DNCR5380.c410 data = NCR5380_read(CURRENT_SCSI_DATA_REG); in NCR5380_print()
411 status = NCR5380_read(STATUS_REG); in NCR5380_print()
412 mr = NCR5380_read(MODE_REG); in NCR5380_print()
413 icr = NCR5380_read(INITIATOR_COMMAND_REG); in NCR5380_print()
414 basr = NCR5380_read(BUS_AND_STATUS_REG); in NCR5380_print()
464 status = NCR5380_read(STATUS_REG); in NCR5380_print_phase()
1030 for (pass = 1; (NCR5380_read(STATUS_REG) & SR_BSY) && pass <= 6; ++pass) { in NCR5380_init()
1037 while (time_before(jiffies, timeout) && (NCR5380_read(STATUS_REG) & SR_BSY)); in NCR5380_init()
1306 basr = NCR5380_read(BUS_AND_STATUS_REG); in NCR5380_intr()
1310 if ((NCR5380_read(STATUS_REG) & (SR_SEL | SR_IO)) == (SR_SEL | SR_IO)) { in NCR5380_intr()
[all …]
Dsun3_NCR5380.c568 data = NCR5380_read(CURRENT_SCSI_DATA_REG); in NCR5380_print()
569 status = NCR5380_read(STATUS_REG); in NCR5380_print()
570 mr = NCR5380_read(MODE_REG); in NCR5380_print()
571 icr = NCR5380_read(INITIATOR_COMMAND_REG); in NCR5380_print()
572 basr = NCR5380_read(BUS_AND_STATUS_REG); in NCR5380_print()
614 status = NCR5380_read(STATUS_REG); in NCR5380_print_phase()
1208 HOSTNO, NCR5380_read(BUS_AND_STATUS_REG), in NCR5380_dma_complete()
1209 NCR5380_read(STATUS_REG)); in NCR5380_dma_complete()
1219 if((NCR5380_read(BUS_AND_STATUS_REG) & (BASR_PHASE_MATCH | in NCR5380_dma_complete()
1222 printk("scsi%d: BASR %02x\n", HOSTNO, NCR5380_read(BUS_AND_STATUS_REG)); in NCR5380_dma_complete()
[all …]
Datari_NCR5380.c560 data = NCR5380_read(CURRENT_SCSI_DATA_REG); in NCR5380_print()
561 status = NCR5380_read(STATUS_REG); in NCR5380_print()
562 mr = NCR5380_read(MODE_REG); in NCR5380_print()
563 icr = NCR5380_read(INITIATOR_COMMAND_REG); in NCR5380_print()
564 basr = NCR5380_read(BUS_AND_STATUS_REG); in NCR5380_print()
606 status = NCR5380_read(STATUS_REG); in NCR5380_print_phase()
1221 if ((((NCR5380_read(BUS_AND_STATUS_REG)) & in NCR5380_dma_complete()
1224 saved_data = NCR5380_read(INPUT_DATA_REG); in NCR5380_dma_complete()
1232 HOSTNO, NCR5380_read(BUS_AND_STATUS_REG), in NCR5380_dma_complete()
1233 NCR5380_read(STATUS_REG)); in NCR5380_dma_complete()
[all …]
Dg_NCR5380.c550 if ((bl = NCR5380_read(C400_BLOCK_COUNTER_REG)) == 0) { in NCR5380_pread()
553 if (NCR5380_read(C400_CONTROL_STATUS_REG) & CSR_GATED_53C80_IRQ) { in NCR5380_pread()
557 while (NCR5380_read(C400_CONTROL_STATUS_REG) & CSR_HOST_BUF_NOT_RDY); in NCR5380_pread()
563 dst[start + i] = NCR5380_read(C400_HOST_BUFFER); in NCR5380_pread()
574 while (NCR5380_read(C400_CONTROL_STATUS_REG) & CSR_HOST_BUF_NOT_RDY) in NCR5380_pread()
583 dst[start + i] = NCR5380_read(C400_HOST_BUFFER); in NCR5380_pread()
593 if (!(NCR5380_read(C400_CONTROL_STATUS_REG) & CSR_GATED_53C80_IRQ)) in NCR5380_pread()
601 while (NCR5380_read(C400_CONTROL_STATUS_REG) & CSR_53C80_REG) in NCR5380_pread()
604 if (!(NCR5380_read(BUS_AND_STATUS_REG) & BASR_END_DMA_TRANSFER)) in NCR5380_pread()
608 NCR5380_read(RESET_PARITY_INTERRUPT_REG); in NCR5380_pread()
[all …]
Dmac_scsi.c357 PHASE_SR_TO_TCR( NCR5380_read(STATUS_REG) )); in mac_scsi_reset_boot()
365 NCR5380_read( RESET_PARITY_INTERRUPT_REG ); in mac_scsi_reset_boot()
465 while (!(NCR5380_read(BUS_AND_STATUS_REG) & BASR_DRQ) in macscsi_pread()
466 && !(NCR5380_read(STATUS_REG) & SR_REQ)) in macscsi_pread()
468 if (!(NCR5380_read(BUS_AND_STATUS_REG) & BASR_DRQ) in macscsi_pread()
469 && (NCR5380_read(BUS_AND_STATUS_REG) & BASR_PHASE_MATCH)) { in macscsi_pread()
557 while (!(NCR5380_read(BUS_AND_STATUS_REG) & BASR_DRQ) in macscsi_pwrite()
558 && (!(NCR5380_read(STATUS_REG) & SR_REQ) in macscsi_pwrite()
559 || (NCR5380_read(BUS_AND_STATUS_REG) & BASR_PHASE_MATCH))) in macscsi_pwrite()
561 if (!(NCR5380_read(BUS_AND_STATUS_REG) & BASR_DRQ)) { in macscsi_pwrite()
Ddtc.c337 NCR5380_read(RESET_PARITY_INTERRUPT_REG); in NCR5380_pread()
347 while (NCR5380_read(DTC_CONTROL_REG) & CSR_HOST_BUF_NOT_RDY) in NCR5380_pread()
358 while (!(NCR5380_read(DTC_CONTROL_REG) & D_CR_ACCESS)) in NCR5380_pread()
362 NCR5380_read(RESET_PARITY_INTERRUPT_REG); in NCR5380_pread()
384 NCR5380_read(RESET_PARITY_INTERRUPT_REG); in NCR5380_pwrite()
395 while (NCR5380_read(DTC_CONTROL_REG) & CSR_HOST_BUF_NOT_RDY) in NCR5380_pwrite()
403 while (!(NCR5380_read(DTC_CONTROL_REG) & D_CR_ACCESS)) in NCR5380_pwrite()
407 while (!(NCR5380_read(TARGET_COMMAND_REG) & TCR_LAST_BYTE_SENT)) in NCR5380_pwrite()
Dt128.h147 #define NCR5380_read(reg) isa_readb(T128_address(reg)) macro
150 #define NCR5380_read(reg) \ macro
Ddtc.h94 #define NCR5380_read(reg) (isa_readb(DTC_address(reg))) macro
97 #define NCR5380_read(reg) (isa_readb(DTC_address(reg))) macro
Dpas16.h170 #define NCR5380_read(reg) ( inb(PAS16_io_port(reg)) ) macro
173 #define NCR5380_read(reg) \ macro
Dg_NCR5380.h104 #define NCR5380_read(reg) (inb(NCR5380_map_name + (reg))) macro
120 #define NCR5380_read(reg) isa_readb(NCR5380_map_name + NCR53C400_mem_base + (reg)) macro
Dsun3_scsi.c341 PHASE_SR_TO_TCR( NCR5380_read(STATUS_REG) )); in sun3_scsi_reset_boot()
351 NCR5380_read( RESET_PARITY_INTERRUPT_REG ); in sun3_scsi_reset_boot()
564 if(count && (NCR5380_read(BUS_AND_STATUS_REG) & in sun3scsi_dma_finish()
567 printk("basr now %02x\n", NCR5380_read(BUS_AND_STATUS_REG)); in sun3scsi_dma_finish()
Dpas16.c227 NCR5380_read(RESET_PARITY_INTERRUPT_REG); in init_board()
297 if (NCR5380_read(MODE_REG) != 0x20) /* Write to a reg. */ in pas16_hw_detect()
300 if (NCR5380_read(MODE_REG) != 0x00) in pas16_hw_detect()
Ddmx3191d.h51 #define NCR5380_read(reg) inb(port + reg) macro
Dmac_scsi.h96 #define NCR5380_read(reg) macscsi_read(_instance, reg) macro
Dsun3_scsi_vme.c317 PHASE_SR_TO_TCR( NCR5380_read(STATUS_REG) )); in sun3_scsi_reset_boot()
327 NCR5380_read( RESET_PARITY_INTERRUPT_REG ); in sun3_scsi_reset_boot()
Datari_scsi.c881 PHASE_SR_TO_TCR( NCR5380_read(STATUS_REG) )); in atari_scsi_reset_boot()
889 NCR5380_read( RESET_PARITY_INTERRUPT_REG ); in atari_scsi_reset_boot()
Datari_scsi.h70 #define NCR5380_read(reg) atari_scsi_reg_read( reg ) macro
Dsun3_scsi.h123 #define NCR5380_read(reg) sun3scsi_read(reg) macro
/linux-2.4.37.9/drivers/acorn/scsi/
Doak.c66 #define NCR5380_read(reg) oakscsi_read(_instance, reg) macro
Decoscsi.c247 #define NCR5380_read(reg) ecoscsi_read(_instance, reg) macro
Dcumana_1.c84 #define NCR5380_read(reg) cumanascsi_read(_instance, reg) macro