550 		if ((bl = NCR5380_read(C400_BLOCK_COUNTER_REG)) == 0) {  in NCR5380_pread()
553 		if (NCR5380_read(C400_CONTROL_STATUS_REG) & CSR_GATED_53C80_IRQ) {  in NCR5380_pread()
557 		while (NCR5380_read(C400_CONTROL_STATUS_REG) & CSR_HOST_BUF_NOT_RDY);  in NCR5380_pread()
563 				dst[start + i] = NCR5380_read(C400_HOST_BUFFER);  in NCR5380_pread()
574 		while (NCR5380_read(C400_CONTROL_STATUS_REG) & CSR_HOST_BUF_NOT_RDY)  in NCR5380_pread()
583 				dst[start + i] = NCR5380_read(C400_HOST_BUFFER);  in NCR5380_pread()
593 	if (!(NCR5380_read(C400_CONTROL_STATUS_REG) & CSR_GATED_53C80_IRQ))  in NCR5380_pread()
601 	while (NCR5380_read(C400_CONTROL_STATUS_REG) & CSR_53C80_REG)  in NCR5380_pread()
604 	if (!(NCR5380_read(BUS_AND_STATUS_REG) & BASR_END_DMA_TRANSFER))  in NCR5380_pread()
608 	NCR5380_read(RESET_PARITY_INTERRUPT_REG);  in NCR5380_pread()
635 		if (NCR5380_read(C400_CONTROL_STATUS_REG) & CSR_GATED_53C80_IRQ) {  in NCR5380_pwrite()
640 		if ((bl = NCR5380_read(C400_BLOCK_COUNTER_REG)) == 0) {  in NCR5380_pwrite()
643 		while (NCR5380_read(C400_CONTROL_STATUS_REG) & CSR_HOST_BUF_NOT_RDY)  in NCR5380_pwrite()
658 		while (NCR5380_read(C400_CONTROL_STATUS_REG) & CSR_HOST_BUF_NOT_RDY)  in NCR5380_pwrite()
676 	THEY NEVER DO ! while (NCR5380_read(C400_CONTROL_STATUS_REG) & CSR_53C80_REG);  in NCR5380_pwrite()
684 	while (!(i = NCR5380_read(C400_CONTROL_STATUS_REG) & CSR_GATED_53C80_IRQ))  in NCR5380_pwrite()
692 		if (!((i = NCR5380_read(BUS_AND_STATUS_REG)) & BASR_END_DMA_TRANSFER))  in NCR5380_pwrite()
698 	if (!(NCR5380_read(BUS_AND_STATUS_REG) & BASR_END_DMA_TRANSFER)) {  in NCR5380_pwrite()
702 	while (!(NCR5380_read(TARGET_COMMAND_REG) & TCR_LAST_BYTE_SENT))  in NCR5380_pwrite()
850 	status = NCR5380_read(STATUS_REG);  in generic_NCR5380_proc_info()