Searched refs:Memory (Results 1 – 25 of 212) sorted by relevance
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46 Memory, enumerator77 Memory, enumerator
37 Memory, enumerator68 Memory, enumerator
5 comment 'Memory Technology Devices (MTD)'7 tristate 'Memory Technology Device (MTD) support' CONFIG_MTD
5 Memory Addresses:49 Memory Size:
458 (I/O and Memory | 1 1 * 0 0 0 0 * 1 1 0 1 |594 4-6: Memory Base Address Select637 Setting the Base Memory (RAM) buffer Address1033 SW2: DIP-Switches for Memory Base and I/O Base addresses1229 Memory Switch 0 (MS0) didn't seem to work properly when set to OFF1235 43210 Memory address1316 S1 1-5: Base Memory Address Select1394 Setting the Base Memory (RAM) buffer Address1400 Switches 1-5 of switch block SW1 select the Memory Base address.1533 7-10: Base Memory Address Select[all …]
166 Operation Mode: Memory Mode169 Memory Base Address: D0000493 * Shared Memory Test494 The Shared Memory test insures the CS8900/20 can be accessed in memory 621 Memory Address Device 13 Math Coprocessor655 * IO Base, Memory Base, IO or memory mode enabled, IRQ, DMA channel
57 Memory addresses:
104 32MB/64MB ECC SDRAM Memory110 32MB/64MB ECC SDRAM Memory116 32MB/64MB ECC SDRAM Memory121 16MB/32MB/64MB ECC SDRAM Memory126 Built in 16M ECC SDRAM Memory133 16MB/32MB/64MB Parity SDRAM Memory with Battery Backup139 4MB/8MB/16MB/32MB/64MB/128MB ECC EDO Memory145 4MB/8MB/16MB/32MB/64MB/128MB ECC EDO Memory151 4MB Parity EDO Memory155 4MB/8MB/16MB/32MB/64MB/128MB ECC EDO Memory[all …]
162 If you want to use the PCI Memory-Write-Invalidate transaction,166 may support Memory-Write-Invalidate.186 Memory and port addresses and interrupt numbers should NOT be read from the214 pci_set_mwi() Enable Memory-Write-Invalidate transactions.215 pci_clear_mwi() Disable Memory-Write-Invalidate transactions.
61 membase - Memory start address of that card.62 memsize - Memory size of that card, in kilobytes. If given, this value130 Memory base addr: eg. 80000 - Memory address where the board's memory starts.
1 MTRR (Memory Type Range Register) control7 the Memory Type Range Registers (MTRRs) may be used to control
64 # Memory options66 comment 'Memory options'68 int 'Memory size (in MB)' CONFIG_MEMORY_SIZE_IN_MB 64
41 dep_tristate 'Micro Memory MM5415 Battery Backed RAM support (EXPERIMENTAL)' CONFIG_BLK_DEV_UMEM $C…
37 mov r0, r4 @ get the Memory layout from firmware
63 bool 'MTRR (Memory Type Range Register) support' CONFIG_MTRR250 # bool ' Memory mapped I/O debugging' CONFIG_DEBUG_IOVIRT
175 unsigned short Memory:1; /* RW: Reset memory interface */ member
225 choice 'High Memory Support' \243 bool 'MTRR (Memory Type Range Register) support' CONFIG_MTRR496 bool ' Memory mapped I/O debugging' CONFIG_DEBUG_IOVIRT
37 Memory interfaces:86 Memory: 13872k/16384k available (587k kernel code, 2512k reserved, 44k data, 24k init)
15 4.72.01 - I/O Mapped Memory release ( so "insmod ips" does not Fail )
49 4.72.01 - I/O Mapped Memory release ( so "insmod ips" does not Fail )
71 Memory Sel Bus Use192 Memory Sel Use
59 # Memory Technology Devices (MTD)
742 00fc CPC710 Dual Bridge and Memory Controller (PCI-64)743 0105 CPC710 Dual Bridge and Memory Controller (PCI-32)1242 0645 SiS645 Host & Memory & AGP Controller1243 0646 SiS645DX Host & Memory & AGP Controller1568 808a Memory Stick Controller2475 5471 M5471 Memory Stick Controller2722 01ab nForce 420 Memory Controller (DDR)2723 01ac nForce 220/420 Memory Controller2724 01ad nForce 220/420 Memory Controller3434 5579 VMIPCI-5579 (Reflective Memory Card)[all …]
99 Memory at .....
91 # Memory Technology Devices (MTD)