Searched refs:DMA_INT_ENAB (Results 1 – 8 of 8) sorted by relevance
115 #define DMA_INT_ENAB 0x00000010 /* Turn on interrupts */ macro174 #define DMA_INTSOFF(regs) ((((regs)->cond_reg) &= (~DMA_INT_ENAB)))175 #define DMA_INTSON(regs) ((((regs)->cond_reg) |= (DMA_INT_ENAB)))179 ((((regs)->cond_reg |= (DMA_ST_WRITE|DMA_ENABLE|DMA_INT_ENAB))))181 ((((regs)->cond_reg |= ((DMA_ENABLE|DMA_INT_ENAB)&(~DMA_ST_WRITE)))))
103 #define DMA_INT_ENAB 0x00000010 /* Turn on interrupts */ macro166 tmp &= ~DMA_INT_ENAB; \171 tmp |= DMA_INT_ENAB; \183 tmp |= (DMA_ST_WRITE|DMA_ENABLE|DMA_INT_ENAB); \188 tmp |= (DMA_ENABLE|DMA_INT_ENAB); \
150 #define DMA_INT_ENAB 0x00000010 /* Turn on interrupts */ macro203 #define DMA_INTSOFF(regs) ((((regs)->cond_reg) &= (~DMA_INT_ENAB)))204 #define DMA_INTSON(regs) ((((regs)->cond_reg) |= (DMA_INT_ENAB)))208 ((((regs)->cond_reg |= (DMA_ST_WRITE|DMA_ENABLE|DMA_INT_ENAB))))210 ((((regs)->cond_reg |= ((DMA_ENABLE|DMA_INT_ENAB)&(~DMA_ST_WRITE)))))
21 #define DMA_PORTS_P (dregs->cond_reg & DMA_INT_ENAB)
300 & DMA_INT_ENAB); in dma_ports_p()
393 sbus_writel(sbus_readl((__dregs)+DMA_CSR)&~(DMA_INT_ENAB), (__dregs)+DMA_CSR)395 sbus_writel(sbus_readl((__dregs)+DMA_CSR)|DMA_INT_ENAB, (__dregs)+DMA_CSR)499 esp->prev_hme_dmacsr = (DMA_PARITY_OFF|DMA_2CLKS|DMA_SCSI_DISAB|DMA_INT_ENAB); in esp_reset_dma()1952 don = (sbus_readl(esp->dregs + DMA_CSR) & DMA_INT_ENAB); in esp_abort()2301 DMA_SCSI_DISAB | DMA_INT_ENAB)) & in dma_invalidate()
58 tmp &= ~DMA_INT_ENAB; in parport_sunbpp_disable_irq()68 tmp |= DMA_INT_ENAB; in parport_sunbpp_enable_irq()
499 csr |= DMA_INT_ENAB; in init_restart_lance()