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Searched refs:CSR5 (Results 1 – 9 of 9) sorted by relevance

/linux-2.4.37.9/drivers/net/tulip/
Dinterrupt.c92 if(((inl(dev->base_addr + CSR5)>>17)&0x07) == 4) { in tulip_refill_rx()
345 csr5 = inl(ioaddr + CSR5); in tulip_interrupt()
357 outl(csr5 & 0x0001ffff, ioaddr + CSR5); in tulip_interrupt()
361 dev->name, csr5, inl(dev->base_addr + CSR5)); in tulip_interrupt()
506 outl(0x0800f7ba, ioaddr + CSR5); in tulip_interrupt()
528 outl(0x8001ffff, ioaddr + CSR5); in tulip_interrupt()
559 csr5 = inl(ioaddr + CSR5); in tulip_interrupt()
578 outl(TimerInt, ioaddr + CSR5); in tulip_interrupt()
591 dev->name, inl(ioaddr + CSR5)); in tulip_interrupt()
Dpnic.c64 if (inl(ioaddr + CSR5) & TPLnkFail) { in pnic_lnk_change()
78 } else if (inl(ioaddr + CSR5) & TPLnkPass) { in pnic_lnk_change()
115 int csr5 = inl(ioaddr + CSR5); in pnic_timer()
133 inl(ioaddr + CSR5), inl(ioaddr + 0xB8)); in pnic_timer()
Dtulip_core.c441 outl(inl(ioaddr+CSR5)| 0x00008010, ioaddr + CSR5); in tulip_up()
449 } else if (inl(ioaddr + CSR5) & TPLnkPass) in tulip_up()
487 outl(tulip_tbl[tp->chip_id].valid_intrs, ioaddr + CSR5); in tulip_up()
494 dev->name, inl(ioaddr + CSR0), inl(ioaddr + CSR5), in tulip_up()
574 dev->name, inl(ioaddr + CSR5), csr12, in tulip_tx_timeout()
592 dev->name, inl(ioaddr + CSR5), inl(ioaddr + CSR12), in tulip_tx_timeout()
611 dev->name, (int)inl(ioaddr + CSR5), (int)inl(ioaddr + CSR6), in tulip_tx_timeout()
616 dev->name, inl(ioaddr + CSR5), inl(ioaddr + CSR12)); in tulip_tx_timeout()
864 dev->name, inl (ioaddr + CSR5)); in tulip_close()
Dtulip.h109 CSR5 = 0x28, enumerator
526 while (--i && (inl(ioaddr + CSR5) & (CSR5_TS|CSR5_RS))) in tulip_stop_rxtx()
Dtimer.c32 dev->name, medianame[dev->if_port], inl(ioaddr + CSR5), in tulip_timer()
D21142.c187 dev->name, inl(ioaddr + CSR5)); in t21142_lnk_change()
/linux-2.4.37.9/drivers/net/pcmcia/
Dxircom_cb.c57 #define CSR5 0x28 macro
337 status = inl(card->io_port+CSR5); in xircom_interrupt()
365 outl(status,card->io_port+CSR5); in xircom_interrupt()
673 val = inl(card->io_port + CSR5); /* Status register */ in link_status_changed()
683 outl(val, card->io_port + CSR5); in link_status_changed()
699 val = inl(card->io_port + CSR5); /* Status register */ in transmit_active()
720 val = inl(card->io_port + CSR5); /* Status register */ in receive_active()
Dxircom_tulip_cb.c217 CSR0=0, CSR1=0x08, CSR2=0x10, CSR3=0x18, CSR4=0x20, CSR5=0x28, enumerator
375 csr5 = inl(ioaddr + CSR5); in outl_CSR6()
777 outl(xircom_tbl[tp->chip_id].valid_intrs, ioaddr + CSR5); in xircom_up()
790 dev->name, inl(ioaddr + CSR0), inl(ioaddr + CSR5), in xircom_up()
1075 csr5 = inl(ioaddr + CSR5); in xircom_interrupt()
1077 outl(csr5 & 0x0001ffff, ioaddr + CSR5); in xircom_interrupt()
1081 dev->name, csr5, inl(dev->base_addr + CSR5)); in xircom_interrupt()
1179 outl(0x0800f7ba, ioaddr + CSR5); in xircom_interrupt()
1186 outl(0x8001ffff, ioaddr + CSR5); in xircom_interrupt()
1193 dev->name, inl(ioaddr + CSR5)); in xircom_interrupt()
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/linux-2.4.37.9/Documentation/networking/
DNAPI_HOWTO.txt647 "pending work" is indicated by the status bit(CSR5 in tulip).
649 the CSR5 will continue to be turned on with new packet arrivals even if
668 CSR5 := read
669 if (CSR5 is not set) {
678 CSR5 bit of interest is only the rx status.
683 we are counting that CSR5 will be set in that small window of opportunity