Lines Matching refs:CSR5
217 CSR0=0, CSR1=0x08, CSR2=0x10, CSR3=0x18, CSR4=0x20, CSR5=0x28, enumerator
375 csr5 = inl(ioaddr + CSR5); in outl_CSR6()
777 outl(xircom_tbl[tp->chip_id].valid_intrs, ioaddr + CSR5); in xircom_up()
790 dev->name, inl(ioaddr + CSR0), inl(ioaddr + CSR5), in xircom_up()
1075 csr5 = inl(ioaddr + CSR5); in xircom_interrupt()
1077 outl(csr5 & 0x0001ffff, ioaddr + CSR5); in xircom_interrupt()
1081 dev->name, csr5, inl(dev->base_addr + CSR5)); in xircom_interrupt()
1179 outl(0x0800f7ba, ioaddr + CSR5); in xircom_interrupt()
1186 outl(0x8001ffff, ioaddr + CSR5); in xircom_interrupt()
1193 dev->name, inl(ioaddr + CSR5)); in xircom_interrupt()
1325 dev->name, inl(ioaddr + CSR5)); in xircom_close()