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Searched refs:BIT3 (Results 1 – 9 of 9) sorted by relevance

/linux-2.4.37.9/drivers/scsi/
Dtmscsim.h285 #define BIT3 0x00000008 macro
294 #define UNIT_RETRY BIT3
306 #define SRB_MSGIN BIT3
323 #define UNDER_RUN BIT3
385 #define WIDE_NEGO_DONE BIT3 /* Not used ;-) */
491 #define SEND_START_ BIT3
498 #define ACTIVE_NEGATION BIT3
548 #define GROUP_CODE_VALID BIT3
557 #define SUCCESSFUL_OP BIT3
563 #define SYNC_OFFSET_FLAG BIT3
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/linux-2.4.37.9/drivers/net/
Dmv64340_eth.h16 #define BIT3 0x00000008 macro
243 #define ETH_RX_FLOW_CTRL_ENBALED BIT3
265 #define ETH_DEFAULT_RX_QUEUE_4 BIT3
266 #define ETH_DEFAULT_RX_QUEUE_5 (BIT3 | BIT1)
267 #define ETH_DEFAULT_RX_QUEUE_6 (BIT3 | BIT2)
268 #define ETH_DEFAULT_RX_QUEUE_7 (BIT3 | BIT2 | BIT1)
326 #define ETH_QUEUE_3_ENABLE BIT3
347 #define ETH_RX_BURST_SIZE_16_64BIT BIT3
370 #define ETH_DISABLE_AUTO_NEG_FOR_FLOW_CTRL BIT3
/linux-2.4.37.9/include/asm-arm/arch-integrator/
Dbits.h29 #define BIT3 0x00000008 macro
/linux-2.4.37.9/include/asm-arm/arch-omaha/
Dbits.h29 #define BIT3 0x00000008 macro
Dplatform.h599 #define PLD_INT_STATUS_nWP BIT3 /* Flash write protect (r/w) */
627 #define PLD_CF_VS2 BIT3 /* Voltage Sense 2. r/o */
/linux-2.4.37.9/include/linux/
Dsynclink.h23 #define BIT3 0x0008 macro
/linux-2.4.37.9/drivers/char/pcmcia/
Dsynclink_cs.c342 #define PVR_AUTOCTS BIT3
915 #define CMD_TXFIFO BIT3 // release current tx FIFO
1432 if (gis & (BIT3 + BIT2)) in mgslpc_isr()
3598 val |= BIT3; in hdlc_mode()
3607 val |= BIT4 + BIT3; in hdlc_mode()
3738 set_reg_bits(info, CHA + PVR, BIT3); in hdlc_mode()
3740 clear_reg_bits(info, CHA + PVR, BIT3); in hdlc_mode()
3775 clear_reg_bits(info, CHA + MODE, BIT3); in rx_stop()
3792 set_reg_bits(info, CHA + MODE, BIT3); in rx_start()
4008 val |= BIT3; in async_mode()
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/linux-2.4.37.9/drivers/char/
Dsynclinkmp.c449 #define CCTS BIT3
465 #define OVRN BIT3
1692 RegValue |= BIT3; in set_break()
1694 RegValue &= ~BIT3; in set_break()
2556 if (status & BIT3 << shift) in synclinkmp_interrupt()
2565 if (dmastatus & BIT3 << shift) in synclinkmp_interrupt()
4433 case 6: RegValue |= BIT5 + BIT3; break; in async_mode()
4434 case 5: RegValue |= BIT5 + BIT4 + BIT3 + BIT2; break; in async_mode()
4609 RegValue |= BIT3; in hdlc_mode()
4771 if (!(status & BIT3)) in get_signals()
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Dsynclink.c527 #define TRANSMIT_STATUS BIT3
544 #define RXSTATUS_CRC_ERROR BIT3
545 #define RXSTATUS_FRAMING_ERROR BIT3
584 #define TXSTATUS_CRC_SENT BIT3
604 #define MISCSTATUS_RCC_UNDERRUN BIT3
630 #define SICR_RCC_UNDERFLOW BIT3
664 #define TXSTATUS_CRC_SENT BIT3
1518 usc_OutReg( info, RICR+LSBONLY, (u16)(usc_InReg(info, RICR+LSBONLY) & ~BIT3 )); in mgsl_isr_receive_data()
1688 if ( status & BIT3 ) { in mgsl_isr_receive_dma()
5413 usc_OutReg(info, SICR, (u16)(usc_InReg(info,SICR) | BIT3)); in usc_set_sdlc_mode()
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