1 /*
2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details.
5 *
6 * Copyright (C) 1999, 2000 Ralf Baechle (ralf@gnu.org)
7 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
8 */
9 #include <linux/init.h>
10 #include <linux/kernel.h>
11 #include <linux/pci.h>
12 #include <asm/sn/arch.h>
13 #include <asm/pci/bridge.h>
14 #include <asm/paccess.h>
15 #include <asm/sn/sn0/ip27.h>
16 #include <asm/sn/sn0/hub.h>
17
18 /*
19 * Max #PCI busses we can handle; ie, max #PCI bridges.
20 */
21 #define MAX_PCI_BUSSES 40
22
23 /*
24 * Max #PCI devices (like scsi controllers) we handle on a bus.
25 */
26 #define MAX_DEVICES_PER_PCIBUS 8
27
28 /*
29 * No locking needed until PCI initialization is done parallely.
30 */
31 int irqstore[MAX_PCI_BUSSES][MAX_DEVICES_PER_PCIBUS];
32 int lastirq = BASE_PCI_IRQ;
33
34 /*
35 * Translate from irq to software PCI bus number and PCI slot.
36 */
37 int irq_to_bus[MAX_PCI_BUSSES * MAX_DEVICES_PER_PCIBUS];
38 int irq_to_slot[MAX_PCI_BUSSES * MAX_DEVICES_PER_PCIBUS];
39
40 /*
41 * The Bridge ASIC supports both type 0 and type 1 access. Type 1 is
42 * not really documented, so right now I can't write code which uses it.
43 * Therefore we use type 0 accesses for now even though they won't work
44 * correcly for PCI-to-PCI bridges.
45 */
46 #define CF0_READ_PCI_CFG(dev,where,value,bm,mask) \
47 do { \
48 bridge_t *bridge; \
49 int slot = PCI_SLOT(dev->devfn); \
50 int fn = PCI_FUNC(dev->devfn); \
51 volatile u32 *addr; \
52 u32 cf, __bit; \
53 unsigned int bus_id = (unsigned) dev->bus->number; \
54 \
55 bridge = (bridge_t *) NODE_SWIN_BASE(bus_to_nid[bus_id], \
56 bus_to_wid[bus_id]); \
57 \
58 if (dev->vendor == PCI_VENDOR_ID_SGI \
59 && dev->device == PCI_DEVICE_ID_SGI_IOC3 \
60 && ((where >= 0x14 && where < 0x40) || (where >= 0x48))) { \
61 *value = 0; \
62 return PCIBIOS_SUCCESSFUL; \
63 } \
64 \
65 __bit = (((where) & (bm)) << 3); \
66 addr = &bridge->b_type0_cfg_dev[slot].f[fn].l[where >> 2]; \
67 if (get_dbe(cf, addr)) \
68 return PCIBIOS_DEVICE_NOT_FOUND; \
69 *value = (cf >> __bit) & (mask); \
70 return PCIBIOS_SUCCESSFUL; \
71 } while (0)
72
pci_conf0_read_config_byte(struct pci_dev * dev,int where,u8 * value)73 static int pci_conf0_read_config_byte(struct pci_dev *dev, int where,
74 u8 *value)
75 {
76 CF0_READ_PCI_CFG(dev,where,value,3,0xff);
77 }
78
pci_conf0_read_config_word(struct pci_dev * dev,int where,u16 * value)79 static int pci_conf0_read_config_word(struct pci_dev *dev, int where,
80 u16 *value)
81 {
82 CF0_READ_PCI_CFG(dev,where,value,2,0xffff);
83 }
84
pci_conf0_read_config_dword(struct pci_dev * dev,int where,u32 * value)85 static int pci_conf0_read_config_dword(struct pci_dev *dev, int where,
86 u32 *value)
87 {
88 CF0_READ_PCI_CFG(dev,where,value,0,0xffffffff);
89 }
90
91 #define CF0_WRITE_PCI_CFG(dev,where,value,bm,mask) \
92 do { \
93 bridge_t *bridge; \
94 int slot = PCI_SLOT(dev->devfn); \
95 int fn = PCI_FUNC(dev->devfn); \
96 volatile u32 *addr; \
97 u32 cf, __bit; \
98 unsigned int bus_id = (unsigned) dev->bus->number; \
99 \
100 bridge = (bridge_t *) NODE_SWIN_BASE(bus_to_nid[bus_id], \
101 bus_to_wid[bus_id]); \
102 \
103 if (dev->vendor == PCI_VENDOR_ID_SGI \
104 && dev->device == PCI_DEVICE_ID_SGI_IOC3 \
105 && ((where >= 0x14 && where < 0x40) || (where >= 0x48))) \
106 return PCIBIOS_SUCCESSFUL; \
107 \
108 __bit = (((where) & (bm)) << 3); \
109 addr = &bridge->b_type0_cfg_dev[slot].f[fn].l[where >> 2]; \
110 if (get_dbe(cf, addr)) \
111 return PCIBIOS_DEVICE_NOT_FOUND; \
112 cf &= (~mask); \
113 cf |= (value); \
114 put_dbe(cf, addr); \
115 return PCIBIOS_SUCCESSFUL; \
116 } while (0)
117
pci_conf0_write_config_byte(struct pci_dev * dev,int where,u8 value)118 static int pci_conf0_write_config_byte(struct pci_dev *dev, int where,
119 u8 value)
120 {
121 CF0_WRITE_PCI_CFG(dev,where,value,3,0xff);
122 }
123
pci_conf0_write_config_word(struct pci_dev * dev,int where,u16 value)124 static int pci_conf0_write_config_word(struct pci_dev *dev, int where,
125 u16 value)
126 {
127 CF0_WRITE_PCI_CFG(dev,where,value,2,0xffff);
128 }
129
pci_conf0_write_config_dword(struct pci_dev * dev,int where,u32 value)130 static int pci_conf0_write_config_dword(struct pci_dev *dev, int where,
131 u32 value)
132 {
133 CF0_WRITE_PCI_CFG(dev,where,value,0,0xffffffff);
134 }
135
136
137 static struct pci_ops bridge_pci_ops = {
138 pci_conf0_read_config_byte,
139 pci_conf0_read_config_word,
140 pci_conf0_read_config_dword,
141 pci_conf0_write_config_byte,
142 pci_conf0_write_config_word,
143 pci_conf0_write_config_dword
144 };
145
pcibios_init(void)146 void __init pcibios_init(void)
147 {
148 struct pci_ops *ops = &bridge_pci_ops;
149 int i;
150
151 ioport_resource.end = ~0UL;
152 iomem_resource.end = ~0UL;
153
154 for (i=0; i<num_bridges; i++) {
155 printk("PCI: Probing PCI hardware on host bus %2d.\n", i);
156 pci_scan_bus(i, ops, NULL);
157 }
158 }
159
bridge_swizzle(u8 pin,u8 slot)160 static inline u8 bridge_swizzle(u8 pin, u8 slot)
161 {
162 return (((pin-1) + slot) % 4) + 1;
163 }
164
pci_swizzle(struct pci_dev * dev,u8 * pinp)165 static u8 __devinit pci_swizzle(struct pci_dev *dev, u8 *pinp)
166 {
167 u8 pin = *pinp;
168
169 while (dev->bus->self) { /* Move up the chain of bridges. */
170 pin = bridge_swizzle(pin, PCI_SLOT(dev->devfn));
171 dev = dev->bus->self;
172 }
173 *pinp = pin;
174
175 return PCI_SLOT(dev->devfn);
176 }
177
178 /*
179 * All observed requests have pin == 1. We could have a global here, that
180 * gets incremented and returned every time - unfortunately, pci_map_irq
181 * may be called on the same device over and over, and need to return the
182 * same value. On O2000, pin can be 0 or 1, and PCI slots can be [0..7].
183 *
184 * A given PCI device, in general, should be able to intr any of the cpus
185 * on any one of the hubs connected to its xbow.
186 */
pci_map_irq(struct pci_dev * dev,u8 slot,u8 pin)187 static int __devinit pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
188 {
189 if ((dev->bus->number >= MAX_PCI_BUSSES)
190 || (pin != 1)
191 || (slot >= MAX_DEVICES_PER_PCIBUS))
192 panic("Increase supported PCI busses %d,%d,%d",
193 dev->bus->number, slot, pin);
194
195 /*
196 * Already assigned? Then return previously assigned value ...
197 */
198 if (irqstore[dev->bus->number][slot])
199 return irqstore[dev->bus->number][slot];
200
201 irq_to_bus[lastirq] = dev->bus->number;
202 irq_to_slot[lastirq] = slot;
203 irqstore[dev->bus->number][slot] = lastirq;
204 lastirq++;
205 return lastirq - 1;
206 }
207
pcibios_update_irq(struct pci_dev * dev,int irq)208 void __init pcibios_update_irq(struct pci_dev *dev, int irq)
209 {
210 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
211 }
212
pcibios_fixup_bus(struct pci_bus * b)213 void __devinit pcibios_fixup_bus(struct pci_bus *b)
214 {
215 pci_fixup_irqs(pci_swizzle, pci_map_irq);
216 }
217
pcibios_fixup_pbus_ranges(struct pci_bus * bus,struct pbus_set_ranges_data * ranges)218 void __init pcibios_fixup_pbus_ranges(struct pci_bus * bus,
219 struct pbus_set_ranges_data * ranges)
220 {
221 ranges->io_start -= bus->resource[0]->start;
222 ranges->io_end -= bus->resource[0]->start;
223 ranges->mem_start -= bus->resource[1]->start;
224 ranges->mem_end -= bus->resource[1]->start;
225 }
226
pcibios_assign_all_busses(void)227 unsigned int pcibios_assign_all_busses(void)
228 {
229 return 0;
230 }
231
232 /*
233 * Device might live on a subordinate PCI bus. XXX Walk up the chain of buses
234 * to find the slot number in sense of the bridge device register.
235 * XXX This also means multiple devices might rely on conflicting bridge
236 * settings.
237 */
238
pci_disable_swapping(struct pci_dev * dev)239 static void __init pci_disable_swapping(struct pci_dev *dev)
240 {
241 unsigned int bus_id = (unsigned) dev->bus->number;
242 bridge_t *bridge = (bridge_t *) NODE_SWIN_BASE(bus_to_nid[bus_id],
243 bus_to_wid[bus_id]);
244 int slot = PCI_SLOT(dev->devfn);
245
246 /* Turn off byte swapping */
247 bridge->b_device[slot].reg &= ~BRIDGE_DEV_SWAP_DIR;
248 bridge->b_widget.w_tflush; /* Flush */
249 }
250
pci_enable_swapping(struct pci_dev * dev)251 static void __init pci_enable_swapping(struct pci_dev *dev)
252 {
253 unsigned int bus_id = (unsigned) dev->bus->number;
254 bridge_t *bridge = (bridge_t *) NODE_SWIN_BASE(bus_to_nid[bus_id],
255 bus_to_wid[bus_id]);
256 int slot = PCI_SLOT(dev->devfn);
257
258 /* Turn on byte swapping */
259 bridge->b_device[slot].reg |= BRIDGE_DEV_SWAP_DIR;
260 bridge->b_widget.w_tflush; /* Flush */
261 }
262
pci_fixup_ioc3(struct pci_dev * d)263 static void __init pci_fixup_ioc3(struct pci_dev *d)
264 {
265 unsigned long bus_id = (unsigned) d->bus->number;
266
267 printk("PCI: Fixing base addresses for IOC3 device %s\n", d->slot_name);
268
269 d->resource[0].start |= NODE_OFFSET(bus_to_nid[bus_id]);
270 d->resource[0].end |= NODE_OFFSET(bus_to_nid[bus_id]);
271
272 pci_disable_swapping(d);
273 }
274
pci_fixup_isp1020(struct pci_dev * d)275 static void __init pci_fixup_isp1020(struct pci_dev *d)
276 {
277 unsigned short command;
278
279 d->resource[0].start |= ((unsigned long)(bus_to_nid[d->bus->number])<<32);
280 printk("PCI: Fixing isp1020 in [bus:slot.fn] %s\n", d->slot_name);
281
282 /*
283 * Configure device to allow bus mastering, i/o and memory mapping.
284 * Older qlogicisp driver expects to have the IO space enable
285 * bit set. Things stop working if we program the controllers as not
286 * having PCI_COMMAND_MEMORY, so we have to fudge the mem_flags.
287 */
288
289 pci_set_master(d);
290 pci_read_config_word(d, PCI_COMMAND, &command);
291 command |= PCI_COMMAND_MEMORY;
292 command |= PCI_COMMAND_IO;
293 pci_write_config_word(d, PCI_COMMAND, command);
294 d->resource[1].flags |= 1;
295
296 pci_enable_swapping(d);
297 }
298
pci_fixup_isp2x00(struct pci_dev * d)299 static void __init pci_fixup_isp2x00(struct pci_dev *d)
300 {
301 unsigned int bus_id = (unsigned) d->bus->number;
302 bridge_t *bridge = (bridge_t *) NODE_SWIN_BASE(bus_to_nid[bus_id],
303 bus_to_wid[bus_id]);
304 bridgereg_t devreg;
305 int i;
306 int slot = PCI_SLOT(d->devfn);
307 unsigned int start;
308 unsigned short command;
309
310 printk("PCI: Fixing isp2x00 in [bus:slot.fn] %s\n", d->slot_name);
311
312 /* set the resource struct for this device */
313 start = (u32) (u64)bridge; /* yes, we want to lose the upper 32 bits here */
314 start |= BRIDGE_DEVIO(slot);
315
316 d->resource[0].start = start;
317 d->resource[0].end = d->resource[0].start + 0xff;
318 d->resource[0].flags = IORESOURCE_IO;
319
320 d->resource[1].start = start;
321 d->resource[1].end = d->resource[0].start + 0xfff;
322 d->resource[1].flags = IORESOURCE_MEM;
323
324 /*
325 * set the bridge device(x) reg for this device
326 */
327 devreg = bridge->b_device[slot].reg;
328 /* point device(x) to it appropriate small window */
329 devreg &= ~BRIDGE_DEV_OFF_MASK;
330 devreg |= (start >> 20) & BRIDGE_DEV_OFF_MASK;
331 bridge->b_device[slot].reg = devreg;
332
333 pci_enable_swapping(d);
334
335 /* set card's base addr reg */
336 //pci_conf0_write_config_dword(d, PCI_BASE_ADDRESS_0, 0x500001);
337 //pci_conf0_write_config_dword(d, PCI_BASE_ADDRESS_1, 0x8b00000);
338 //pci_conf0_write_config_dword(d, PCI_ROM_ADDRESS, 0x8b20000);
339
340 /* I got these from booting irix on system...*/
341 pci_conf0_write_config_dword(d, PCI_BASE_ADDRESS_0, 0x200001);
342 //pci_conf0_write_config_dword(d, PCI_BASE_ADDRESS_1, 0xf800000);
343 pci_conf0_write_config_dword(d, PCI_ROM_ADDRESS, 0x10200000);
344
345 pci_conf0_write_config_dword(d, PCI_BASE_ADDRESS_1, start);
346 //pci_conf0_write_config_dword(d, PCI_ROM_ADDRESS, (start | 0x20000));
347
348 /* set cache line size */
349 pci_conf0_write_config_dword(d, PCI_CACHE_LINE_SIZE, 0xf080);
350
351 /* set pci bus timeout */
352 bridge->b_bus_timeout |= BRIDGE_BUS_PCI_RETRY_HLD(0x3);
353 bridge->b_wid_tflush;
354 printk("PCI: bridge bus timeout= 0x%x \n", bridge->b_bus_timeout);
355
356 /* set host error field */
357 bridge->b_int_host_err = 0x44;
358 bridge->b_wid_tflush;
359
360 bridge->b_wid_tflush; /* wait until Bridge PIO complete */
361 for (i=0; i<8; i++)
362 printk("PCI: device(%d)= 0x%x\n",i,bridge->b_device[i].reg);
363
364 /* configure device to allow bus mastering, i/o and memory mapping */
365 pci_set_master(d);
366 pci_read_config_word(d, PCI_COMMAND, &command);
367 command |= PCI_COMMAND_MEMORY;
368 command |= PCI_COMMAND_IO;
369 pci_write_config_word(d, PCI_COMMAND, command);
370 /*d->resource[1].flags |= 1;*/
371 }
372
373 struct pci_fixup pcibios_fixups[] = {
374 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
375 pci_fixup_ioc3 },
376 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP1020,
377 pci_fixup_isp1020 },
378 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2100,
379 pci_fixup_isp2x00 },
380 { PCI_FIXUP_HEADER, PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2200,
381 pci_fixup_isp2x00 },
382 { 0 }
383 };
384