1 /*
2 * ti_hdmi_4xxx_ip.c
3 *
4 * HDMI TI81xx, TI38xx, TI OMAP4 etc IP driver Library
5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com/
6 * Authors: Yong Zhi
7 * Mythri pk <mythripk@ti.com>
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published by
11 * the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * more details.
17 *
18 * You should have received a copy of the GNU General Public License along with
19 * this program. If not, see <http://www.gnu.org/licenses/>.
20 */
21
22 #include <linux/kernel.h>
23 #include <linux/module.h>
24 #include <linux/err.h>
25 #include <linux/io.h>
26 #include <linux/interrupt.h>
27 #include <linux/mutex.h>
28 #include <linux/delay.h>
29 #include <linux/string.h>
30 #include <linux/seq_file.h>
31 #include <linux/gpio.h>
32
33 #include "ti_hdmi_4xxx_ip.h"
34 #include "dss.h"
35
hdmi_write_reg(void __iomem * base_addr,const u16 idx,u32 val)36 static inline void hdmi_write_reg(void __iomem *base_addr,
37 const u16 idx, u32 val)
38 {
39 __raw_writel(val, base_addr + idx);
40 }
41
hdmi_read_reg(void __iomem * base_addr,const u16 idx)42 static inline u32 hdmi_read_reg(void __iomem *base_addr,
43 const u16 idx)
44 {
45 return __raw_readl(base_addr + idx);
46 }
47
hdmi_wp_base(struct hdmi_ip_data * ip_data)48 static inline void __iomem *hdmi_wp_base(struct hdmi_ip_data *ip_data)
49 {
50 return ip_data->base_wp;
51 }
52
hdmi_phy_base(struct hdmi_ip_data * ip_data)53 static inline void __iomem *hdmi_phy_base(struct hdmi_ip_data *ip_data)
54 {
55 return ip_data->base_wp + ip_data->phy_offset;
56 }
57
hdmi_pll_base(struct hdmi_ip_data * ip_data)58 static inline void __iomem *hdmi_pll_base(struct hdmi_ip_data *ip_data)
59 {
60 return ip_data->base_wp + ip_data->pll_offset;
61 }
62
hdmi_av_base(struct hdmi_ip_data * ip_data)63 static inline void __iomem *hdmi_av_base(struct hdmi_ip_data *ip_data)
64 {
65 return ip_data->base_wp + ip_data->core_av_offset;
66 }
67
hdmi_core_sys_base(struct hdmi_ip_data * ip_data)68 static inline void __iomem *hdmi_core_sys_base(struct hdmi_ip_data *ip_data)
69 {
70 return ip_data->base_wp + ip_data->core_sys_offset;
71 }
72
hdmi_wait_for_bit_change(void __iomem * base_addr,const u16 idx,int b2,int b1,u32 val)73 static inline int hdmi_wait_for_bit_change(void __iomem *base_addr,
74 const u16 idx,
75 int b2, int b1, u32 val)
76 {
77 u32 t = 0;
78 while (val != REG_GET(base_addr, idx, b2, b1)) {
79 udelay(1);
80 if (t++ > 10000)
81 return !val;
82 }
83 return val;
84 }
85
hdmi_pll_init(struct hdmi_ip_data * ip_data)86 static int hdmi_pll_init(struct hdmi_ip_data *ip_data)
87 {
88 u32 r;
89 void __iomem *pll_base = hdmi_pll_base(ip_data);
90 struct hdmi_pll_info *fmt = &ip_data->pll_data;
91
92 /* PLL start always use manual mode */
93 REG_FLD_MOD(pll_base, PLLCTRL_PLL_CONTROL, 0x0, 0, 0);
94
95 r = hdmi_read_reg(pll_base, PLLCTRL_CFG1);
96 r = FLD_MOD(r, fmt->regm, 20, 9); /* CFG1_PLL_REGM */
97 r = FLD_MOD(r, fmt->regn - 1, 8, 1); /* CFG1_PLL_REGN */
98
99 hdmi_write_reg(pll_base, PLLCTRL_CFG1, r);
100
101 r = hdmi_read_reg(pll_base, PLLCTRL_CFG2);
102
103 r = FLD_MOD(r, 0x0, 12, 12); /* PLL_HIGHFREQ divide by 2 */
104 r = FLD_MOD(r, 0x1, 13, 13); /* PLL_REFEN */
105 r = FLD_MOD(r, 0x0, 14, 14); /* PHY_CLKINEN de-assert during locking */
106 r = FLD_MOD(r, fmt->refsel, 22, 21); /* REFSEL */
107
108 if (fmt->dcofreq) {
109 /* divider programming for frequency beyond 1000Mhz */
110 REG_FLD_MOD(pll_base, PLLCTRL_CFG3, fmt->regsd, 17, 10);
111 r = FLD_MOD(r, 0x4, 3, 1); /* 1000MHz and 2000MHz */
112 } else {
113 r = FLD_MOD(r, 0x2, 3, 1); /* 500MHz and 1000MHz */
114 }
115
116 hdmi_write_reg(pll_base, PLLCTRL_CFG2, r);
117
118 r = hdmi_read_reg(pll_base, PLLCTRL_CFG4);
119 r = FLD_MOD(r, fmt->regm2, 24, 18);
120 r = FLD_MOD(r, fmt->regmf, 17, 0);
121
122 hdmi_write_reg(pll_base, PLLCTRL_CFG4, r);
123
124 /* go now */
125 REG_FLD_MOD(pll_base, PLLCTRL_PLL_GO, 0x1, 0, 0);
126
127 /* wait for bit change */
128 if (hdmi_wait_for_bit_change(pll_base, PLLCTRL_PLL_GO,
129 0, 0, 1) != 1) {
130 pr_err("PLL GO bit not set\n");
131 return -ETIMEDOUT;
132 }
133
134 /* Wait till the lock bit is set in PLL status */
135 if (hdmi_wait_for_bit_change(pll_base,
136 PLLCTRL_PLL_STATUS, 1, 1, 1) != 1) {
137 pr_err("cannot lock PLL\n");
138 pr_err("CFG1 0x%x\n",
139 hdmi_read_reg(pll_base, PLLCTRL_CFG1));
140 pr_err("CFG2 0x%x\n",
141 hdmi_read_reg(pll_base, PLLCTRL_CFG2));
142 pr_err("CFG4 0x%x\n",
143 hdmi_read_reg(pll_base, PLLCTRL_CFG4));
144 return -ETIMEDOUT;
145 }
146
147 pr_debug("PLL locked!\n");
148
149 return 0;
150 }
151
152 /* PHY_PWR_CMD */
hdmi_set_phy_pwr(struct hdmi_ip_data * ip_data,enum hdmi_phy_pwr val)153 static int hdmi_set_phy_pwr(struct hdmi_ip_data *ip_data, enum hdmi_phy_pwr val)
154 {
155 /* Command for power control of HDMI PHY */
156 REG_FLD_MOD(hdmi_wp_base(ip_data), HDMI_WP_PWR_CTRL, val, 7, 6);
157
158 /* Status of the power control of HDMI PHY */
159 if (hdmi_wait_for_bit_change(hdmi_wp_base(ip_data),
160 HDMI_WP_PWR_CTRL, 5, 4, val) != val) {
161 pr_err("Failed to set PHY power mode to %d\n", val);
162 return -ETIMEDOUT;
163 }
164
165 return 0;
166 }
167
168 /* PLL_PWR_CMD */
hdmi_set_pll_pwr(struct hdmi_ip_data * ip_data,enum hdmi_pll_pwr val)169 static int hdmi_set_pll_pwr(struct hdmi_ip_data *ip_data, enum hdmi_pll_pwr val)
170 {
171 /* Command for power control of HDMI PLL */
172 REG_FLD_MOD(hdmi_wp_base(ip_data), HDMI_WP_PWR_CTRL, val, 3, 2);
173
174 /* wait till PHY_PWR_STATUS is set */
175 if (hdmi_wait_for_bit_change(hdmi_wp_base(ip_data), HDMI_WP_PWR_CTRL,
176 1, 0, val) != val) {
177 pr_err("Failed to set PLL_PWR_STATUS\n");
178 return -ETIMEDOUT;
179 }
180
181 return 0;
182 }
183
hdmi_pll_reset(struct hdmi_ip_data * ip_data)184 static int hdmi_pll_reset(struct hdmi_ip_data *ip_data)
185 {
186 /* SYSRESET controlled by power FSM */
187 REG_FLD_MOD(hdmi_pll_base(ip_data), PLLCTRL_PLL_CONTROL, 0x0, 3, 3);
188
189 /* READ 0x0 reset is in progress */
190 if (hdmi_wait_for_bit_change(hdmi_pll_base(ip_data),
191 PLLCTRL_PLL_STATUS, 0, 0, 1) != 1) {
192 pr_err("Failed to sysreset PLL\n");
193 return -ETIMEDOUT;
194 }
195
196 return 0;
197 }
198
ti_hdmi_4xxx_pll_enable(struct hdmi_ip_data * ip_data)199 int ti_hdmi_4xxx_pll_enable(struct hdmi_ip_data *ip_data)
200 {
201 u16 r = 0;
202
203 r = hdmi_set_pll_pwr(ip_data, HDMI_PLLPWRCMD_ALLOFF);
204 if (r)
205 return r;
206
207 r = hdmi_set_pll_pwr(ip_data, HDMI_PLLPWRCMD_BOTHON_ALLCLKS);
208 if (r)
209 return r;
210
211 r = hdmi_pll_reset(ip_data);
212 if (r)
213 return r;
214
215 r = hdmi_pll_init(ip_data);
216 if (r)
217 return r;
218
219 return 0;
220 }
221
ti_hdmi_4xxx_pll_disable(struct hdmi_ip_data * ip_data)222 void ti_hdmi_4xxx_pll_disable(struct hdmi_ip_data *ip_data)
223 {
224 hdmi_set_pll_pwr(ip_data, HDMI_PLLPWRCMD_ALLOFF);
225 }
226
hdmi_check_hpd_state(struct hdmi_ip_data * ip_data)227 static int hdmi_check_hpd_state(struct hdmi_ip_data *ip_data)
228 {
229 unsigned long flags;
230 bool hpd;
231 int r;
232 /* this should be in ti_hdmi_4xxx_ip private data */
233 static DEFINE_SPINLOCK(phy_tx_lock);
234
235 spin_lock_irqsave(&phy_tx_lock, flags);
236
237 hpd = gpio_get_value(ip_data->hpd_gpio);
238
239 if (hpd == ip_data->phy_tx_enabled) {
240 spin_unlock_irqrestore(&phy_tx_lock, flags);
241 return 0;
242 }
243
244 if (hpd)
245 r = hdmi_set_phy_pwr(ip_data, HDMI_PHYPWRCMD_TXON);
246 else
247 r = hdmi_set_phy_pwr(ip_data, HDMI_PHYPWRCMD_LDOON);
248
249 if (r) {
250 DSSERR("Failed to %s PHY TX power\n",
251 hpd ? "enable" : "disable");
252 goto err;
253 }
254
255 ip_data->phy_tx_enabled = hpd;
256 err:
257 spin_unlock_irqrestore(&phy_tx_lock, flags);
258 return r;
259 }
260
hpd_irq_handler(int irq,void * data)261 static irqreturn_t hpd_irq_handler(int irq, void *data)
262 {
263 struct hdmi_ip_data *ip_data = data;
264
265 hdmi_check_hpd_state(ip_data);
266
267 return IRQ_HANDLED;
268 }
269
ti_hdmi_4xxx_phy_enable(struct hdmi_ip_data * ip_data)270 int ti_hdmi_4xxx_phy_enable(struct hdmi_ip_data *ip_data)
271 {
272 u16 r = 0;
273 void __iomem *phy_base = hdmi_phy_base(ip_data);
274
275 r = hdmi_set_phy_pwr(ip_data, HDMI_PHYPWRCMD_LDOON);
276 if (r)
277 return r;
278
279 /*
280 * Read address 0 in order to get the SCP reset done completed
281 * Dummy access performed to make sure reset is done
282 */
283 hdmi_read_reg(phy_base, HDMI_TXPHY_TX_CTRL);
284
285 /*
286 * Write to phy address 0 to configure the clock
287 * use HFBITCLK write HDMI_TXPHY_TX_CONTROL_FREQOUT field
288 */
289 REG_FLD_MOD(phy_base, HDMI_TXPHY_TX_CTRL, 0x1, 31, 30);
290
291 /* Write to phy address 1 to start HDMI line (TXVALID and TMDSCLKEN) */
292 hdmi_write_reg(phy_base, HDMI_TXPHY_DIGITAL_CTRL, 0xF0000000);
293
294 /* Setup max LDO voltage */
295 REG_FLD_MOD(phy_base, HDMI_TXPHY_POWER_CTRL, 0xB, 3, 0);
296
297 /* Write to phy address 3 to change the polarity control */
298 REG_FLD_MOD(phy_base, HDMI_TXPHY_PAD_CFG_CTRL, 0x1, 27, 27);
299
300 r = request_threaded_irq(gpio_to_irq(ip_data->hpd_gpio),
301 NULL, hpd_irq_handler,
302 IRQF_DISABLED | IRQF_TRIGGER_RISING |
303 IRQF_TRIGGER_FALLING, "hpd", ip_data);
304 if (r) {
305 DSSERR("HPD IRQ request failed\n");
306 hdmi_set_phy_pwr(ip_data, HDMI_PHYPWRCMD_OFF);
307 return r;
308 }
309
310 r = hdmi_check_hpd_state(ip_data);
311 if (r) {
312 free_irq(gpio_to_irq(ip_data->hpd_gpio), ip_data);
313 hdmi_set_phy_pwr(ip_data, HDMI_PHYPWRCMD_OFF);
314 return r;
315 }
316
317 return 0;
318 }
319
ti_hdmi_4xxx_phy_disable(struct hdmi_ip_data * ip_data)320 void ti_hdmi_4xxx_phy_disable(struct hdmi_ip_data *ip_data)
321 {
322 free_irq(gpio_to_irq(ip_data->hpd_gpio), ip_data);
323
324 hdmi_set_phy_pwr(ip_data, HDMI_PHYPWRCMD_OFF);
325 ip_data->phy_tx_enabled = false;
326 }
327
hdmi_core_ddc_init(struct hdmi_ip_data * ip_data)328 static int hdmi_core_ddc_init(struct hdmi_ip_data *ip_data)
329 {
330 void __iomem *base = hdmi_core_sys_base(ip_data);
331
332 /* Turn on CLK for DDC */
333 REG_FLD_MOD(base, HDMI_CORE_AV_DPD, 0x7, 2, 0);
334
335 /* IN_PROG */
336 if (REG_GET(base, HDMI_CORE_DDC_STATUS, 4, 4) == 1) {
337 /* Abort transaction */
338 REG_FLD_MOD(base, HDMI_CORE_DDC_CMD, 0xf, 3, 0);
339 /* IN_PROG */
340 if (hdmi_wait_for_bit_change(base, HDMI_CORE_DDC_STATUS,
341 4, 4, 0) != 0) {
342 DSSERR("Timeout aborting DDC transaction\n");
343 return -ETIMEDOUT;
344 }
345 }
346
347 /* Clk SCL Devices */
348 REG_FLD_MOD(base, HDMI_CORE_DDC_CMD, 0xA, 3, 0);
349
350 /* HDMI_CORE_DDC_STATUS_IN_PROG */
351 if (hdmi_wait_for_bit_change(base, HDMI_CORE_DDC_STATUS,
352 4, 4, 0) != 0) {
353 DSSERR("Timeout starting SCL clock\n");
354 return -ETIMEDOUT;
355 }
356
357 /* Clear FIFO */
358 REG_FLD_MOD(base, HDMI_CORE_DDC_CMD, 0x9, 3, 0);
359
360 /* HDMI_CORE_DDC_STATUS_IN_PROG */
361 if (hdmi_wait_for_bit_change(base, HDMI_CORE_DDC_STATUS,
362 4, 4, 0) != 0) {
363 DSSERR("Timeout clearing DDC fifo\n");
364 return -ETIMEDOUT;
365 }
366
367 return 0;
368 }
369
hdmi_core_ddc_edid(struct hdmi_ip_data * ip_data,u8 * pedid,int ext)370 static int hdmi_core_ddc_edid(struct hdmi_ip_data *ip_data,
371 u8 *pedid, int ext)
372 {
373 void __iomem *base = hdmi_core_sys_base(ip_data);
374 u32 i;
375 char checksum;
376 u32 offset = 0;
377
378 /* HDMI_CORE_DDC_STATUS_IN_PROG */
379 if (hdmi_wait_for_bit_change(base, HDMI_CORE_DDC_STATUS,
380 4, 4, 0) != 0) {
381 DSSERR("Timeout waiting DDC to be ready\n");
382 return -ETIMEDOUT;
383 }
384
385 if (ext % 2 != 0)
386 offset = 0x80;
387
388 /* Load Segment Address Register */
389 REG_FLD_MOD(base, HDMI_CORE_DDC_SEGM, ext / 2, 7, 0);
390
391 /* Load Slave Address Register */
392 REG_FLD_MOD(base, HDMI_CORE_DDC_ADDR, 0xA0 >> 1, 7, 1);
393
394 /* Load Offset Address Register */
395 REG_FLD_MOD(base, HDMI_CORE_DDC_OFFSET, offset, 7, 0);
396
397 /* Load Byte Count */
398 REG_FLD_MOD(base, HDMI_CORE_DDC_COUNT1, 0x80, 7, 0);
399 REG_FLD_MOD(base, HDMI_CORE_DDC_COUNT2, 0x0, 1, 0);
400
401 /* Set DDC_CMD */
402 if (ext)
403 REG_FLD_MOD(base, HDMI_CORE_DDC_CMD, 0x4, 3, 0);
404 else
405 REG_FLD_MOD(base, HDMI_CORE_DDC_CMD, 0x2, 3, 0);
406
407 /* HDMI_CORE_DDC_STATUS_BUS_LOW */
408 if (REG_GET(base, HDMI_CORE_DDC_STATUS, 6, 6) == 1) {
409 pr_err("I2C Bus Low?\n");
410 return -EIO;
411 }
412 /* HDMI_CORE_DDC_STATUS_NO_ACK */
413 if (REG_GET(base, HDMI_CORE_DDC_STATUS, 5, 5) == 1) {
414 pr_err("I2C No Ack\n");
415 return -EIO;
416 }
417
418 for (i = 0; i < 0x80; ++i) {
419 int t;
420
421 /* IN_PROG */
422 if (REG_GET(base, HDMI_CORE_DDC_STATUS, 4, 4) == 0) {
423 DSSERR("operation stopped when reading edid\n");
424 return -EIO;
425 }
426
427 t = 0;
428 /* FIFO_EMPTY */
429 while (REG_GET(base, HDMI_CORE_DDC_STATUS, 2, 2) == 1) {
430 if (t++ > 10000) {
431 DSSERR("timeout reading edid\n");
432 return -ETIMEDOUT;
433 }
434 udelay(1);
435 }
436
437 pedid[i] = REG_GET(base, HDMI_CORE_DDC_DATA, 7, 0);
438 }
439
440 checksum = 0;
441 for (i = 0; i < 0x80; ++i)
442 checksum += pedid[i];
443
444 if (checksum != 0) {
445 pr_err("E-EDID checksum failed!!\n");
446 return -EIO;
447 }
448
449 return 0;
450 }
451
ti_hdmi_4xxx_read_edid(struct hdmi_ip_data * ip_data,u8 * edid,int len)452 int ti_hdmi_4xxx_read_edid(struct hdmi_ip_data *ip_data,
453 u8 *edid, int len)
454 {
455 int r, l;
456
457 if (len < 128)
458 return -EINVAL;
459
460 r = hdmi_core_ddc_init(ip_data);
461 if (r)
462 return r;
463
464 r = hdmi_core_ddc_edid(ip_data, edid, 0);
465 if (r)
466 return r;
467
468 l = 128;
469
470 if (len >= 128 * 2 && edid[0x7e] > 0) {
471 r = hdmi_core_ddc_edid(ip_data, edid + 0x80, 1);
472 if (r)
473 return r;
474 l += 128;
475 }
476
477 return l;
478 }
479
ti_hdmi_4xxx_detect(struct hdmi_ip_data * ip_data)480 bool ti_hdmi_4xxx_detect(struct hdmi_ip_data *ip_data)
481 {
482 return gpio_get_value(ip_data->hpd_gpio);
483 }
484
hdmi_core_init(struct hdmi_core_video_config * video_cfg,struct hdmi_core_infoframe_avi * avi_cfg,struct hdmi_core_packet_enable_repeat * repeat_cfg)485 static void hdmi_core_init(struct hdmi_core_video_config *video_cfg,
486 struct hdmi_core_infoframe_avi *avi_cfg,
487 struct hdmi_core_packet_enable_repeat *repeat_cfg)
488 {
489 pr_debug("Enter hdmi_core_init\n");
490
491 /* video core */
492 video_cfg->ip_bus_width = HDMI_INPUT_8BIT;
493 video_cfg->op_dither_truc = HDMI_OUTPUTTRUNCATION_8BIT;
494 video_cfg->deep_color_pkt = HDMI_DEEPCOLORPACKECTDISABLE;
495 video_cfg->pkt_mode = HDMI_PACKETMODERESERVEDVALUE;
496 video_cfg->hdmi_dvi = HDMI_DVI;
497 video_cfg->tclk_sel_clkmult = HDMI_FPLL10IDCK;
498
499 /* info frame */
500 avi_cfg->db1_format = 0;
501 avi_cfg->db1_active_info = 0;
502 avi_cfg->db1_bar_info_dv = 0;
503 avi_cfg->db1_scan_info = 0;
504 avi_cfg->db2_colorimetry = 0;
505 avi_cfg->db2_aspect_ratio = 0;
506 avi_cfg->db2_active_fmt_ar = 0;
507 avi_cfg->db3_itc = 0;
508 avi_cfg->db3_ec = 0;
509 avi_cfg->db3_q_range = 0;
510 avi_cfg->db3_nup_scaling = 0;
511 avi_cfg->db4_videocode = 0;
512 avi_cfg->db5_pixel_repeat = 0;
513 avi_cfg->db6_7_line_eoftop = 0 ;
514 avi_cfg->db8_9_line_sofbottom = 0;
515 avi_cfg->db10_11_pixel_eofleft = 0;
516 avi_cfg->db12_13_pixel_sofright = 0;
517
518 /* packet enable and repeat */
519 repeat_cfg->audio_pkt = 0;
520 repeat_cfg->audio_pkt_repeat = 0;
521 repeat_cfg->avi_infoframe = 0;
522 repeat_cfg->avi_infoframe_repeat = 0;
523 repeat_cfg->gen_cntrl_pkt = 0;
524 repeat_cfg->gen_cntrl_pkt_repeat = 0;
525 repeat_cfg->generic_pkt = 0;
526 repeat_cfg->generic_pkt_repeat = 0;
527 }
528
hdmi_core_powerdown_disable(struct hdmi_ip_data * ip_data)529 static void hdmi_core_powerdown_disable(struct hdmi_ip_data *ip_data)
530 {
531 pr_debug("Enter hdmi_core_powerdown_disable\n");
532 REG_FLD_MOD(hdmi_core_sys_base(ip_data), HDMI_CORE_CTRL1, 0x0, 0, 0);
533 }
534
hdmi_core_swreset_release(struct hdmi_ip_data * ip_data)535 static void hdmi_core_swreset_release(struct hdmi_ip_data *ip_data)
536 {
537 pr_debug("Enter hdmi_core_swreset_release\n");
538 REG_FLD_MOD(hdmi_core_sys_base(ip_data), HDMI_CORE_SYS_SRST, 0x0, 0, 0);
539 }
540
hdmi_core_swreset_assert(struct hdmi_ip_data * ip_data)541 static void hdmi_core_swreset_assert(struct hdmi_ip_data *ip_data)
542 {
543 pr_debug("Enter hdmi_core_swreset_assert\n");
544 REG_FLD_MOD(hdmi_core_sys_base(ip_data), HDMI_CORE_SYS_SRST, 0x1, 0, 0);
545 }
546
547 /* HDMI_CORE_VIDEO_CONFIG */
hdmi_core_video_config(struct hdmi_ip_data * ip_data,struct hdmi_core_video_config * cfg)548 static void hdmi_core_video_config(struct hdmi_ip_data *ip_data,
549 struct hdmi_core_video_config *cfg)
550 {
551 u32 r = 0;
552 void __iomem *core_sys_base = hdmi_core_sys_base(ip_data);
553
554 /* sys_ctrl1 default configuration not tunable */
555 r = hdmi_read_reg(core_sys_base, HDMI_CORE_CTRL1);
556 r = FLD_MOD(r, HDMI_CORE_CTRL1_VEN_FOLLOWVSYNC, 5, 5);
557 r = FLD_MOD(r, HDMI_CORE_CTRL1_HEN_FOLLOWHSYNC, 4, 4);
558 r = FLD_MOD(r, HDMI_CORE_CTRL1_BSEL_24BITBUS, 2, 2);
559 r = FLD_MOD(r, HDMI_CORE_CTRL1_EDGE_RISINGEDGE, 1, 1);
560 hdmi_write_reg(core_sys_base, HDMI_CORE_CTRL1, r);
561
562 REG_FLD_MOD(core_sys_base,
563 HDMI_CORE_SYS_VID_ACEN, cfg->ip_bus_width, 7, 6);
564
565 /* Vid_Mode */
566 r = hdmi_read_reg(core_sys_base, HDMI_CORE_SYS_VID_MODE);
567
568 /* dither truncation configuration */
569 if (cfg->op_dither_truc > HDMI_OUTPUTTRUNCATION_12BIT) {
570 r = FLD_MOD(r, cfg->op_dither_truc - 3, 7, 6);
571 r = FLD_MOD(r, 1, 5, 5);
572 } else {
573 r = FLD_MOD(r, cfg->op_dither_truc, 7, 6);
574 r = FLD_MOD(r, 0, 5, 5);
575 }
576 hdmi_write_reg(core_sys_base, HDMI_CORE_SYS_VID_MODE, r);
577
578 /* HDMI_Ctrl */
579 r = hdmi_read_reg(hdmi_av_base(ip_data), HDMI_CORE_AV_HDMI_CTRL);
580 r = FLD_MOD(r, cfg->deep_color_pkt, 6, 6);
581 r = FLD_MOD(r, cfg->pkt_mode, 5, 3);
582 r = FLD_MOD(r, cfg->hdmi_dvi, 0, 0);
583 hdmi_write_reg(hdmi_av_base(ip_data), HDMI_CORE_AV_HDMI_CTRL, r);
584
585 /* TMDS_CTRL */
586 REG_FLD_MOD(core_sys_base,
587 HDMI_CORE_SYS_TMDS_CTRL, cfg->tclk_sel_clkmult, 6, 5);
588 }
589
hdmi_core_aux_infoframe_avi_config(struct hdmi_ip_data * ip_data)590 static void hdmi_core_aux_infoframe_avi_config(struct hdmi_ip_data *ip_data)
591 {
592 u32 val;
593 char sum = 0, checksum = 0;
594 void __iomem *av_base = hdmi_av_base(ip_data);
595 struct hdmi_core_infoframe_avi info_avi = ip_data->avi_cfg;
596
597 sum += 0x82 + 0x002 + 0x00D;
598 hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_TYPE, 0x082);
599 hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_VERS, 0x002);
600 hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_LEN, 0x00D);
601
602 val = (info_avi.db1_format << 5) |
603 (info_avi.db1_active_info << 4) |
604 (info_avi.db1_bar_info_dv << 2) |
605 (info_avi.db1_scan_info);
606 hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(0), val);
607 sum += val;
608
609 val = (info_avi.db2_colorimetry << 6) |
610 (info_avi.db2_aspect_ratio << 4) |
611 (info_avi.db2_active_fmt_ar);
612 hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(1), val);
613 sum += val;
614
615 val = (info_avi.db3_itc << 7) |
616 (info_avi.db3_ec << 4) |
617 (info_avi.db3_q_range << 2) |
618 (info_avi.db3_nup_scaling);
619 hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(2), val);
620 sum += val;
621
622 hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(3),
623 info_avi.db4_videocode);
624 sum += info_avi.db4_videocode;
625
626 val = info_avi.db5_pixel_repeat;
627 hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(4), val);
628 sum += val;
629
630 val = info_avi.db6_7_line_eoftop & 0x00FF;
631 hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(5), val);
632 sum += val;
633
634 val = ((info_avi.db6_7_line_eoftop >> 8) & 0x00FF);
635 hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(6), val);
636 sum += val;
637
638 val = info_avi.db8_9_line_sofbottom & 0x00FF;
639 hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(7), val);
640 sum += val;
641
642 val = ((info_avi.db8_9_line_sofbottom >> 8) & 0x00FF);
643 hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(8), val);
644 sum += val;
645
646 val = info_avi.db10_11_pixel_eofleft & 0x00FF;
647 hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(9), val);
648 sum += val;
649
650 val = ((info_avi.db10_11_pixel_eofleft >> 8) & 0x00FF);
651 hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(10), val);
652 sum += val;
653
654 val = info_avi.db12_13_pixel_sofright & 0x00FF;
655 hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(11), val);
656 sum += val;
657
658 val = ((info_avi.db12_13_pixel_sofright >> 8) & 0x00FF);
659 hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_DBYTE(12), val);
660 sum += val;
661
662 checksum = 0x100 - sum;
663 hdmi_write_reg(av_base, HDMI_CORE_AV_AVI_CHSUM, checksum);
664 }
665
hdmi_core_av_packet_config(struct hdmi_ip_data * ip_data,struct hdmi_core_packet_enable_repeat repeat_cfg)666 static void hdmi_core_av_packet_config(struct hdmi_ip_data *ip_data,
667 struct hdmi_core_packet_enable_repeat repeat_cfg)
668 {
669 /* enable/repeat the infoframe */
670 hdmi_write_reg(hdmi_av_base(ip_data), HDMI_CORE_AV_PB_CTRL1,
671 (repeat_cfg.audio_pkt << 5) |
672 (repeat_cfg.audio_pkt_repeat << 4) |
673 (repeat_cfg.avi_infoframe << 1) |
674 (repeat_cfg.avi_infoframe_repeat));
675
676 /* enable/repeat the packet */
677 hdmi_write_reg(hdmi_av_base(ip_data), HDMI_CORE_AV_PB_CTRL2,
678 (repeat_cfg.gen_cntrl_pkt << 3) |
679 (repeat_cfg.gen_cntrl_pkt_repeat << 2) |
680 (repeat_cfg.generic_pkt << 1) |
681 (repeat_cfg.generic_pkt_repeat));
682 }
683
hdmi_wp_init(struct omap_video_timings * timings,struct hdmi_video_format * video_fmt)684 static void hdmi_wp_init(struct omap_video_timings *timings,
685 struct hdmi_video_format *video_fmt)
686 {
687 pr_debug("Enter hdmi_wp_init\n");
688
689 timings->hbp = 0;
690 timings->hfp = 0;
691 timings->hsw = 0;
692 timings->vbp = 0;
693 timings->vfp = 0;
694 timings->vsw = 0;
695
696 video_fmt->packing_mode = HDMI_PACK_10b_RGB_YUV444;
697 video_fmt->y_res = 0;
698 video_fmt->x_res = 0;
699
700 }
701
ti_hdmi_4xxx_wp_video_start(struct hdmi_ip_data * ip_data,bool start)702 void ti_hdmi_4xxx_wp_video_start(struct hdmi_ip_data *ip_data, bool start)
703 {
704 REG_FLD_MOD(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_CFG, start, 31, 31);
705 }
706
hdmi_wp_video_init_format(struct hdmi_video_format * video_fmt,struct omap_video_timings * timings,struct hdmi_config * param)707 static void hdmi_wp_video_init_format(struct hdmi_video_format *video_fmt,
708 struct omap_video_timings *timings, struct hdmi_config *param)
709 {
710 pr_debug("Enter hdmi_wp_video_init_format\n");
711
712 video_fmt->y_res = param->timings.y_res;
713 video_fmt->x_res = param->timings.x_res;
714
715 timings->hbp = param->timings.hbp;
716 timings->hfp = param->timings.hfp;
717 timings->hsw = param->timings.hsw;
718 timings->vbp = param->timings.vbp;
719 timings->vfp = param->timings.vfp;
720 timings->vsw = param->timings.vsw;
721 }
722
hdmi_wp_video_config_format(struct hdmi_ip_data * ip_data,struct hdmi_video_format * video_fmt)723 static void hdmi_wp_video_config_format(struct hdmi_ip_data *ip_data,
724 struct hdmi_video_format *video_fmt)
725 {
726 u32 l = 0;
727
728 REG_FLD_MOD(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_CFG,
729 video_fmt->packing_mode, 10, 8);
730
731 l |= FLD_VAL(video_fmt->y_res, 31, 16);
732 l |= FLD_VAL(video_fmt->x_res, 15, 0);
733 hdmi_write_reg(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_SIZE, l);
734 }
735
hdmi_wp_video_config_interface(struct hdmi_ip_data * ip_data)736 static void hdmi_wp_video_config_interface(struct hdmi_ip_data *ip_data)
737 {
738 u32 r;
739 pr_debug("Enter hdmi_wp_video_config_interface\n");
740
741 r = hdmi_read_reg(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_CFG);
742 r = FLD_MOD(r, ip_data->cfg.timings.vsync_pol, 7, 7);
743 r = FLD_MOD(r, ip_data->cfg.timings.hsync_pol, 6, 6);
744 r = FLD_MOD(r, ip_data->cfg.timings.interlace, 3, 3);
745 r = FLD_MOD(r, 1, 1, 0); /* HDMI_TIMING_MASTER_24BIT */
746 hdmi_write_reg(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_CFG, r);
747 }
748
hdmi_wp_video_config_timing(struct hdmi_ip_data * ip_data,struct omap_video_timings * timings)749 static void hdmi_wp_video_config_timing(struct hdmi_ip_data *ip_data,
750 struct omap_video_timings *timings)
751 {
752 u32 timing_h = 0;
753 u32 timing_v = 0;
754
755 pr_debug("Enter hdmi_wp_video_config_timing\n");
756
757 timing_h |= FLD_VAL(timings->hbp, 31, 20);
758 timing_h |= FLD_VAL(timings->hfp, 19, 8);
759 timing_h |= FLD_VAL(timings->hsw, 7, 0);
760 hdmi_write_reg(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_TIMING_H, timing_h);
761
762 timing_v |= FLD_VAL(timings->vbp, 31, 20);
763 timing_v |= FLD_VAL(timings->vfp, 19, 8);
764 timing_v |= FLD_VAL(timings->vsw, 7, 0);
765 hdmi_write_reg(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_TIMING_V, timing_v);
766 }
767
ti_hdmi_4xxx_basic_configure(struct hdmi_ip_data * ip_data)768 void ti_hdmi_4xxx_basic_configure(struct hdmi_ip_data *ip_data)
769 {
770 /* HDMI */
771 struct omap_video_timings video_timing;
772 struct hdmi_video_format video_format;
773 /* HDMI core */
774 struct hdmi_core_infoframe_avi avi_cfg = ip_data->avi_cfg;
775 struct hdmi_core_video_config v_core_cfg;
776 struct hdmi_core_packet_enable_repeat repeat_cfg;
777 struct hdmi_config *cfg = &ip_data->cfg;
778
779 hdmi_wp_init(&video_timing, &video_format);
780
781 hdmi_core_init(&v_core_cfg,
782 &avi_cfg,
783 &repeat_cfg);
784
785 hdmi_wp_video_init_format(&video_format, &video_timing, cfg);
786
787 hdmi_wp_video_config_timing(ip_data, &video_timing);
788
789 /* video config */
790 video_format.packing_mode = HDMI_PACK_24b_RGB_YUV444_YUV422;
791
792 hdmi_wp_video_config_format(ip_data, &video_format);
793
794 hdmi_wp_video_config_interface(ip_data);
795
796 /*
797 * configure core video part
798 * set software reset in the core
799 */
800 hdmi_core_swreset_assert(ip_data);
801
802 /* power down off */
803 hdmi_core_powerdown_disable(ip_data);
804
805 v_core_cfg.pkt_mode = HDMI_PACKETMODE24BITPERPIXEL;
806 v_core_cfg.hdmi_dvi = cfg->cm.mode;
807
808 hdmi_core_video_config(ip_data, &v_core_cfg);
809
810 /* release software reset in the core */
811 hdmi_core_swreset_release(ip_data);
812
813 /*
814 * configure packet
815 * info frame video see doc CEA861-D page 65
816 */
817 avi_cfg.db1_format = HDMI_INFOFRAME_AVI_DB1Y_RGB;
818 avi_cfg.db1_active_info =
819 HDMI_INFOFRAME_AVI_DB1A_ACTIVE_FORMAT_OFF;
820 avi_cfg.db1_bar_info_dv = HDMI_INFOFRAME_AVI_DB1B_NO;
821 avi_cfg.db1_scan_info = HDMI_INFOFRAME_AVI_DB1S_0;
822 avi_cfg.db2_colorimetry = HDMI_INFOFRAME_AVI_DB2C_NO;
823 avi_cfg.db2_aspect_ratio = HDMI_INFOFRAME_AVI_DB2M_NO;
824 avi_cfg.db2_active_fmt_ar = HDMI_INFOFRAME_AVI_DB2R_SAME;
825 avi_cfg.db3_itc = HDMI_INFOFRAME_AVI_DB3ITC_NO;
826 avi_cfg.db3_ec = HDMI_INFOFRAME_AVI_DB3EC_XVYUV601;
827 avi_cfg.db3_q_range = HDMI_INFOFRAME_AVI_DB3Q_DEFAULT;
828 avi_cfg.db3_nup_scaling = HDMI_INFOFRAME_AVI_DB3SC_NO;
829 avi_cfg.db4_videocode = cfg->cm.code;
830 avi_cfg.db5_pixel_repeat = HDMI_INFOFRAME_AVI_DB5PR_NO;
831 avi_cfg.db6_7_line_eoftop = 0;
832 avi_cfg.db8_9_line_sofbottom = 0;
833 avi_cfg.db10_11_pixel_eofleft = 0;
834 avi_cfg.db12_13_pixel_sofright = 0;
835
836 hdmi_core_aux_infoframe_avi_config(ip_data);
837
838 /* enable/repeat the infoframe */
839 repeat_cfg.avi_infoframe = HDMI_PACKETENABLE;
840 repeat_cfg.avi_infoframe_repeat = HDMI_PACKETREPEATON;
841 /* wakeup */
842 repeat_cfg.audio_pkt = HDMI_PACKETENABLE;
843 repeat_cfg.audio_pkt_repeat = HDMI_PACKETREPEATON;
844 hdmi_core_av_packet_config(ip_data, repeat_cfg);
845 }
846
ti_hdmi_4xxx_wp_dump(struct hdmi_ip_data * ip_data,struct seq_file * s)847 void ti_hdmi_4xxx_wp_dump(struct hdmi_ip_data *ip_data, struct seq_file *s)
848 {
849 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r,\
850 hdmi_read_reg(hdmi_wp_base(ip_data), r))
851
852 DUMPREG(HDMI_WP_REVISION);
853 DUMPREG(HDMI_WP_SYSCONFIG);
854 DUMPREG(HDMI_WP_IRQSTATUS_RAW);
855 DUMPREG(HDMI_WP_IRQSTATUS);
856 DUMPREG(HDMI_WP_PWR_CTRL);
857 DUMPREG(HDMI_WP_IRQENABLE_SET);
858 DUMPREG(HDMI_WP_VIDEO_CFG);
859 DUMPREG(HDMI_WP_VIDEO_SIZE);
860 DUMPREG(HDMI_WP_VIDEO_TIMING_H);
861 DUMPREG(HDMI_WP_VIDEO_TIMING_V);
862 DUMPREG(HDMI_WP_WP_CLK);
863 DUMPREG(HDMI_WP_AUDIO_CFG);
864 DUMPREG(HDMI_WP_AUDIO_CFG2);
865 DUMPREG(HDMI_WP_AUDIO_CTRL);
866 DUMPREG(HDMI_WP_AUDIO_DATA);
867 }
868
ti_hdmi_4xxx_pll_dump(struct hdmi_ip_data * ip_data,struct seq_file * s)869 void ti_hdmi_4xxx_pll_dump(struct hdmi_ip_data *ip_data, struct seq_file *s)
870 {
871 #define DUMPPLL(r) seq_printf(s, "%-35s %08x\n", #r,\
872 hdmi_read_reg(hdmi_pll_base(ip_data), r))
873
874 DUMPPLL(PLLCTRL_PLL_CONTROL);
875 DUMPPLL(PLLCTRL_PLL_STATUS);
876 DUMPPLL(PLLCTRL_PLL_GO);
877 DUMPPLL(PLLCTRL_CFG1);
878 DUMPPLL(PLLCTRL_CFG2);
879 DUMPPLL(PLLCTRL_CFG3);
880 DUMPPLL(PLLCTRL_CFG4);
881 }
882
ti_hdmi_4xxx_core_dump(struct hdmi_ip_data * ip_data,struct seq_file * s)883 void ti_hdmi_4xxx_core_dump(struct hdmi_ip_data *ip_data, struct seq_file *s)
884 {
885 int i;
886
887 #define CORE_REG(i, name) name(i)
888 #define DUMPCORE(r) seq_printf(s, "%-35s %08x\n", #r,\
889 hdmi_read_reg(hdmi_pll_base(ip_data), r))
890 #define DUMPCOREAV(i, r) seq_printf(s, "%s[%d]%*s %08x\n", #r, i, \
891 (i < 10) ? 32 - strlen(#r) : 31 - strlen(#r), " ", \
892 hdmi_read_reg(hdmi_pll_base(ip_data), CORE_REG(i, r)))
893
894 DUMPCORE(HDMI_CORE_SYS_VND_IDL);
895 DUMPCORE(HDMI_CORE_SYS_DEV_IDL);
896 DUMPCORE(HDMI_CORE_SYS_DEV_IDH);
897 DUMPCORE(HDMI_CORE_SYS_DEV_REV);
898 DUMPCORE(HDMI_CORE_SYS_SRST);
899 DUMPCORE(HDMI_CORE_CTRL1);
900 DUMPCORE(HDMI_CORE_SYS_SYS_STAT);
901 DUMPCORE(HDMI_CORE_SYS_VID_ACEN);
902 DUMPCORE(HDMI_CORE_SYS_VID_MODE);
903 DUMPCORE(HDMI_CORE_SYS_INTR_STATE);
904 DUMPCORE(HDMI_CORE_SYS_INTR1);
905 DUMPCORE(HDMI_CORE_SYS_INTR2);
906 DUMPCORE(HDMI_CORE_SYS_INTR3);
907 DUMPCORE(HDMI_CORE_SYS_INTR4);
908 DUMPCORE(HDMI_CORE_SYS_UMASK1);
909 DUMPCORE(HDMI_CORE_SYS_TMDS_CTRL);
910 DUMPCORE(HDMI_CORE_SYS_DE_DLY);
911 DUMPCORE(HDMI_CORE_SYS_DE_CTRL);
912 DUMPCORE(HDMI_CORE_SYS_DE_TOP);
913 DUMPCORE(HDMI_CORE_SYS_DE_CNTL);
914 DUMPCORE(HDMI_CORE_SYS_DE_CNTH);
915 DUMPCORE(HDMI_CORE_SYS_DE_LINL);
916 DUMPCORE(HDMI_CORE_SYS_DE_LINH_1);
917
918 DUMPCORE(HDMI_CORE_DDC_CMD);
919 DUMPCORE(HDMI_CORE_DDC_STATUS);
920 DUMPCORE(HDMI_CORE_DDC_ADDR);
921 DUMPCORE(HDMI_CORE_DDC_OFFSET);
922 DUMPCORE(HDMI_CORE_DDC_COUNT1);
923 DUMPCORE(HDMI_CORE_DDC_COUNT2);
924 DUMPCORE(HDMI_CORE_DDC_DATA);
925 DUMPCORE(HDMI_CORE_DDC_SEGM);
926
927 DUMPCORE(HDMI_CORE_AV_HDMI_CTRL);
928 DUMPCORE(HDMI_CORE_AV_DPD);
929 DUMPCORE(HDMI_CORE_AV_PB_CTRL1);
930 DUMPCORE(HDMI_CORE_AV_PB_CTRL2);
931 DUMPCORE(HDMI_CORE_AV_AVI_TYPE);
932 DUMPCORE(HDMI_CORE_AV_AVI_VERS);
933 DUMPCORE(HDMI_CORE_AV_AVI_LEN);
934 DUMPCORE(HDMI_CORE_AV_AVI_CHSUM);
935
936 for (i = 0; i < HDMI_CORE_AV_AVI_DBYTE_NELEMS; i++)
937 DUMPCOREAV(i, HDMI_CORE_AV_AVI_DBYTE);
938
939 for (i = 0; i < HDMI_CORE_AV_SPD_DBYTE_NELEMS; i++)
940 DUMPCOREAV(i, HDMI_CORE_AV_SPD_DBYTE);
941
942 for (i = 0; i < HDMI_CORE_AV_AUD_DBYTE_NELEMS; i++)
943 DUMPCOREAV(i, HDMI_CORE_AV_AUD_DBYTE);
944
945 for (i = 0; i < HDMI_CORE_AV_MPEG_DBYTE_NELEMS; i++)
946 DUMPCOREAV(i, HDMI_CORE_AV_MPEG_DBYTE);
947
948 for (i = 0; i < HDMI_CORE_AV_GEN_DBYTE_NELEMS; i++)
949 DUMPCOREAV(i, HDMI_CORE_AV_GEN_DBYTE);
950
951 for (i = 0; i < HDMI_CORE_AV_GEN2_DBYTE_NELEMS; i++)
952 DUMPCOREAV(i, HDMI_CORE_AV_GEN2_DBYTE);
953
954 DUMPCORE(HDMI_CORE_AV_ACR_CTRL);
955 DUMPCORE(HDMI_CORE_AV_FREQ_SVAL);
956 DUMPCORE(HDMI_CORE_AV_N_SVAL1);
957 DUMPCORE(HDMI_CORE_AV_N_SVAL2);
958 DUMPCORE(HDMI_CORE_AV_N_SVAL3);
959 DUMPCORE(HDMI_CORE_AV_CTS_SVAL1);
960 DUMPCORE(HDMI_CORE_AV_CTS_SVAL2);
961 DUMPCORE(HDMI_CORE_AV_CTS_SVAL3);
962 DUMPCORE(HDMI_CORE_AV_CTS_HVAL1);
963 DUMPCORE(HDMI_CORE_AV_CTS_HVAL2);
964 DUMPCORE(HDMI_CORE_AV_CTS_HVAL3);
965 DUMPCORE(HDMI_CORE_AV_AUD_MODE);
966 DUMPCORE(HDMI_CORE_AV_SPDIF_CTRL);
967 DUMPCORE(HDMI_CORE_AV_HW_SPDIF_FS);
968 DUMPCORE(HDMI_CORE_AV_SWAP_I2S);
969 DUMPCORE(HDMI_CORE_AV_SPDIF_ERTH);
970 DUMPCORE(HDMI_CORE_AV_I2S_IN_MAP);
971 DUMPCORE(HDMI_CORE_AV_I2S_IN_CTRL);
972 DUMPCORE(HDMI_CORE_AV_I2S_CHST0);
973 DUMPCORE(HDMI_CORE_AV_I2S_CHST1);
974 DUMPCORE(HDMI_CORE_AV_I2S_CHST2);
975 DUMPCORE(HDMI_CORE_AV_I2S_CHST4);
976 DUMPCORE(HDMI_CORE_AV_I2S_CHST5);
977 DUMPCORE(HDMI_CORE_AV_ASRC);
978 DUMPCORE(HDMI_CORE_AV_I2S_IN_LEN);
979 DUMPCORE(HDMI_CORE_AV_HDMI_CTRL);
980 DUMPCORE(HDMI_CORE_AV_AUDO_TXSTAT);
981 DUMPCORE(HDMI_CORE_AV_AUD_PAR_BUSCLK_1);
982 DUMPCORE(HDMI_CORE_AV_AUD_PAR_BUSCLK_2);
983 DUMPCORE(HDMI_CORE_AV_AUD_PAR_BUSCLK_3);
984 DUMPCORE(HDMI_CORE_AV_TEST_TXCTRL);
985 DUMPCORE(HDMI_CORE_AV_DPD);
986 DUMPCORE(HDMI_CORE_AV_PB_CTRL1);
987 DUMPCORE(HDMI_CORE_AV_PB_CTRL2);
988 DUMPCORE(HDMI_CORE_AV_AVI_TYPE);
989 DUMPCORE(HDMI_CORE_AV_AVI_VERS);
990 DUMPCORE(HDMI_CORE_AV_AVI_LEN);
991 DUMPCORE(HDMI_CORE_AV_AVI_CHSUM);
992 DUMPCORE(HDMI_CORE_AV_SPD_TYPE);
993 DUMPCORE(HDMI_CORE_AV_SPD_VERS);
994 DUMPCORE(HDMI_CORE_AV_SPD_LEN);
995 DUMPCORE(HDMI_CORE_AV_SPD_CHSUM);
996 DUMPCORE(HDMI_CORE_AV_AUDIO_TYPE);
997 DUMPCORE(HDMI_CORE_AV_AUDIO_VERS);
998 DUMPCORE(HDMI_CORE_AV_AUDIO_LEN);
999 DUMPCORE(HDMI_CORE_AV_AUDIO_CHSUM);
1000 DUMPCORE(HDMI_CORE_AV_MPEG_TYPE);
1001 DUMPCORE(HDMI_CORE_AV_MPEG_VERS);
1002 DUMPCORE(HDMI_CORE_AV_MPEG_LEN);
1003 DUMPCORE(HDMI_CORE_AV_MPEG_CHSUM);
1004 DUMPCORE(HDMI_CORE_AV_CP_BYTE1);
1005 DUMPCORE(HDMI_CORE_AV_CEC_ADDR_ID);
1006 }
1007
ti_hdmi_4xxx_phy_dump(struct hdmi_ip_data * ip_data,struct seq_file * s)1008 void ti_hdmi_4xxx_phy_dump(struct hdmi_ip_data *ip_data, struct seq_file *s)
1009 {
1010 #define DUMPPHY(r) seq_printf(s, "%-35s %08x\n", #r,\
1011 hdmi_read_reg(hdmi_phy_base(ip_data), r))
1012
1013 DUMPPHY(HDMI_TXPHY_TX_CTRL);
1014 DUMPPHY(HDMI_TXPHY_DIGITAL_CTRL);
1015 DUMPPHY(HDMI_TXPHY_POWER_CTRL);
1016 DUMPPHY(HDMI_TXPHY_PAD_CFG_CTRL);
1017 }
1018
1019 #if defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI) || \
1020 defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI_MODULE)
hdmi_wp_audio_config_format(struct hdmi_ip_data * ip_data,struct hdmi_audio_format * aud_fmt)1021 void hdmi_wp_audio_config_format(struct hdmi_ip_data *ip_data,
1022 struct hdmi_audio_format *aud_fmt)
1023 {
1024 u32 r;
1025
1026 DSSDBG("Enter hdmi_wp_audio_config_format\n");
1027
1028 r = hdmi_read_reg(hdmi_wp_base(ip_data), HDMI_WP_AUDIO_CFG);
1029 r = FLD_MOD(r, aud_fmt->stereo_channels, 26, 24);
1030 r = FLD_MOD(r, aud_fmt->active_chnnls_msk, 23, 16);
1031 r = FLD_MOD(r, aud_fmt->en_sig_blk_strt_end, 5, 5);
1032 r = FLD_MOD(r, aud_fmt->type, 4, 4);
1033 r = FLD_MOD(r, aud_fmt->justification, 3, 3);
1034 r = FLD_MOD(r, aud_fmt->sample_order, 2, 2);
1035 r = FLD_MOD(r, aud_fmt->samples_per_word, 1, 1);
1036 r = FLD_MOD(r, aud_fmt->sample_size, 0, 0);
1037 hdmi_write_reg(hdmi_wp_base(ip_data), HDMI_WP_AUDIO_CFG, r);
1038 }
1039
hdmi_wp_audio_config_dma(struct hdmi_ip_data * ip_data,struct hdmi_audio_dma * aud_dma)1040 void hdmi_wp_audio_config_dma(struct hdmi_ip_data *ip_data,
1041 struct hdmi_audio_dma *aud_dma)
1042 {
1043 u32 r;
1044
1045 DSSDBG("Enter hdmi_wp_audio_config_dma\n");
1046
1047 r = hdmi_read_reg(hdmi_wp_base(ip_data), HDMI_WP_AUDIO_CFG2);
1048 r = FLD_MOD(r, aud_dma->transfer_size, 15, 8);
1049 r = FLD_MOD(r, aud_dma->block_size, 7, 0);
1050 hdmi_write_reg(hdmi_wp_base(ip_data), HDMI_WP_AUDIO_CFG2, r);
1051
1052 r = hdmi_read_reg(hdmi_wp_base(ip_data), HDMI_WP_AUDIO_CTRL);
1053 r = FLD_MOD(r, aud_dma->mode, 9, 9);
1054 r = FLD_MOD(r, aud_dma->fifo_threshold, 8, 0);
1055 hdmi_write_reg(hdmi_wp_base(ip_data), HDMI_WP_AUDIO_CTRL, r);
1056 }
1057
hdmi_core_audio_config(struct hdmi_ip_data * ip_data,struct hdmi_core_audio_config * cfg)1058 void hdmi_core_audio_config(struct hdmi_ip_data *ip_data,
1059 struct hdmi_core_audio_config *cfg)
1060 {
1061 u32 r;
1062 void __iomem *av_base = hdmi_av_base(ip_data);
1063
1064 /*
1065 * Parameters for generation of Audio Clock Recovery packets
1066 */
1067 REG_FLD_MOD(av_base, HDMI_CORE_AV_N_SVAL1, cfg->n, 7, 0);
1068 REG_FLD_MOD(av_base, HDMI_CORE_AV_N_SVAL2, cfg->n >> 8, 7, 0);
1069 REG_FLD_MOD(av_base, HDMI_CORE_AV_N_SVAL3, cfg->n >> 16, 7, 0);
1070
1071 if (cfg->cts_mode == HDMI_AUDIO_CTS_MODE_SW) {
1072 REG_FLD_MOD(av_base, HDMI_CORE_AV_CTS_SVAL1, cfg->cts, 7, 0);
1073 REG_FLD_MOD(av_base,
1074 HDMI_CORE_AV_CTS_SVAL2, cfg->cts >> 8, 7, 0);
1075 REG_FLD_MOD(av_base,
1076 HDMI_CORE_AV_CTS_SVAL3, cfg->cts >> 16, 7, 0);
1077 } else {
1078 REG_FLD_MOD(av_base, HDMI_CORE_AV_AUD_PAR_BUSCLK_1,
1079 cfg->aud_par_busclk, 7, 0);
1080 REG_FLD_MOD(av_base, HDMI_CORE_AV_AUD_PAR_BUSCLK_2,
1081 (cfg->aud_par_busclk >> 8), 7, 0);
1082 REG_FLD_MOD(av_base, HDMI_CORE_AV_AUD_PAR_BUSCLK_3,
1083 (cfg->aud_par_busclk >> 16), 7, 0);
1084 }
1085
1086 /* Set ACR clock divisor */
1087 REG_FLD_MOD(av_base,
1088 HDMI_CORE_AV_FREQ_SVAL, cfg->mclk_mode, 2, 0);
1089
1090 r = hdmi_read_reg(av_base, HDMI_CORE_AV_ACR_CTRL);
1091 /*
1092 * Use TMDS clock for ACR packets. For devices that use
1093 * the MCLK, this is the first part of the MCLK initialization.
1094 */
1095 r = FLD_MOD(r, 0, 2, 2);
1096
1097 r = FLD_MOD(r, cfg->en_acr_pkt, 1, 1);
1098 r = FLD_MOD(r, cfg->cts_mode, 0, 0);
1099 hdmi_write_reg(av_base, HDMI_CORE_AV_ACR_CTRL, r);
1100
1101 /* For devices using MCLK, this completes its initialization. */
1102 if (cfg->use_mclk)
1103 REG_FLD_MOD(av_base, HDMI_CORE_AV_ACR_CTRL, 1, 2, 2);
1104
1105 /* Override of SPDIF sample frequency with value in I2S_CHST4 */
1106 REG_FLD_MOD(av_base, HDMI_CORE_AV_SPDIF_CTRL,
1107 cfg->fs_override, 1, 1);
1108
1109 /* I2S parameters */
1110 REG_FLD_MOD(av_base, HDMI_CORE_AV_I2S_CHST4,
1111 cfg->freq_sample, 3, 0);
1112
1113 r = hdmi_read_reg(av_base, HDMI_CORE_AV_I2S_IN_CTRL);
1114 r = FLD_MOD(r, cfg->i2s_cfg.en_high_bitrate_aud, 7, 7);
1115 r = FLD_MOD(r, cfg->i2s_cfg.sck_edge_mode, 6, 6);
1116 r = FLD_MOD(r, cfg->i2s_cfg.cbit_order, 5, 5);
1117 r = FLD_MOD(r, cfg->i2s_cfg.vbit, 4, 4);
1118 r = FLD_MOD(r, cfg->i2s_cfg.ws_polarity, 3, 3);
1119 r = FLD_MOD(r, cfg->i2s_cfg.justification, 2, 2);
1120 r = FLD_MOD(r, cfg->i2s_cfg.direction, 1, 1);
1121 r = FLD_MOD(r, cfg->i2s_cfg.shift, 0, 0);
1122 hdmi_write_reg(av_base, HDMI_CORE_AV_I2S_IN_CTRL, r);
1123
1124 r = hdmi_read_reg(av_base, HDMI_CORE_AV_I2S_CHST5);
1125 r = FLD_MOD(r, cfg->freq_sample, 7, 4);
1126 r = FLD_MOD(r, cfg->i2s_cfg.word_length, 3, 1);
1127 r = FLD_MOD(r, cfg->i2s_cfg.word_max_length, 0, 0);
1128 hdmi_write_reg(av_base, HDMI_CORE_AV_I2S_CHST5, r);
1129
1130 REG_FLD_MOD(av_base, HDMI_CORE_AV_I2S_IN_LEN,
1131 cfg->i2s_cfg.in_length_bits, 3, 0);
1132
1133 /* Audio channels and mode parameters */
1134 REG_FLD_MOD(av_base, HDMI_CORE_AV_HDMI_CTRL, cfg->layout, 2, 1);
1135 r = hdmi_read_reg(av_base, HDMI_CORE_AV_AUD_MODE);
1136 r = FLD_MOD(r, cfg->i2s_cfg.active_sds, 7, 4);
1137 r = FLD_MOD(r, cfg->en_dsd_audio, 3, 3);
1138 r = FLD_MOD(r, cfg->en_parallel_aud_input, 2, 2);
1139 r = FLD_MOD(r, cfg->en_spdif, 1, 1);
1140 hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_MODE, r);
1141 }
1142
hdmi_core_audio_infoframe_config(struct hdmi_ip_data * ip_data,struct hdmi_core_infoframe_audio * info_aud)1143 void hdmi_core_audio_infoframe_config(struct hdmi_ip_data *ip_data,
1144 struct hdmi_core_infoframe_audio *info_aud)
1145 {
1146 u8 val;
1147 u8 sum = 0, checksum = 0;
1148 void __iomem *av_base = hdmi_av_base(ip_data);
1149
1150 /*
1151 * Set audio info frame type, version and length as
1152 * described in HDMI 1.4a Section 8.2.2 specification.
1153 * Checksum calculation is defined in Section 5.3.5.
1154 */
1155 hdmi_write_reg(av_base, HDMI_CORE_AV_AUDIO_TYPE, 0x84);
1156 hdmi_write_reg(av_base, HDMI_CORE_AV_AUDIO_VERS, 0x01);
1157 hdmi_write_reg(av_base, HDMI_CORE_AV_AUDIO_LEN, 0x0a);
1158 sum += 0x84 + 0x001 + 0x00a;
1159
1160 val = (info_aud->db1_coding_type << 4)
1161 | (info_aud->db1_channel_count - 1);
1162 hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(0), val);
1163 sum += val;
1164
1165 val = (info_aud->db2_sample_freq << 2) | info_aud->db2_sample_size;
1166 hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(1), val);
1167 sum += val;
1168
1169 hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(2), 0x00);
1170
1171 val = info_aud->db4_channel_alloc;
1172 hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(3), val);
1173 sum += val;
1174
1175 val = (info_aud->db5_downmix_inh << 7) | (info_aud->db5_lsv << 3);
1176 hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(4), val);
1177 sum += val;
1178
1179 hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(5), 0x00);
1180 hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(6), 0x00);
1181 hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(7), 0x00);
1182 hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(8), 0x00);
1183 hdmi_write_reg(av_base, HDMI_CORE_AV_AUD_DBYTE(9), 0x00);
1184
1185 checksum = 0x100 - sum;
1186 hdmi_write_reg(av_base,
1187 HDMI_CORE_AV_AUDIO_CHSUM, checksum);
1188
1189 /*
1190 * TODO: Add MPEG and SPD enable and repeat cfg when EDID parsing
1191 * is available.
1192 */
1193 }
1194
hdmi_config_audio_acr(struct hdmi_ip_data * ip_data,u32 sample_freq,u32 * n,u32 * cts)1195 int hdmi_config_audio_acr(struct hdmi_ip_data *ip_data,
1196 u32 sample_freq, u32 *n, u32 *cts)
1197 {
1198 u32 r;
1199 u32 deep_color = 0;
1200 u32 pclk = ip_data->cfg.timings.pixel_clock;
1201
1202 if (n == NULL || cts == NULL)
1203 return -EINVAL;
1204 /*
1205 * Obtain current deep color configuration. This needed
1206 * to calculate the TMDS clock based on the pixel clock.
1207 */
1208 r = REG_GET(hdmi_wp_base(ip_data), HDMI_WP_VIDEO_CFG, 1, 0);
1209 switch (r) {
1210 case 1: /* No deep color selected */
1211 deep_color = 100;
1212 break;
1213 case 2: /* 10-bit deep color selected */
1214 deep_color = 125;
1215 break;
1216 case 3: /* 12-bit deep color selected */
1217 deep_color = 150;
1218 break;
1219 default:
1220 return -EINVAL;
1221 }
1222
1223 switch (sample_freq) {
1224 case 32000:
1225 if ((deep_color == 125) && ((pclk == 54054)
1226 || (pclk == 74250)))
1227 *n = 8192;
1228 else
1229 *n = 4096;
1230 break;
1231 case 44100:
1232 *n = 6272;
1233 break;
1234 case 48000:
1235 if ((deep_color == 125) && ((pclk == 54054)
1236 || (pclk == 74250)))
1237 *n = 8192;
1238 else
1239 *n = 6144;
1240 break;
1241 default:
1242 *n = 0;
1243 return -EINVAL;
1244 }
1245
1246 /* Calculate CTS. See HDMI 1.3a or 1.4a specifications */
1247 *cts = pclk * (*n / 128) * deep_color / (sample_freq / 10);
1248
1249 return 0;
1250 }
1251
ti_hdmi_4xxx_wp_audio_enable(struct hdmi_ip_data * ip_data,bool enable)1252 void ti_hdmi_4xxx_wp_audio_enable(struct hdmi_ip_data *ip_data, bool enable)
1253 {
1254 REG_FLD_MOD(hdmi_av_base(ip_data),
1255 HDMI_CORE_AV_AUD_MODE, enable, 0, 0);
1256 REG_FLD_MOD(hdmi_wp_base(ip_data),
1257 HDMI_WP_AUDIO_CTRL, enable, 31, 31);
1258 REG_FLD_MOD(hdmi_wp_base(ip_data),
1259 HDMI_WP_AUDIO_CTRL, enable, 30, 30);
1260 }
1261 #endif
1262