Lines Matching refs:reg_field

79 static const struct reg_field por_en = REG_FIELD(WIZ_SERDES_CTRL, 31, 31);
80 static const struct reg_field phy_reset_n = REG_FIELD(WIZ_SERDES_RST, 31, 31);
81 static const struct reg_field phy_en_refclk = REG_FIELD(WIZ_SERDES_RST, 30, 30);
82 static const struct reg_field pll1_refclk_mux_sel =
84 static const struct reg_field pll0_refclk_mux_sel =
86 static const struct reg_field refclk_dig_sel_16g =
88 static const struct reg_field refclk_dig_sel_10g =
90 static const struct reg_field pma_cmn_refclk_int_mode =
92 static const struct reg_field pma_cmn_refclk_mode =
94 static const struct reg_field pma_cmn_refclk_dig_div =
96 static const struct reg_field pma_cmn_refclk1_dig_div =
99 static const struct reg_field sup_pll0_refclk_mux_sel =
101 static const struct reg_field sup_pll1_refclk_mux_sel =
103 static const struct reg_field sup_pma_cmn_refclk1_int_mode =
105 static const struct reg_field sup_refclk_dig_sel_10g =
107 static const struct reg_field sup_legacy_clk_override =
117 static const struct reg_field p_enable[WIZ_MAX_LANES] = {
126 static const struct reg_field p_align[WIZ_MAX_LANES] = {
133 static const struct reg_field p_raw_auto_start[WIZ_MAX_LANES] = {
140 static const struct reg_field p_standard_mode[WIZ_MAX_LANES] = {
147 static const struct reg_field p0_fullrt_div[WIZ_MAX_LANES] = {
154 static const struct reg_field p0_mac_src_sel[WIZ_MAX_LANES] = {
161 static const struct reg_field p0_rxfclk_sel[WIZ_MAX_LANES] = {
168 static const struct reg_field p0_refclk_sel[WIZ_MAX_LANES] = {
174 static const struct reg_field p_mac_div_sel0[WIZ_MAX_LANES] = {
181 static const struct reg_field p_mac_div_sel1[WIZ_MAX_LANES] = {
188 static const struct reg_field typec_ln10_swap =
322 	const struct reg_field *pll0_refclk_mux_sel;
323 	const struct reg_field *pll1_refclk_mux_sel;
324 	const struct reg_field *refclk_dig_sel;
325 	const struct reg_field *pma_cmn_refclk1_dig_div;
326 	const struct reg_field *pma_cmn_refclk1_int_mode;