23 #define dma_outb	outb_p  macro
25 #define dma_outb	outb  macro
171 		dma_outb(dmanr,  DMA1_MASK_REG);  in enable_dma()
173 		dma_outb(dmanr & 3,  DMA2_MASK_REG);  in enable_dma()
179 		dma_outb(dmanr | 4,  DMA1_MASK_REG);  in disable_dma()
181 		dma_outb((dmanr & 3) | 4,  DMA2_MASK_REG);  in disable_dma()
194 		dma_outb(0,  DMA1_CLEAR_FF_REG);  in clear_dma_ff()
196 		dma_outb(0,  DMA2_CLEAR_FF_REG);  in clear_dma_ff()
203 		dma_outb(mode | dmanr,  DMA1_MODE_REG);  in set_dma_mode()
205 		dma_outb(mode | (dmanr&3),  DMA2_MODE_REG);  in set_dma_mode()
217 			dma_outb(pagenr, DMA_PAGE_0);  in set_dma_page()
220 			dma_outb(pagenr, DMA_PAGE_1);  in set_dma_page()
223 			dma_outb(pagenr, DMA_PAGE_2);  in set_dma_page()
226 			dma_outb(pagenr, DMA_PAGE_3);  in set_dma_page()
229 			dma_outb(pagenr & 0xfe, DMA_PAGE_5);  in set_dma_page()
232 			dma_outb(pagenr & 0xfe, DMA_PAGE_6);  in set_dma_page()
235 			dma_outb(pagenr & 0xfe, DMA_PAGE_7);  in set_dma_page()
248 	    dma_outb( a & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE );  in set_dma_addr()
249             dma_outb( (a>>8) & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE );  in set_dma_addr()
251 	    dma_outb( (a>>1) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE );  in set_dma_addr()
252 	    dma_outb( (a>>9) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE );  in set_dma_addr()
269 	    dma_outb( count & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE );  in set_dma_count()
270 	    dma_outb( (count>>8) & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE );  in set_dma_count()
272 	    dma_outb( (count>>1) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE );  in set_dma_count()
273 	    dma_outb( (count>>9) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE );  in set_dma_count()