256 __u8 ReadReg(unsigned int BaseAddr, int iRegNum)  in ReadReg()  argument
258 	return ((__u8) inb(BaseAddr + iRegNum));  in ReadReg()
261 void WriteReg(unsigned int BaseAddr, int iRegNum, unsigned char iVal)  in WriteReg()  argument
263 	outb(iVal, BaseAddr + iRegNum);  in WriteReg()
266 int WriteRegBit(unsigned int BaseAddr, unsigned char RegNum,  in WriteRegBit()  argument
276 	Rtemp = ReadReg(BaseAddr, RegNum);  in WriteRegBit()
285 	WriteReg(BaseAddr, RegNum, Wtemp);  in WriteRegBit()
289 __u8 CheckRegBit(unsigned int BaseAddr, unsigned char RegNum,  in CheckRegBit()  argument
299 	temp = ReadReg(BaseAddr, RegNum);  in CheckRegBit()
455 #define CRC16(BaseAddr,val)         WriteRegBit(BaseAddr,I_CF_L_0,7,val)	//0 for 32 CRC  argument
462 #define SIRFilter(BaseAddr,val)     WriteRegBit(BaseAddr,I_CF_L_0,3,val)  argument
463 #define Filter(BaseAddr,val)        WriteRegBit(BaseAddr,I_CF_L_0,2,val)  argument
464 #define InvertTX(BaseAddr,val)      WriteRegBit(BaseAddr,I_CF_L_0,1,val)  argument
465 #define InvertRX(BaseAddr,val)      WriteRegBit(BaseAddr,I_CF_L_0,0,val)  argument
467 #define EnableTX(BaseAddr,val)      WriteRegBit(BaseAddr,I_CF_H_0,4,val)  argument
468 #define EnableRX(BaseAddr,val)      WriteRegBit(BaseAddr,I_CF_H_0,3,val)  argument
469 #define EnableDMA(BaseAddr,val)     WriteRegBit(BaseAddr,I_CF_H_0,2,val)  argument
470 #define SIRRecvAny(BaseAddr,val)    WriteRegBit(BaseAddr,I_CF_H_0,1,val)  argument
471 #define DiableTrans(BaseAddr,val)   WriteRegBit(BaseAddr,I_CF_H_0,0,val)  argument
473 #define SetSIRBOF(BaseAddr,val)     WriteReg(BaseAddr,I_SIR_BOF,val)  argument
474 #define SetSIREOF(BaseAddr,val)     WriteReg(BaseAddr,I_SIR_EOF,val)  argument
475 #define GetSIRBOF(BaseAddr)        ReadReg(BaseAddr,I_SIR_BOF)  argument
476 #define GetSIREOF(BaseAddr)        ReadReg(BaseAddr,I_SIR_EOF)  argument
478 #define EnPhys(BaseAddr,val)   WriteRegBit(BaseAddr,I_ST_CT_0,7,val)  argument
479 #define IsModeError(BaseAddr) CheckRegBit(BaseAddr,I_ST_CT_0,6)	//RO  argument
480 #define IsVFIROn(BaseAddr)     CheckRegBit(BaseAddr,0x14,0)	//RO for VT1211 only  argument
481 #define IsFIROn(BaseAddr)     CheckRegBit(BaseAddr,I_ST_CT_0,5)	//RO  argument
482 #define IsMIROn(BaseAddr)     CheckRegBit(BaseAddr,I_ST_CT_0,4)	//RO  argument
483 #define IsSIROn(BaseAddr)     CheckRegBit(BaseAddr,I_ST_CT_0,3)	//RO  argument
484 #define IsEnableTX(BaseAddr)  CheckRegBit(BaseAddr,I_ST_CT_0,2)	//RO  argument
485 #define IsEnableRX(BaseAddr)  CheckRegBit(BaseAddr,I_ST_CT_0,1)	//RO  argument
486 #define Is16CRC(BaseAddr)     CheckRegBit(BaseAddr,I_ST_CT_0,0)	//RO  argument
488 #define DisableAdjacentPulseWidth(BaseAddr,val) WriteRegBit(BaseAddr,I_CF_3,5,val)	//1 disable  argument
489 #define DisablePulseWidthAdjust(BaseAddr,val)   WriteRegBit(BaseAddr,I_CF_3,4,val)	//1 disable  argument
490 #define UseOneRX(BaseAddr,val)                  WriteRegBit(BaseAddr,I_CF_3,1,val)	//0 use two RX  argument
491 #define SlowIRRXLowActive(BaseAddr,val)         WriteRegBit(BaseAddr,I_CF_3,0,val)	//0 show RX high…  argument
493 #define EnAllInt(BaseAddr,val)   WriteRegBit(BaseAddr,H_CT,7,val)  argument
494 #define TXStart(BaseAddr,val)    WriteRegBit(BaseAddr,H_CT,6,val)  argument
495 #define RXStart(BaseAddr,val)    WriteRegBit(BaseAddr,H_CT,5,val)  argument
496 #define ClearRXInt(BaseAddr,val)   WriteRegBit(BaseAddr,H_CT,4,val)	// 1 clear  argument
498 #define IsRXInt(BaseAddr)           CheckRegBit(BaseAddr,H_ST,4)  argument
499 #define GetIntIndentify(BaseAddr)   ((ReadReg(BaseAddr,H_ST)&0xf1) >>1)  argument
500 #define IsHostBusy(BaseAddr)        CheckRegBit(BaseAddr,H_ST,0)  argument
501 #define GetHostStatus(BaseAddr)     ReadReg(BaseAddr,H_ST)	//RO  argument
503 #define EnTXDMA(BaseAddr,val)         WriteRegBit(BaseAddr,M_CT,7,val)  argument
504 #define EnRXDMA(BaseAddr,val)         WriteRegBit(BaseAddr,M_CT,6,val)  argument
505 #define SwapDMA(BaseAddr,val)         WriteRegBit(BaseAddr,M_CT,5,val)  argument
506 #define EnInternalLoop(BaseAddr,val)  WriteRegBit(BaseAddr,M_CT,4,val)  argument
507 #define EnExternalLoop(BaseAddr,val)  WriteRegBit(BaseAddr,M_CT,3,val)  argument
509 #define EnTXFIFOHalfLevelInt(BaseAddr,val)   WriteRegBit(BaseAddr,TX_CT_1,4,val)	//half empty int (…  argument
510 #define EnTXFIFOUnderrunEOMInt(BaseAddr,val) WriteRegBit(BaseAddr,TX_CT_1,5,val)  argument
511 #define EnTXFIFOReadyInt(BaseAddr,val)       WriteRegBit(BaseAddr,TX_CT_1,6,val)	//int when reach i…  argument
513 #define ForceUnderrun(BaseAddr,val)   WriteRegBit(BaseAddr,TX_CT_2,7,val)	// force an underrun int  argument
514 #define EnTXCRC(BaseAddr,val)         WriteRegBit(BaseAddr,TX_CT_2,6,val)	//1 for FIR,MIR...0 (not …  argument
515 #define ForceBADCRC(BaseAddr,val)     WriteRegBit(BaseAddr,TX_CT_2,5,val)	//force an bad CRC  argument
516 #define SendSIP(BaseAddr,val)         WriteRegBit(BaseAddr,TX_CT_2,4,val)	//send indication pulse f…  argument
517 #define ClearEnTX(BaseAddr,val)       WriteRegBit(BaseAddr,TX_CT_2,3,val)	// opposite to EnTX  argument
519 #define GetTXStatus(BaseAddr) 	ReadReg(BaseAddr,TX_ST)	//RO  argument
521 #define EnRXSpecInt(BaseAddr,val)           WriteRegBit(BaseAddr,RX_CT,0,val)  argument
522 #define EnRXFIFOReadyInt(BaseAddr,val)      WriteRegBit(BaseAddr,RX_CT,1,val)	//enable int when rea…  argument
523 #define EnRXFIFOHalfLevelInt(BaseAddr,val)  WriteRegBit(BaseAddr,RX_CT,7,val)	//enable int when (1)…  argument
525 #define GetRXStatus(BaseAddr) 	ReadReg(BaseAddr,RX_ST)	//RO  argument
527 #define SetPacketAddr(BaseAddr,addr)        WriteReg(BaseAddr,P_ADDR,addr)  argument
529 #define EnGPIOtoRX2(BaseAddr,val)	WriteRegBit(BaseAddr,I_CF_4,7,val)  argument
530 #define EnTimerInt(BaseAddr,val)		WriteRegBit(BaseAddr,I_CF_4,1,val)  argument
531 #define ClearTimerInt(BaseAddr,val)	WriteRegBit(BaseAddr,I_CF_4,0,val)  argument
533 #define WriteGIO(BaseAddr,val)	    WriteRegBit(BaseAddr,I_T_C_L,7,val)  argument
534 #define ReadGIO(BaseAddr)		    CheckRegBit(BaseAddr,I_T_C_L,7)  argument
535 #define ReadRX(BaseAddr)		    CheckRegBit(BaseAddr,I_T_C_L,3)	//RO  argument
536 #define WriteTX(BaseAddr,val)		WriteRegBit(BaseAddr,I_T_C_L,0,val)  argument
538 #define EnRX2(BaseAddr,val)		    WriteRegBit(BaseAddr,I_T_C_H,7,val)  argument
539 #define ReadRX2(BaseAddr)           CheckRegBit(BaseAddr,I_T_C_H,7)  argument
541 #define GetFIRVersion(BaseAddr)		ReadReg(BaseAddr,VERSION)  argument
985 void SetVFIR(__u16 BaseAddr, __u8 val)  in SetVFIR()  argument
989 	tmp = ReadReg(BaseAddr, I_CF_L_0);  in SetVFIR()
990 	WriteReg(BaseAddr, I_CF_L_0, tmp & 0x8f);  in SetVFIR()
991 	WriteRegBit(BaseAddr, I_CF_H_0, 5, val);  in SetVFIR()
994 void SetFIR(__u16 BaseAddr, __u8 val)  in SetFIR()  argument
998 	WriteRegBit(BaseAddr, I_CF_H_0, 5, 0);  in SetFIR()
999 	tmp = ReadReg(BaseAddr, I_CF_L_0);  in SetFIR()
1000 	WriteReg(BaseAddr, I_CF_L_0, tmp & 0x8f);  in SetFIR()
1001 	WriteRegBit(BaseAddr, I_CF_L_0, 6, val);  in SetFIR()
1004 void SetMIR(__u16 BaseAddr, __u8 val)  in SetMIR()  argument
1008 	WriteRegBit(BaseAddr, I_CF_H_0, 5, 0);  in SetMIR()
1009 	tmp = ReadReg(BaseAddr, I_CF_L_0);  in SetMIR()
1010 	WriteReg(BaseAddr, I_CF_L_0, tmp & 0x8f);  in SetMIR()
1011 	WriteRegBit(BaseAddr, I_CF_L_0, 5, val);  in SetMIR()
1014 void SetSIR(__u16 BaseAddr, __u8 val)  in SetSIR()  argument
1018 	WriteRegBit(BaseAddr, I_CF_H_0, 5, 0);  in SetSIR()
1019 	tmp = ReadReg(BaseAddr, I_CF_L_0);  in SetSIR()
1020 	WriteReg(BaseAddr, I_CF_L_0, tmp & 0x8f);  in SetSIR()
1021 	WriteRegBit(BaseAddr, I_CF_L_0, 4, val);  in SetSIR()