Lines Matching refs:reg_write
584 static inline void reg_write(const struct lanai_dev *lanai, u32 val, in reg_write() function
595 reg_write(lanai, lanai->conf1, Config1_Reg); in conf1_write()
600 reg_write(lanai, lanai->conf2, Config2_Reg); in conf2_write()
606 reg_write(lanai, 0, Reset_Reg); in reset_board()
1210 reg_write(lanai, i, IntControlEna_Reg); in intr_enable()
1215 reg_write(lanai, i, IntControlDis_Reg); in intr_disable()
1401 reg_write(lanai, (ptr << 12) | lvcc->vci, Butt_Reg); in lanai_endtx()
1773 reg_write(lanai, INT_ALL, IntAck_Reg); in lanai_reset()
1792 reg_write(lanai, 0, ServWrite_Reg); in service_buffer_allocate()
1794 reg_write(lanai, in service_buffer_allocate()
1924 reg_write(lanai, wreg, ServRead_Reg); in run_service()
2047 reg_write(lanai, ack, IntAck_Reg); in lanai_int_1()
2297 reg_write(lanai, pcr_to_cbricg(&lanai->cbrvcc->qos), CBR_ICG_Reg); in lanai_cbr_setup()
2298 reg_write(lanai, lanai->cbrvcc->vci, CBR_PTR_Reg); in lanai_cbr_setup()
2353 reg_write(lanai, lanai->conf1 | CONFIG1_GPOUT1, Config1_Reg); in lanai_dev_open()
2378 reg_write(lanai, lanai->conf1 | CONFIG1_GPOUT1, Config1_Reg); in lanai_dev_open()
2399 reg_write(lanai, TX_FIFO_DEPTH, TxDepth_Reg); in lanai_dev_open()
2400 reg_write(lanai, 0, CBR_ICG_Reg); /* CBR defaults to no limit */ in lanai_dev_open()