Lines Matching refs:xcp
170 (xcp->cp0_status & FR_BIT) || !(x & 1) ? \
173 #define SITOREG(si,x) (ctx->regs[x & ~((xcp->cp0_status & FR_BIT) == 0)] = \
174 (xcp->cp0_status & FR_BIT) || !(x & 1) ? \
179 ctx->regs[x & ~((xcp->cp0_status & FR_BIT) == 0)])
180 #define DITOREG(di,x) (ctx->regs[x & ~((xcp->cp0_status & FR_BIT) == 0)] \
183 ctx->regs[x & ~((xcp->cp0_status & FR_BIT) == 0)])
184 #define DITOREG(di,x) (ctx->regs[x & ~((xcp->cp0_status & FR_BIT) == 0)] \
197 static int cop1Emulate(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx) in cop1Emulate() argument
203 if (get_user(ir, (mips_instruction *) xcp->cp0_epc)) { in cop1Emulate()
209 if ((xcp->cp0_cause & CAUSEF_BD) && !isBranchInstr(&ir)) in cop1Emulate()
210 xcp->cp0_cause &= ~CAUSEF_BD; in cop1Emulate()
212 if (xcp->cp0_cause & CAUSEF_BD) { in cop1Emulate()
225 emulpc = REG_TO_VA(xcp->cp0_epc + 4); /* Snapshot emulation target */ in cop1Emulate()
227 if (__compute_return_epc(xcp)) { in cop1Emulate()
230 REG_TO_VA(xcp->cp0_epc)); in cop1Emulate()
239 contpc = REG_TO_VA xcp->cp0_epc; in cop1Emulate()
241 xcp->cp0_epc = VA_TO_REG emulpc - 4; in cop1Emulate()
244 emulpc = REG_TO_VA xcp->cp0_epc; in cop1Emulate()
245 contpc = REG_TO_VA(xcp->cp0_epc + 4); in cop1Emulate()
253 u64 *va = REG_TO_VA(xcp->regs[MIPSInst_RS(ir)] + in cop1Emulate()
267 u64 *va = REG_TO_VA(xcp->regs[MIPSInst_RS(ir)] + in cop1Emulate()
282 u32 *va = REG_TO_VA(xcp->regs[MIPSInst_RS(ir)] + in cop1Emulate()
302 u32 *va = REG_TO_VA(xcp->regs[MIPSInst_RS(ir)] + in cop1Emulate()
328 DIFROMREG(xcp->regs[MIPSInst_RT(ir)], in cop1Emulate()
335 DITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir)); in cop1Emulate()
348 SIFROMREG(xcp->regs[MIPSInst_RT(ir)], in cop1Emulate()
361 SITOREG(xcp->regs[MIPSInst_RT(ir)], MIPSInst_RD(ir)); in cop1Emulate()
369 return do_dsemulret(xcp); in cop1Emulate()
375 REG_TO_VA(xcp->cp0_epc), in cop1Emulate()
384 xcp->regs[MIPSInst_RT(ir)] = value; in cop1Emulate()
395 value = xcp->regs[MIPSInst_RT(ir)]; in cop1Emulate()
402 REG_TO_VA(xcp->cp0_epc), in cop1Emulate()
420 if (xcp->cp0_cause & CAUSEF_BD) in cop1Emulate()
443 xcp->cp0_cause |= CAUSEF_BD; in cop1Emulate()
448 xcp->cp0_epc += 4; in cop1Emulate()
450 (xcp->cp0_epc + in cop1Emulate()
454 REG_TO_VA xcp->cp0_epc)) { in cop1Emulate()
484 return mips_dsemul(xcp, ir, VA_TO_REG contpc); in cop1Emulate()
493 xcp->cp0_epc += 4; in cop1Emulate()
511 if ((sig = fpu_emu(xcp, ctx, ir))) in cop1Emulate()
521 if ((sig = fpux_emu(xcp, ctx, ir))) in cop1Emulate()
533 xcp->regs[MIPSInst_RD(ir)] = in cop1Emulate()
534 xcp->regs[MIPSInst_RS(ir)]; in cop1Emulate()
543 xcp->cp0_epc = VA_TO_REG(contpc); in cop1Emulate()
544 xcp->cp0_cause &= ~CAUSEF_BD; in cop1Emulate()
615 static int fpux_emu(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx, in fpux_emu() argument
632 va = REG_TO_VA(xcp->regs[MIPSInst_FR(ir)] + in fpux_emu()
633 xcp->regs[MIPSInst_FT(ir)]); in fpux_emu()
652 va = REG_TO_VA(xcp->regs[MIPSInst_FR(ir)] + in fpux_emu()
653 xcp->regs[MIPSInst_FT(ir)]); in fpux_emu()
728 va = REG_TO_VA(xcp->regs[MIPSInst_FR(ir)] + in fpux_emu()
729 xcp->regs[MIPSInst_FT(ir)]); in fpux_emu()
740 va = REG_TO_VA(xcp->regs[MIPSInst_FR(ir)] + in fpux_emu()
741 xcp->regs[MIPSInst_FT(ir)]); in fpux_emu()
799 static int fpu_emu(struct pt_regs *xcp, struct mips_fpu_soft_struct *ctx, in fpu_emu() argument
860 if (xcp->regs[MIPSInst_FT(ir)] != 0) in fpu_emu()
865 if (xcp->regs[MIPSInst_FT(ir)] == 0) in fpu_emu()
1050 if (xcp->regs[MIPSInst_FT(ir)] != 0) in fpu_emu()
1055 if (xcp->regs[MIPSInst_FT(ir)] == 0) in fpu_emu()
1283 int fpu_emulator_cop1Handler(int xcptno, struct pt_regs *xcp,
1290 oldepc = xcp->cp0_epc;
1292 prevepc = xcp->cp0_epc;
1294 if (get_user(insn, (mips_instruction *) xcp->cp0_epc)) {
1299 xcp->cp0_epc += 4; /* skip nops */
1306 sig = cop1Emulate(xcp, ctx);
1320 } while (xcp->cp0_epc > prevepc);
1323 if (sig == SIGILL && xcp->cp0_epc != oldepc)