Lines Matching refs:bridge
239 bridge_t *bridge = pcibr_soft->bs_base; in pcibr_error_dump() local
257 int_status_64 = (bridge->p_int_status_64 & ~BRIDGE_ISR_INT_MSK); in pcibr_error_dump()
261 int_status_32 = (bridge->b_int_status & ~BRIDGE_ISR_INT_MSK); in pcibr_error_dump()
315 bridge->p_ate_parity_err_64); in pcibr_error_dump()
321 bridge->b_arb); in pcibr_error_dump()
329 bridge->p_pcix_dma_req_err_addr_64, in pcibr_error_dump()
330 bridge->p_pcix_dma_req_err_attr_64); in pcibr_error_dump()
340 bridge->p_pcix_pio_split_addr_64, in pcibr_error_dump()
341 bridge->p_pcix_pio_split_attr_64); in pcibr_error_dump()
357 bridge->p_pcix_bus_err_addr_64, in pcibr_error_dump()
358 bridge->p_pcix_bus_err_attr_64, in pcibr_error_dump()
359 bridge->p_pcix_bus_err_data_64); in pcibr_error_dump()
369 bridge->b_ram_perr_or_map_fault); in pcibr_error_dump()
373 print_bridge_errcmd(bridge->b_wid_aux_err, "Aux "); in pcibr_error_dump()
381 bridge->p_pcix_dma_req_err_addr_64, in pcibr_error_dump()
382 bridge->p_pcix_dma_req_err_attr_64); in pcibr_error_dump()
389 print_bridge_errcmd(bridge->b_wid_aux_err, "Aux "); in pcibr_error_dump()
401 bridge->p_pcix_dma_req_err_addr_64, in pcibr_error_dump()
402 bridge->p_pcix_dma_req_err_attr_64); in pcibr_error_dump()
404 addr= (((uint64_t)(bridge->b_wid_resp_upper & 0xFFFF)<<32) in pcibr_error_dump()
405 | bridge->b_wid_resp_lower); in pcibr_error_dump()
409 bridge->b_wid_resp_upper, bridge->b_wid_resp_lower, in pcibr_error_dump()
410 ((bridge->b_wid_resp_upper >> 20) & 0x3), in pcibr_error_dump()
411 ((bridge->b_wid_resp_upper >> 16) & 0xF), in pcibr_error_dump()
423 print_bridge_errcmd(bridge->b_wid_err_cmdword, ""); in pcibr_error_dump()
428 (uint64_t) bridge->b_wid_err_upper, in pcibr_error_dump()
429 (uint64_t) bridge->b_wid_err_lower, in pcibr_error_dump()
430 (((uint64_t) bridge->b_wid_err_upper << 32) | in pcibr_error_dump()
431 bridge->b_wid_err_lower)); in pcibr_error_dump()
436 print_bridge_errcmd(bridge->b_wid_aux_err, "Aux "); in pcibr_error_dump()
439 bridge->p_addr_lkerr_64); in pcibr_error_dump()
441 print_bridge_errcmd(bridge->b_wid_err_cmdword, ""); in pcibr_error_dump()
446 (uint64_t) bridge->b_wid_err_upper, in pcibr_error_dump()
447 (uint64_t) bridge->b_wid_err_lower, in pcibr_error_dump()
448 (((uint64_t) bridge->b_wid_err_upper << 32) | in pcibr_error_dump()
449 bridge->b_wid_err_lower)); in pcibr_error_dump()
456 print_bridge_errcmd(bridge->b_wid_aux_err, "Aux "); in pcibr_error_dump()
459 bridge->p_addr_lkerr_64); in pcibr_error_dump()
467 bridge->b_ram_perr); in pcibr_error_dump()
482 (uint64_t) bridge->b_pci_err_upper, in pcibr_error_dump()
483 (uint64_t) bridge->b_pci_err_lower, in pcibr_error_dump()
484 (((uint64_t) bridge->b_pci_err_upper << 32) | in pcibr_error_dump()
485 bridge->b_pci_err_lower)); in pcibr_error_dump()
489 addr = (((uint64_t)(bridge->b_wid_resp_upper & 0xFFFF) << 32) in pcibr_error_dump()
490 | bridge->b_wid_resp_lower); in pcibr_error_dump()
495 bridge->b_wid_resp_upper, bridge->b_wid_resp_lower, in pcibr_error_dump()
496 ((bridge->b_wid_resp_upper >> 20) & 0x3), in pcibr_error_dump()
497 ((bridge->b_wid_resp_upper >> 16) & 0xF), in pcibr_error_dump()
509 mult_int_64 = (bridge->p_mult_int_64 & ~BRIDGE_ISR_INT_MSK); in pcibr_error_dump()
513 mult_int_32 = (bridge->b_mult_int & ~BRIDGE_ISR_INT_MSK); in pcibr_error_dump()
559 bridge_t *bridge; in pcibr_pioerr_check() local
573 bridge = soft->bs_base; in pcibr_pioerr_check()
580 int_status_64 = (bridge->p_int_status_64 & ~BRIDGE_ISR_INT_MSK); in pcibr_pioerr_check()
583 int_status_32 = (bridge->b_int_status & ~BRIDGE_ISR_INT_MSK); in pcibr_pioerr_check()
588 pci_err_lower = bridge->b_pci_err_lower; in pcibr_pioerr_check()
589 pci_err_upper = bridge->b_pci_err_upper; in pcibr_pioerr_check()
646 bridge_t *bridge; in pcibr_error_intr_handler() local
677 bridge = pcibr_soft->bs_base; in pcibr_error_intr_handler()
703 nasid = NASID_GET(bridge); in pcibr_error_intr_handler()
717 int_status_64 = (bridge->p_int_status_64 & ~BRIDGE_ISR_INT_MSK); in pcibr_error_intr_handler()
721 int_status_32 = (bridge->b_int_status & ~BRIDGE_ISR_INT_MSK); in pcibr_error_intr_handler()
889 bridge->p_int_enable_64 &= (picreg_t)(~disable_errintr_mask); in pcibr_error_intr_handler()
891 bridge->b_int_enable &= (bridgereg_t)(~disable_errintr_mask); in pcibr_error_intr_handler()
901 (0x00000000 == bridge->b_wid_err_upper) && in pcibr_error_intr_handler()
902 (0x00C00000 == (0xFFC00000 & bridge->b_wid_err_lower)) && in pcibr_error_intr_handler()
903 (0x00402000 == (0x00F07F00 & bridge->b_wid_err_cmdword))) { in pcibr_error_intr_handler()
918 ((((uint64_t) bridge->b_wid_err_upper << 32) | (bridge->b_wid_err_lower)) in pcibr_error_intr_handler()
959 bridge->p_int_rst_stat_64 = (picreg_t)(int_status | BRIDGE_IRR_MULTI_CLR); in pcibr_error_intr_handler()
961 bridge->b_int_rst_stat = (bridgereg_t)pcibr_errintr_group(int_status); in pcibr_error_intr_handler()
971 bridge->b_arb |= (0xf << 20); in pcibr_error_intr_handler()
981 bridge_t *bridge = pcibr_soft->bs_base; in pcibr_error_cleanup() local
987 bridge->p_int_rst_stat_64 = BRIDGE_IRR_PCI_GRP_CLR | in pcibr_error_cleanup()
991 bridge->b_int_rst_stat = BRIDGE_IRR_PCI_GRP_CLR | BRIDGE_IRR_MULTI_CLR; in pcibr_error_cleanup()
994 (void) bridge->b_wid_tflush; /* flushbus */ in pcibr_error_cleanup()
1086 bridge_t *bridge = pcibr_soft->bs_base; in pcibr_pioerror() local
1427 if (bridge->p_int_status_64 & (picreg_t)BRIDGE_ISR_PCIBUS_PIOERR) in pcibr_pioerror()
1430 if (bridge->b_int_status & (bridgereg_t)BRIDGE_ISR_PCIBUS_PIOERR) in pcibr_pioerror()
1441 bridgereg_t device = bridge->b_device[slot].reg; in pcibr_pioerror()
1494 bridge_t *bridge = pcibr_soft->bs_base; in pcibr_dmard_error() local
1510 ASSERT(bridge); in pcibr_dmard_error()
1515 bus_lowaddr = bridge->b_wid_resp_lower; in pcibr_dmard_error()
1516 bus_uppraddr = bridge->b_wid_resp_upper; in pcibr_dmard_error()
1550 bridge->b_int_rst_stat = BRIDGE_IRR_RESP_BUF_GRP_CLR; in pcibr_dmard_error()
1564 ? &bridge->b_odd_resp in pcibr_dmard_error()
1565 : &bridge->b_even_resp; in pcibr_dmard_error()