680     pub fn read_config(&self, bus_device_function: BusDeviceFunction, register_offset: u16) -> u32 {  in read_config()  method
723     let result = PciArch::read_config(&bus_device_function, STATUS_COMMAND_OFFSET);  in capabilities_offset()
726         let cap_pointer = PciArch::read_config(&bus_device_function, 0x34) as u8 & 0xFC;  in capabilities_offset()
742     let result = PciArch::read_config(&bus_device_function, 0x00);  in pci_read_header()
746     let result = PciArch::read_config(&bus_device_function, 0x04);  in pci_read_header()
750     let result = PciArch::read_config(&bus_device_function, 0x08);  in pci_read_header()
756     let result = PciArch::read_config(&bus_device_function, 0x0c);  in pci_read_header()
822     let cardbus_cis_pointer = PciArch::read_config(bus_device_function, 0x28);  in pci_read_general_device_header()
824     let result = PciArch::read_config(bus_device_function, 0x2c);  in pci_read_general_device_header()
828     let expansion_rom_base_address = PciArch::read_config(bus_device_function, 0x30);  in pci_read_general_device_header()
830     let result = PciArch::read_config(bus_device_function, 0x34);  in pci_read_general_device_header()
835     let reserved2 = PciArch::read_config(bus_device_function, 0x38);  in pci_read_general_device_header()
837     let result = PciArch::read_config(bus_device_function, 0x3c);  in pci_read_general_device_header()
871     let bar0 = PciArch::read_config(bus_device_function, 0x10);  in pci_read_pci_to_pci_bridge_header()
872     let bar1 = PciArch::read_config(bus_device_function, 0x14);  in pci_read_pci_to_pci_bridge_header()
874     let result = PciArch::read_config(bus_device_function, 0x18);  in pci_read_pci_to_pci_bridge_header()
881     let result = PciArch::read_config(bus_device_function, 0x1c);  in pci_read_pci_to_pci_bridge_header()
886     let result = PciArch::read_config(bus_device_function, 0x20);  in pci_read_pci_to_pci_bridge_header()
890     let result = PciArch::read_config(bus_device_function, 0x24);  in pci_read_pci_to_pci_bridge_header()
894     let prefetchable_base_upper_32_bits = PciArch::read_config(bus_device_function, 0x28);  in pci_read_pci_to_pci_bridge_header()
895     let prefetchable_limit_upper_32_bits = PciArch::read_config(bus_device_function, 0x2c);  in pci_read_pci_to_pci_bridge_header()
897     let result = PciArch::read_config(bus_device_function, 0x30);  in pci_read_pci_to_pci_bridge_header()
901     let result = PciArch::read_config(bus_device_function, 0x34);  in pci_read_pci_to_pci_bridge_header()
906     let expansion_rom_base_address = PciArch::read_config(bus_device_function, 0x38);  in pci_read_pci_to_pci_bridge_header()
908     let result = PciArch::read_config(bus_device_function, 0x3c);  in pci_read_pci_to_pci_bridge_header()
952     let cardbus_socket_ex_ca_base_address = PciArch::read_config(busdevicefunction, 0x10);  in pci_read_pci_to_cardbus_bridge_header()
954     let result = PciArch::read_config(busdevicefunction, 0x14);  in pci_read_pci_to_cardbus_bridge_header()
959     let result = PciArch::read_config(busdevicefunction, 0x18);  in pci_read_pci_to_cardbus_bridge_header()
965     let memory_base_address0 = PciArch::read_config(busdevicefunction, 0x1c);  in pci_read_pci_to_cardbus_bridge_header()
966     let memory_limit0 = PciArch::read_config(busdevicefunction, 0x20);  in pci_read_pci_to_cardbus_bridge_header()
967     let memory_base_address1 = PciArch::read_config(busdevicefunction, 0x24);  in pci_read_pci_to_cardbus_bridge_header()
968     let memory_limit1 = PciArch::read_config(busdevicefunction, 0x28);  in pci_read_pci_to_cardbus_bridge_header()
970     let io_base_address0 = PciArch::read_config(busdevicefunction, 0x2c);  in pci_read_pci_to_cardbus_bridge_header()
971     let io_limit0 = PciArch::read_config(busdevicefunction, 0x30);  in pci_read_pci_to_cardbus_bridge_header()
972     let io_base_address1 = PciArch::read_config(busdevicefunction, 0x34);  in pci_read_pci_to_cardbus_bridge_header()
973     let io_limit1 = PciArch::read_config(busdevicefunction, 0x38);  in pci_read_pci_to_cardbus_bridge_header()
974     let result = PciArch::read_config(busdevicefunction, 0x3c);  in pci_read_pci_to_cardbus_bridge_header()
979     let result = PciArch::read_config(busdevicefunction, 0x40);  in pci_read_pci_to_cardbus_bridge_header()
983     let pc_card_legacy_mode_base_address_16_bit = PciArch::read_config(busdevicefunction, 0x44);  in pci_read_pci_to_cardbus_bridge_header()
1382         let bar_orig = PciArch::read_config(&bus_device_function, BAR0_OFFSET + 4 * bar_index);  in pci_bar_init()
1388         let size_mask = PciArch::read_config(&bus_device_function, BAR0_OFFSET + 4 * bar_index);  in pci_bar_init()
1412                     PciArch::read_config(&bus_device_function, BAR0_OFFSET + 4 * (bar_index + 1));  in pci_bar_init()
1510         let capability_header = PciArch::read_config(&self.bus_device_function, offset);  in next()
1558         let capability_header = self.root.read_config(self.bus_device_function, offset);  in next()