1// SPDX-License-Identifier: GPL-2.0 OR X11
2/*
3 * Copyright (C) 2016 Amarula Solutions B.V.
4 * Copyright (C) 2016 Engicam S.r.l.
5 */
6
7/dts-v1/;
8
9#include <dt-bindings/gpio/gpio.h>
10#include <dt-bindings/input/input.h>
11#include "imx6ul.dtsi"
12
13/ {
14	model = "Engicam GEAM6UL Starter Kit";
15	compatible = "engicam,imx6ul-geam", "fsl,imx6ul";
16
17	memory@80000000 {
18		device_type = "memory";
19		reg = <0x80000000 0x08000000>;
20	};
21
22	backlight {
23		compatible = "pwm-backlight";
24		pwms = <&pwm8 0 100000>;
25		brightness-levels = < 0  1  2  3  4  5  6  7  8  9
26				     10 11 12 13 14 15 16 17 18 19
27				     20 21 22 23 24 25 26 27 28 29
28				     30 31 32 33 34 35 36 37 38 39
29				     40 41 42 43 44 45 46 47 48 49
30				     50 51 52 53 54 55 56 57 58 59
31				     60 61 62 63 64 65 66 67 68 69
32				     70 71 72 73 74 75 76 77 78 79
33				     80 81 82 83 84 85 86 87 88 89
34				     90 91 92 93 94 95 96 97 98 99
35				    100>;
36		default-brightness-level = <100>;
37	};
38
39	chosen {
40		stdout-path = &uart1;
41	};
42
43	reg_1p8v: regulator-1p8v {
44		compatible = "regulator-fixed";
45		regulator-name = "1P8V";
46		regulator-min-microvolt = <1800000>;
47		regulator-max-microvolt = <1800000>;
48		regulator-always-on;
49		regulator-boot-on;
50	};
51
52	reg_3p3v: regulator-3p3v {
53		compatible = "regulator-fixed";
54		regulator-name = "3P3V";
55		regulator-min-microvolt = <3300000>;
56		regulator-max-microvolt = <3300000>;
57		regulator-always-on;
58		regulator-boot-on;
59	};
60
61	sound {
62		compatible = "simple-audio-card";
63		simple-audio-card,name = "imx6ul-geam-sgtl5000";
64		simple-audio-card,format = "i2s";
65		simple-audio-card,bitclock-master = <&dailink_master>;
66		simple-audio-card,frame-master = <&dailink_master>;
67		simple-audio-card,widgets =
68			"Microphone", "Mic Jack",
69			"Line", "Line In",
70			"Line", "Line Out",
71			"Headphone", "Headphone Jack";
72		simple-audio-card,routing =
73			"MIC_IN", "Mic Jack",
74			"Mic Jack", "Mic Bias",
75			"Headphone Jack", "HP_OUT";
76
77		simple-audio-card,cpu {
78			sound-dai = <&sai2>;
79		};
80
81		dailink_master: simple-audio-card,codec {
82			sound-dai = <&sgtl5000>;
83			clocks = <&clks IMX6UL_CLK_SAI2>;
84		};
85	};
86};
87
88&can1 {
89	pinctrl-names = "default";
90	pinctrl-0 = <&pinctrl_flexcan1>;
91	xceiver-supply = <&reg_3p3v>;
92	status = "okay";
93};
94
95&can2 {
96	pinctrl-names = "default";
97	pinctrl-0 = <&pinctrl_flexcan2>;
98	xceiver-supply = <&reg_3p3v>;
99	status = "okay";
100};
101
102&fec1 {
103	pinctrl-names = "default";
104	pinctrl-0 = <&pinctrl_enet1>;
105	phy-mode = "rmii";
106	phy-handle = <&ethphy0>;
107	status = "okay";
108};
109
110&fec2 {
111	pinctrl-names = "default";
112	pinctrl-0 = <&pinctrl_enet2>;
113	phy-mode = "rmii";
114	phy-handle = <&ethphy1>;
115	status = "okay";
116
117	mdio {
118		#address-cells = <1>;
119		#size-cells = <0>;
120
121		ethphy0: ethernet-phy@0 {
122			compatible = "ethernet-phy-ieee802.3-c22";
123			reg = <0>;
124		};
125
126		ethphy1: ethernet-phy@1 {
127			compatible = "ethernet-phy-ieee802.3-c22";
128			reg = <1>;
129		};
130	};
131};
132
133&gpmi {
134	pinctrl-names = "default";
135	pinctrl-0 = <&pinctrl_gpmi_nand>;
136	nand-on-flash-bbt;
137	status = "okay";
138};
139
140&i2c1 {
141	clock-frequency = <100000>;
142	pinctrl-names = "default";
143	pinctrl-0 = <&pinctrl_i2c1>;
144	status = "okay";
145
146	sgtl5000: codec@a {
147		compatible = "fsl,sgtl5000";
148		reg = <0x0a>;
149		#sound-dai-cells = <0>;
150		clocks = <&clks IMX6UL_CLK_OSC>;
151		VDDA-supply = <&reg_3p3v>;
152		VDDIO-supply = <&reg_3p3v>;
153		VDDD-supply = <&reg_1p8v>;
154	};
155};
156
157&i2c2 {
158	clock-frequency = <100000>;
159	pinctrl-names = "default";
160	pinctrl-0 = <&pinctrl_i2c2>;
161	status = "okay";
162};
163
164&lcdif {
165	pinctrl-names = "default";
166	pinctrl-0 = <&pinctrl_lcdif_dat
167		     &pinctrl_lcdif_ctrl>;
168	display = <&display0>;
169	status = "okay";
170
171	display0: display0 {
172		bits-per-pixel = <16>;
173		bus-width = <18>;
174
175		display-timings {
176			native-mode = <&timing0>;
177			timing0: timing0 {
178				clock-frequency = <28000000>;
179				hactive = <800>;
180				vactive = <480>;
181				hfront-porch = <30>;
182				hback-porch = <30>;
183				hsync-len = <64>;
184				vback-porch = <5>;
185				vfront-porch = <5>;
186				vsync-len = <20>;
187				hsync-active = <0>;
188				vsync-active = <0>;
189				de-active = <1>;
190				pixelclk-active = <0>;
191			};
192		};
193	};
194};
195
196&pwm8 {
197	#pwm-cells = <2>;
198	pinctrl-names = "default";
199	pinctrl-0 = <&pinctrl_pwm8>;
200	status = "okay";
201};
202
203&tsc {
204	pinctrl-names = "default";
205	pinctrl-0 = <&pinctrl_tsc>;
206	xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
207};
208
209&sai2 {
210	pinctrl-names = "default";
211	pinctrl-0 = <&pinctrl_sai2>;
212	status = "okay";
213};
214
215&tsc {
216	measure-delay-time = <0x1ffff>;
217	pre-charge-time = <0x1fff>;
218	status = "okay";
219};
220
221&uart1 {
222	pinctrl-names = "default";
223	pinctrl-0 = <&pinctrl_uart1>;
224	status = "okay";
225};
226
227&uart2 {
228	pinctrl-names = "default";
229	pinctrl-0 = <&pinctrl_uart2>;
230	status = "okay";
231};
232
233&usbotg1 {
234	dr_mode = "peripheral";
235	status = "okay";
236};
237
238&usbotg2 {
239	dr_mode = "host";
240	status = "okay";
241};
242
243&usdhc1 {
244	pinctrl-names = "default", "state_100mhz", "state_200mhz";
245	pinctrl-0 = <&pinctrl_usdhc1>;
246	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
247	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
248	bus-width = <4>;
249	cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
250	no-1-8-v;
251	status = "okay";
252};
253
254&iomuxc {
255	pinctrl_enet1: enet1grp {
256		fsl,pins = <
257			MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN	0x1b0b0
258			MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00	0x1b0b0
259			MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01	0x1b0b0
260			MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN	0x1b0b0
261			MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00	0x1b0b0
262			MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01	0x1b0b0
263			MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1	0x4001b031
264		>;
265	};
266
267	pinctrl_enet2: enet2grp {
268		fsl,pins = <
269			MX6UL_PAD_GPIO1_IO07__ENET2_MDC		0x1b0b0
270			MX6UL_PAD_GPIO1_IO06__ENET2_MDIO	0x1b0b0
271			MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN	0x1b0b0
272			MX6UL_PAD_ENET2_RX_ER__GPIO2_IO15	0x1b0b0		/* ENET_nRST */
273			MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00	0x1b0b0
274			MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01	0x1b0b0
275			MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN	0x1b0b0
276			MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00	0x1b0b0
277			MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01	0x1b0b0
278			MX6UL_PAD_GPIO1_IO05__ENET2_REF_CLK2	0x4001b031
279		>;
280	};
281
282	pinctrl_flexcan1: flexcan1grp {
283		fsl,pins = <
284			MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX	0x1b020
285			MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX	0x1b020
286		>;
287	};
288
289	pinctrl_flexcan2: flexcan2grp {
290		fsl,pins = <
291			MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX	0x1b020
292			MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX	0x1b020
293		>;
294	};
295
296	pinctrl_gpmi_nand: gpminandgrp {
297		fsl,pins = <
298			MX6UL_PAD_NAND_CLE__RAWNAND_CLE         0xb0b1
299			MX6UL_PAD_NAND_ALE__RAWNAND_ALE         0xb0b1
300			MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B       0xb0b1
301			MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0xb000
302			MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B     0xb0b1
303			MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B       0xb0b1
304			MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B       0xb0b1
305			MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00   0xb0b1
306			MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01   0xb0b1
307			MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02   0xb0b1
308			MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03   0xb0b1
309			MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04   0xb0b1
310			MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05   0xb0b1
311			MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06   0xb0b1
312			MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07   0xb0b1
313		>;
314	};
315
316	pinctrl_i2c1: i2c1grp {
317		fsl,pins = <
318			MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0
319			MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0
320		>;
321	};
322
323	pinctrl_i2c2: i2c2grp {
324			fsl,pins = <
325			MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0
326			MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0
327		>;
328	};
329
330	pinctrl_lcdif_ctrl: lcdifctrlgrp {
331		fsl,pins = <
332			MX6UL_PAD_LCD_CLK__LCDIF_CLK	    0x79
333			MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE  0x79
334			MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC    0x79
335			MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC    0x79
336		>;
337	};
338
339	pinctrl_lcdif_dat: lcdifdatgrp {
340		fsl,pins = <
341			MX6UL_PAD_LCD_DATA00__LCDIF_DATA00  0x79
342			MX6UL_PAD_LCD_DATA01__LCDIF_DATA01  0x79
343			MX6UL_PAD_LCD_DATA02__LCDIF_DATA02  0x79
344			MX6UL_PAD_LCD_DATA03__LCDIF_DATA03  0x79
345			MX6UL_PAD_LCD_DATA04__LCDIF_DATA04  0x79
346			MX6UL_PAD_LCD_DATA05__LCDIF_DATA05  0x79
347			MX6UL_PAD_LCD_DATA06__LCDIF_DATA06  0x79
348			MX6UL_PAD_LCD_DATA07__LCDIF_DATA07  0x79
349			MX6UL_PAD_LCD_DATA08__LCDIF_DATA08  0x79
350			MX6UL_PAD_LCD_DATA09__LCDIF_DATA09  0x79
351			MX6UL_PAD_LCD_DATA10__LCDIF_DATA10  0x79
352			MX6UL_PAD_LCD_DATA11__LCDIF_DATA11  0x79
353			MX6UL_PAD_LCD_DATA12__LCDIF_DATA12  0x79
354			MX6UL_PAD_LCD_DATA13__LCDIF_DATA13  0x79
355			MX6UL_PAD_LCD_DATA14__LCDIF_DATA14  0x79
356			MX6UL_PAD_LCD_DATA15__LCDIF_DATA15  0x79
357			MX6UL_PAD_LCD_DATA16__LCDIF_DATA16  0x79
358			MX6UL_PAD_LCD_DATA17__LCDIF_DATA17  0x79
359		>;
360	};
361
362	pinctrl_pwm8: pwm8grp {
363		fsl,pins = <
364			MX6UL_PAD_ENET1_RX_ER__PWM8_OUT   0x110b0
365		>;
366	};
367
368	pinctrl_tsc: tscgrp {
369		fsl,pin = <
370			MX6UL_PAD_GPIO1_IO01__GPIO1_IO01	0xb0
371			MX6UL_PAD_GPIO1_IO02__GPIO1_IO02	0xb0
372			MX6UL_PAD_GPIO1_IO03__GPIO1_IO03	0xb0
373			MX6UL_PAD_GPIO1_IO04__GPIO1_IO04	0xb0
374		>;
375	};
376
377	pinctrl_sai2: sai2grp {
378		fsl,pins = <
379			MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA	0x130b0
380			MX6UL_PAD_JTAG_TMS__CCM_CLKO1		0x4001b031
381			MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK	0x17088
382			MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC	0x17088
383			MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA	0x120b0
384		>;
385	};
386
387	pinctrl_uart1: uart1grp {
388		fsl,pins = <
389			MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
390			MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
391		>;
392	};
393
394	pinctrl_uart2: uart2grp {
395		fsl,pins = <
396			MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX	0x1b0b1
397			MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX	0x1b0b1
398			MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS	0x1b0b1
399			MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS	0x1b0b1
400		>;
401	};
402
403	pinctrl_usdhc1: usdhc1grp {
404		fsl,pins = <
405			MX6UL_PAD_SD1_CMD__USDHC1_CMD     0x17059
406			MX6UL_PAD_SD1_CLK__USDHC1_CLK     0x10059
407			MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
408			MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
409			MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
410			MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
411		>;
412	};
413
414	pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
415		fsl,pins = <
416			MX6UL_PAD_SD1_CMD__USDHC1_CMD     0x170b9
417			MX6UL_PAD_SD1_CLK__USDHC1_CLK     0x100b9
418			MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9
419			MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
420			MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
421			MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9
422		>;
423	};
424
425	pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
426		fsl,pins = <
427			MX6UL_PAD_SD1_CMD__USDHC1_CMD     0x170f9
428			MX6UL_PAD_SD1_CLK__USDHC1_CLK     0x100f9
429			MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9
430			MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9
431			MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9
432			MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9
433		>;
434	};
435
436	pinctrl_usdhc2: usdhc2grp {
437		fsl,pins = <
438			MX6UL_PAD_CSI_VSYNC__USDHC2_CLK     0x17070
439			MX6UL_PAD_CSI_HSYNC__USDHC2_CMD     0x10070
440			MX6UL_PAD_CSI_DATA00__USDHC2_DATA0  0x17070
441			MX6UL_PAD_CSI_DATA01__USDHC2_DATA1  0x17070
442			MX6UL_PAD_CSI_DATA02__USDHC2_DATA2  0x17070
443			MX6UL_PAD_CSI_DATA03__USDHC2_DATA3  0x17070
444		>;
445	};
446};
447