1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Digi International's ConnectCore6UL SBC Express board device tree source
4 *
5 * Copyright 2018 Digi International, Inc.
6 *
7 */
8
9/dts-v1/;
10#include <dt-bindings/input/input.h>
11#include <dt-bindings/interrupt-controller/irq.h>
12#include "imx6ul.dtsi"
13#include "imx6ul-ccimx6ulsom.dtsi"
14
15/ {
16	model = "Digi International ConnectCore 6UL SBC Express.";
17	compatible = "digi,ccimx6ulsbcexpress", "digi,ccimx6ulsom",
18		     "fsl,imx6ul";
19};
20
21&adc1 {
22	pinctrl-names = "default";
23	pinctrl-0 = <&pinctrl_adc1>;
24	status = "okay";
25};
26
27&can1 {
28	pinctrl-names = "default";
29	pinctrl-0 = <&pinctrl_flexcan1>;
30	xceiver-supply = <&ext_3v3>;
31	status = "okay";
32};
33
34&ecspi3 {
35	cs-gpios = <&gpio1 20 GPIO_ACTIVE_LOW>;
36	pinctrl-names = "default";
37	pinctrl-0 = <&pinctrl_ecspi3_master>;
38	status = "okay";
39};
40
41&fec1 {
42	pinctrl-names = "default";
43	pinctrl-0 = <&pinctrl_enet1>;
44	phy-mode = "rmii";
45	phy-handle = <&ethphy0>;
46	status = "okay";
47
48	mdio {
49		#address-cells = <1>;
50		#size-cells = <0>;
51
52		ethphy0: ethernet-phy@0 {
53			compatible = "ethernet-phy-ieee802.3-c22";
54			smsc,disable-energy-detect;
55			reg = <0>;
56		};
57	};
58};
59
60&i2c2 {
61	pinctrl-names = "default";
62	pinctrl-0 = <&pinctrl_i2c2>;
63	status = "okay";
64};
65
66&pwm1 {
67	pinctrl-names = "default";
68	pinctrl-0 = <&pinctrl_pwm1>;
69	status = "okay";
70};
71
72&uart4 {
73	pinctrl-names = "default";
74	pinctrl-0 = <&pinctrl_uart4>;
75	status = "okay";
76};
77
78&uart5 {
79	pinctrl-names = "default";
80	pinctrl-0 = <&pinctrl_uart5>;
81	status = "okay";
82};
83
84&usbotg1 {
85	dr_mode = "host";
86	disable-over-current;
87	status = "okay";
88};
89
90&usbotg2 {
91	dr_mode = "host";
92	disable-over-current;
93	status = "okay";
94};
95
96&usdhc2 {
97	pinctrl-names = "default";
98	pinctrl-0 = <&pinctrl_usdhc2>;
99	broken-cd;      /* no carrier detect line (use polling) */
100	no-1-8-v;
101	status = "okay";
102};
103
104&iomuxc {
105	pinctrl-names = "default";
106	pinctrl-0 = <&pinctrl_hog>;
107
108	pinctrl_adc1: adc1grp {
109		fsl,pins = <
110			/* GPIO1_4/ADC1_IN4 (pin 7 of the expansion header) */
111			MX6UL_PAD_GPIO1_IO04__GPIO1_IO04        0xb0
112		>;
113	};
114
115	pinctrl_ecspi3_master: ecspi3grp1 {
116		fsl,pins = <
117			MX6UL_PAD_UART2_RX_DATA__ECSPI3_SCLK	0x10b0
118			MX6UL_PAD_UART2_CTS_B__ECSPI3_MOSI	0x10b0
119			MX6UL_PAD_UART2_RTS_B__ECSPI3_MISO	0x10b0
120			MX6UL_PAD_UART2_TX_DATA__GPIO1_IO20	0x10b0 /* Chip Select */
121		>;
122	};
123
124	pinctrl_ecspi3_slave: ecspi3grp2 {
125		fsl,pins = <
126			MX6UL_PAD_UART2_RX_DATA__ECSPI3_SCLK	0x10b0
127			MX6UL_PAD_UART2_CTS_B__ECSPI3_MOSI	0x10b0
128			MX6UL_PAD_UART2_RTS_B__ECSPI3_MISO	0x10b0
129			MX6UL_PAD_UART2_TX_DATA__ECSPI3_SS0	0x10b0 /* Chip Select */
130		>;
131	};
132
133	pinctrl_enet1: enet1grp {
134		fsl,pins = <
135			MX6UL_PAD_GPIO1_IO07__ENET1_MDC		0x1b0b0
136			MX6UL_PAD_GPIO1_IO06__ENET1_MDIO	0x1b0b0
137			MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN	0x1b0b0
138			MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER	0x1b0b0
139			MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00	0x1b0b0
140			MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01	0x1b0b0
141			MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN	0x1b0b0
142			MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00	0x1b0b0
143			MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01	0x1b0b0
144			MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1	0x40017051
145		>;
146	};
147
148	pinctrl_flexcan1: flexcan1grp {
149		fsl,pins = <
150			MX6UL_PAD_LCD_DATA08__FLEXCAN1_TX	0x1b020
151			MX6UL_PAD_LCD_DATA09__FLEXCAN1_RX	0x1b020
152		>;
153	};
154
155	pinctrl_i2c2: i2c2grp {
156		fsl,pins = <
157			MX6UL_PAD_GPIO1_IO00__I2C2_SCL 0x4001b8b0
158			MX6UL_PAD_GPIO1_IO01__I2C2_SDA 0x4001b8b0
159		>;
160	};
161
162	pinctrl_pwm1: pwm1grp {
163		fsl,pins = <
164			MX6UL_PAD_LCD_DATA00__PWM1_OUT		0x10b0
165		>;
166	};
167
168	pinctrl_uart4: uart4grp {
169		fsl,pins = <
170			MX6UL_PAD_LCD_CLK__UART4_DCE_TX		0x1b0b1
171			MX6UL_PAD_LCD_ENABLE__UART4_DCE_RX	0x1b0b1
172		>;
173	};
174
175	pinctrl_uart5: uart5grp {
176		fsl,pins = <
177			MX6UL_PAD_UART5_TX_DATA__UART5_DCE_TX	0x1b0b1
178			MX6UL_PAD_UART5_RX_DATA__UART5_DCE_RX	0x1b0b1
179		>;
180	};
181
182	pinctrl_usdhc2: usdhc2grp {
183		fsl,pins = <
184			MX6UL_PAD_CSI_HSYNC__USDHC2_CMD		0x17059
185			MX6UL_PAD_CSI_VSYNC__USDHC2_CLK		0x10071
186			MX6UL_PAD_CSI_DATA00__USDHC2_DATA0	0x17059
187			MX6UL_PAD_CSI_DATA01__USDHC2_DATA1	0x17059
188			MX6UL_PAD_CSI_DATA02__USDHC2_DATA2	0x17059
189			MX6UL_PAD_CSI_DATA03__USDHC2_DATA3	0x17059
190		>;
191	};
192
193	/* General purpose pinctrl */
194	pinctrl_hog: hoggrp {
195		fsl,pins = <
196			/* GPIOs BANK 3 */
197			MX6UL_PAD_LCD_RESET__GPIO3_IO04		0xf030
198		>;
199	};
200};
201