1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/spi/mediatek,spi-mtk-snfi.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: SPI-NAND flash controller for MediaTek ARM SoCs 8 9maintainers: 10 - Chuanhong Guo <gch981213@gmail.com> 11 12description: | 13 The Mediatek SPI-NAND flash controller is an extended version of 14 the Mediatek NAND flash controller. It can perform standard SPI 15 instructions with one continuous write and one read for up-to 0xa0 16 bytes. It also supports typical SPI-NAND page cache operations 17 in single, dual or quad IO mode with pipelined ECC encoding/decoding 18 using the accompanying ECC engine. There should be only one spi 19 slave device following generic spi bindings. 20 21properties: 22 compatible: 23 enum: 24 - mediatek,mt7622-snand 25 - mediatek,mt7629-snand 26 - mediatek,mt7986-snand 27 28 reg: 29 items: 30 - description: core registers 31 32 interrupts: 33 items: 34 - description: NFI interrupt 35 36 clocks: 37 minItems: 2 38 maxItems: 3 39 40 clock-names: 41 minItems: 2 42 maxItems: 3 43 44 nand-ecc-engine: 45 description: device-tree node of the accompanying ECC engine. 46 $ref: /schemas/types.yaml#/definitions/phandle 47 48 mediatek,rx-latch-latency-ns: 49 description: Data read latch latency, unit is nanoseconds. 50 51required: 52 - compatible 53 - reg 54 - interrupts 55 - clocks 56 - clock-names 57 - nand-ecc-engine 58 59allOf: 60 - $ref: /schemas/spi/spi-controller.yaml# 61 - if: 62 properties: 63 compatible: 64 enum: 65 - mediatek,mt7622-snand 66 - mediatek,mt7629-snand 67 then: 68 properties: 69 clocks: 70 items: 71 - description: clock used for the controller 72 - description: clock used for the SPI bus 73 clock-names: 74 items: 75 - const: nfi_clk 76 - const: pad_clk 77 78 - if: 79 properties: 80 compatible: 81 enum: 82 - mediatek,mt7986-snand 83 then: 84 properties: 85 clocks: 86 items: 87 - description: clock used for the controller 88 - description: clock used for the SPI bus 89 - description: clock used for the AHB bus 90 clock-names: 91 items: 92 - const: nfi_clk 93 - const: pad_clk 94 - const: nfi_hclk 95 96unevaluatedProperties: false 97 98examples: 99 - | 100 #include <dt-bindings/interrupt-controller/irq.h> 101 #include <dt-bindings/interrupt-controller/arm-gic.h> 102 #include <dt-bindings/clock/mt7622-clk.h> 103 soc { 104 #address-cells = <2>; 105 #size-cells = <2>; 106 snfi: spi@1100d000 { 107 compatible = "mediatek,mt7622-snand"; 108 reg = <0 0x1100d000 0 0x1000>; 109 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_LOW>; 110 clocks = <&pericfg CLK_PERI_NFI_PD>, <&pericfg CLK_PERI_SNFI_PD>; 111 clock-names = "nfi_clk", "pad_clk"; 112 nand-ecc-engine = <&bch>; 113 #address-cells = <1>; 114 #size-cells = <0>; 115 116 flash@0 { 117 compatible = "spi-nand"; 118 reg = <0>; 119 spi-tx-bus-width = <4>; 120 spi-rx-bus-width = <4>; 121 nand-ecc-engine = <&snfi>; 122 }; 123 }; 124 }; 125