1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pinctrl/qcom,sm8350-tlmm.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Technologies, Inc. SM8350 TLMM block
8
9maintainers:
10  - Vinod Koul <vkoul@kernel.org>
11
12description:
13  Top Level Mode Multiplexer pin controller in Qualcomm SM8350 SoC.
14
15allOf:
16  - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
17
18properties:
19  compatible:
20    const: qcom,sm8350-tlmm
21
22  reg:
23    maxItems: 1
24
25  interrupts:
26    maxItems: 1
27
28  interrupt-controller: true
29  "#interrupt-cells": true
30  gpio-controller: true
31
32  gpio-reserved-ranges:
33    minItems: 1
34    maxItems: 102
35
36  gpio-line-names:
37    maxItems: 203
38
39  "#gpio-cells": true
40  gpio-ranges: true
41  wakeup-parent: true
42
43required:
44  - compatible
45  - reg
46
47additionalProperties: false
48
49patternProperties:
50  "-state$":
51    oneOf:
52      - $ref: "#/$defs/qcom-sm8350-tlmm-state"
53      - patternProperties:
54          "-pins$":
55            $ref: "#/$defs/qcom-sm8350-tlmm-state"
56        additionalProperties: false
57
58$defs:
59  qcom-sm8350-tlmm-state:
60    type: object
61    description:
62      Pinctrl node's client devices use subnodes for desired pin configuration.
63      Client device subnodes use below standard properties.
64    $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
65    unevaluatedProperties: false
66
67    properties:
68      pins:
69        description:
70          List of gpio pins affected by the properties specified in this
71          subnode.
72        items:
73          oneOf:
74            - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|20[0-2])$"
75            - enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd, sdc2_data ]
76        minItems: 1
77        maxItems: 36
78
79      function:
80        description:
81          Specify the alternative function to be configured for the specified
82          pins.
83
84        enum: [ atest_char, atest_usb, audio_ref, cam_mclk, cci_async,
85                cci_i2c, cci_timer, cmu_rng, coex_uart1, coex_uart2, cri_trng,
86                cri_trng0, cri_trng1, dbg_out, ddr_bist, ddr_pxi0, ddr_pxi1,
87                ddr_pxi2, ddr_pxi3, dp_hot, dp_lcd, gcc_gp1, gcc_gp2, gcc_gp3,
88                gpio, ibi_i3c, jitter_bist, lpass_slimbus, mdp_vsync, mdp_vsync0,
89                mdp_vsync1, mdp_vsync2, mdp_vsync3, mi2s0_data0, mi2s0_data1,
90                mi2s0_sck, mi2s0_ws, mi2s1_data0, mi2s1_data1, mi2s1_sck,
91                mi2s1_ws, mi2s2_data0, mi2s2_data1, mi2s2_sck, mi2s2_ws,
92                mss_grfc0, mss_grfc1, mss_grfc10, mss_grfc11, mss_grfc12,
93                mss_grfc2, mss_grfc3, mss_grfc4, mss_grfc5, mss_grfc6,
94                mss_grfc7, mss_grfc8, mss_grfc9, nav_gpio, pa_indicator,
95                pcie0_clkreqn, pcie1_clkreqn, phase_flag, pll_bist, pll_clk,
96                pri_mi2s, prng_rosc, qdss_cti, qdss_gpio, qlink0_enable,
97                qlink0_request, qlink0_wmss, qlink1_enable, qlink1_request,
98                qlink1_wmss, qlink2_enable, qlink2_request, qlink2_wmss, qspi0,
99                qspi1, qspi2, qspi3, qspi_clk, qspi_cs, qup0, qup1, qup10,
100                qup11, qup12, qup13, qup14, qup15, qup16, qup17, qup18, qup19,
101                qup2, qup3, qup4, qup5, qup6, qup7, qup8, qup9, qup_l4, qup_l5,
102                qup_l6, sd_write, sdc40, sdc41, sdc42, sdc43, sdc4_clk,
103                sdc4_cmd, sec_mi2s, tb_trig, tgu_ch0, tgu_ch1, tgu_ch2,
104                tgu_ch3, tsense_pwm1, tsense_pwm2, uim0_clk, uim0_data,
105                uim0_present, uim0_reset, uim1_clk, uim1_data, uim1_present,
106                uim1_reset, usb2phy_ac, usb_phy, vfr_0, vfr_1, vsense_trigger ]
107
108    required:
109      - pins
110
111examples:
112  - |
113    #include <dt-bindings/interrupt-controller/arm-gic.h>
114    pinctrl@f100000 {
115        compatible = "qcom,sm8350-tlmm";
116        reg = <0x0f100000 0x300000>;
117        interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
118        gpio-controller;
119        #gpio-cells = <2>;
120        interrupt-controller;
121        #interrupt-cells = <2>;
122        gpio-ranges = <&tlmm 0 0 204>; /* GPIOs + ufs_reset */
123
124        gpio-wo-subnode-state {
125            pins = "gpio1";
126            function = "gpio";
127        };
128
129        uart-w-subnodes-state {
130            rx-pins {
131                pins = "gpio18";
132                function = "qup3";
133                bias-pull-up;
134            };
135
136            tx-pins {
137                pins = "gpio19";
138                function = "qup3";
139                bias-disable;
140            };
141        };
142    };
143...
144