1 /* 2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 #ifndef MLX5_IFC_H 33 #define MLX5_IFC_H 34 35 #include "mlx5_ifc_fpga.h" 36 37 enum { 38 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0, 39 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1, 40 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2, 41 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3, 42 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13, 43 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14, 44 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c, 45 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d, 46 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4, 47 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5, 48 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7, 49 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc, 50 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10, 51 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11, 52 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12, 53 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8, 54 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9, 55 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15, 56 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19, 57 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a, 58 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b, 59 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f, 60 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa, 61 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb, 62 MLX5_EVENT_TYPE_CODING_FPGA_ERROR = 0x20, 63 MLX5_EVENT_TYPE_CODING_FPGA_QP_ERROR = 0x21 64 }; 65 66 enum { 67 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0, 68 MLX5_SET_HCA_CAP_OP_MOD_ODP = 0x2, 69 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3, 70 MLX5_SET_HCA_CAP_OP_MOD_ROCE = 0x4, 71 MLX5_SET_HCA_CAP_OP_MODE_PORT_SELECTION = 0x25, 72 }; 73 74 enum { 75 MLX5_SHARED_RESOURCE_UID = 0xffff, 76 }; 77 78 enum { 79 MLX5_OBJ_TYPE_SW_ICM = 0x0008, 80 }; 81 82 enum { 83 MLX5_GENERAL_OBJ_TYPES_CAP_SW_ICM = (1ULL << MLX5_OBJ_TYPE_SW_ICM), 84 MLX5_GENERAL_OBJ_TYPES_CAP_GENEVE_TLV_OPT = (1ULL << 11), 85 MLX5_GENERAL_OBJ_TYPES_CAP_VIRTIO_NET_Q = (1ULL << 13), 86 MLX5_GENERAL_OBJ_TYPES_CAP_MACSEC_OFFLOAD = (1ULL << 39), 87 }; 88 89 enum { 90 MLX5_OBJ_TYPE_GENEVE_TLV_OPT = 0x000b, 91 MLX5_OBJ_TYPE_VIRTIO_NET_Q = 0x000d, 92 MLX5_OBJ_TYPE_VIRTIO_Q_COUNTERS = 0x001c, 93 MLX5_OBJ_TYPE_MATCH_DEFINER = 0x0018, 94 MLX5_OBJ_TYPE_PAGE_TRACK = 0x46, 95 MLX5_OBJ_TYPE_MKEY = 0xff01, 96 MLX5_OBJ_TYPE_QP = 0xff02, 97 MLX5_OBJ_TYPE_PSV = 0xff03, 98 MLX5_OBJ_TYPE_RMP = 0xff04, 99 MLX5_OBJ_TYPE_XRC_SRQ = 0xff05, 100 MLX5_OBJ_TYPE_RQ = 0xff06, 101 MLX5_OBJ_TYPE_SQ = 0xff07, 102 MLX5_OBJ_TYPE_TIR = 0xff08, 103 MLX5_OBJ_TYPE_TIS = 0xff09, 104 MLX5_OBJ_TYPE_DCT = 0xff0a, 105 MLX5_OBJ_TYPE_XRQ = 0xff0b, 106 MLX5_OBJ_TYPE_RQT = 0xff0e, 107 MLX5_OBJ_TYPE_FLOW_COUNTER = 0xff0f, 108 MLX5_OBJ_TYPE_CQ = 0xff10, 109 }; 110 111 enum { 112 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100, 113 MLX5_CMD_OP_QUERY_ADAPTER = 0x101, 114 MLX5_CMD_OP_INIT_HCA = 0x102, 115 MLX5_CMD_OP_TEARDOWN_HCA = 0x103, 116 MLX5_CMD_OP_ENABLE_HCA = 0x104, 117 MLX5_CMD_OP_DISABLE_HCA = 0x105, 118 MLX5_CMD_OP_QUERY_PAGES = 0x107, 119 MLX5_CMD_OP_MANAGE_PAGES = 0x108, 120 MLX5_CMD_OP_SET_HCA_CAP = 0x109, 121 MLX5_CMD_OP_QUERY_ISSI = 0x10a, 122 MLX5_CMD_OP_SET_ISSI = 0x10b, 123 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d, 124 MLX5_CMD_OP_QUERY_SF_PARTITION = 0x111, 125 MLX5_CMD_OP_ALLOC_SF = 0x113, 126 MLX5_CMD_OP_DEALLOC_SF = 0x114, 127 MLX5_CMD_OP_SUSPEND_VHCA = 0x115, 128 MLX5_CMD_OP_RESUME_VHCA = 0x116, 129 MLX5_CMD_OP_QUERY_VHCA_MIGRATION_STATE = 0x117, 130 MLX5_CMD_OP_SAVE_VHCA_STATE = 0x118, 131 MLX5_CMD_OP_LOAD_VHCA_STATE = 0x119, 132 MLX5_CMD_OP_CREATE_MKEY = 0x200, 133 MLX5_CMD_OP_QUERY_MKEY = 0x201, 134 MLX5_CMD_OP_DESTROY_MKEY = 0x202, 135 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203, 136 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204, 137 MLX5_CMD_OP_ALLOC_MEMIC = 0x205, 138 MLX5_CMD_OP_DEALLOC_MEMIC = 0x206, 139 MLX5_CMD_OP_MODIFY_MEMIC = 0x207, 140 MLX5_CMD_OP_CREATE_EQ = 0x301, 141 MLX5_CMD_OP_DESTROY_EQ = 0x302, 142 MLX5_CMD_OP_QUERY_EQ = 0x303, 143 MLX5_CMD_OP_GEN_EQE = 0x304, 144 MLX5_CMD_OP_CREATE_CQ = 0x400, 145 MLX5_CMD_OP_DESTROY_CQ = 0x401, 146 MLX5_CMD_OP_QUERY_CQ = 0x402, 147 MLX5_CMD_OP_MODIFY_CQ = 0x403, 148 MLX5_CMD_OP_CREATE_QP = 0x500, 149 MLX5_CMD_OP_DESTROY_QP = 0x501, 150 MLX5_CMD_OP_RST2INIT_QP = 0x502, 151 MLX5_CMD_OP_INIT2RTR_QP = 0x503, 152 MLX5_CMD_OP_RTR2RTS_QP = 0x504, 153 MLX5_CMD_OP_RTS2RTS_QP = 0x505, 154 MLX5_CMD_OP_SQERR2RTS_QP = 0x506, 155 MLX5_CMD_OP_2ERR_QP = 0x507, 156 MLX5_CMD_OP_2RST_QP = 0x50a, 157 MLX5_CMD_OP_QUERY_QP = 0x50b, 158 MLX5_CMD_OP_SQD_RTS_QP = 0x50c, 159 MLX5_CMD_OP_INIT2INIT_QP = 0x50e, 160 MLX5_CMD_OP_CREATE_PSV = 0x600, 161 MLX5_CMD_OP_DESTROY_PSV = 0x601, 162 MLX5_CMD_OP_CREATE_SRQ = 0x700, 163 MLX5_CMD_OP_DESTROY_SRQ = 0x701, 164 MLX5_CMD_OP_QUERY_SRQ = 0x702, 165 MLX5_CMD_OP_ARM_RQ = 0x703, 166 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705, 167 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706, 168 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707, 169 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708, 170 MLX5_CMD_OP_CREATE_DCT = 0x710, 171 MLX5_CMD_OP_DESTROY_DCT = 0x711, 172 MLX5_CMD_OP_DRAIN_DCT = 0x712, 173 MLX5_CMD_OP_QUERY_DCT = 0x713, 174 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714, 175 MLX5_CMD_OP_CREATE_XRQ = 0x717, 176 MLX5_CMD_OP_DESTROY_XRQ = 0x718, 177 MLX5_CMD_OP_QUERY_XRQ = 0x719, 178 MLX5_CMD_OP_ARM_XRQ = 0x71a, 179 MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY = 0x725, 180 MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY = 0x726, 181 MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS = 0x727, 182 MLX5_CMD_OP_RELEASE_XRQ_ERROR = 0x729, 183 MLX5_CMD_OP_MODIFY_XRQ = 0x72a, 184 MLX5_CMD_OP_QUERY_ESW_FUNCTIONS = 0x740, 185 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750, 186 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751, 187 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752, 188 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753, 189 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754, 190 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755, 191 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760, 192 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761, 193 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762, 194 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763, 195 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764, 196 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765, 197 MLX5_CMD_OP_QUERY_VNIC_ENV = 0x76f, 198 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770, 199 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771, 200 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772, 201 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773, 202 MLX5_CMD_OP_SET_MONITOR_COUNTER = 0x774, 203 MLX5_CMD_OP_ARM_MONITOR_COUNTER = 0x775, 204 MLX5_CMD_OP_SET_PP_RATE_LIMIT = 0x780, 205 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781, 206 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782, 207 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783, 208 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784, 209 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785, 210 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786, 211 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787, 212 MLX5_CMD_OP_ALLOC_PD = 0x800, 213 MLX5_CMD_OP_DEALLOC_PD = 0x801, 214 MLX5_CMD_OP_ALLOC_UAR = 0x802, 215 MLX5_CMD_OP_DEALLOC_UAR = 0x803, 216 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804, 217 MLX5_CMD_OP_ACCESS_REG = 0x805, 218 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806, 219 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807, 220 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a, 221 MLX5_CMD_OP_MAD_IFC = 0x50d, 222 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b, 223 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c, 224 MLX5_CMD_OP_NOP = 0x80d, 225 MLX5_CMD_OP_ALLOC_XRCD = 0x80e, 226 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f, 227 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816, 228 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817, 229 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822, 230 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823, 231 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824, 232 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825, 233 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826, 234 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827, 235 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828, 236 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829, 237 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a, 238 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b, 239 MLX5_CMD_OP_SET_WOL_ROL = 0x830, 240 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831, 241 MLX5_CMD_OP_CREATE_LAG = 0x840, 242 MLX5_CMD_OP_MODIFY_LAG = 0x841, 243 MLX5_CMD_OP_QUERY_LAG = 0x842, 244 MLX5_CMD_OP_DESTROY_LAG = 0x843, 245 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844, 246 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845, 247 MLX5_CMD_OP_CREATE_TIR = 0x900, 248 MLX5_CMD_OP_MODIFY_TIR = 0x901, 249 MLX5_CMD_OP_DESTROY_TIR = 0x902, 250 MLX5_CMD_OP_QUERY_TIR = 0x903, 251 MLX5_CMD_OP_CREATE_SQ = 0x904, 252 MLX5_CMD_OP_MODIFY_SQ = 0x905, 253 MLX5_CMD_OP_DESTROY_SQ = 0x906, 254 MLX5_CMD_OP_QUERY_SQ = 0x907, 255 MLX5_CMD_OP_CREATE_RQ = 0x908, 256 MLX5_CMD_OP_MODIFY_RQ = 0x909, 257 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910, 258 MLX5_CMD_OP_DESTROY_RQ = 0x90a, 259 MLX5_CMD_OP_QUERY_RQ = 0x90b, 260 MLX5_CMD_OP_CREATE_RMP = 0x90c, 261 MLX5_CMD_OP_MODIFY_RMP = 0x90d, 262 MLX5_CMD_OP_DESTROY_RMP = 0x90e, 263 MLX5_CMD_OP_QUERY_RMP = 0x90f, 264 MLX5_CMD_OP_CREATE_TIS = 0x912, 265 MLX5_CMD_OP_MODIFY_TIS = 0x913, 266 MLX5_CMD_OP_DESTROY_TIS = 0x914, 267 MLX5_CMD_OP_QUERY_TIS = 0x915, 268 MLX5_CMD_OP_CREATE_RQT = 0x916, 269 MLX5_CMD_OP_MODIFY_RQT = 0x917, 270 MLX5_CMD_OP_DESTROY_RQT = 0x918, 271 MLX5_CMD_OP_QUERY_RQT = 0x919, 272 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f, 273 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930, 274 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931, 275 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932, 276 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933, 277 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934, 278 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935, 279 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936, 280 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937, 281 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938, 282 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939, 283 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a, 284 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b, 285 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c, 286 MLX5_CMD_OP_ALLOC_PACKET_REFORMAT_CONTEXT = 0x93d, 287 MLX5_CMD_OP_DEALLOC_PACKET_REFORMAT_CONTEXT = 0x93e, 288 MLX5_CMD_OP_QUERY_PACKET_REFORMAT_CONTEXT = 0x93f, 289 MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940, 290 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941, 291 MLX5_CMD_OP_QUERY_MODIFY_HEADER_CONTEXT = 0x942, 292 MLX5_CMD_OP_FPGA_CREATE_QP = 0x960, 293 MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961, 294 MLX5_CMD_OP_FPGA_QUERY_QP = 0x962, 295 MLX5_CMD_OP_FPGA_DESTROY_QP = 0x963, 296 MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS = 0x964, 297 MLX5_CMD_OP_CREATE_GENERAL_OBJECT = 0xa00, 298 MLX5_CMD_OP_MODIFY_GENERAL_OBJECT = 0xa01, 299 MLX5_CMD_OP_QUERY_GENERAL_OBJECT = 0xa02, 300 MLX5_CMD_OP_DESTROY_GENERAL_OBJECT = 0xa03, 301 MLX5_CMD_OP_CREATE_UCTX = 0xa04, 302 MLX5_CMD_OP_DESTROY_UCTX = 0xa06, 303 MLX5_CMD_OP_CREATE_UMEM = 0xa08, 304 MLX5_CMD_OP_DESTROY_UMEM = 0xa0a, 305 MLX5_CMD_OP_SYNC_STEERING = 0xb00, 306 MLX5_CMD_OP_QUERY_VHCA_STATE = 0xb0d, 307 MLX5_CMD_OP_MODIFY_VHCA_STATE = 0xb0e, 308 MLX5_CMD_OP_MAX 309 }; 310 311 /* Valid range for general commands that don't work over an object */ 312 enum { 313 MLX5_CMD_OP_GENERAL_START = 0xb00, 314 MLX5_CMD_OP_GENERAL_END = 0xd00, 315 }; 316 317 struct mlx5_ifc_flow_table_fields_supported_bits { 318 u8 outer_dmac[0x1]; 319 u8 outer_smac[0x1]; 320 u8 outer_ether_type[0x1]; 321 u8 outer_ip_version[0x1]; 322 u8 outer_first_prio[0x1]; 323 u8 outer_first_cfi[0x1]; 324 u8 outer_first_vid[0x1]; 325 u8 outer_ipv4_ttl[0x1]; 326 u8 outer_second_prio[0x1]; 327 u8 outer_second_cfi[0x1]; 328 u8 outer_second_vid[0x1]; 329 u8 reserved_at_b[0x1]; 330 u8 outer_sip[0x1]; 331 u8 outer_dip[0x1]; 332 u8 outer_frag[0x1]; 333 u8 outer_ip_protocol[0x1]; 334 u8 outer_ip_ecn[0x1]; 335 u8 outer_ip_dscp[0x1]; 336 u8 outer_udp_sport[0x1]; 337 u8 outer_udp_dport[0x1]; 338 u8 outer_tcp_sport[0x1]; 339 u8 outer_tcp_dport[0x1]; 340 u8 outer_tcp_flags[0x1]; 341 u8 outer_gre_protocol[0x1]; 342 u8 outer_gre_key[0x1]; 343 u8 outer_vxlan_vni[0x1]; 344 u8 outer_geneve_vni[0x1]; 345 u8 outer_geneve_oam[0x1]; 346 u8 outer_geneve_protocol_type[0x1]; 347 u8 outer_geneve_opt_len[0x1]; 348 u8 source_vhca_port[0x1]; 349 u8 source_eswitch_port[0x1]; 350 351 u8 inner_dmac[0x1]; 352 u8 inner_smac[0x1]; 353 u8 inner_ether_type[0x1]; 354 u8 inner_ip_version[0x1]; 355 u8 inner_first_prio[0x1]; 356 u8 inner_first_cfi[0x1]; 357 u8 inner_first_vid[0x1]; 358 u8 reserved_at_27[0x1]; 359 u8 inner_second_prio[0x1]; 360 u8 inner_second_cfi[0x1]; 361 u8 inner_second_vid[0x1]; 362 u8 reserved_at_2b[0x1]; 363 u8 inner_sip[0x1]; 364 u8 inner_dip[0x1]; 365 u8 inner_frag[0x1]; 366 u8 inner_ip_protocol[0x1]; 367 u8 inner_ip_ecn[0x1]; 368 u8 inner_ip_dscp[0x1]; 369 u8 inner_udp_sport[0x1]; 370 u8 inner_udp_dport[0x1]; 371 u8 inner_tcp_sport[0x1]; 372 u8 inner_tcp_dport[0x1]; 373 u8 inner_tcp_flags[0x1]; 374 u8 reserved_at_37[0x9]; 375 376 u8 geneve_tlv_option_0_data[0x1]; 377 u8 geneve_tlv_option_0_exist[0x1]; 378 u8 reserved_at_42[0x3]; 379 u8 outer_first_mpls_over_udp[0x4]; 380 u8 outer_first_mpls_over_gre[0x4]; 381 u8 inner_first_mpls[0x4]; 382 u8 outer_first_mpls[0x4]; 383 u8 reserved_at_55[0x2]; 384 u8 outer_esp_spi[0x1]; 385 u8 reserved_at_58[0x2]; 386 u8 bth_dst_qp[0x1]; 387 u8 reserved_at_5b[0x5]; 388 389 u8 reserved_at_60[0x18]; 390 u8 metadata_reg_c_7[0x1]; 391 u8 metadata_reg_c_6[0x1]; 392 u8 metadata_reg_c_5[0x1]; 393 u8 metadata_reg_c_4[0x1]; 394 u8 metadata_reg_c_3[0x1]; 395 u8 metadata_reg_c_2[0x1]; 396 u8 metadata_reg_c_1[0x1]; 397 u8 metadata_reg_c_0[0x1]; 398 }; 399 400 struct mlx5_ifc_flow_table_fields_supported_2_bits { 401 u8 reserved_at_0[0xe]; 402 u8 bth_opcode[0x1]; 403 u8 reserved_at_f[0x11]; 404 405 u8 reserved_at_20[0x60]; 406 }; 407 408 struct mlx5_ifc_flow_table_prop_layout_bits { 409 u8 ft_support[0x1]; 410 u8 reserved_at_1[0x1]; 411 u8 flow_counter[0x1]; 412 u8 flow_modify_en[0x1]; 413 u8 modify_root[0x1]; 414 u8 identified_miss_table_mode[0x1]; 415 u8 flow_table_modify[0x1]; 416 u8 reformat[0x1]; 417 u8 decap[0x1]; 418 u8 reserved_at_9[0x1]; 419 u8 pop_vlan[0x1]; 420 u8 push_vlan[0x1]; 421 u8 reserved_at_c[0x1]; 422 u8 pop_vlan_2[0x1]; 423 u8 push_vlan_2[0x1]; 424 u8 reformat_and_vlan_action[0x1]; 425 u8 reserved_at_10[0x1]; 426 u8 sw_owner[0x1]; 427 u8 reformat_l3_tunnel_to_l2[0x1]; 428 u8 reformat_l2_to_l3_tunnel[0x1]; 429 u8 reformat_and_modify_action[0x1]; 430 u8 ignore_flow_level[0x1]; 431 u8 reserved_at_16[0x1]; 432 u8 table_miss_action_domain[0x1]; 433 u8 termination_table[0x1]; 434 u8 reformat_and_fwd_to_table[0x1]; 435 u8 reserved_at_1a[0x2]; 436 u8 ipsec_encrypt[0x1]; 437 u8 ipsec_decrypt[0x1]; 438 u8 sw_owner_v2[0x1]; 439 u8 reserved_at_1f[0x1]; 440 441 u8 termination_table_raw_traffic[0x1]; 442 u8 reserved_at_21[0x1]; 443 u8 log_max_ft_size[0x6]; 444 u8 log_max_modify_header_context[0x8]; 445 u8 max_modify_header_actions[0x8]; 446 u8 max_ft_level[0x8]; 447 448 u8 reserved_at_40[0x6]; 449 u8 execute_aso[0x1]; 450 u8 reserved_at_47[0x19]; 451 452 u8 reserved_at_60[0x2]; 453 u8 reformat_insert[0x1]; 454 u8 reformat_remove[0x1]; 455 u8 macsec_encrypt[0x1]; 456 u8 macsec_decrypt[0x1]; 457 u8 reserved_at_66[0x2]; 458 u8 reformat_add_macsec[0x1]; 459 u8 reformat_remove_macsec[0x1]; 460 u8 reserved_at_6a[0xe]; 461 u8 log_max_ft_num[0x8]; 462 463 u8 reserved_at_80[0x10]; 464 u8 log_max_flow_counter[0x8]; 465 u8 log_max_destination[0x8]; 466 467 u8 reserved_at_a0[0x18]; 468 u8 log_max_flow[0x8]; 469 470 u8 reserved_at_c0[0x40]; 471 472 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support; 473 474 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support; 475 }; 476 477 struct mlx5_ifc_odp_per_transport_service_cap_bits { 478 u8 send[0x1]; 479 u8 receive[0x1]; 480 u8 write[0x1]; 481 u8 read[0x1]; 482 u8 atomic[0x1]; 483 u8 srq_receive[0x1]; 484 u8 reserved_at_6[0x1a]; 485 }; 486 487 struct mlx5_ifc_ipv4_layout_bits { 488 u8 reserved_at_0[0x60]; 489 490 u8 ipv4[0x20]; 491 }; 492 493 struct mlx5_ifc_ipv6_layout_bits { 494 u8 ipv6[16][0x8]; 495 }; 496 497 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits { 498 struct mlx5_ifc_ipv6_layout_bits ipv6_layout; 499 struct mlx5_ifc_ipv4_layout_bits ipv4_layout; 500 u8 reserved_at_0[0x80]; 501 }; 502 503 struct mlx5_ifc_fte_match_set_lyr_2_4_bits { 504 u8 smac_47_16[0x20]; 505 506 u8 smac_15_0[0x10]; 507 u8 ethertype[0x10]; 508 509 u8 dmac_47_16[0x20]; 510 511 u8 dmac_15_0[0x10]; 512 u8 first_prio[0x3]; 513 u8 first_cfi[0x1]; 514 u8 first_vid[0xc]; 515 516 u8 ip_protocol[0x8]; 517 u8 ip_dscp[0x6]; 518 u8 ip_ecn[0x2]; 519 u8 cvlan_tag[0x1]; 520 u8 svlan_tag[0x1]; 521 u8 frag[0x1]; 522 u8 ip_version[0x4]; 523 u8 tcp_flags[0x9]; 524 525 u8 tcp_sport[0x10]; 526 u8 tcp_dport[0x10]; 527 528 u8 reserved_at_c0[0x10]; 529 u8 ipv4_ihl[0x4]; 530 u8 reserved_at_c4[0x4]; 531 532 u8 ttl_hoplimit[0x8]; 533 534 u8 udp_sport[0x10]; 535 u8 udp_dport[0x10]; 536 537 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6; 538 539 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6; 540 }; 541 542 struct mlx5_ifc_nvgre_key_bits { 543 u8 hi[0x18]; 544 u8 lo[0x8]; 545 }; 546 547 union mlx5_ifc_gre_key_bits { 548 struct mlx5_ifc_nvgre_key_bits nvgre; 549 u8 key[0x20]; 550 }; 551 552 struct mlx5_ifc_fte_match_set_misc_bits { 553 u8 gre_c_present[0x1]; 554 u8 reserved_at_1[0x1]; 555 u8 gre_k_present[0x1]; 556 u8 gre_s_present[0x1]; 557 u8 source_vhca_port[0x4]; 558 u8 source_sqn[0x18]; 559 560 u8 source_eswitch_owner_vhca_id[0x10]; 561 u8 source_port[0x10]; 562 563 u8 outer_second_prio[0x3]; 564 u8 outer_second_cfi[0x1]; 565 u8 outer_second_vid[0xc]; 566 u8 inner_second_prio[0x3]; 567 u8 inner_second_cfi[0x1]; 568 u8 inner_second_vid[0xc]; 569 570 u8 outer_second_cvlan_tag[0x1]; 571 u8 inner_second_cvlan_tag[0x1]; 572 u8 outer_second_svlan_tag[0x1]; 573 u8 inner_second_svlan_tag[0x1]; 574 u8 reserved_at_64[0xc]; 575 u8 gre_protocol[0x10]; 576 577 union mlx5_ifc_gre_key_bits gre_key; 578 579 u8 vxlan_vni[0x18]; 580 u8 bth_opcode[0x8]; 581 582 u8 geneve_vni[0x18]; 583 u8 reserved_at_d8[0x6]; 584 u8 geneve_tlv_option_0_exist[0x1]; 585 u8 geneve_oam[0x1]; 586 587 u8 reserved_at_e0[0xc]; 588 u8 outer_ipv6_flow_label[0x14]; 589 590 u8 reserved_at_100[0xc]; 591 u8 inner_ipv6_flow_label[0x14]; 592 593 u8 reserved_at_120[0xa]; 594 u8 geneve_opt_len[0x6]; 595 u8 geneve_protocol_type[0x10]; 596 597 u8 reserved_at_140[0x8]; 598 u8 bth_dst_qp[0x18]; 599 u8 reserved_at_160[0x20]; 600 u8 outer_esp_spi[0x20]; 601 u8 reserved_at_1a0[0x60]; 602 }; 603 604 struct mlx5_ifc_fte_match_mpls_bits { 605 u8 mpls_label[0x14]; 606 u8 mpls_exp[0x3]; 607 u8 mpls_s_bos[0x1]; 608 u8 mpls_ttl[0x8]; 609 }; 610 611 struct mlx5_ifc_fte_match_set_misc2_bits { 612 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls; 613 614 struct mlx5_ifc_fte_match_mpls_bits inner_first_mpls; 615 616 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_gre; 617 618 struct mlx5_ifc_fte_match_mpls_bits outer_first_mpls_over_udp; 619 620 u8 metadata_reg_c_7[0x20]; 621 622 u8 metadata_reg_c_6[0x20]; 623 624 u8 metadata_reg_c_5[0x20]; 625 626 u8 metadata_reg_c_4[0x20]; 627 628 u8 metadata_reg_c_3[0x20]; 629 630 u8 metadata_reg_c_2[0x20]; 631 632 u8 metadata_reg_c_1[0x20]; 633 634 u8 metadata_reg_c_0[0x20]; 635 636 u8 metadata_reg_a[0x20]; 637 638 u8 reserved_at_1a0[0x8]; 639 640 u8 macsec_syndrome[0x8]; 641 642 u8 reserved_at_1b0[0x50]; 643 }; 644 645 struct mlx5_ifc_fte_match_set_misc3_bits { 646 u8 inner_tcp_seq_num[0x20]; 647 648 u8 outer_tcp_seq_num[0x20]; 649 650 u8 inner_tcp_ack_num[0x20]; 651 652 u8 outer_tcp_ack_num[0x20]; 653 654 u8 reserved_at_80[0x8]; 655 u8 outer_vxlan_gpe_vni[0x18]; 656 657 u8 outer_vxlan_gpe_next_protocol[0x8]; 658 u8 outer_vxlan_gpe_flags[0x8]; 659 u8 reserved_at_b0[0x10]; 660 661 u8 icmp_header_data[0x20]; 662 663 u8 icmpv6_header_data[0x20]; 664 665 u8 icmp_type[0x8]; 666 u8 icmp_code[0x8]; 667 u8 icmpv6_type[0x8]; 668 u8 icmpv6_code[0x8]; 669 670 u8 geneve_tlv_option_0_data[0x20]; 671 672 u8 gtpu_teid[0x20]; 673 674 u8 gtpu_msg_type[0x8]; 675 u8 gtpu_msg_flags[0x8]; 676 u8 reserved_at_170[0x10]; 677 678 u8 gtpu_dw_2[0x20]; 679 680 u8 gtpu_first_ext_dw_0[0x20]; 681 682 u8 gtpu_dw_0[0x20]; 683 684 u8 reserved_at_1e0[0x20]; 685 }; 686 687 struct mlx5_ifc_fte_match_set_misc4_bits { 688 u8 prog_sample_field_value_0[0x20]; 689 690 u8 prog_sample_field_id_0[0x20]; 691 692 u8 prog_sample_field_value_1[0x20]; 693 694 u8 prog_sample_field_id_1[0x20]; 695 696 u8 prog_sample_field_value_2[0x20]; 697 698 u8 prog_sample_field_id_2[0x20]; 699 700 u8 prog_sample_field_value_3[0x20]; 701 702 u8 prog_sample_field_id_3[0x20]; 703 704 u8 reserved_at_100[0x100]; 705 }; 706 707 struct mlx5_ifc_fte_match_set_misc5_bits { 708 u8 macsec_tag_0[0x20]; 709 710 u8 macsec_tag_1[0x20]; 711 712 u8 macsec_tag_2[0x20]; 713 714 u8 macsec_tag_3[0x20]; 715 716 u8 tunnel_header_0[0x20]; 717 718 u8 tunnel_header_1[0x20]; 719 720 u8 tunnel_header_2[0x20]; 721 722 u8 tunnel_header_3[0x20]; 723 724 u8 reserved_at_100[0x100]; 725 }; 726 727 struct mlx5_ifc_cmd_pas_bits { 728 u8 pa_h[0x20]; 729 730 u8 pa_l[0x14]; 731 u8 reserved_at_34[0xc]; 732 }; 733 734 struct mlx5_ifc_uint64_bits { 735 u8 hi[0x20]; 736 737 u8 lo[0x20]; 738 }; 739 740 enum { 741 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0, 742 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7, 743 MLX5_ADS_STAT_RATE_10GBPS = 0x8, 744 MLX5_ADS_STAT_RATE_30GBPS = 0x9, 745 MLX5_ADS_STAT_RATE_5GBPS = 0xa, 746 MLX5_ADS_STAT_RATE_20GBPS = 0xb, 747 MLX5_ADS_STAT_RATE_40GBPS = 0xc, 748 MLX5_ADS_STAT_RATE_60GBPS = 0xd, 749 MLX5_ADS_STAT_RATE_80GBPS = 0xe, 750 MLX5_ADS_STAT_RATE_120GBPS = 0xf, 751 }; 752 753 struct mlx5_ifc_ads_bits { 754 u8 fl[0x1]; 755 u8 free_ar[0x1]; 756 u8 reserved_at_2[0xe]; 757 u8 pkey_index[0x10]; 758 759 u8 reserved_at_20[0x8]; 760 u8 grh[0x1]; 761 u8 mlid[0x7]; 762 u8 rlid[0x10]; 763 764 u8 ack_timeout[0x5]; 765 u8 reserved_at_45[0x3]; 766 u8 src_addr_index[0x8]; 767 u8 reserved_at_50[0x4]; 768 u8 stat_rate[0x4]; 769 u8 hop_limit[0x8]; 770 771 u8 reserved_at_60[0x4]; 772 u8 tclass[0x8]; 773 u8 flow_label[0x14]; 774 775 u8 rgid_rip[16][0x8]; 776 777 u8 reserved_at_100[0x4]; 778 u8 f_dscp[0x1]; 779 u8 f_ecn[0x1]; 780 u8 reserved_at_106[0x1]; 781 u8 f_eth_prio[0x1]; 782 u8 ecn[0x2]; 783 u8 dscp[0x6]; 784 u8 udp_sport[0x10]; 785 786 u8 dei_cfi[0x1]; 787 u8 eth_prio[0x3]; 788 u8 sl[0x4]; 789 u8 vhca_port_num[0x8]; 790 u8 rmac_47_32[0x10]; 791 792 u8 rmac_31_0[0x20]; 793 }; 794 795 struct mlx5_ifc_flow_table_nic_cap_bits { 796 u8 nic_rx_multi_path_tirs[0x1]; 797 u8 nic_rx_multi_path_tirs_fts[0x1]; 798 u8 allow_sniffer_and_nic_rx_shared_tir[0x1]; 799 u8 reserved_at_3[0x4]; 800 u8 sw_owner_reformat_supported[0x1]; 801 u8 reserved_at_8[0x18]; 802 803 u8 encap_general_header[0x1]; 804 u8 reserved_at_21[0xa]; 805 u8 log_max_packet_reformat_context[0x5]; 806 u8 reserved_at_30[0x6]; 807 u8 max_encap_header_size[0xa]; 808 u8 reserved_at_40[0x1c0]; 809 810 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive; 811 812 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_rdma; 813 814 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer; 815 816 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit; 817 818 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_rdma; 819 820 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer; 821 822 u8 reserved_at_e00[0x700]; 823 824 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_receive_rdma; 825 826 u8 reserved_at_1580[0x280]; 827 828 struct mlx5_ifc_flow_table_fields_supported_2_bits ft_field_support_2_nic_transmit_rdma; 829 830 u8 reserved_at_1880[0x780]; 831 832 u8 sw_steering_nic_rx_action_drop_icm_address[0x40]; 833 834 u8 sw_steering_nic_tx_action_drop_icm_address[0x40]; 835 836 u8 sw_steering_nic_tx_action_allow_icm_address[0x40]; 837 838 u8 reserved_at_20c0[0x5f40]; 839 }; 840 841 struct mlx5_ifc_port_selection_cap_bits { 842 u8 reserved_at_0[0x10]; 843 u8 port_select_flow_table[0x1]; 844 u8 reserved_at_11[0x1]; 845 u8 port_select_flow_table_bypass[0x1]; 846 u8 reserved_at_13[0xd]; 847 848 u8 reserved_at_20[0x1e0]; 849 850 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_port_selection; 851 852 u8 reserved_at_400[0x7c00]; 853 }; 854 855 enum { 856 MLX5_FDB_TO_VPORT_REG_C_0 = 0x01, 857 MLX5_FDB_TO_VPORT_REG_C_1 = 0x02, 858 MLX5_FDB_TO_VPORT_REG_C_2 = 0x04, 859 MLX5_FDB_TO_VPORT_REG_C_3 = 0x08, 860 MLX5_FDB_TO_VPORT_REG_C_4 = 0x10, 861 MLX5_FDB_TO_VPORT_REG_C_5 = 0x20, 862 MLX5_FDB_TO_VPORT_REG_C_6 = 0x40, 863 MLX5_FDB_TO_VPORT_REG_C_7 = 0x80, 864 }; 865 866 struct mlx5_ifc_flow_table_eswitch_cap_bits { 867 u8 fdb_to_vport_reg_c_id[0x8]; 868 u8 reserved_at_8[0xd]; 869 u8 fdb_modify_header_fwd_to_table[0x1]; 870 u8 fdb_ipv4_ttl_modify[0x1]; 871 u8 flow_source[0x1]; 872 u8 reserved_at_18[0x2]; 873 u8 multi_fdb_encap[0x1]; 874 u8 egress_acl_forward_to_vport[0x1]; 875 u8 fdb_multi_path_to_table[0x1]; 876 u8 reserved_at_1d[0x3]; 877 878 u8 reserved_at_20[0x1e0]; 879 880 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb; 881 882 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress; 883 884 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress; 885 886 u8 reserved_at_800[0x1000]; 887 888 u8 sw_steering_fdb_action_drop_icm_address_rx[0x40]; 889 890 u8 sw_steering_fdb_action_drop_icm_address_tx[0x40]; 891 892 u8 sw_steering_uplink_icm_address_rx[0x40]; 893 894 u8 sw_steering_uplink_icm_address_tx[0x40]; 895 896 u8 reserved_at_1900[0x6700]; 897 }; 898 899 enum { 900 MLX5_COUNTER_SOURCE_ESWITCH = 0x0, 901 MLX5_COUNTER_FLOW_ESWITCH = 0x1, 902 }; 903 904 struct mlx5_ifc_e_switch_cap_bits { 905 u8 vport_svlan_strip[0x1]; 906 u8 vport_cvlan_strip[0x1]; 907 u8 vport_svlan_insert[0x1]; 908 u8 vport_cvlan_insert_if_not_exist[0x1]; 909 u8 vport_cvlan_insert_overwrite[0x1]; 910 u8 reserved_at_5[0x1]; 911 u8 vport_cvlan_insert_always[0x1]; 912 u8 esw_shared_ingress_acl[0x1]; 913 u8 esw_uplink_ingress_acl[0x1]; 914 u8 root_ft_on_other_esw[0x1]; 915 u8 reserved_at_a[0xf]; 916 u8 esw_functions_changed[0x1]; 917 u8 reserved_at_1a[0x1]; 918 u8 ecpf_vport_exists[0x1]; 919 u8 counter_eswitch_affinity[0x1]; 920 u8 merged_eswitch[0x1]; 921 u8 nic_vport_node_guid_modify[0x1]; 922 u8 nic_vport_port_guid_modify[0x1]; 923 924 u8 vxlan_encap_decap[0x1]; 925 u8 nvgre_encap_decap[0x1]; 926 u8 reserved_at_22[0x1]; 927 u8 log_max_fdb_encap_uplink[0x5]; 928 u8 reserved_at_21[0x3]; 929 u8 log_max_packet_reformat_context[0x5]; 930 u8 reserved_2b[0x6]; 931 u8 max_encap_header_size[0xa]; 932 933 u8 reserved_at_40[0xb]; 934 u8 log_max_esw_sf[0x5]; 935 u8 esw_sf_base_id[0x10]; 936 937 u8 reserved_at_60[0x7a0]; 938 939 }; 940 941 struct mlx5_ifc_qos_cap_bits { 942 u8 packet_pacing[0x1]; 943 u8 esw_scheduling[0x1]; 944 u8 esw_bw_share[0x1]; 945 u8 esw_rate_limit[0x1]; 946 u8 reserved_at_4[0x1]; 947 u8 packet_pacing_burst_bound[0x1]; 948 u8 packet_pacing_typical_size[0x1]; 949 u8 reserved_at_7[0x1]; 950 u8 nic_sq_scheduling[0x1]; 951 u8 nic_bw_share[0x1]; 952 u8 nic_rate_limit[0x1]; 953 u8 packet_pacing_uid[0x1]; 954 u8 log_esw_max_sched_depth[0x4]; 955 u8 reserved_at_10[0x10]; 956 957 u8 reserved_at_20[0xb]; 958 u8 log_max_qos_nic_queue_group[0x5]; 959 u8 reserved_at_30[0x10]; 960 961 u8 packet_pacing_max_rate[0x20]; 962 963 u8 packet_pacing_min_rate[0x20]; 964 965 u8 reserved_at_80[0x10]; 966 u8 packet_pacing_rate_table_size[0x10]; 967 968 u8 esw_element_type[0x10]; 969 u8 esw_tsar_type[0x10]; 970 971 u8 reserved_at_c0[0x10]; 972 u8 max_qos_para_vport[0x10]; 973 974 u8 max_tsar_bw_share[0x20]; 975 976 u8 reserved_at_100[0x20]; 977 978 u8 reserved_at_120[0x3]; 979 u8 log_meter_aso_granularity[0x5]; 980 u8 reserved_at_128[0x3]; 981 u8 log_meter_aso_max_alloc[0x5]; 982 u8 reserved_at_130[0x3]; 983 u8 log_max_num_meter_aso[0x5]; 984 u8 reserved_at_138[0x8]; 985 986 u8 reserved_at_140[0x6c0]; 987 }; 988 989 struct mlx5_ifc_debug_cap_bits { 990 u8 core_dump_general[0x1]; 991 u8 core_dump_qp[0x1]; 992 u8 reserved_at_2[0x7]; 993 u8 resource_dump[0x1]; 994 u8 reserved_at_a[0x16]; 995 996 u8 reserved_at_20[0x2]; 997 u8 stall_detect[0x1]; 998 u8 reserved_at_23[0x1d]; 999 1000 u8 reserved_at_40[0x7c0]; 1001 }; 1002 1003 struct mlx5_ifc_per_protocol_networking_offload_caps_bits { 1004 u8 csum_cap[0x1]; 1005 u8 vlan_cap[0x1]; 1006 u8 lro_cap[0x1]; 1007 u8 lro_psh_flag[0x1]; 1008 u8 lro_time_stamp[0x1]; 1009 u8 reserved_at_5[0x2]; 1010 u8 wqe_vlan_insert[0x1]; 1011 u8 self_lb_en_modifiable[0x1]; 1012 u8 reserved_at_9[0x2]; 1013 u8 max_lso_cap[0x5]; 1014 u8 multi_pkt_send_wqe[0x2]; 1015 u8 wqe_inline_mode[0x2]; 1016 u8 rss_ind_tbl_cap[0x4]; 1017 u8 reg_umr_sq[0x1]; 1018 u8 scatter_fcs[0x1]; 1019 u8 enhanced_multi_pkt_send_wqe[0x1]; 1020 u8 tunnel_lso_const_out_ip_id[0x1]; 1021 u8 tunnel_lro_gre[0x1]; 1022 u8 tunnel_lro_vxlan[0x1]; 1023 u8 tunnel_stateless_gre[0x1]; 1024 u8 tunnel_stateless_vxlan[0x1]; 1025 1026 u8 swp[0x1]; 1027 u8 swp_csum[0x1]; 1028 u8 swp_lso[0x1]; 1029 u8 cqe_checksum_full[0x1]; 1030 u8 tunnel_stateless_geneve_tx[0x1]; 1031 u8 tunnel_stateless_mpls_over_udp[0x1]; 1032 u8 tunnel_stateless_mpls_over_gre[0x1]; 1033 u8 tunnel_stateless_vxlan_gpe[0x1]; 1034 u8 tunnel_stateless_ipv4_over_vxlan[0x1]; 1035 u8 tunnel_stateless_ip_over_ip[0x1]; 1036 u8 insert_trailer[0x1]; 1037 u8 reserved_at_2b[0x1]; 1038 u8 tunnel_stateless_ip_over_ip_rx[0x1]; 1039 u8 tunnel_stateless_ip_over_ip_tx[0x1]; 1040 u8 reserved_at_2e[0x2]; 1041 u8 max_vxlan_udp_ports[0x8]; 1042 u8 reserved_at_38[0x6]; 1043 u8 max_geneve_opt_len[0x1]; 1044 u8 tunnel_stateless_geneve_rx[0x1]; 1045 1046 u8 reserved_at_40[0x10]; 1047 u8 lro_min_mss_size[0x10]; 1048 1049 u8 reserved_at_60[0x120]; 1050 1051 u8 lro_timer_supported_periods[4][0x20]; 1052 1053 u8 reserved_at_200[0x600]; 1054 }; 1055 1056 enum { 1057 MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING = 0x0, 1058 MLX5_TIMESTAMP_FORMAT_CAP_REAL_TIME = 0x1, 1059 MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME = 0x2, 1060 }; 1061 1062 struct mlx5_ifc_roce_cap_bits { 1063 u8 roce_apm[0x1]; 1064 u8 reserved_at_1[0x3]; 1065 u8 sw_r_roce_src_udp_port[0x1]; 1066 u8 fl_rc_qp_when_roce_disabled[0x1]; 1067 u8 fl_rc_qp_when_roce_enabled[0x1]; 1068 u8 reserved_at_7[0x17]; 1069 u8 qp_ts_format[0x2]; 1070 1071 u8 reserved_at_20[0x60]; 1072 1073 u8 reserved_at_80[0xc]; 1074 u8 l3_type[0x4]; 1075 u8 reserved_at_90[0x8]; 1076 u8 roce_version[0x8]; 1077 1078 u8 reserved_at_a0[0x10]; 1079 u8 r_roce_dest_udp_port[0x10]; 1080 1081 u8 r_roce_max_src_udp_port[0x10]; 1082 u8 r_roce_min_src_udp_port[0x10]; 1083 1084 u8 reserved_at_e0[0x10]; 1085 u8 roce_address_table_size[0x10]; 1086 1087 u8 reserved_at_100[0x700]; 1088 }; 1089 1090 struct mlx5_ifc_sync_steering_in_bits { 1091 u8 opcode[0x10]; 1092 u8 uid[0x10]; 1093 1094 u8 reserved_at_20[0x10]; 1095 u8 op_mod[0x10]; 1096 1097 u8 reserved_at_40[0xc0]; 1098 }; 1099 1100 struct mlx5_ifc_sync_steering_out_bits { 1101 u8 status[0x8]; 1102 u8 reserved_at_8[0x18]; 1103 1104 u8 syndrome[0x20]; 1105 1106 u8 reserved_at_40[0x40]; 1107 }; 1108 1109 struct mlx5_ifc_device_mem_cap_bits { 1110 u8 memic[0x1]; 1111 u8 reserved_at_1[0x1f]; 1112 1113 u8 reserved_at_20[0xb]; 1114 u8 log_min_memic_alloc_size[0x5]; 1115 u8 reserved_at_30[0x8]; 1116 u8 log_max_memic_addr_alignment[0x8]; 1117 1118 u8 memic_bar_start_addr[0x40]; 1119 1120 u8 memic_bar_size[0x20]; 1121 1122 u8 max_memic_size[0x20]; 1123 1124 u8 steering_sw_icm_start_address[0x40]; 1125 1126 u8 reserved_at_100[0x8]; 1127 u8 log_header_modify_sw_icm_size[0x8]; 1128 u8 reserved_at_110[0x2]; 1129 u8 log_sw_icm_alloc_granularity[0x6]; 1130 u8 log_steering_sw_icm_size[0x8]; 1131 1132 u8 reserved_at_120[0x18]; 1133 u8 log_header_modify_pattern_sw_icm_size[0x8]; 1134 1135 u8 header_modify_sw_icm_start_address[0x40]; 1136 1137 u8 reserved_at_180[0x40]; 1138 1139 u8 header_modify_pattern_sw_icm_start_address[0x40]; 1140 1141 u8 memic_operations[0x20]; 1142 1143 u8 reserved_at_220[0x5e0]; 1144 }; 1145 1146 struct mlx5_ifc_device_event_cap_bits { 1147 u8 user_affiliated_events[4][0x40]; 1148 1149 u8 user_unaffiliated_events[4][0x40]; 1150 }; 1151 1152 struct mlx5_ifc_virtio_emulation_cap_bits { 1153 u8 desc_tunnel_offload_type[0x1]; 1154 u8 eth_frame_offload_type[0x1]; 1155 u8 virtio_version_1_0[0x1]; 1156 u8 device_features_bits_mask[0xd]; 1157 u8 event_mode[0x8]; 1158 u8 virtio_queue_type[0x8]; 1159 1160 u8 max_tunnel_desc[0x10]; 1161 u8 reserved_at_30[0x3]; 1162 u8 log_doorbell_stride[0x5]; 1163 u8 reserved_at_38[0x3]; 1164 u8 log_doorbell_bar_size[0x5]; 1165 1166 u8 doorbell_bar_offset[0x40]; 1167 1168 u8 max_emulated_devices[0x8]; 1169 u8 max_num_virtio_queues[0x18]; 1170 1171 u8 reserved_at_a0[0x60]; 1172 1173 u8 umem_1_buffer_param_a[0x20]; 1174 1175 u8 umem_1_buffer_param_b[0x20]; 1176 1177 u8 umem_2_buffer_param_a[0x20]; 1178 1179 u8 umem_2_buffer_param_b[0x20]; 1180 1181 u8 umem_3_buffer_param_a[0x20]; 1182 1183 u8 umem_3_buffer_param_b[0x20]; 1184 1185 u8 reserved_at_1c0[0x640]; 1186 }; 1187 1188 enum { 1189 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0, 1190 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2, 1191 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4, 1192 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8, 1193 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10, 1194 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20, 1195 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40, 1196 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80, 1197 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100, 1198 }; 1199 1200 enum { 1201 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1, 1202 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2, 1203 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4, 1204 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8, 1205 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10, 1206 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20, 1207 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40, 1208 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80, 1209 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100, 1210 }; 1211 1212 struct mlx5_ifc_atomic_caps_bits { 1213 u8 reserved_at_0[0x40]; 1214 1215 u8 atomic_req_8B_endianness_mode[0x2]; 1216 u8 reserved_at_42[0x4]; 1217 u8 supported_atomic_req_8B_endianness_mode_1[0x1]; 1218 1219 u8 reserved_at_47[0x19]; 1220 1221 u8 reserved_at_60[0x20]; 1222 1223 u8 reserved_at_80[0x10]; 1224 u8 atomic_operations[0x10]; 1225 1226 u8 reserved_at_a0[0x10]; 1227 u8 atomic_size_qp[0x10]; 1228 1229 u8 reserved_at_c0[0x10]; 1230 u8 atomic_size_dc[0x10]; 1231 1232 u8 reserved_at_e0[0x720]; 1233 }; 1234 1235 struct mlx5_ifc_odp_cap_bits { 1236 u8 reserved_at_0[0x40]; 1237 1238 u8 sig[0x1]; 1239 u8 reserved_at_41[0x1f]; 1240 1241 u8 reserved_at_60[0x20]; 1242 1243 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps; 1244 1245 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps; 1246 1247 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps; 1248 1249 struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps; 1250 1251 struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps; 1252 1253 u8 reserved_at_120[0x6E0]; 1254 }; 1255 1256 struct mlx5_ifc_calc_op { 1257 u8 reserved_at_0[0x10]; 1258 u8 reserved_at_10[0x9]; 1259 u8 op_swap_endianness[0x1]; 1260 u8 op_min[0x1]; 1261 u8 op_xor[0x1]; 1262 u8 op_or[0x1]; 1263 u8 op_and[0x1]; 1264 u8 op_max[0x1]; 1265 u8 op_add[0x1]; 1266 }; 1267 1268 struct mlx5_ifc_vector_calc_cap_bits { 1269 u8 calc_matrix[0x1]; 1270 u8 reserved_at_1[0x1f]; 1271 u8 reserved_at_20[0x8]; 1272 u8 max_vec_count[0x8]; 1273 u8 reserved_at_30[0xd]; 1274 u8 max_chunk_size[0x3]; 1275 struct mlx5_ifc_calc_op calc0; 1276 struct mlx5_ifc_calc_op calc1; 1277 struct mlx5_ifc_calc_op calc2; 1278 struct mlx5_ifc_calc_op calc3; 1279 1280 u8 reserved_at_c0[0x720]; 1281 }; 1282 1283 struct mlx5_ifc_tls_cap_bits { 1284 u8 tls_1_2_aes_gcm_128[0x1]; 1285 u8 tls_1_3_aes_gcm_128[0x1]; 1286 u8 tls_1_2_aes_gcm_256[0x1]; 1287 u8 tls_1_3_aes_gcm_256[0x1]; 1288 u8 reserved_at_4[0x1c]; 1289 1290 u8 reserved_at_20[0x7e0]; 1291 }; 1292 1293 struct mlx5_ifc_ipsec_cap_bits { 1294 u8 ipsec_full_offload[0x1]; 1295 u8 ipsec_crypto_offload[0x1]; 1296 u8 ipsec_esn[0x1]; 1297 u8 ipsec_crypto_esp_aes_gcm_256_encrypt[0x1]; 1298 u8 ipsec_crypto_esp_aes_gcm_128_encrypt[0x1]; 1299 u8 ipsec_crypto_esp_aes_gcm_256_decrypt[0x1]; 1300 u8 ipsec_crypto_esp_aes_gcm_128_decrypt[0x1]; 1301 u8 reserved_at_7[0x4]; 1302 u8 log_max_ipsec_offload[0x5]; 1303 u8 reserved_at_10[0x10]; 1304 1305 u8 min_log_ipsec_full_replay_window[0x8]; 1306 u8 max_log_ipsec_full_replay_window[0x8]; 1307 u8 reserved_at_30[0x7d0]; 1308 }; 1309 1310 struct mlx5_ifc_macsec_cap_bits { 1311 u8 macsec_epn[0x1]; 1312 u8 reserved_at_1[0x2]; 1313 u8 macsec_crypto_esp_aes_gcm_256_encrypt[0x1]; 1314 u8 macsec_crypto_esp_aes_gcm_128_encrypt[0x1]; 1315 u8 macsec_crypto_esp_aes_gcm_256_decrypt[0x1]; 1316 u8 macsec_crypto_esp_aes_gcm_128_decrypt[0x1]; 1317 u8 reserved_at_7[0x4]; 1318 u8 log_max_macsec_offload[0x5]; 1319 u8 reserved_at_10[0x10]; 1320 1321 u8 min_log_macsec_full_replay_window[0x8]; 1322 u8 max_log_macsec_full_replay_window[0x8]; 1323 u8 reserved_at_30[0x10]; 1324 1325 u8 reserved_at_40[0x7c0]; 1326 }; 1327 1328 enum { 1329 MLX5_WQ_TYPE_LINKED_LIST = 0x0, 1330 MLX5_WQ_TYPE_CYCLIC = 0x1, 1331 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2, 1332 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ = 0x3, 1333 }; 1334 1335 enum { 1336 MLX5_WQ_END_PAD_MODE_NONE = 0x0, 1337 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1, 1338 }; 1339 1340 enum { 1341 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0, 1342 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1, 1343 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2, 1344 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3, 1345 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4, 1346 }; 1347 1348 enum { 1349 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0, 1350 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1, 1351 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2, 1352 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3, 1353 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4, 1354 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5, 1355 }; 1356 1357 enum { 1358 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0, 1359 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1, 1360 }; 1361 1362 enum { 1363 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0, 1364 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1, 1365 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3, 1366 }; 1367 1368 enum { 1369 MLX5_CAP_PORT_TYPE_IB = 0x0, 1370 MLX5_CAP_PORT_TYPE_ETH = 0x1, 1371 }; 1372 1373 enum { 1374 MLX5_CAP_UMR_FENCE_STRONG = 0x0, 1375 MLX5_CAP_UMR_FENCE_SMALL = 0x1, 1376 MLX5_CAP_UMR_FENCE_NONE = 0x2, 1377 }; 1378 1379 enum { 1380 MLX5_FLEX_PARSER_GENEVE_ENABLED = 1 << 3, 1381 MLX5_FLEX_PARSER_MPLS_OVER_GRE_ENABLED = 1 << 4, 1382 MLX5_FLEX_PARSER_MPLS_OVER_UDP_ENABLED = 1 << 5, 1383 MLX5_FLEX_PARSER_VXLAN_GPE_ENABLED = 1 << 7, 1384 MLX5_FLEX_PARSER_ICMP_V4_ENABLED = 1 << 8, 1385 MLX5_FLEX_PARSER_ICMP_V6_ENABLED = 1 << 9, 1386 MLX5_FLEX_PARSER_GENEVE_TLV_OPTION_0_ENABLED = 1 << 10, 1387 MLX5_FLEX_PARSER_GTPU_ENABLED = 1 << 11, 1388 MLX5_FLEX_PARSER_GTPU_DW_2_ENABLED = 1 << 16, 1389 MLX5_FLEX_PARSER_GTPU_FIRST_EXT_DW_0_ENABLED = 1 << 17, 1390 MLX5_FLEX_PARSER_GTPU_DW_0_ENABLED = 1 << 18, 1391 MLX5_FLEX_PARSER_GTPU_TEID_ENABLED = 1 << 19, 1392 }; 1393 1394 enum { 1395 MLX5_UCTX_CAP_RAW_TX = 1UL << 0, 1396 MLX5_UCTX_CAP_INTERNAL_DEV_RES = 1UL << 1, 1397 }; 1398 1399 #define MLX5_FC_BULK_SIZE_FACTOR 128 1400 1401 enum mlx5_fc_bulk_alloc_bitmask { 1402 MLX5_FC_BULK_128 = (1 << 0), 1403 MLX5_FC_BULK_256 = (1 << 1), 1404 MLX5_FC_BULK_512 = (1 << 2), 1405 MLX5_FC_BULK_1024 = (1 << 3), 1406 MLX5_FC_BULK_2048 = (1 << 4), 1407 MLX5_FC_BULK_4096 = (1 << 5), 1408 MLX5_FC_BULK_8192 = (1 << 6), 1409 MLX5_FC_BULK_16384 = (1 << 7), 1410 }; 1411 1412 #define MLX5_FC_BULK_NUM_FCS(fc_enum) (MLX5_FC_BULK_SIZE_FACTOR * (fc_enum)) 1413 1414 #define MLX5_FT_MAX_MULTIPATH_LEVEL 63 1415 1416 enum { 1417 MLX5_STEERING_FORMAT_CONNECTX_5 = 0, 1418 MLX5_STEERING_FORMAT_CONNECTX_6DX = 1, 1419 MLX5_STEERING_FORMAT_CONNECTX_7 = 2, 1420 }; 1421 1422 struct mlx5_ifc_cmd_hca_cap_bits { 1423 u8 reserved_at_0[0x10]; 1424 u8 shared_object_to_user_object_allowed[0x1]; 1425 u8 reserved_at_13[0xe]; 1426 u8 vhca_resource_manager[0x1]; 1427 1428 u8 hca_cap_2[0x1]; 1429 u8 create_lag_when_not_master_up[0x1]; 1430 u8 dtor[0x1]; 1431 u8 event_on_vhca_state_teardown_request[0x1]; 1432 u8 event_on_vhca_state_in_use[0x1]; 1433 u8 event_on_vhca_state_active[0x1]; 1434 u8 event_on_vhca_state_allocated[0x1]; 1435 u8 event_on_vhca_state_invalid[0x1]; 1436 u8 reserved_at_28[0x8]; 1437 u8 vhca_id[0x10]; 1438 1439 u8 reserved_at_40[0x40]; 1440 1441 u8 log_max_srq_sz[0x8]; 1442 u8 log_max_qp_sz[0x8]; 1443 u8 event_cap[0x1]; 1444 u8 reserved_at_91[0x2]; 1445 u8 isolate_vl_tc_new[0x1]; 1446 u8 reserved_at_94[0x4]; 1447 u8 prio_tag_required[0x1]; 1448 u8 reserved_at_99[0x2]; 1449 u8 log_max_qp[0x5]; 1450 1451 u8 reserved_at_a0[0x3]; 1452 u8 ece_support[0x1]; 1453 u8 reserved_at_a4[0x5]; 1454 u8 reg_c_preserve[0x1]; 1455 u8 reserved_at_aa[0x1]; 1456 u8 log_max_srq[0x5]; 1457 u8 reserved_at_b0[0x1]; 1458 u8 uplink_follow[0x1]; 1459 u8 ts_cqe_to_dest_cqn[0x1]; 1460 u8 reserved_at_b3[0x7]; 1461 u8 shampo[0x1]; 1462 u8 reserved_at_bb[0x5]; 1463 1464 u8 max_sgl_for_optimized_performance[0x8]; 1465 u8 log_max_cq_sz[0x8]; 1466 u8 relaxed_ordering_write_umr[0x1]; 1467 u8 relaxed_ordering_read_umr[0x1]; 1468 u8 reserved_at_d2[0x7]; 1469 u8 virtio_net_device_emualtion_manager[0x1]; 1470 u8 virtio_blk_device_emualtion_manager[0x1]; 1471 u8 log_max_cq[0x5]; 1472 1473 u8 log_max_eq_sz[0x8]; 1474 u8 relaxed_ordering_write[0x1]; 1475 u8 relaxed_ordering_read[0x1]; 1476 u8 log_max_mkey[0x6]; 1477 u8 reserved_at_f0[0x8]; 1478 u8 dump_fill_mkey[0x1]; 1479 u8 reserved_at_f9[0x2]; 1480 u8 fast_teardown[0x1]; 1481 u8 log_max_eq[0x4]; 1482 1483 u8 max_indirection[0x8]; 1484 u8 fixed_buffer_size[0x1]; 1485 u8 log_max_mrw_sz[0x7]; 1486 u8 force_teardown[0x1]; 1487 u8 reserved_at_111[0x1]; 1488 u8 log_max_bsf_list_size[0x6]; 1489 u8 umr_extended_translation_offset[0x1]; 1490 u8 null_mkey[0x1]; 1491 u8 log_max_klm_list_size[0x6]; 1492 1493 u8 reserved_at_120[0xa]; 1494 u8 log_max_ra_req_dc[0x6]; 1495 u8 reserved_at_130[0x2]; 1496 u8 eth_wqe_too_small[0x1]; 1497 u8 reserved_at_133[0x6]; 1498 u8 vnic_env_cq_overrun[0x1]; 1499 u8 log_max_ra_res_dc[0x6]; 1500 1501 u8 reserved_at_140[0x5]; 1502 u8 release_all_pages[0x1]; 1503 u8 must_not_use[0x1]; 1504 u8 reserved_at_147[0x2]; 1505 u8 roce_accl[0x1]; 1506 u8 log_max_ra_req_qp[0x6]; 1507 u8 reserved_at_150[0xa]; 1508 u8 log_max_ra_res_qp[0x6]; 1509 1510 u8 end_pad[0x1]; 1511 u8 cc_query_allowed[0x1]; 1512 u8 cc_modify_allowed[0x1]; 1513 u8 start_pad[0x1]; 1514 u8 cache_line_128byte[0x1]; 1515 u8 reserved_at_165[0x4]; 1516 u8 rts2rts_qp_counters_set_id[0x1]; 1517 u8 reserved_at_16a[0x2]; 1518 u8 vnic_env_int_rq_oob[0x1]; 1519 u8 sbcam_reg[0x1]; 1520 u8 reserved_at_16e[0x1]; 1521 u8 qcam_reg[0x1]; 1522 u8 gid_table_size[0x10]; 1523 1524 u8 out_of_seq_cnt[0x1]; 1525 u8 vport_counters[0x1]; 1526 u8 retransmission_q_counters[0x1]; 1527 u8 debug[0x1]; 1528 u8 modify_rq_counter_set_id[0x1]; 1529 u8 rq_delay_drop[0x1]; 1530 u8 max_qp_cnt[0xa]; 1531 u8 pkey_table_size[0x10]; 1532 1533 u8 vport_group_manager[0x1]; 1534 u8 vhca_group_manager[0x1]; 1535 u8 ib_virt[0x1]; 1536 u8 eth_virt[0x1]; 1537 u8 vnic_env_queue_counters[0x1]; 1538 u8 ets[0x1]; 1539 u8 nic_flow_table[0x1]; 1540 u8 eswitch_manager[0x1]; 1541 u8 device_memory[0x1]; 1542 u8 mcam_reg[0x1]; 1543 u8 pcam_reg[0x1]; 1544 u8 local_ca_ack_delay[0x5]; 1545 u8 port_module_event[0x1]; 1546 u8 enhanced_error_q_counters[0x1]; 1547 u8 ports_check[0x1]; 1548 u8 reserved_at_1b3[0x1]; 1549 u8 disable_link_up[0x1]; 1550 u8 beacon_led[0x1]; 1551 u8 port_type[0x2]; 1552 u8 num_ports[0x8]; 1553 1554 u8 reserved_at_1c0[0x1]; 1555 u8 pps[0x1]; 1556 u8 pps_modify[0x1]; 1557 u8 log_max_msg[0x5]; 1558 u8 reserved_at_1c8[0x4]; 1559 u8 max_tc[0x4]; 1560 u8 temp_warn_event[0x1]; 1561 u8 dcbx[0x1]; 1562 u8 general_notification_event[0x1]; 1563 u8 reserved_at_1d3[0x2]; 1564 u8 fpga[0x1]; 1565 u8 rol_s[0x1]; 1566 u8 rol_g[0x1]; 1567 u8 reserved_at_1d8[0x1]; 1568 u8 wol_s[0x1]; 1569 u8 wol_g[0x1]; 1570 u8 wol_a[0x1]; 1571 u8 wol_b[0x1]; 1572 u8 wol_m[0x1]; 1573 u8 wol_u[0x1]; 1574 u8 wol_p[0x1]; 1575 1576 u8 stat_rate_support[0x10]; 1577 u8 reserved_at_1f0[0x1]; 1578 u8 pci_sync_for_fw_update_event[0x1]; 1579 u8 reserved_at_1f2[0x6]; 1580 u8 init2_lag_tx_port_affinity[0x1]; 1581 u8 reserved_at_1fa[0x3]; 1582 u8 cqe_version[0x4]; 1583 1584 u8 compact_address_vector[0x1]; 1585 u8 striding_rq[0x1]; 1586 u8 reserved_at_202[0x1]; 1587 u8 ipoib_enhanced_offloads[0x1]; 1588 u8 ipoib_basic_offloads[0x1]; 1589 u8 reserved_at_205[0x1]; 1590 u8 repeated_block_disabled[0x1]; 1591 u8 umr_modify_entity_size_disabled[0x1]; 1592 u8 umr_modify_atomic_disabled[0x1]; 1593 u8 umr_indirect_mkey_disabled[0x1]; 1594 u8 umr_fence[0x2]; 1595 u8 dc_req_scat_data_cqe[0x1]; 1596 u8 reserved_at_20d[0x2]; 1597 u8 drain_sigerr[0x1]; 1598 u8 cmdif_checksum[0x2]; 1599 u8 sigerr_cqe[0x1]; 1600 u8 reserved_at_213[0x1]; 1601 u8 wq_signature[0x1]; 1602 u8 sctr_data_cqe[0x1]; 1603 u8 reserved_at_216[0x1]; 1604 u8 sho[0x1]; 1605 u8 tph[0x1]; 1606 u8 rf[0x1]; 1607 u8 dct[0x1]; 1608 u8 qos[0x1]; 1609 u8 eth_net_offloads[0x1]; 1610 u8 roce[0x1]; 1611 u8 atomic[0x1]; 1612 u8 reserved_at_21f[0x1]; 1613 1614 u8 cq_oi[0x1]; 1615 u8 cq_resize[0x1]; 1616 u8 cq_moderation[0x1]; 1617 u8 reserved_at_223[0x3]; 1618 u8 cq_eq_remap[0x1]; 1619 u8 pg[0x1]; 1620 u8 block_lb_mc[0x1]; 1621 u8 reserved_at_229[0x1]; 1622 u8 scqe_break_moderation[0x1]; 1623 u8 cq_period_start_from_cqe[0x1]; 1624 u8 cd[0x1]; 1625 u8 reserved_at_22d[0x1]; 1626 u8 apm[0x1]; 1627 u8 vector_calc[0x1]; 1628 u8 umr_ptr_rlky[0x1]; 1629 u8 imaicl[0x1]; 1630 u8 qp_packet_based[0x1]; 1631 u8 reserved_at_233[0x3]; 1632 u8 qkv[0x1]; 1633 u8 pkv[0x1]; 1634 u8 set_deth_sqpn[0x1]; 1635 u8 reserved_at_239[0x3]; 1636 u8 xrc[0x1]; 1637 u8 ud[0x1]; 1638 u8 uc[0x1]; 1639 u8 rc[0x1]; 1640 1641 u8 uar_4k[0x1]; 1642 u8 reserved_at_241[0x9]; 1643 u8 uar_sz[0x6]; 1644 u8 port_selection_cap[0x1]; 1645 u8 reserved_at_248[0x1]; 1646 u8 umem_uid_0[0x1]; 1647 u8 reserved_at_250[0x5]; 1648 u8 log_pg_sz[0x8]; 1649 1650 u8 bf[0x1]; 1651 u8 driver_version[0x1]; 1652 u8 pad_tx_eth_packet[0x1]; 1653 u8 reserved_at_263[0x3]; 1654 u8 mkey_by_name[0x1]; 1655 u8 reserved_at_267[0x4]; 1656 1657 u8 log_bf_reg_size[0x5]; 1658 1659 u8 reserved_at_270[0x6]; 1660 u8 lag_dct[0x2]; 1661 u8 lag_tx_port_affinity[0x1]; 1662 u8 lag_native_fdb_selection[0x1]; 1663 u8 reserved_at_27a[0x1]; 1664 u8 lag_master[0x1]; 1665 u8 num_lag_ports[0x4]; 1666 1667 u8 reserved_at_280[0x10]; 1668 u8 max_wqe_sz_sq[0x10]; 1669 1670 u8 reserved_at_2a0[0x10]; 1671 u8 max_wqe_sz_rq[0x10]; 1672 1673 u8 max_flow_counter_31_16[0x10]; 1674 u8 max_wqe_sz_sq_dc[0x10]; 1675 1676 u8 reserved_at_2e0[0x7]; 1677 u8 max_qp_mcg[0x19]; 1678 1679 u8 reserved_at_300[0x10]; 1680 u8 flow_counter_bulk_alloc[0x8]; 1681 u8 log_max_mcg[0x8]; 1682 1683 u8 reserved_at_320[0x3]; 1684 u8 log_max_transport_domain[0x5]; 1685 u8 reserved_at_328[0x3]; 1686 u8 log_max_pd[0x5]; 1687 u8 reserved_at_330[0xb]; 1688 u8 log_max_xrcd[0x5]; 1689 1690 u8 nic_receive_steering_discard[0x1]; 1691 u8 receive_discard_vport_down[0x1]; 1692 u8 transmit_discard_vport_down[0x1]; 1693 u8 eq_overrun_count[0x1]; 1694 u8 reserved_at_344[0x1]; 1695 u8 invalid_command_count[0x1]; 1696 u8 quota_exceeded_count[0x1]; 1697 u8 reserved_at_347[0x1]; 1698 u8 log_max_flow_counter_bulk[0x8]; 1699 u8 max_flow_counter_15_0[0x10]; 1700 1701 1702 u8 reserved_at_360[0x3]; 1703 u8 log_max_rq[0x5]; 1704 u8 reserved_at_368[0x3]; 1705 u8 log_max_sq[0x5]; 1706 u8 reserved_at_370[0x3]; 1707 u8 log_max_tir[0x5]; 1708 u8 reserved_at_378[0x3]; 1709 u8 log_max_tis[0x5]; 1710 1711 u8 basic_cyclic_rcv_wqe[0x1]; 1712 u8 reserved_at_381[0x2]; 1713 u8 log_max_rmp[0x5]; 1714 u8 reserved_at_388[0x3]; 1715 u8 log_max_rqt[0x5]; 1716 u8 reserved_at_390[0x3]; 1717 u8 log_max_rqt_size[0x5]; 1718 u8 reserved_at_398[0x3]; 1719 u8 log_max_tis_per_sq[0x5]; 1720 1721 u8 ext_stride_num_range[0x1]; 1722 u8 roce_rw_supported[0x1]; 1723 u8 log_max_current_uc_list_wr_supported[0x1]; 1724 u8 log_max_stride_sz_rq[0x5]; 1725 u8 reserved_at_3a8[0x3]; 1726 u8 log_min_stride_sz_rq[0x5]; 1727 u8 reserved_at_3b0[0x3]; 1728 u8 log_max_stride_sz_sq[0x5]; 1729 u8 reserved_at_3b8[0x3]; 1730 u8 log_min_stride_sz_sq[0x5]; 1731 1732 u8 hairpin[0x1]; 1733 u8 reserved_at_3c1[0x2]; 1734 u8 log_max_hairpin_queues[0x5]; 1735 u8 reserved_at_3c8[0x3]; 1736 u8 log_max_hairpin_wq_data_sz[0x5]; 1737 u8 reserved_at_3d0[0x3]; 1738 u8 log_max_hairpin_num_packets[0x5]; 1739 u8 reserved_at_3d8[0x3]; 1740 u8 log_max_wq_sz[0x5]; 1741 1742 u8 nic_vport_change_event[0x1]; 1743 u8 disable_local_lb_uc[0x1]; 1744 u8 disable_local_lb_mc[0x1]; 1745 u8 log_min_hairpin_wq_data_sz[0x5]; 1746 u8 reserved_at_3e8[0x2]; 1747 u8 vhca_state[0x1]; 1748 u8 log_max_vlan_list[0x5]; 1749 u8 reserved_at_3f0[0x3]; 1750 u8 log_max_current_mc_list[0x5]; 1751 u8 reserved_at_3f8[0x3]; 1752 u8 log_max_current_uc_list[0x5]; 1753 1754 u8 general_obj_types[0x40]; 1755 1756 u8 sq_ts_format[0x2]; 1757 u8 rq_ts_format[0x2]; 1758 u8 steering_format_version[0x4]; 1759 u8 create_qp_start_hint[0x18]; 1760 1761 u8 reserved_at_460[0x1]; 1762 u8 ats[0x1]; 1763 u8 reserved_at_462[0x1]; 1764 u8 log_max_uctx[0x5]; 1765 u8 reserved_at_468[0x2]; 1766 u8 ipsec_offload[0x1]; 1767 u8 log_max_umem[0x5]; 1768 u8 max_num_eqs[0x10]; 1769 1770 u8 reserved_at_480[0x1]; 1771 u8 tls_tx[0x1]; 1772 u8 tls_rx[0x1]; 1773 u8 log_max_l2_table[0x5]; 1774 u8 reserved_at_488[0x8]; 1775 u8 log_uar_page_sz[0x10]; 1776 1777 u8 reserved_at_4a0[0x20]; 1778 u8 device_frequency_mhz[0x20]; 1779 u8 device_frequency_khz[0x20]; 1780 1781 u8 reserved_at_500[0x20]; 1782 u8 num_of_uars_per_page[0x20]; 1783 1784 u8 flex_parser_protocols[0x20]; 1785 1786 u8 max_geneve_tlv_options[0x8]; 1787 u8 reserved_at_568[0x3]; 1788 u8 max_geneve_tlv_option_data_len[0x5]; 1789 u8 reserved_at_570[0x9]; 1790 u8 adv_virtualization[0x1]; 1791 u8 reserved_at_57a[0x6]; 1792 1793 u8 reserved_at_580[0xb]; 1794 u8 log_max_dci_stream_channels[0x5]; 1795 u8 reserved_at_590[0x3]; 1796 u8 log_max_dci_errored_streams[0x5]; 1797 u8 reserved_at_598[0x8]; 1798 1799 u8 reserved_at_5a0[0x10]; 1800 u8 enhanced_cqe_compression[0x1]; 1801 u8 reserved_at_5b1[0x2]; 1802 u8 log_max_dek[0x5]; 1803 u8 reserved_at_5b8[0x4]; 1804 u8 mini_cqe_resp_stride_index[0x1]; 1805 u8 cqe_128_always[0x1]; 1806 u8 cqe_compression_128[0x1]; 1807 u8 cqe_compression[0x1]; 1808 1809 u8 cqe_compression_timeout[0x10]; 1810 u8 cqe_compression_max_num[0x10]; 1811 1812 u8 reserved_at_5e0[0x8]; 1813 u8 flex_parser_id_gtpu_dw_0[0x4]; 1814 u8 reserved_at_5ec[0x4]; 1815 u8 tag_matching[0x1]; 1816 u8 rndv_offload_rc[0x1]; 1817 u8 rndv_offload_dc[0x1]; 1818 u8 log_tag_matching_list_sz[0x5]; 1819 u8 reserved_at_5f8[0x3]; 1820 u8 log_max_xrq[0x5]; 1821 1822 u8 affiliate_nic_vport_criteria[0x8]; 1823 u8 native_port_num[0x8]; 1824 u8 num_vhca_ports[0x8]; 1825 u8 flex_parser_id_gtpu_teid[0x4]; 1826 u8 reserved_at_61c[0x2]; 1827 u8 sw_owner_id[0x1]; 1828 u8 reserved_at_61f[0x1]; 1829 1830 u8 max_num_of_monitor_counters[0x10]; 1831 u8 num_ppcnt_monitor_counters[0x10]; 1832 1833 u8 max_num_sf[0x10]; 1834 u8 num_q_monitor_counters[0x10]; 1835 1836 u8 reserved_at_660[0x20]; 1837 1838 u8 sf[0x1]; 1839 u8 sf_set_partition[0x1]; 1840 u8 reserved_at_682[0x1]; 1841 u8 log_max_sf[0x5]; 1842 u8 apu[0x1]; 1843 u8 reserved_at_689[0x4]; 1844 u8 migration[0x1]; 1845 u8 reserved_at_68e[0x2]; 1846 u8 log_min_sf_size[0x8]; 1847 u8 max_num_sf_partitions[0x8]; 1848 1849 u8 uctx_cap[0x20]; 1850 1851 u8 reserved_at_6c0[0x4]; 1852 u8 flex_parser_id_geneve_tlv_option_0[0x4]; 1853 u8 flex_parser_id_icmp_dw1[0x4]; 1854 u8 flex_parser_id_icmp_dw0[0x4]; 1855 u8 flex_parser_id_icmpv6_dw1[0x4]; 1856 u8 flex_parser_id_icmpv6_dw0[0x4]; 1857 u8 flex_parser_id_outer_first_mpls_over_gre[0x4]; 1858 u8 flex_parser_id_outer_first_mpls_over_udp_label[0x4]; 1859 1860 u8 max_num_match_definer[0x10]; 1861 u8 sf_base_id[0x10]; 1862 1863 u8 flex_parser_id_gtpu_dw_2[0x4]; 1864 u8 flex_parser_id_gtpu_first_ext_dw_0[0x4]; 1865 u8 num_total_dynamic_vf_msix[0x18]; 1866 u8 reserved_at_720[0x14]; 1867 u8 dynamic_msix_table_size[0xc]; 1868 u8 reserved_at_740[0xc]; 1869 u8 min_dynamic_vf_msix_table_size[0x4]; 1870 u8 reserved_at_750[0x4]; 1871 u8 max_dynamic_vf_msix_table_size[0xc]; 1872 1873 u8 reserved_at_760[0x20]; 1874 u8 vhca_tunnel_commands[0x40]; 1875 u8 match_definer_format_supported[0x40]; 1876 }; 1877 1878 struct mlx5_ifc_cmd_hca_cap_2_bits { 1879 u8 reserved_at_0[0xa0]; 1880 1881 u8 max_reformat_insert_size[0x8]; 1882 u8 max_reformat_insert_offset[0x8]; 1883 u8 max_reformat_remove_size[0x8]; 1884 u8 max_reformat_remove_offset[0x8]; 1885 1886 u8 reserved_at_c0[0xe0]; 1887 1888 u8 reserved_at_1a0[0xb]; 1889 u8 log_min_mkey_entity_size[0x5]; 1890 u8 reserved_at_1b0[0x10]; 1891 1892 u8 reserved_at_1c0[0x60]; 1893 1894 u8 reserved_at_220[0x1]; 1895 u8 sw_vhca_id_valid[0x1]; 1896 u8 sw_vhca_id[0xe]; 1897 u8 reserved_at_230[0x10]; 1898 1899 u8 reserved_at_240[0xb]; 1900 u8 ts_cqe_metadata_size2wqe_counter[0x5]; 1901 u8 reserved_at_250[0x10]; 1902 1903 u8 reserved_at_260[0x5a0]; 1904 }; 1905 1906 enum mlx5_ifc_flow_destination_type { 1907 MLX5_IFC_FLOW_DESTINATION_TYPE_VPORT = 0x0, 1908 MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1, 1909 MLX5_IFC_FLOW_DESTINATION_TYPE_TIR = 0x2, 1910 MLX5_IFC_FLOW_DESTINATION_TYPE_FLOW_SAMPLER = 0x6, 1911 MLX5_IFC_FLOW_DESTINATION_TYPE_UPLINK = 0x8, 1912 }; 1913 1914 enum mlx5_flow_table_miss_action { 1915 MLX5_FLOW_TABLE_MISS_ACTION_DEF, 1916 MLX5_FLOW_TABLE_MISS_ACTION_FWD, 1917 MLX5_FLOW_TABLE_MISS_ACTION_SWITCH_DOMAIN, 1918 }; 1919 1920 struct mlx5_ifc_dest_format_struct_bits { 1921 u8 destination_type[0x8]; 1922 u8 destination_id[0x18]; 1923 1924 u8 destination_eswitch_owner_vhca_id_valid[0x1]; 1925 u8 packet_reformat[0x1]; 1926 u8 reserved_at_22[0xe]; 1927 u8 destination_eswitch_owner_vhca_id[0x10]; 1928 }; 1929 1930 struct mlx5_ifc_flow_counter_list_bits { 1931 u8 flow_counter_id[0x20]; 1932 1933 u8 reserved_at_20[0x20]; 1934 }; 1935 1936 struct mlx5_ifc_extended_dest_format_bits { 1937 struct mlx5_ifc_dest_format_struct_bits destination_entry; 1938 1939 u8 packet_reformat_id[0x20]; 1940 1941 u8 reserved_at_60[0x20]; 1942 }; 1943 1944 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits { 1945 struct mlx5_ifc_extended_dest_format_bits extended_dest_format; 1946 struct mlx5_ifc_flow_counter_list_bits flow_counter_list; 1947 }; 1948 1949 struct mlx5_ifc_fte_match_param_bits { 1950 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers; 1951 1952 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters; 1953 1954 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers; 1955 1956 struct mlx5_ifc_fte_match_set_misc2_bits misc_parameters_2; 1957 1958 struct mlx5_ifc_fte_match_set_misc3_bits misc_parameters_3; 1959 1960 struct mlx5_ifc_fte_match_set_misc4_bits misc_parameters_4; 1961 1962 struct mlx5_ifc_fte_match_set_misc5_bits misc_parameters_5; 1963 1964 u8 reserved_at_e00[0x200]; 1965 }; 1966 1967 enum { 1968 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0, 1969 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1, 1970 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2, 1971 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3, 1972 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4, 1973 }; 1974 1975 struct mlx5_ifc_rx_hash_field_select_bits { 1976 u8 l3_prot_type[0x1]; 1977 u8 l4_prot_type[0x1]; 1978 u8 selected_fields[0x1e]; 1979 }; 1980 1981 enum { 1982 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0, 1983 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1, 1984 }; 1985 1986 enum { 1987 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0, 1988 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1, 1989 }; 1990 1991 struct mlx5_ifc_wq_bits { 1992 u8 wq_type[0x4]; 1993 u8 wq_signature[0x1]; 1994 u8 end_padding_mode[0x2]; 1995 u8 cd_slave[0x1]; 1996 u8 reserved_at_8[0x18]; 1997 1998 u8 hds_skip_first_sge[0x1]; 1999 u8 log2_hds_buf_size[0x3]; 2000 u8 reserved_at_24[0x7]; 2001 u8 page_offset[0x5]; 2002 u8 lwm[0x10]; 2003 2004 u8 reserved_at_40[0x8]; 2005 u8 pd[0x18]; 2006 2007 u8 reserved_at_60[0x8]; 2008 u8 uar_page[0x18]; 2009 2010 u8 dbr_addr[0x40]; 2011 2012 u8 hw_counter[0x20]; 2013 2014 u8 sw_counter[0x20]; 2015 2016 u8 reserved_at_100[0xc]; 2017 u8 log_wq_stride[0x4]; 2018 u8 reserved_at_110[0x3]; 2019 u8 log_wq_pg_sz[0x5]; 2020 u8 reserved_at_118[0x3]; 2021 u8 log_wq_sz[0x5]; 2022 2023 u8 dbr_umem_valid[0x1]; 2024 u8 wq_umem_valid[0x1]; 2025 u8 reserved_at_122[0x1]; 2026 u8 log_hairpin_num_packets[0x5]; 2027 u8 reserved_at_128[0x3]; 2028 u8 log_hairpin_data_sz[0x5]; 2029 2030 u8 reserved_at_130[0x4]; 2031 u8 log_wqe_num_of_strides[0x4]; 2032 u8 two_byte_shift_en[0x1]; 2033 u8 reserved_at_139[0x4]; 2034 u8 log_wqe_stride_size[0x3]; 2035 2036 u8 reserved_at_140[0x80]; 2037 2038 u8 headers_mkey[0x20]; 2039 2040 u8 shampo_enable[0x1]; 2041 u8 reserved_at_1e1[0x4]; 2042 u8 log_reservation_size[0x3]; 2043 u8 reserved_at_1e8[0x5]; 2044 u8 log_max_num_of_packets_per_reservation[0x3]; 2045 u8 reserved_at_1f0[0x6]; 2046 u8 log_headers_entry_size[0x2]; 2047 u8 reserved_at_1f8[0x4]; 2048 u8 log_headers_buffer_entry_num[0x4]; 2049 2050 u8 reserved_at_200[0x400]; 2051 2052 struct mlx5_ifc_cmd_pas_bits pas[]; 2053 }; 2054 2055 struct mlx5_ifc_rq_num_bits { 2056 u8 reserved_at_0[0x8]; 2057 u8 rq_num[0x18]; 2058 }; 2059 2060 struct mlx5_ifc_mac_address_layout_bits { 2061 u8 reserved_at_0[0x10]; 2062 u8 mac_addr_47_32[0x10]; 2063 2064 u8 mac_addr_31_0[0x20]; 2065 }; 2066 2067 struct mlx5_ifc_vlan_layout_bits { 2068 u8 reserved_at_0[0x14]; 2069 u8 vlan[0x0c]; 2070 2071 u8 reserved_at_20[0x20]; 2072 }; 2073 2074 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits { 2075 u8 reserved_at_0[0xa0]; 2076 2077 u8 min_time_between_cnps[0x20]; 2078 2079 u8 reserved_at_c0[0x12]; 2080 u8 cnp_dscp[0x6]; 2081 u8 reserved_at_d8[0x4]; 2082 u8 cnp_prio_mode[0x1]; 2083 u8 cnp_802p_prio[0x3]; 2084 2085 u8 reserved_at_e0[0x720]; 2086 }; 2087 2088 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits { 2089 u8 reserved_at_0[0x60]; 2090 2091 u8 reserved_at_60[0x4]; 2092 u8 clamp_tgt_rate[0x1]; 2093 u8 reserved_at_65[0x3]; 2094 u8 clamp_tgt_rate_after_time_inc[0x1]; 2095 u8 reserved_at_69[0x17]; 2096 2097 u8 reserved_at_80[0x20]; 2098 2099 u8 rpg_time_reset[0x20]; 2100 2101 u8 rpg_byte_reset[0x20]; 2102 2103 u8 rpg_threshold[0x20]; 2104 2105 u8 rpg_max_rate[0x20]; 2106 2107 u8 rpg_ai_rate[0x20]; 2108 2109 u8 rpg_hai_rate[0x20]; 2110 2111 u8 rpg_gd[0x20]; 2112 2113 u8 rpg_min_dec_fac[0x20]; 2114 2115 u8 rpg_min_rate[0x20]; 2116 2117 u8 reserved_at_1c0[0xe0]; 2118 2119 u8 rate_to_set_on_first_cnp[0x20]; 2120 2121 u8 dce_tcp_g[0x20]; 2122 2123 u8 dce_tcp_rtt[0x20]; 2124 2125 u8 rate_reduce_monitor_period[0x20]; 2126 2127 u8 reserved_at_320[0x20]; 2128 2129 u8 initial_alpha_value[0x20]; 2130 2131 u8 reserved_at_360[0x4a0]; 2132 }; 2133 2134 struct mlx5_ifc_cong_control_802_1qau_rp_bits { 2135 u8 reserved_at_0[0x80]; 2136 2137 u8 rppp_max_rps[0x20]; 2138 2139 u8 rpg_time_reset[0x20]; 2140 2141 u8 rpg_byte_reset[0x20]; 2142 2143 u8 rpg_threshold[0x20]; 2144 2145 u8 rpg_max_rate[0x20]; 2146 2147 u8 rpg_ai_rate[0x20]; 2148 2149 u8 rpg_hai_rate[0x20]; 2150 2151 u8 rpg_gd[0x20]; 2152 2153 u8 rpg_min_dec_fac[0x20]; 2154 2155 u8 rpg_min_rate[0x20]; 2156 2157 u8 reserved_at_1c0[0x640]; 2158 }; 2159 2160 enum { 2161 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1, 2162 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2, 2163 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4, 2164 }; 2165 2166 struct mlx5_ifc_resize_field_select_bits { 2167 u8 resize_field_select[0x20]; 2168 }; 2169 2170 struct mlx5_ifc_resource_dump_bits { 2171 u8 more_dump[0x1]; 2172 u8 inline_dump[0x1]; 2173 u8 reserved_at_2[0xa]; 2174 u8 seq_num[0x4]; 2175 u8 segment_type[0x10]; 2176 2177 u8 reserved_at_20[0x10]; 2178 u8 vhca_id[0x10]; 2179 2180 u8 index1[0x20]; 2181 2182 u8 index2[0x20]; 2183 2184 u8 num_of_obj1[0x10]; 2185 u8 num_of_obj2[0x10]; 2186 2187 u8 reserved_at_a0[0x20]; 2188 2189 u8 device_opaque[0x40]; 2190 2191 u8 mkey[0x20]; 2192 2193 u8 size[0x20]; 2194 2195 u8 address[0x40]; 2196 2197 u8 inline_data[52][0x20]; 2198 }; 2199 2200 struct mlx5_ifc_resource_dump_menu_record_bits { 2201 u8 reserved_at_0[0x4]; 2202 u8 num_of_obj2_supports_active[0x1]; 2203 u8 num_of_obj2_supports_all[0x1]; 2204 u8 must_have_num_of_obj2[0x1]; 2205 u8 support_num_of_obj2[0x1]; 2206 u8 num_of_obj1_supports_active[0x1]; 2207 u8 num_of_obj1_supports_all[0x1]; 2208 u8 must_have_num_of_obj1[0x1]; 2209 u8 support_num_of_obj1[0x1]; 2210 u8 must_have_index2[0x1]; 2211 u8 support_index2[0x1]; 2212 u8 must_have_index1[0x1]; 2213 u8 support_index1[0x1]; 2214 u8 segment_type[0x10]; 2215 2216 u8 segment_name[4][0x20]; 2217 2218 u8 index1_name[4][0x20]; 2219 2220 u8 index2_name[4][0x20]; 2221 }; 2222 2223 struct mlx5_ifc_resource_dump_segment_header_bits { 2224 u8 length_dw[0x10]; 2225 u8 segment_type[0x10]; 2226 }; 2227 2228 struct mlx5_ifc_resource_dump_command_segment_bits { 2229 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2230 2231 u8 segment_called[0x10]; 2232 u8 vhca_id[0x10]; 2233 2234 u8 index1[0x20]; 2235 2236 u8 index2[0x20]; 2237 2238 u8 num_of_obj1[0x10]; 2239 u8 num_of_obj2[0x10]; 2240 }; 2241 2242 struct mlx5_ifc_resource_dump_error_segment_bits { 2243 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2244 2245 u8 reserved_at_20[0x10]; 2246 u8 syndrome_id[0x10]; 2247 2248 u8 reserved_at_40[0x40]; 2249 2250 u8 error[8][0x20]; 2251 }; 2252 2253 struct mlx5_ifc_resource_dump_info_segment_bits { 2254 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2255 2256 u8 reserved_at_20[0x18]; 2257 u8 dump_version[0x8]; 2258 2259 u8 hw_version[0x20]; 2260 2261 u8 fw_version[0x20]; 2262 }; 2263 2264 struct mlx5_ifc_resource_dump_menu_segment_bits { 2265 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2266 2267 u8 reserved_at_20[0x10]; 2268 u8 num_of_records[0x10]; 2269 2270 struct mlx5_ifc_resource_dump_menu_record_bits record[]; 2271 }; 2272 2273 struct mlx5_ifc_resource_dump_resource_segment_bits { 2274 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2275 2276 u8 reserved_at_20[0x20]; 2277 2278 u8 index1[0x20]; 2279 2280 u8 index2[0x20]; 2281 2282 u8 payload[][0x20]; 2283 }; 2284 2285 struct mlx5_ifc_resource_dump_terminate_segment_bits { 2286 struct mlx5_ifc_resource_dump_segment_header_bits segment_header; 2287 }; 2288 2289 struct mlx5_ifc_menu_resource_dump_response_bits { 2290 struct mlx5_ifc_resource_dump_info_segment_bits info; 2291 struct mlx5_ifc_resource_dump_command_segment_bits cmd; 2292 struct mlx5_ifc_resource_dump_menu_segment_bits menu; 2293 struct mlx5_ifc_resource_dump_terminate_segment_bits terminate; 2294 }; 2295 2296 enum { 2297 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1, 2298 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2, 2299 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4, 2300 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8, 2301 }; 2302 2303 struct mlx5_ifc_modify_field_select_bits { 2304 u8 modify_field_select[0x20]; 2305 }; 2306 2307 struct mlx5_ifc_field_select_r_roce_np_bits { 2308 u8 field_select_r_roce_np[0x20]; 2309 }; 2310 2311 struct mlx5_ifc_field_select_r_roce_rp_bits { 2312 u8 field_select_r_roce_rp[0x20]; 2313 }; 2314 2315 enum { 2316 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4, 2317 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8, 2318 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10, 2319 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20, 2320 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40, 2321 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80, 2322 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100, 2323 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200, 2324 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400, 2325 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800, 2326 }; 2327 2328 struct mlx5_ifc_field_select_802_1qau_rp_bits { 2329 u8 field_select_8021qaurp[0x20]; 2330 }; 2331 2332 struct mlx5_ifc_phys_layer_cntrs_bits { 2333 u8 time_since_last_clear_high[0x20]; 2334 2335 u8 time_since_last_clear_low[0x20]; 2336 2337 u8 symbol_errors_high[0x20]; 2338 2339 u8 symbol_errors_low[0x20]; 2340 2341 u8 sync_headers_errors_high[0x20]; 2342 2343 u8 sync_headers_errors_low[0x20]; 2344 2345 u8 edpl_bip_errors_lane0_high[0x20]; 2346 2347 u8 edpl_bip_errors_lane0_low[0x20]; 2348 2349 u8 edpl_bip_errors_lane1_high[0x20]; 2350 2351 u8 edpl_bip_errors_lane1_low[0x20]; 2352 2353 u8 edpl_bip_errors_lane2_high[0x20]; 2354 2355 u8 edpl_bip_errors_lane2_low[0x20]; 2356 2357 u8 edpl_bip_errors_lane3_high[0x20]; 2358 2359 u8 edpl_bip_errors_lane3_low[0x20]; 2360 2361 u8 fc_fec_corrected_blocks_lane0_high[0x20]; 2362 2363 u8 fc_fec_corrected_blocks_lane0_low[0x20]; 2364 2365 u8 fc_fec_corrected_blocks_lane1_high[0x20]; 2366 2367 u8 fc_fec_corrected_blocks_lane1_low[0x20]; 2368 2369 u8 fc_fec_corrected_blocks_lane2_high[0x20]; 2370 2371 u8 fc_fec_corrected_blocks_lane2_low[0x20]; 2372 2373 u8 fc_fec_corrected_blocks_lane3_high[0x20]; 2374 2375 u8 fc_fec_corrected_blocks_lane3_low[0x20]; 2376 2377 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20]; 2378 2379 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20]; 2380 2381 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20]; 2382 2383 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20]; 2384 2385 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20]; 2386 2387 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20]; 2388 2389 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20]; 2390 2391 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20]; 2392 2393 u8 rs_fec_corrected_blocks_high[0x20]; 2394 2395 u8 rs_fec_corrected_blocks_low[0x20]; 2396 2397 u8 rs_fec_uncorrectable_blocks_high[0x20]; 2398 2399 u8 rs_fec_uncorrectable_blocks_low[0x20]; 2400 2401 u8 rs_fec_no_errors_blocks_high[0x20]; 2402 2403 u8 rs_fec_no_errors_blocks_low[0x20]; 2404 2405 u8 rs_fec_single_error_blocks_high[0x20]; 2406 2407 u8 rs_fec_single_error_blocks_low[0x20]; 2408 2409 u8 rs_fec_corrected_symbols_total_high[0x20]; 2410 2411 u8 rs_fec_corrected_symbols_total_low[0x20]; 2412 2413 u8 rs_fec_corrected_symbols_lane0_high[0x20]; 2414 2415 u8 rs_fec_corrected_symbols_lane0_low[0x20]; 2416 2417 u8 rs_fec_corrected_symbols_lane1_high[0x20]; 2418 2419 u8 rs_fec_corrected_symbols_lane1_low[0x20]; 2420 2421 u8 rs_fec_corrected_symbols_lane2_high[0x20]; 2422 2423 u8 rs_fec_corrected_symbols_lane2_low[0x20]; 2424 2425 u8 rs_fec_corrected_symbols_lane3_high[0x20]; 2426 2427 u8 rs_fec_corrected_symbols_lane3_low[0x20]; 2428 2429 u8 link_down_events[0x20]; 2430 2431 u8 successful_recovery_events[0x20]; 2432 2433 u8 reserved_at_640[0x180]; 2434 }; 2435 2436 struct mlx5_ifc_phys_layer_statistical_cntrs_bits { 2437 u8 time_since_last_clear_high[0x20]; 2438 2439 u8 time_since_last_clear_low[0x20]; 2440 2441 u8 phy_received_bits_high[0x20]; 2442 2443 u8 phy_received_bits_low[0x20]; 2444 2445 u8 phy_symbol_errors_high[0x20]; 2446 2447 u8 phy_symbol_errors_low[0x20]; 2448 2449 u8 phy_corrected_bits_high[0x20]; 2450 2451 u8 phy_corrected_bits_low[0x20]; 2452 2453 u8 phy_corrected_bits_lane0_high[0x20]; 2454 2455 u8 phy_corrected_bits_lane0_low[0x20]; 2456 2457 u8 phy_corrected_bits_lane1_high[0x20]; 2458 2459 u8 phy_corrected_bits_lane1_low[0x20]; 2460 2461 u8 phy_corrected_bits_lane2_high[0x20]; 2462 2463 u8 phy_corrected_bits_lane2_low[0x20]; 2464 2465 u8 phy_corrected_bits_lane3_high[0x20]; 2466 2467 u8 phy_corrected_bits_lane3_low[0x20]; 2468 2469 u8 reserved_at_200[0x5c0]; 2470 }; 2471 2472 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits { 2473 u8 symbol_error_counter[0x10]; 2474 2475 u8 link_error_recovery_counter[0x8]; 2476 2477 u8 link_downed_counter[0x8]; 2478 2479 u8 port_rcv_errors[0x10]; 2480 2481 u8 port_rcv_remote_physical_errors[0x10]; 2482 2483 u8 port_rcv_switch_relay_errors[0x10]; 2484 2485 u8 port_xmit_discards[0x10]; 2486 2487 u8 port_xmit_constraint_errors[0x8]; 2488 2489 u8 port_rcv_constraint_errors[0x8]; 2490 2491 u8 reserved_at_70[0x8]; 2492 2493 u8 link_overrun_errors[0x8]; 2494 2495 u8 reserved_at_80[0x10]; 2496 2497 u8 vl_15_dropped[0x10]; 2498 2499 u8 reserved_at_a0[0x80]; 2500 2501 u8 port_xmit_wait[0x20]; 2502 }; 2503 2504 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits { 2505 u8 transmit_queue_high[0x20]; 2506 2507 u8 transmit_queue_low[0x20]; 2508 2509 u8 no_buffer_discard_uc_high[0x20]; 2510 2511 u8 no_buffer_discard_uc_low[0x20]; 2512 2513 u8 reserved_at_80[0x740]; 2514 }; 2515 2516 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits { 2517 u8 wred_discard_high[0x20]; 2518 2519 u8 wred_discard_low[0x20]; 2520 2521 u8 ecn_marked_tc_high[0x20]; 2522 2523 u8 ecn_marked_tc_low[0x20]; 2524 2525 u8 reserved_at_80[0x740]; 2526 }; 2527 2528 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits { 2529 u8 rx_octets_high[0x20]; 2530 2531 u8 rx_octets_low[0x20]; 2532 2533 u8 reserved_at_40[0xc0]; 2534 2535 u8 rx_frames_high[0x20]; 2536 2537 u8 rx_frames_low[0x20]; 2538 2539 u8 tx_octets_high[0x20]; 2540 2541 u8 tx_octets_low[0x20]; 2542 2543 u8 reserved_at_180[0xc0]; 2544 2545 u8 tx_frames_high[0x20]; 2546 2547 u8 tx_frames_low[0x20]; 2548 2549 u8 rx_pause_high[0x20]; 2550 2551 u8 rx_pause_low[0x20]; 2552 2553 u8 rx_pause_duration_high[0x20]; 2554 2555 u8 rx_pause_duration_low[0x20]; 2556 2557 u8 tx_pause_high[0x20]; 2558 2559 u8 tx_pause_low[0x20]; 2560 2561 u8 tx_pause_duration_high[0x20]; 2562 2563 u8 tx_pause_duration_low[0x20]; 2564 2565 u8 rx_pause_transition_high[0x20]; 2566 2567 u8 rx_pause_transition_low[0x20]; 2568 2569 u8 rx_discards_high[0x20]; 2570 2571 u8 rx_discards_low[0x20]; 2572 2573 u8 device_stall_minor_watermark_cnt_high[0x20]; 2574 2575 u8 device_stall_minor_watermark_cnt_low[0x20]; 2576 2577 u8 device_stall_critical_watermark_cnt_high[0x20]; 2578 2579 u8 device_stall_critical_watermark_cnt_low[0x20]; 2580 2581 u8 reserved_at_480[0x340]; 2582 }; 2583 2584 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits { 2585 u8 port_transmit_wait_high[0x20]; 2586 2587 u8 port_transmit_wait_low[0x20]; 2588 2589 u8 reserved_at_40[0x100]; 2590 2591 u8 rx_buffer_almost_full_high[0x20]; 2592 2593 u8 rx_buffer_almost_full_low[0x20]; 2594 2595 u8 rx_buffer_full_high[0x20]; 2596 2597 u8 rx_buffer_full_low[0x20]; 2598 2599 u8 rx_icrc_encapsulated_high[0x20]; 2600 2601 u8 rx_icrc_encapsulated_low[0x20]; 2602 2603 u8 reserved_at_200[0x5c0]; 2604 }; 2605 2606 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits { 2607 u8 dot3stats_alignment_errors_high[0x20]; 2608 2609 u8 dot3stats_alignment_errors_low[0x20]; 2610 2611 u8 dot3stats_fcs_errors_high[0x20]; 2612 2613 u8 dot3stats_fcs_errors_low[0x20]; 2614 2615 u8 dot3stats_single_collision_frames_high[0x20]; 2616 2617 u8 dot3stats_single_collision_frames_low[0x20]; 2618 2619 u8 dot3stats_multiple_collision_frames_high[0x20]; 2620 2621 u8 dot3stats_multiple_collision_frames_low[0x20]; 2622 2623 u8 dot3stats_sqe_test_errors_high[0x20]; 2624 2625 u8 dot3stats_sqe_test_errors_low[0x20]; 2626 2627 u8 dot3stats_deferred_transmissions_high[0x20]; 2628 2629 u8 dot3stats_deferred_transmissions_low[0x20]; 2630 2631 u8 dot3stats_late_collisions_high[0x20]; 2632 2633 u8 dot3stats_late_collisions_low[0x20]; 2634 2635 u8 dot3stats_excessive_collisions_high[0x20]; 2636 2637 u8 dot3stats_excessive_collisions_low[0x20]; 2638 2639 u8 dot3stats_internal_mac_transmit_errors_high[0x20]; 2640 2641 u8 dot3stats_internal_mac_transmit_errors_low[0x20]; 2642 2643 u8 dot3stats_carrier_sense_errors_high[0x20]; 2644 2645 u8 dot3stats_carrier_sense_errors_low[0x20]; 2646 2647 u8 dot3stats_frame_too_longs_high[0x20]; 2648 2649 u8 dot3stats_frame_too_longs_low[0x20]; 2650 2651 u8 dot3stats_internal_mac_receive_errors_high[0x20]; 2652 2653 u8 dot3stats_internal_mac_receive_errors_low[0x20]; 2654 2655 u8 dot3stats_symbol_errors_high[0x20]; 2656 2657 u8 dot3stats_symbol_errors_low[0x20]; 2658 2659 u8 dot3control_in_unknown_opcodes_high[0x20]; 2660 2661 u8 dot3control_in_unknown_opcodes_low[0x20]; 2662 2663 u8 dot3in_pause_frames_high[0x20]; 2664 2665 u8 dot3in_pause_frames_low[0x20]; 2666 2667 u8 dot3out_pause_frames_high[0x20]; 2668 2669 u8 dot3out_pause_frames_low[0x20]; 2670 2671 u8 reserved_at_400[0x3c0]; 2672 }; 2673 2674 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits { 2675 u8 ether_stats_drop_events_high[0x20]; 2676 2677 u8 ether_stats_drop_events_low[0x20]; 2678 2679 u8 ether_stats_octets_high[0x20]; 2680 2681 u8 ether_stats_octets_low[0x20]; 2682 2683 u8 ether_stats_pkts_high[0x20]; 2684 2685 u8 ether_stats_pkts_low[0x20]; 2686 2687 u8 ether_stats_broadcast_pkts_high[0x20]; 2688 2689 u8 ether_stats_broadcast_pkts_low[0x20]; 2690 2691 u8 ether_stats_multicast_pkts_high[0x20]; 2692 2693 u8 ether_stats_multicast_pkts_low[0x20]; 2694 2695 u8 ether_stats_crc_align_errors_high[0x20]; 2696 2697 u8 ether_stats_crc_align_errors_low[0x20]; 2698 2699 u8 ether_stats_undersize_pkts_high[0x20]; 2700 2701 u8 ether_stats_undersize_pkts_low[0x20]; 2702 2703 u8 ether_stats_oversize_pkts_high[0x20]; 2704 2705 u8 ether_stats_oversize_pkts_low[0x20]; 2706 2707 u8 ether_stats_fragments_high[0x20]; 2708 2709 u8 ether_stats_fragments_low[0x20]; 2710 2711 u8 ether_stats_jabbers_high[0x20]; 2712 2713 u8 ether_stats_jabbers_low[0x20]; 2714 2715 u8 ether_stats_collisions_high[0x20]; 2716 2717 u8 ether_stats_collisions_low[0x20]; 2718 2719 u8 ether_stats_pkts64octets_high[0x20]; 2720 2721 u8 ether_stats_pkts64octets_low[0x20]; 2722 2723 u8 ether_stats_pkts65to127octets_high[0x20]; 2724 2725 u8 ether_stats_pkts65to127octets_low[0x20]; 2726 2727 u8 ether_stats_pkts128to255octets_high[0x20]; 2728 2729 u8 ether_stats_pkts128to255octets_low[0x20]; 2730 2731 u8 ether_stats_pkts256to511octets_high[0x20]; 2732 2733 u8 ether_stats_pkts256to511octets_low[0x20]; 2734 2735 u8 ether_stats_pkts512to1023octets_high[0x20]; 2736 2737 u8 ether_stats_pkts512to1023octets_low[0x20]; 2738 2739 u8 ether_stats_pkts1024to1518octets_high[0x20]; 2740 2741 u8 ether_stats_pkts1024to1518octets_low[0x20]; 2742 2743 u8 ether_stats_pkts1519to2047octets_high[0x20]; 2744 2745 u8 ether_stats_pkts1519to2047octets_low[0x20]; 2746 2747 u8 ether_stats_pkts2048to4095octets_high[0x20]; 2748 2749 u8 ether_stats_pkts2048to4095octets_low[0x20]; 2750 2751 u8 ether_stats_pkts4096to8191octets_high[0x20]; 2752 2753 u8 ether_stats_pkts4096to8191octets_low[0x20]; 2754 2755 u8 ether_stats_pkts8192to10239octets_high[0x20]; 2756 2757 u8 ether_stats_pkts8192to10239octets_low[0x20]; 2758 2759 u8 reserved_at_540[0x280]; 2760 }; 2761 2762 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits { 2763 u8 if_in_octets_high[0x20]; 2764 2765 u8 if_in_octets_low[0x20]; 2766 2767 u8 if_in_ucast_pkts_high[0x20]; 2768 2769 u8 if_in_ucast_pkts_low[0x20]; 2770 2771 u8 if_in_discards_high[0x20]; 2772 2773 u8 if_in_discards_low[0x20]; 2774 2775 u8 if_in_errors_high[0x20]; 2776 2777 u8 if_in_errors_low[0x20]; 2778 2779 u8 if_in_unknown_protos_high[0x20]; 2780 2781 u8 if_in_unknown_protos_low[0x20]; 2782 2783 u8 if_out_octets_high[0x20]; 2784 2785 u8 if_out_octets_low[0x20]; 2786 2787 u8 if_out_ucast_pkts_high[0x20]; 2788 2789 u8 if_out_ucast_pkts_low[0x20]; 2790 2791 u8 if_out_discards_high[0x20]; 2792 2793 u8 if_out_discards_low[0x20]; 2794 2795 u8 if_out_errors_high[0x20]; 2796 2797 u8 if_out_errors_low[0x20]; 2798 2799 u8 if_in_multicast_pkts_high[0x20]; 2800 2801 u8 if_in_multicast_pkts_low[0x20]; 2802 2803 u8 if_in_broadcast_pkts_high[0x20]; 2804 2805 u8 if_in_broadcast_pkts_low[0x20]; 2806 2807 u8 if_out_multicast_pkts_high[0x20]; 2808 2809 u8 if_out_multicast_pkts_low[0x20]; 2810 2811 u8 if_out_broadcast_pkts_high[0x20]; 2812 2813 u8 if_out_broadcast_pkts_low[0x20]; 2814 2815 u8 reserved_at_340[0x480]; 2816 }; 2817 2818 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits { 2819 u8 a_frames_transmitted_ok_high[0x20]; 2820 2821 u8 a_frames_transmitted_ok_low[0x20]; 2822 2823 u8 a_frames_received_ok_high[0x20]; 2824 2825 u8 a_frames_received_ok_low[0x20]; 2826 2827 u8 a_frame_check_sequence_errors_high[0x20]; 2828 2829 u8 a_frame_check_sequence_errors_low[0x20]; 2830 2831 u8 a_alignment_errors_high[0x20]; 2832 2833 u8 a_alignment_errors_low[0x20]; 2834 2835 u8 a_octets_transmitted_ok_high[0x20]; 2836 2837 u8 a_octets_transmitted_ok_low[0x20]; 2838 2839 u8 a_octets_received_ok_high[0x20]; 2840 2841 u8 a_octets_received_ok_low[0x20]; 2842 2843 u8 a_multicast_frames_xmitted_ok_high[0x20]; 2844 2845 u8 a_multicast_frames_xmitted_ok_low[0x20]; 2846 2847 u8 a_broadcast_frames_xmitted_ok_high[0x20]; 2848 2849 u8 a_broadcast_frames_xmitted_ok_low[0x20]; 2850 2851 u8 a_multicast_frames_received_ok_high[0x20]; 2852 2853 u8 a_multicast_frames_received_ok_low[0x20]; 2854 2855 u8 a_broadcast_frames_received_ok_high[0x20]; 2856 2857 u8 a_broadcast_frames_received_ok_low[0x20]; 2858 2859 u8 a_in_range_length_errors_high[0x20]; 2860 2861 u8 a_in_range_length_errors_low[0x20]; 2862 2863 u8 a_out_of_range_length_field_high[0x20]; 2864 2865 u8 a_out_of_range_length_field_low[0x20]; 2866 2867 u8 a_frame_too_long_errors_high[0x20]; 2868 2869 u8 a_frame_too_long_errors_low[0x20]; 2870 2871 u8 a_symbol_error_during_carrier_high[0x20]; 2872 2873 u8 a_symbol_error_during_carrier_low[0x20]; 2874 2875 u8 a_mac_control_frames_transmitted_high[0x20]; 2876 2877 u8 a_mac_control_frames_transmitted_low[0x20]; 2878 2879 u8 a_mac_control_frames_received_high[0x20]; 2880 2881 u8 a_mac_control_frames_received_low[0x20]; 2882 2883 u8 a_unsupported_opcodes_received_high[0x20]; 2884 2885 u8 a_unsupported_opcodes_received_low[0x20]; 2886 2887 u8 a_pause_mac_ctrl_frames_received_high[0x20]; 2888 2889 u8 a_pause_mac_ctrl_frames_received_low[0x20]; 2890 2891 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20]; 2892 2893 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20]; 2894 2895 u8 reserved_at_4c0[0x300]; 2896 }; 2897 2898 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits { 2899 u8 life_time_counter_high[0x20]; 2900 2901 u8 life_time_counter_low[0x20]; 2902 2903 u8 rx_errors[0x20]; 2904 2905 u8 tx_errors[0x20]; 2906 2907 u8 l0_to_recovery_eieos[0x20]; 2908 2909 u8 l0_to_recovery_ts[0x20]; 2910 2911 u8 l0_to_recovery_framing[0x20]; 2912 2913 u8 l0_to_recovery_retrain[0x20]; 2914 2915 u8 crc_error_dllp[0x20]; 2916 2917 u8 crc_error_tlp[0x20]; 2918 2919 u8 tx_overflow_buffer_pkt_high[0x20]; 2920 2921 u8 tx_overflow_buffer_pkt_low[0x20]; 2922 2923 u8 outbound_stalled_reads[0x20]; 2924 2925 u8 outbound_stalled_writes[0x20]; 2926 2927 u8 outbound_stalled_reads_events[0x20]; 2928 2929 u8 outbound_stalled_writes_events[0x20]; 2930 2931 u8 reserved_at_200[0x5c0]; 2932 }; 2933 2934 struct mlx5_ifc_cmd_inter_comp_event_bits { 2935 u8 command_completion_vector[0x20]; 2936 2937 u8 reserved_at_20[0xc0]; 2938 }; 2939 2940 struct mlx5_ifc_stall_vl_event_bits { 2941 u8 reserved_at_0[0x18]; 2942 u8 port_num[0x1]; 2943 u8 reserved_at_19[0x3]; 2944 u8 vl[0x4]; 2945 2946 u8 reserved_at_20[0xa0]; 2947 }; 2948 2949 struct mlx5_ifc_db_bf_congestion_event_bits { 2950 u8 event_subtype[0x8]; 2951 u8 reserved_at_8[0x8]; 2952 u8 congestion_level[0x8]; 2953 u8 reserved_at_18[0x8]; 2954 2955 u8 reserved_at_20[0xa0]; 2956 }; 2957 2958 struct mlx5_ifc_gpio_event_bits { 2959 u8 reserved_at_0[0x60]; 2960 2961 u8 gpio_event_hi[0x20]; 2962 2963 u8 gpio_event_lo[0x20]; 2964 2965 u8 reserved_at_a0[0x40]; 2966 }; 2967 2968 struct mlx5_ifc_port_state_change_event_bits { 2969 u8 reserved_at_0[0x40]; 2970 2971 u8 port_num[0x4]; 2972 u8 reserved_at_44[0x1c]; 2973 2974 u8 reserved_at_60[0x80]; 2975 }; 2976 2977 struct mlx5_ifc_dropped_packet_logged_bits { 2978 u8 reserved_at_0[0xe0]; 2979 }; 2980 2981 struct mlx5_ifc_default_timeout_bits { 2982 u8 to_multiplier[0x3]; 2983 u8 reserved_at_3[0x9]; 2984 u8 to_value[0x14]; 2985 }; 2986 2987 struct mlx5_ifc_dtor_reg_bits { 2988 u8 reserved_at_0[0x20]; 2989 2990 struct mlx5_ifc_default_timeout_bits pcie_toggle_to; 2991 2992 u8 reserved_at_40[0x60]; 2993 2994 struct mlx5_ifc_default_timeout_bits health_poll_to; 2995 2996 struct mlx5_ifc_default_timeout_bits full_crdump_to; 2997 2998 struct mlx5_ifc_default_timeout_bits fw_reset_to; 2999 3000 struct mlx5_ifc_default_timeout_bits flush_on_err_to; 3001 3002 struct mlx5_ifc_default_timeout_bits pci_sync_update_to; 3003 3004 struct mlx5_ifc_default_timeout_bits tear_down_to; 3005 3006 struct mlx5_ifc_default_timeout_bits fsm_reactivate_to; 3007 3008 struct mlx5_ifc_default_timeout_bits reclaim_pages_to; 3009 3010 struct mlx5_ifc_default_timeout_bits reclaim_vfs_pages_to; 3011 3012 u8 reserved_at_1c0[0x40]; 3013 }; 3014 3015 enum { 3016 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1, 3017 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2, 3018 }; 3019 3020 struct mlx5_ifc_cq_error_bits { 3021 u8 reserved_at_0[0x8]; 3022 u8 cqn[0x18]; 3023 3024 u8 reserved_at_20[0x20]; 3025 3026 u8 reserved_at_40[0x18]; 3027 u8 syndrome[0x8]; 3028 3029 u8 reserved_at_60[0x80]; 3030 }; 3031 3032 struct mlx5_ifc_rdma_page_fault_event_bits { 3033 u8 bytes_committed[0x20]; 3034 3035 u8 r_key[0x20]; 3036 3037 u8 reserved_at_40[0x10]; 3038 u8 packet_len[0x10]; 3039 3040 u8 rdma_op_len[0x20]; 3041 3042 u8 rdma_va[0x40]; 3043 3044 u8 reserved_at_c0[0x5]; 3045 u8 rdma[0x1]; 3046 u8 write[0x1]; 3047 u8 requestor[0x1]; 3048 u8 qp_number[0x18]; 3049 }; 3050 3051 struct mlx5_ifc_wqe_associated_page_fault_event_bits { 3052 u8 bytes_committed[0x20]; 3053 3054 u8 reserved_at_20[0x10]; 3055 u8 wqe_index[0x10]; 3056 3057 u8 reserved_at_40[0x10]; 3058 u8 len[0x10]; 3059 3060 u8 reserved_at_60[0x60]; 3061 3062 u8 reserved_at_c0[0x5]; 3063 u8 rdma[0x1]; 3064 u8 write_read[0x1]; 3065 u8 requestor[0x1]; 3066 u8 qpn[0x18]; 3067 }; 3068 3069 struct mlx5_ifc_qp_events_bits { 3070 u8 reserved_at_0[0xa0]; 3071 3072 u8 type[0x8]; 3073 u8 reserved_at_a8[0x18]; 3074 3075 u8 reserved_at_c0[0x8]; 3076 u8 qpn_rqn_sqn[0x18]; 3077 }; 3078 3079 struct mlx5_ifc_dct_events_bits { 3080 u8 reserved_at_0[0xc0]; 3081 3082 u8 reserved_at_c0[0x8]; 3083 u8 dct_number[0x18]; 3084 }; 3085 3086 struct mlx5_ifc_comp_event_bits { 3087 u8 reserved_at_0[0xc0]; 3088 3089 u8 reserved_at_c0[0x8]; 3090 u8 cq_number[0x18]; 3091 }; 3092 3093 enum { 3094 MLX5_QPC_STATE_RST = 0x0, 3095 MLX5_QPC_STATE_INIT = 0x1, 3096 MLX5_QPC_STATE_RTR = 0x2, 3097 MLX5_QPC_STATE_RTS = 0x3, 3098 MLX5_QPC_STATE_SQER = 0x4, 3099 MLX5_QPC_STATE_ERR = 0x6, 3100 MLX5_QPC_STATE_SQD = 0x7, 3101 MLX5_QPC_STATE_SUSPENDED = 0x9, 3102 }; 3103 3104 enum { 3105 MLX5_QPC_ST_RC = 0x0, 3106 MLX5_QPC_ST_UC = 0x1, 3107 MLX5_QPC_ST_UD = 0x2, 3108 MLX5_QPC_ST_XRC = 0x3, 3109 MLX5_QPC_ST_DCI = 0x5, 3110 MLX5_QPC_ST_QP0 = 0x7, 3111 MLX5_QPC_ST_QP1 = 0x8, 3112 MLX5_QPC_ST_RAW_DATAGRAM = 0x9, 3113 MLX5_QPC_ST_REG_UMR = 0xc, 3114 }; 3115 3116 enum { 3117 MLX5_QPC_PM_STATE_ARMED = 0x0, 3118 MLX5_QPC_PM_STATE_REARM = 0x1, 3119 MLX5_QPC_PM_STATE_RESERVED = 0x2, 3120 MLX5_QPC_PM_STATE_MIGRATED = 0x3, 3121 }; 3122 3123 enum { 3124 MLX5_QPC_OFFLOAD_TYPE_RNDV = 0x1, 3125 }; 3126 3127 enum { 3128 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0, 3129 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1, 3130 }; 3131 3132 enum { 3133 MLX5_QPC_MTU_256_BYTES = 0x1, 3134 MLX5_QPC_MTU_512_BYTES = 0x2, 3135 MLX5_QPC_MTU_1K_BYTES = 0x3, 3136 MLX5_QPC_MTU_2K_BYTES = 0x4, 3137 MLX5_QPC_MTU_4K_BYTES = 0x5, 3138 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7, 3139 }; 3140 3141 enum { 3142 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1, 3143 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2, 3144 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3, 3145 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4, 3146 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5, 3147 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6, 3148 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7, 3149 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8, 3150 }; 3151 3152 enum { 3153 MLX5_QPC_CS_REQ_DISABLE = 0x0, 3154 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11, 3155 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22, 3156 }; 3157 3158 enum { 3159 MLX5_QPC_CS_RES_DISABLE = 0x0, 3160 MLX5_QPC_CS_RES_UP_TO_32B = 0x1, 3161 MLX5_QPC_CS_RES_UP_TO_64B = 0x2, 3162 }; 3163 3164 enum { 3165 MLX5_TIMESTAMP_FORMAT_FREE_RUNNING = 0x0, 3166 MLX5_TIMESTAMP_FORMAT_DEFAULT = 0x1, 3167 MLX5_TIMESTAMP_FORMAT_REAL_TIME = 0x2, 3168 }; 3169 3170 struct mlx5_ifc_qpc_bits { 3171 u8 state[0x4]; 3172 u8 lag_tx_port_affinity[0x4]; 3173 u8 st[0x8]; 3174 u8 reserved_at_10[0x2]; 3175 u8 isolate_vl_tc[0x1]; 3176 u8 pm_state[0x2]; 3177 u8 reserved_at_15[0x1]; 3178 u8 req_e2e_credit_mode[0x2]; 3179 u8 offload_type[0x4]; 3180 u8 end_padding_mode[0x2]; 3181 u8 reserved_at_1e[0x2]; 3182 3183 u8 wq_signature[0x1]; 3184 u8 block_lb_mc[0x1]; 3185 u8 atomic_like_write_en[0x1]; 3186 u8 latency_sensitive[0x1]; 3187 u8 reserved_at_24[0x1]; 3188 u8 drain_sigerr[0x1]; 3189 u8 reserved_at_26[0x2]; 3190 u8 pd[0x18]; 3191 3192 u8 mtu[0x3]; 3193 u8 log_msg_max[0x5]; 3194 u8 reserved_at_48[0x1]; 3195 u8 log_rq_size[0x4]; 3196 u8 log_rq_stride[0x3]; 3197 u8 no_sq[0x1]; 3198 u8 log_sq_size[0x4]; 3199 u8 reserved_at_55[0x3]; 3200 u8 ts_format[0x2]; 3201 u8 reserved_at_5a[0x1]; 3202 u8 rlky[0x1]; 3203 u8 ulp_stateless_offload_mode[0x4]; 3204 3205 u8 counter_set_id[0x8]; 3206 u8 uar_page[0x18]; 3207 3208 u8 reserved_at_80[0x8]; 3209 u8 user_index[0x18]; 3210 3211 u8 reserved_at_a0[0x3]; 3212 u8 log_page_size[0x5]; 3213 u8 remote_qpn[0x18]; 3214 3215 struct mlx5_ifc_ads_bits primary_address_path; 3216 3217 struct mlx5_ifc_ads_bits secondary_address_path; 3218 3219 u8 log_ack_req_freq[0x4]; 3220 u8 reserved_at_384[0x4]; 3221 u8 log_sra_max[0x3]; 3222 u8 reserved_at_38b[0x2]; 3223 u8 retry_count[0x3]; 3224 u8 rnr_retry[0x3]; 3225 u8 reserved_at_393[0x1]; 3226 u8 fre[0x1]; 3227 u8 cur_rnr_retry[0x3]; 3228 u8 cur_retry_count[0x3]; 3229 u8 reserved_at_39b[0x5]; 3230 3231 u8 reserved_at_3a0[0x20]; 3232 3233 u8 reserved_at_3c0[0x8]; 3234 u8 next_send_psn[0x18]; 3235 3236 u8 reserved_at_3e0[0x3]; 3237 u8 log_num_dci_stream_channels[0x5]; 3238 u8 cqn_snd[0x18]; 3239 3240 u8 reserved_at_400[0x3]; 3241 u8 log_num_dci_errored_streams[0x5]; 3242 u8 deth_sqpn[0x18]; 3243 3244 u8 reserved_at_420[0x20]; 3245 3246 u8 reserved_at_440[0x8]; 3247 u8 last_acked_psn[0x18]; 3248 3249 u8 reserved_at_460[0x8]; 3250 u8 ssn[0x18]; 3251 3252 u8 reserved_at_480[0x8]; 3253 u8 log_rra_max[0x3]; 3254 u8 reserved_at_48b[0x1]; 3255 u8 atomic_mode[0x4]; 3256 u8 rre[0x1]; 3257 u8 rwe[0x1]; 3258 u8 rae[0x1]; 3259 u8 reserved_at_493[0x1]; 3260 u8 page_offset[0x6]; 3261 u8 reserved_at_49a[0x3]; 3262 u8 cd_slave_receive[0x1]; 3263 u8 cd_slave_send[0x1]; 3264 u8 cd_master[0x1]; 3265 3266 u8 reserved_at_4a0[0x3]; 3267 u8 min_rnr_nak[0x5]; 3268 u8 next_rcv_psn[0x18]; 3269 3270 u8 reserved_at_4c0[0x8]; 3271 u8 xrcd[0x18]; 3272 3273 u8 reserved_at_4e0[0x8]; 3274 u8 cqn_rcv[0x18]; 3275 3276 u8 dbr_addr[0x40]; 3277 3278 u8 q_key[0x20]; 3279 3280 u8 reserved_at_560[0x5]; 3281 u8 rq_type[0x3]; 3282 u8 srqn_rmpn_xrqn[0x18]; 3283 3284 u8 reserved_at_580[0x8]; 3285 u8 rmsn[0x18]; 3286 3287 u8 hw_sq_wqebb_counter[0x10]; 3288 u8 sw_sq_wqebb_counter[0x10]; 3289 3290 u8 hw_rq_counter[0x20]; 3291 3292 u8 sw_rq_counter[0x20]; 3293 3294 u8 reserved_at_600[0x20]; 3295 3296 u8 reserved_at_620[0xf]; 3297 u8 cgs[0x1]; 3298 u8 cs_req[0x8]; 3299 u8 cs_res[0x8]; 3300 3301 u8 dc_access_key[0x40]; 3302 3303 u8 reserved_at_680[0x3]; 3304 u8 dbr_umem_valid[0x1]; 3305 3306 u8 reserved_at_684[0xbc]; 3307 }; 3308 3309 struct mlx5_ifc_roce_addr_layout_bits { 3310 u8 source_l3_address[16][0x8]; 3311 3312 u8 reserved_at_80[0x3]; 3313 u8 vlan_valid[0x1]; 3314 u8 vlan_id[0xc]; 3315 u8 source_mac_47_32[0x10]; 3316 3317 u8 source_mac_31_0[0x20]; 3318 3319 u8 reserved_at_c0[0x14]; 3320 u8 roce_l3_type[0x4]; 3321 u8 roce_version[0x8]; 3322 3323 u8 reserved_at_e0[0x20]; 3324 }; 3325 3326 struct mlx5_ifc_shampo_cap_bits { 3327 u8 reserved_at_0[0x3]; 3328 u8 shampo_log_max_reservation_size[0x5]; 3329 u8 reserved_at_8[0x3]; 3330 u8 shampo_log_min_reservation_size[0x5]; 3331 u8 shampo_min_mss_size[0x10]; 3332 3333 u8 reserved_at_20[0x3]; 3334 u8 shampo_max_log_headers_entry_size[0x5]; 3335 u8 reserved_at_28[0x18]; 3336 3337 u8 reserved_at_40[0x7c0]; 3338 }; 3339 3340 union mlx5_ifc_hca_cap_union_bits { 3341 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap; 3342 struct mlx5_ifc_cmd_hca_cap_2_bits cmd_hca_cap_2; 3343 struct mlx5_ifc_odp_cap_bits odp_cap; 3344 struct mlx5_ifc_atomic_caps_bits atomic_caps; 3345 struct mlx5_ifc_roce_cap_bits roce_cap; 3346 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps; 3347 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap; 3348 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap; 3349 struct mlx5_ifc_e_switch_cap_bits e_switch_cap; 3350 struct mlx5_ifc_port_selection_cap_bits port_selection_cap; 3351 struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap; 3352 struct mlx5_ifc_qos_cap_bits qos_cap; 3353 struct mlx5_ifc_debug_cap_bits debug_cap; 3354 struct mlx5_ifc_fpga_cap_bits fpga_cap; 3355 struct mlx5_ifc_tls_cap_bits tls_cap; 3356 struct mlx5_ifc_device_mem_cap_bits device_mem_cap; 3357 struct mlx5_ifc_virtio_emulation_cap_bits virtio_emulation_cap; 3358 struct mlx5_ifc_shampo_cap_bits shampo_cap; 3359 struct mlx5_ifc_macsec_cap_bits macsec_cap; 3360 u8 reserved_at_0[0x8000]; 3361 }; 3362 3363 enum { 3364 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1, 3365 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2, 3366 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4, 3367 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8, 3368 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT = 0x10, 3369 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20, 3370 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR = 0x40, 3371 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP = 0x80, 3372 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH = 0x100, 3373 MLX5_FLOW_CONTEXT_ACTION_VLAN_POP_2 = 0x400, 3374 MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH_2 = 0x800, 3375 MLX5_FLOW_CONTEXT_ACTION_CRYPTO_DECRYPT = 0x1000, 3376 MLX5_FLOW_CONTEXT_ACTION_CRYPTO_ENCRYPT = 0x2000, 3377 MLX5_FLOW_CONTEXT_ACTION_EXECUTE_ASO = 0x4000, 3378 }; 3379 3380 enum { 3381 MLX5_FLOW_CONTEXT_FLOW_SOURCE_ANY_VPORT = 0x0, 3382 MLX5_FLOW_CONTEXT_FLOW_SOURCE_UPLINK = 0x1, 3383 MLX5_FLOW_CONTEXT_FLOW_SOURCE_LOCAL_VPORT = 0x2, 3384 }; 3385 3386 enum { 3387 MLX5_FLOW_CONTEXT_ENCRYPT_DECRYPT_TYPE_IPSEC = 0x0, 3388 MLX5_FLOW_CONTEXT_ENCRYPT_DECRYPT_TYPE_MACSEC = 0x1, 3389 }; 3390 3391 struct mlx5_ifc_vlan_bits { 3392 u8 ethtype[0x10]; 3393 u8 prio[0x3]; 3394 u8 cfi[0x1]; 3395 u8 vid[0xc]; 3396 }; 3397 3398 enum { 3399 MLX5_FLOW_METER_COLOR_RED = 0x0, 3400 MLX5_FLOW_METER_COLOR_YELLOW = 0x1, 3401 MLX5_FLOW_METER_COLOR_GREEN = 0x2, 3402 MLX5_FLOW_METER_COLOR_UNDEFINED = 0x3, 3403 }; 3404 3405 enum { 3406 MLX5_EXE_ASO_FLOW_METER = 0x2, 3407 }; 3408 3409 struct mlx5_ifc_exe_aso_ctrl_flow_meter_bits { 3410 u8 return_reg_id[0x4]; 3411 u8 aso_type[0x4]; 3412 u8 reserved_at_8[0x14]; 3413 u8 action[0x1]; 3414 u8 init_color[0x2]; 3415 u8 meter_id[0x1]; 3416 }; 3417 3418 union mlx5_ifc_exe_aso_ctrl { 3419 struct mlx5_ifc_exe_aso_ctrl_flow_meter_bits exe_aso_ctrl_flow_meter; 3420 }; 3421 3422 struct mlx5_ifc_execute_aso_bits { 3423 u8 valid[0x1]; 3424 u8 reserved_at_1[0x7]; 3425 u8 aso_object_id[0x18]; 3426 3427 union mlx5_ifc_exe_aso_ctrl exe_aso_ctrl; 3428 }; 3429 3430 struct mlx5_ifc_flow_context_bits { 3431 struct mlx5_ifc_vlan_bits push_vlan; 3432 3433 u8 group_id[0x20]; 3434 3435 u8 reserved_at_40[0x8]; 3436 u8 flow_tag[0x18]; 3437 3438 u8 reserved_at_60[0x10]; 3439 u8 action[0x10]; 3440 3441 u8 extended_destination[0x1]; 3442 u8 reserved_at_81[0x1]; 3443 u8 flow_source[0x2]; 3444 u8 encrypt_decrypt_type[0x4]; 3445 u8 destination_list_size[0x18]; 3446 3447 u8 reserved_at_a0[0x8]; 3448 u8 flow_counter_list_size[0x18]; 3449 3450 u8 packet_reformat_id[0x20]; 3451 3452 u8 modify_header_id[0x20]; 3453 3454 struct mlx5_ifc_vlan_bits push_vlan_2; 3455 3456 u8 encrypt_decrypt_obj_id[0x20]; 3457 u8 reserved_at_140[0xc0]; 3458 3459 struct mlx5_ifc_fte_match_param_bits match_value; 3460 3461 struct mlx5_ifc_execute_aso_bits execute_aso[4]; 3462 3463 u8 reserved_at_1300[0x500]; 3464 3465 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[]; 3466 }; 3467 3468 enum { 3469 MLX5_XRC_SRQC_STATE_GOOD = 0x0, 3470 MLX5_XRC_SRQC_STATE_ERROR = 0x1, 3471 }; 3472 3473 struct mlx5_ifc_xrc_srqc_bits { 3474 u8 state[0x4]; 3475 u8 log_xrc_srq_size[0x4]; 3476 u8 reserved_at_8[0x18]; 3477 3478 u8 wq_signature[0x1]; 3479 u8 cont_srq[0x1]; 3480 u8 reserved_at_22[0x1]; 3481 u8 rlky[0x1]; 3482 u8 basic_cyclic_rcv_wqe[0x1]; 3483 u8 log_rq_stride[0x3]; 3484 u8 xrcd[0x18]; 3485 3486 u8 page_offset[0x6]; 3487 u8 reserved_at_46[0x1]; 3488 u8 dbr_umem_valid[0x1]; 3489 u8 cqn[0x18]; 3490 3491 u8 reserved_at_60[0x20]; 3492 3493 u8 user_index_equal_xrc_srqn[0x1]; 3494 u8 reserved_at_81[0x1]; 3495 u8 log_page_size[0x6]; 3496 u8 user_index[0x18]; 3497 3498 u8 reserved_at_a0[0x20]; 3499 3500 u8 reserved_at_c0[0x8]; 3501 u8 pd[0x18]; 3502 3503 u8 lwm[0x10]; 3504 u8 wqe_cnt[0x10]; 3505 3506 u8 reserved_at_100[0x40]; 3507 3508 u8 db_record_addr_h[0x20]; 3509 3510 u8 db_record_addr_l[0x1e]; 3511 u8 reserved_at_17e[0x2]; 3512 3513 u8 reserved_at_180[0x80]; 3514 }; 3515 3516 struct mlx5_ifc_vnic_diagnostic_statistics_bits { 3517 u8 counter_error_queues[0x20]; 3518 3519 u8 total_error_queues[0x20]; 3520 3521 u8 send_queue_priority_update_flow[0x20]; 3522 3523 u8 reserved_at_60[0x20]; 3524 3525 u8 nic_receive_steering_discard[0x40]; 3526 3527 u8 receive_discard_vport_down[0x40]; 3528 3529 u8 transmit_discard_vport_down[0x40]; 3530 3531 u8 async_eq_overrun[0x20]; 3532 3533 u8 comp_eq_overrun[0x20]; 3534 3535 u8 reserved_at_180[0x20]; 3536 3537 u8 invalid_command[0x20]; 3538 3539 u8 quota_exceeded_command[0x20]; 3540 3541 u8 internal_rq_out_of_buffer[0x20]; 3542 3543 u8 cq_overrun[0x20]; 3544 3545 u8 eth_wqe_too_small[0x20]; 3546 3547 u8 reserved_at_220[0xdc0]; 3548 }; 3549 3550 struct mlx5_ifc_traffic_counter_bits { 3551 u8 packets[0x40]; 3552 3553 u8 octets[0x40]; 3554 }; 3555 3556 struct mlx5_ifc_tisc_bits { 3557 u8 strict_lag_tx_port_affinity[0x1]; 3558 u8 tls_en[0x1]; 3559 u8 reserved_at_2[0x2]; 3560 u8 lag_tx_port_affinity[0x04]; 3561 3562 u8 reserved_at_8[0x4]; 3563 u8 prio[0x4]; 3564 u8 reserved_at_10[0x10]; 3565 3566 u8 reserved_at_20[0x100]; 3567 3568 u8 reserved_at_120[0x8]; 3569 u8 transport_domain[0x18]; 3570 3571 u8 reserved_at_140[0x8]; 3572 u8 underlay_qpn[0x18]; 3573 3574 u8 reserved_at_160[0x8]; 3575 u8 pd[0x18]; 3576 3577 u8 reserved_at_180[0x380]; 3578 }; 3579 3580 enum { 3581 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0, 3582 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1, 3583 }; 3584 3585 enum { 3586 MLX5_TIRC_PACKET_MERGE_MASK_IPV4_LRO = BIT(0), 3587 MLX5_TIRC_PACKET_MERGE_MASK_IPV6_LRO = BIT(1), 3588 }; 3589 3590 enum { 3591 MLX5_RX_HASH_FN_NONE = 0x0, 3592 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1, 3593 MLX5_RX_HASH_FN_TOEPLITZ = 0x2, 3594 }; 3595 3596 enum { 3597 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST = 0x1, 3598 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST = 0x2, 3599 }; 3600 3601 struct mlx5_ifc_tirc_bits { 3602 u8 reserved_at_0[0x20]; 3603 3604 u8 disp_type[0x4]; 3605 u8 tls_en[0x1]; 3606 u8 reserved_at_25[0x1b]; 3607 3608 u8 reserved_at_40[0x40]; 3609 3610 u8 reserved_at_80[0x4]; 3611 u8 lro_timeout_period_usecs[0x10]; 3612 u8 packet_merge_mask[0x4]; 3613 u8 lro_max_ip_payload_size[0x8]; 3614 3615 u8 reserved_at_a0[0x40]; 3616 3617 u8 reserved_at_e0[0x8]; 3618 u8 inline_rqn[0x18]; 3619 3620 u8 rx_hash_symmetric[0x1]; 3621 u8 reserved_at_101[0x1]; 3622 u8 tunneled_offload_en[0x1]; 3623 u8 reserved_at_103[0x5]; 3624 u8 indirect_table[0x18]; 3625 3626 u8 rx_hash_fn[0x4]; 3627 u8 reserved_at_124[0x2]; 3628 u8 self_lb_block[0x2]; 3629 u8 transport_domain[0x18]; 3630 3631 u8 rx_hash_toeplitz_key[10][0x20]; 3632 3633 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer; 3634 3635 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner; 3636 3637 u8 reserved_at_2c0[0x4c0]; 3638 }; 3639 3640 enum { 3641 MLX5_SRQC_STATE_GOOD = 0x0, 3642 MLX5_SRQC_STATE_ERROR = 0x1, 3643 }; 3644 3645 struct mlx5_ifc_srqc_bits { 3646 u8 state[0x4]; 3647 u8 log_srq_size[0x4]; 3648 u8 reserved_at_8[0x18]; 3649 3650 u8 wq_signature[0x1]; 3651 u8 cont_srq[0x1]; 3652 u8 reserved_at_22[0x1]; 3653 u8 rlky[0x1]; 3654 u8 reserved_at_24[0x1]; 3655 u8 log_rq_stride[0x3]; 3656 u8 xrcd[0x18]; 3657 3658 u8 page_offset[0x6]; 3659 u8 reserved_at_46[0x2]; 3660 u8 cqn[0x18]; 3661 3662 u8 reserved_at_60[0x20]; 3663 3664 u8 reserved_at_80[0x2]; 3665 u8 log_page_size[0x6]; 3666 u8 reserved_at_88[0x18]; 3667 3668 u8 reserved_at_a0[0x20]; 3669 3670 u8 reserved_at_c0[0x8]; 3671 u8 pd[0x18]; 3672 3673 u8 lwm[0x10]; 3674 u8 wqe_cnt[0x10]; 3675 3676 u8 reserved_at_100[0x40]; 3677 3678 u8 dbr_addr[0x40]; 3679 3680 u8 reserved_at_180[0x80]; 3681 }; 3682 3683 enum { 3684 MLX5_SQC_STATE_RST = 0x0, 3685 MLX5_SQC_STATE_RDY = 0x1, 3686 MLX5_SQC_STATE_ERR = 0x3, 3687 }; 3688 3689 struct mlx5_ifc_sqc_bits { 3690 u8 rlky[0x1]; 3691 u8 cd_master[0x1]; 3692 u8 fre[0x1]; 3693 u8 flush_in_error_en[0x1]; 3694 u8 allow_multi_pkt_send_wqe[0x1]; 3695 u8 min_wqe_inline_mode[0x3]; 3696 u8 state[0x4]; 3697 u8 reg_umr[0x1]; 3698 u8 allow_swp[0x1]; 3699 u8 hairpin[0x1]; 3700 u8 reserved_at_f[0xb]; 3701 u8 ts_format[0x2]; 3702 u8 reserved_at_1c[0x4]; 3703 3704 u8 reserved_at_20[0x8]; 3705 u8 user_index[0x18]; 3706 3707 u8 reserved_at_40[0x8]; 3708 u8 cqn[0x18]; 3709 3710 u8 reserved_at_60[0x8]; 3711 u8 hairpin_peer_rq[0x18]; 3712 3713 u8 reserved_at_80[0x10]; 3714 u8 hairpin_peer_vhca[0x10]; 3715 3716 u8 reserved_at_a0[0x20]; 3717 3718 u8 reserved_at_c0[0x8]; 3719 u8 ts_cqe_to_dest_cqn[0x18]; 3720 3721 u8 reserved_at_e0[0x10]; 3722 u8 packet_pacing_rate_limit_index[0x10]; 3723 u8 tis_lst_sz[0x10]; 3724 u8 qos_queue_group_id[0x10]; 3725 3726 u8 reserved_at_120[0x40]; 3727 3728 u8 reserved_at_160[0x8]; 3729 u8 tis_num_0[0x18]; 3730 3731 struct mlx5_ifc_wq_bits wq; 3732 }; 3733 3734 enum { 3735 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0, 3736 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1, 3737 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2, 3738 SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3, 3739 SCHEDULING_CONTEXT_ELEMENT_TYPE_QUEUE_GROUP = 0x4, 3740 }; 3741 3742 enum { 3743 ELEMENT_TYPE_CAP_MASK_TASR = 1 << 0, 3744 ELEMENT_TYPE_CAP_MASK_VPORT = 1 << 1, 3745 ELEMENT_TYPE_CAP_MASK_VPORT_TC = 1 << 2, 3746 ELEMENT_TYPE_CAP_MASK_PARA_VPORT_TC = 1 << 3, 3747 }; 3748 3749 struct mlx5_ifc_scheduling_context_bits { 3750 u8 element_type[0x8]; 3751 u8 reserved_at_8[0x18]; 3752 3753 u8 element_attributes[0x20]; 3754 3755 u8 parent_element_id[0x20]; 3756 3757 u8 reserved_at_60[0x40]; 3758 3759 u8 bw_share[0x20]; 3760 3761 u8 max_average_bw[0x20]; 3762 3763 u8 reserved_at_e0[0x120]; 3764 }; 3765 3766 struct mlx5_ifc_rqtc_bits { 3767 u8 reserved_at_0[0xa0]; 3768 3769 u8 reserved_at_a0[0x5]; 3770 u8 list_q_type[0x3]; 3771 u8 reserved_at_a8[0x8]; 3772 u8 rqt_max_size[0x10]; 3773 3774 u8 rq_vhca_id_format[0x1]; 3775 u8 reserved_at_c1[0xf]; 3776 u8 rqt_actual_size[0x10]; 3777 3778 u8 reserved_at_e0[0x6a0]; 3779 3780 struct mlx5_ifc_rq_num_bits rq_num[]; 3781 }; 3782 3783 enum { 3784 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0, 3785 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1, 3786 }; 3787 3788 enum { 3789 MLX5_RQC_STATE_RST = 0x0, 3790 MLX5_RQC_STATE_RDY = 0x1, 3791 MLX5_RQC_STATE_ERR = 0x3, 3792 }; 3793 3794 enum { 3795 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_BYTE = 0x0, 3796 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_STRIDE = 0x1, 3797 MLX5_RQC_SHAMPO_NO_MATCH_ALIGNMENT_GRANULARITY_PAGE = 0x2, 3798 }; 3799 3800 enum { 3801 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_NO_MATCH = 0x0, 3802 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_EXTENDED = 0x1, 3803 MLX5_RQC_SHAMPO_MATCH_CRITERIA_TYPE_FIVE_TUPLE = 0x2, 3804 }; 3805 3806 struct mlx5_ifc_rqc_bits { 3807 u8 rlky[0x1]; 3808 u8 delay_drop_en[0x1]; 3809 u8 scatter_fcs[0x1]; 3810 u8 vsd[0x1]; 3811 u8 mem_rq_type[0x4]; 3812 u8 state[0x4]; 3813 u8 reserved_at_c[0x1]; 3814 u8 flush_in_error_en[0x1]; 3815 u8 hairpin[0x1]; 3816 u8 reserved_at_f[0xb]; 3817 u8 ts_format[0x2]; 3818 u8 reserved_at_1c[0x4]; 3819 3820 u8 reserved_at_20[0x8]; 3821 u8 user_index[0x18]; 3822 3823 u8 reserved_at_40[0x8]; 3824 u8 cqn[0x18]; 3825 3826 u8 counter_set_id[0x8]; 3827 u8 reserved_at_68[0x18]; 3828 3829 u8 reserved_at_80[0x8]; 3830 u8 rmpn[0x18]; 3831 3832 u8 reserved_at_a0[0x8]; 3833 u8 hairpin_peer_sq[0x18]; 3834 3835 u8 reserved_at_c0[0x10]; 3836 u8 hairpin_peer_vhca[0x10]; 3837 3838 u8 reserved_at_e0[0x46]; 3839 u8 shampo_no_match_alignment_granularity[0x2]; 3840 u8 reserved_at_128[0x6]; 3841 u8 shampo_match_criteria_type[0x2]; 3842 u8 reservation_timeout[0x10]; 3843 3844 u8 reserved_at_140[0x40]; 3845 3846 struct mlx5_ifc_wq_bits wq; 3847 }; 3848 3849 enum { 3850 MLX5_RMPC_STATE_RDY = 0x1, 3851 MLX5_RMPC_STATE_ERR = 0x3, 3852 }; 3853 3854 struct mlx5_ifc_rmpc_bits { 3855 u8 reserved_at_0[0x8]; 3856 u8 state[0x4]; 3857 u8 reserved_at_c[0x14]; 3858 3859 u8 basic_cyclic_rcv_wqe[0x1]; 3860 u8 reserved_at_21[0x1f]; 3861 3862 u8 reserved_at_40[0x140]; 3863 3864 struct mlx5_ifc_wq_bits wq; 3865 }; 3866 3867 enum { 3868 VHCA_ID_TYPE_HW = 0, 3869 VHCA_ID_TYPE_SW = 1, 3870 }; 3871 3872 struct mlx5_ifc_nic_vport_context_bits { 3873 u8 reserved_at_0[0x5]; 3874 u8 min_wqe_inline_mode[0x3]; 3875 u8 reserved_at_8[0x15]; 3876 u8 disable_mc_local_lb[0x1]; 3877 u8 disable_uc_local_lb[0x1]; 3878 u8 roce_en[0x1]; 3879 3880 u8 arm_change_event[0x1]; 3881 u8 reserved_at_21[0x1a]; 3882 u8 event_on_mtu[0x1]; 3883 u8 event_on_promisc_change[0x1]; 3884 u8 event_on_vlan_change[0x1]; 3885 u8 event_on_mc_address_change[0x1]; 3886 u8 event_on_uc_address_change[0x1]; 3887 3888 u8 vhca_id_type[0x1]; 3889 u8 reserved_at_41[0xb]; 3890 u8 affiliation_criteria[0x4]; 3891 u8 affiliated_vhca_id[0x10]; 3892 3893 u8 reserved_at_60[0xd0]; 3894 3895 u8 mtu[0x10]; 3896 3897 u8 system_image_guid[0x40]; 3898 u8 port_guid[0x40]; 3899 u8 node_guid[0x40]; 3900 3901 u8 reserved_at_200[0x140]; 3902 u8 qkey_violation_counter[0x10]; 3903 u8 reserved_at_350[0x430]; 3904 3905 u8 promisc_uc[0x1]; 3906 u8 promisc_mc[0x1]; 3907 u8 promisc_all[0x1]; 3908 u8 reserved_at_783[0x2]; 3909 u8 allowed_list_type[0x3]; 3910 u8 reserved_at_788[0xc]; 3911 u8 allowed_list_size[0xc]; 3912 3913 struct mlx5_ifc_mac_address_layout_bits permanent_address; 3914 3915 u8 reserved_at_7e0[0x20]; 3916 3917 u8 current_uc_mac_address[][0x40]; 3918 }; 3919 3920 enum { 3921 MLX5_MKC_ACCESS_MODE_PA = 0x0, 3922 MLX5_MKC_ACCESS_MODE_MTT = 0x1, 3923 MLX5_MKC_ACCESS_MODE_KLMS = 0x2, 3924 MLX5_MKC_ACCESS_MODE_KSM = 0x3, 3925 MLX5_MKC_ACCESS_MODE_SW_ICM = 0x4, 3926 MLX5_MKC_ACCESS_MODE_MEMIC = 0x5, 3927 }; 3928 3929 struct mlx5_ifc_mkc_bits { 3930 u8 reserved_at_0[0x1]; 3931 u8 free[0x1]; 3932 u8 reserved_at_2[0x1]; 3933 u8 access_mode_4_2[0x3]; 3934 u8 reserved_at_6[0x7]; 3935 u8 relaxed_ordering_write[0x1]; 3936 u8 reserved_at_e[0x1]; 3937 u8 small_fence_on_rdma_read_response[0x1]; 3938 u8 umr_en[0x1]; 3939 u8 a[0x1]; 3940 u8 rw[0x1]; 3941 u8 rr[0x1]; 3942 u8 lw[0x1]; 3943 u8 lr[0x1]; 3944 u8 access_mode_1_0[0x2]; 3945 u8 reserved_at_18[0x2]; 3946 u8 ma_translation_mode[0x2]; 3947 u8 reserved_at_1c[0x4]; 3948 3949 u8 qpn[0x18]; 3950 u8 mkey_7_0[0x8]; 3951 3952 u8 reserved_at_40[0x20]; 3953 3954 u8 length64[0x1]; 3955 u8 bsf_en[0x1]; 3956 u8 sync_umr[0x1]; 3957 u8 reserved_at_63[0x2]; 3958 u8 expected_sigerr_count[0x1]; 3959 u8 reserved_at_66[0x1]; 3960 u8 en_rinval[0x1]; 3961 u8 pd[0x18]; 3962 3963 u8 start_addr[0x40]; 3964 3965 u8 len[0x40]; 3966 3967 u8 bsf_octword_size[0x20]; 3968 3969 u8 reserved_at_120[0x80]; 3970 3971 u8 translations_octword_size[0x20]; 3972 3973 u8 reserved_at_1c0[0x19]; 3974 u8 relaxed_ordering_read[0x1]; 3975 u8 reserved_at_1d9[0x1]; 3976 u8 log_page_size[0x5]; 3977 3978 u8 reserved_at_1e0[0x20]; 3979 }; 3980 3981 struct mlx5_ifc_pkey_bits { 3982 u8 reserved_at_0[0x10]; 3983 u8 pkey[0x10]; 3984 }; 3985 3986 struct mlx5_ifc_array128_auto_bits { 3987 u8 array128_auto[16][0x8]; 3988 }; 3989 3990 struct mlx5_ifc_hca_vport_context_bits { 3991 u8 field_select[0x20]; 3992 3993 u8 reserved_at_20[0xe0]; 3994 3995 u8 sm_virt_aware[0x1]; 3996 u8 has_smi[0x1]; 3997 u8 has_raw[0x1]; 3998 u8 grh_required[0x1]; 3999 u8 reserved_at_104[0xc]; 4000 u8 port_physical_state[0x4]; 4001 u8 vport_state_policy[0x4]; 4002 u8 port_state[0x4]; 4003 u8 vport_state[0x4]; 4004 4005 u8 reserved_at_120[0x20]; 4006 4007 u8 system_image_guid[0x40]; 4008 4009 u8 port_guid[0x40]; 4010 4011 u8 node_guid[0x40]; 4012 4013 u8 cap_mask1[0x20]; 4014 4015 u8 cap_mask1_field_select[0x20]; 4016 4017 u8 cap_mask2[0x20]; 4018 4019 u8 cap_mask2_field_select[0x20]; 4020 4021 u8 reserved_at_280[0x80]; 4022 4023 u8 lid[0x10]; 4024 u8 reserved_at_310[0x4]; 4025 u8 init_type_reply[0x4]; 4026 u8 lmc[0x3]; 4027 u8 subnet_timeout[0x5]; 4028 4029 u8 sm_lid[0x10]; 4030 u8 sm_sl[0x4]; 4031 u8 reserved_at_334[0xc]; 4032 4033 u8 qkey_violation_counter[0x10]; 4034 u8 pkey_violation_counter[0x10]; 4035 4036 u8 reserved_at_360[0xca0]; 4037 }; 4038 4039 struct mlx5_ifc_esw_vport_context_bits { 4040 u8 fdb_to_vport_reg_c[0x1]; 4041 u8 reserved_at_1[0x2]; 4042 u8 vport_svlan_strip[0x1]; 4043 u8 vport_cvlan_strip[0x1]; 4044 u8 vport_svlan_insert[0x1]; 4045 u8 vport_cvlan_insert[0x2]; 4046 u8 fdb_to_vport_reg_c_id[0x8]; 4047 u8 reserved_at_10[0x10]; 4048 4049 u8 reserved_at_20[0x20]; 4050 4051 u8 svlan_cfi[0x1]; 4052 u8 svlan_pcp[0x3]; 4053 u8 svlan_id[0xc]; 4054 u8 cvlan_cfi[0x1]; 4055 u8 cvlan_pcp[0x3]; 4056 u8 cvlan_id[0xc]; 4057 4058 u8 reserved_at_60[0x720]; 4059 4060 u8 sw_steering_vport_icm_address_rx[0x40]; 4061 4062 u8 sw_steering_vport_icm_address_tx[0x40]; 4063 }; 4064 4065 enum { 4066 MLX5_EQC_STATUS_OK = 0x0, 4067 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa, 4068 }; 4069 4070 enum { 4071 MLX5_EQC_ST_ARMED = 0x9, 4072 MLX5_EQC_ST_FIRED = 0xa, 4073 }; 4074 4075 struct mlx5_ifc_eqc_bits { 4076 u8 status[0x4]; 4077 u8 reserved_at_4[0x9]; 4078 u8 ec[0x1]; 4079 u8 oi[0x1]; 4080 u8 reserved_at_f[0x5]; 4081 u8 st[0x4]; 4082 u8 reserved_at_18[0x8]; 4083 4084 u8 reserved_at_20[0x20]; 4085 4086 u8 reserved_at_40[0x14]; 4087 u8 page_offset[0x6]; 4088 u8 reserved_at_5a[0x6]; 4089 4090 u8 reserved_at_60[0x3]; 4091 u8 log_eq_size[0x5]; 4092 u8 uar_page[0x18]; 4093 4094 u8 reserved_at_80[0x20]; 4095 4096 u8 reserved_at_a0[0x14]; 4097 u8 intr[0xc]; 4098 4099 u8 reserved_at_c0[0x3]; 4100 u8 log_page_size[0x5]; 4101 u8 reserved_at_c8[0x18]; 4102 4103 u8 reserved_at_e0[0x60]; 4104 4105 u8 reserved_at_140[0x8]; 4106 u8 consumer_counter[0x18]; 4107 4108 u8 reserved_at_160[0x8]; 4109 u8 producer_counter[0x18]; 4110 4111 u8 reserved_at_180[0x80]; 4112 }; 4113 4114 enum { 4115 MLX5_DCTC_STATE_ACTIVE = 0x0, 4116 MLX5_DCTC_STATE_DRAINING = 0x1, 4117 MLX5_DCTC_STATE_DRAINED = 0x2, 4118 }; 4119 4120 enum { 4121 MLX5_DCTC_CS_RES_DISABLE = 0x0, 4122 MLX5_DCTC_CS_RES_NA = 0x1, 4123 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2, 4124 }; 4125 4126 enum { 4127 MLX5_DCTC_MTU_256_BYTES = 0x1, 4128 MLX5_DCTC_MTU_512_BYTES = 0x2, 4129 MLX5_DCTC_MTU_1K_BYTES = 0x3, 4130 MLX5_DCTC_MTU_2K_BYTES = 0x4, 4131 MLX5_DCTC_MTU_4K_BYTES = 0x5, 4132 }; 4133 4134 struct mlx5_ifc_dctc_bits { 4135 u8 reserved_at_0[0x4]; 4136 u8 state[0x4]; 4137 u8 reserved_at_8[0x18]; 4138 4139 u8 reserved_at_20[0x8]; 4140 u8 user_index[0x18]; 4141 4142 u8 reserved_at_40[0x8]; 4143 u8 cqn[0x18]; 4144 4145 u8 counter_set_id[0x8]; 4146 u8 atomic_mode[0x4]; 4147 u8 rre[0x1]; 4148 u8 rwe[0x1]; 4149 u8 rae[0x1]; 4150 u8 atomic_like_write_en[0x1]; 4151 u8 latency_sensitive[0x1]; 4152 u8 rlky[0x1]; 4153 u8 free_ar[0x1]; 4154 u8 reserved_at_73[0xd]; 4155 4156 u8 reserved_at_80[0x8]; 4157 u8 cs_res[0x8]; 4158 u8 reserved_at_90[0x3]; 4159 u8 min_rnr_nak[0x5]; 4160 u8 reserved_at_98[0x8]; 4161 4162 u8 reserved_at_a0[0x8]; 4163 u8 srqn_xrqn[0x18]; 4164 4165 u8 reserved_at_c0[0x8]; 4166 u8 pd[0x18]; 4167 4168 u8 tclass[0x8]; 4169 u8 reserved_at_e8[0x4]; 4170 u8 flow_label[0x14]; 4171 4172 u8 dc_access_key[0x40]; 4173 4174 u8 reserved_at_140[0x5]; 4175 u8 mtu[0x3]; 4176 u8 port[0x8]; 4177 u8 pkey_index[0x10]; 4178 4179 u8 reserved_at_160[0x8]; 4180 u8 my_addr_index[0x8]; 4181 u8 reserved_at_170[0x8]; 4182 u8 hop_limit[0x8]; 4183 4184 u8 dc_access_key_violation_count[0x20]; 4185 4186 u8 reserved_at_1a0[0x14]; 4187 u8 dei_cfi[0x1]; 4188 u8 eth_prio[0x3]; 4189 u8 ecn[0x2]; 4190 u8 dscp[0x6]; 4191 4192 u8 reserved_at_1c0[0x20]; 4193 u8 ece[0x20]; 4194 }; 4195 4196 enum { 4197 MLX5_CQC_STATUS_OK = 0x0, 4198 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9, 4199 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa, 4200 }; 4201 4202 enum { 4203 MLX5_CQC_CQE_SZ_64_BYTES = 0x0, 4204 MLX5_CQC_CQE_SZ_128_BYTES = 0x1, 4205 }; 4206 4207 enum { 4208 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6, 4209 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9, 4210 MLX5_CQC_ST_FIRED = 0xa, 4211 }; 4212 4213 enum { 4214 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0, 4215 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1, 4216 MLX5_CQ_PERIOD_NUM_MODES 4217 }; 4218 4219 struct mlx5_ifc_cqc_bits { 4220 u8 status[0x4]; 4221 u8 reserved_at_4[0x2]; 4222 u8 dbr_umem_valid[0x1]; 4223 u8 apu_cq[0x1]; 4224 u8 cqe_sz[0x3]; 4225 u8 cc[0x1]; 4226 u8 reserved_at_c[0x1]; 4227 u8 scqe_break_moderation_en[0x1]; 4228 u8 oi[0x1]; 4229 u8 cq_period_mode[0x2]; 4230 u8 cqe_comp_en[0x1]; 4231 u8 mini_cqe_res_format[0x2]; 4232 u8 st[0x4]; 4233 u8 reserved_at_18[0x6]; 4234 u8 cqe_compression_layout[0x2]; 4235 4236 u8 reserved_at_20[0x20]; 4237 4238 u8 reserved_at_40[0x14]; 4239 u8 page_offset[0x6]; 4240 u8 reserved_at_5a[0x6]; 4241 4242 u8 reserved_at_60[0x3]; 4243 u8 log_cq_size[0x5]; 4244 u8 uar_page[0x18]; 4245 4246 u8 reserved_at_80[0x4]; 4247 u8 cq_period[0xc]; 4248 u8 cq_max_count[0x10]; 4249 4250 u8 c_eqn_or_apu_element[0x20]; 4251 4252 u8 reserved_at_c0[0x3]; 4253 u8 log_page_size[0x5]; 4254 u8 reserved_at_c8[0x18]; 4255 4256 u8 reserved_at_e0[0x20]; 4257 4258 u8 reserved_at_100[0x8]; 4259 u8 last_notified_index[0x18]; 4260 4261 u8 reserved_at_120[0x8]; 4262 u8 last_solicit_index[0x18]; 4263 4264 u8 reserved_at_140[0x8]; 4265 u8 consumer_counter[0x18]; 4266 4267 u8 reserved_at_160[0x8]; 4268 u8 producer_counter[0x18]; 4269 4270 u8 reserved_at_180[0x40]; 4271 4272 u8 dbr_addr[0x40]; 4273 }; 4274 4275 union mlx5_ifc_cong_control_roce_ecn_auto_bits { 4276 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp; 4277 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp; 4278 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np; 4279 u8 reserved_at_0[0x800]; 4280 }; 4281 4282 struct mlx5_ifc_query_adapter_param_block_bits { 4283 u8 reserved_at_0[0xc0]; 4284 4285 u8 reserved_at_c0[0x8]; 4286 u8 ieee_vendor_id[0x18]; 4287 4288 u8 reserved_at_e0[0x10]; 4289 u8 vsd_vendor_id[0x10]; 4290 4291 u8 vsd[208][0x8]; 4292 4293 u8 vsd_contd_psid[16][0x8]; 4294 }; 4295 4296 enum { 4297 MLX5_XRQC_STATE_GOOD = 0x0, 4298 MLX5_XRQC_STATE_ERROR = 0x1, 4299 }; 4300 4301 enum { 4302 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0, 4303 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1, 4304 }; 4305 4306 enum { 4307 MLX5_XRQC_OFFLOAD_RNDV = 0x1, 4308 }; 4309 4310 struct mlx5_ifc_tag_matching_topology_context_bits { 4311 u8 log_matching_list_sz[0x4]; 4312 u8 reserved_at_4[0xc]; 4313 u8 append_next_index[0x10]; 4314 4315 u8 sw_phase_cnt[0x10]; 4316 u8 hw_phase_cnt[0x10]; 4317 4318 u8 reserved_at_40[0x40]; 4319 }; 4320 4321 struct mlx5_ifc_xrqc_bits { 4322 u8 state[0x4]; 4323 u8 rlkey[0x1]; 4324 u8 reserved_at_5[0xf]; 4325 u8 topology[0x4]; 4326 u8 reserved_at_18[0x4]; 4327 u8 offload[0x4]; 4328 4329 u8 reserved_at_20[0x8]; 4330 u8 user_index[0x18]; 4331 4332 u8 reserved_at_40[0x8]; 4333 u8 cqn[0x18]; 4334 4335 u8 reserved_at_60[0xa0]; 4336 4337 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context; 4338 4339 u8 reserved_at_180[0x280]; 4340 4341 struct mlx5_ifc_wq_bits wq; 4342 }; 4343 4344 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits { 4345 struct mlx5_ifc_modify_field_select_bits modify_field_select; 4346 struct mlx5_ifc_resize_field_select_bits resize_field_select; 4347 u8 reserved_at_0[0x20]; 4348 }; 4349 4350 union mlx5_ifc_field_select_802_1_r_roce_auto_bits { 4351 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp; 4352 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp; 4353 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np; 4354 u8 reserved_at_0[0x20]; 4355 }; 4356 4357 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits { 4358 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 4359 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 4360 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 4361 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 4362 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 4363 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 4364 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout; 4365 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout; 4366 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 4367 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 4368 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs; 4369 u8 reserved_at_0[0x7c0]; 4370 }; 4371 4372 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits { 4373 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout; 4374 u8 reserved_at_0[0x7c0]; 4375 }; 4376 4377 union mlx5_ifc_event_auto_bits { 4378 struct mlx5_ifc_comp_event_bits comp_event; 4379 struct mlx5_ifc_dct_events_bits dct_events; 4380 struct mlx5_ifc_qp_events_bits qp_events; 4381 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event; 4382 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event; 4383 struct mlx5_ifc_cq_error_bits cq_error; 4384 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged; 4385 struct mlx5_ifc_port_state_change_event_bits port_state_change_event; 4386 struct mlx5_ifc_gpio_event_bits gpio_event; 4387 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event; 4388 struct mlx5_ifc_stall_vl_event_bits stall_vl_event; 4389 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event; 4390 u8 reserved_at_0[0xe0]; 4391 }; 4392 4393 struct mlx5_ifc_health_buffer_bits { 4394 u8 reserved_at_0[0x100]; 4395 4396 u8 assert_existptr[0x20]; 4397 4398 u8 assert_callra[0x20]; 4399 4400 u8 reserved_at_140[0x20]; 4401 4402 u8 time[0x20]; 4403 4404 u8 fw_version[0x20]; 4405 4406 u8 hw_id[0x20]; 4407 4408 u8 rfr[0x1]; 4409 u8 reserved_at_1c1[0x3]; 4410 u8 valid[0x1]; 4411 u8 severity[0x3]; 4412 u8 reserved_at_1c8[0x18]; 4413 4414 u8 irisc_index[0x8]; 4415 u8 synd[0x8]; 4416 u8 ext_synd[0x10]; 4417 }; 4418 4419 struct mlx5_ifc_register_loopback_control_bits { 4420 u8 no_lb[0x1]; 4421 u8 reserved_at_1[0x7]; 4422 u8 port[0x8]; 4423 u8 reserved_at_10[0x10]; 4424 4425 u8 reserved_at_20[0x60]; 4426 }; 4427 4428 struct mlx5_ifc_vport_tc_element_bits { 4429 u8 traffic_class[0x4]; 4430 u8 reserved_at_4[0xc]; 4431 u8 vport_number[0x10]; 4432 }; 4433 4434 struct mlx5_ifc_vport_element_bits { 4435 u8 reserved_at_0[0x10]; 4436 u8 vport_number[0x10]; 4437 }; 4438 4439 enum { 4440 TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0, 4441 TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1, 4442 TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2, 4443 }; 4444 4445 struct mlx5_ifc_tsar_element_bits { 4446 u8 reserved_at_0[0x8]; 4447 u8 tsar_type[0x8]; 4448 u8 reserved_at_10[0x10]; 4449 }; 4450 4451 enum { 4452 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0, 4453 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1, 4454 }; 4455 4456 struct mlx5_ifc_teardown_hca_out_bits { 4457 u8 status[0x8]; 4458 u8 reserved_at_8[0x18]; 4459 4460 u8 syndrome[0x20]; 4461 4462 u8 reserved_at_40[0x3f]; 4463 4464 u8 state[0x1]; 4465 }; 4466 4467 enum { 4468 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0, 4469 MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1, 4470 MLX5_TEARDOWN_HCA_IN_PROFILE_PREPARE_FAST_TEARDOWN = 0x2, 4471 }; 4472 4473 struct mlx5_ifc_teardown_hca_in_bits { 4474 u8 opcode[0x10]; 4475 u8 reserved_at_10[0x10]; 4476 4477 u8 reserved_at_20[0x10]; 4478 u8 op_mod[0x10]; 4479 4480 u8 reserved_at_40[0x10]; 4481 u8 profile[0x10]; 4482 4483 u8 reserved_at_60[0x20]; 4484 }; 4485 4486 struct mlx5_ifc_sqerr2rts_qp_out_bits { 4487 u8 status[0x8]; 4488 u8 reserved_at_8[0x18]; 4489 4490 u8 syndrome[0x20]; 4491 4492 u8 reserved_at_40[0x40]; 4493 }; 4494 4495 struct mlx5_ifc_sqerr2rts_qp_in_bits { 4496 u8 opcode[0x10]; 4497 u8 uid[0x10]; 4498 4499 u8 reserved_at_20[0x10]; 4500 u8 op_mod[0x10]; 4501 4502 u8 reserved_at_40[0x8]; 4503 u8 qpn[0x18]; 4504 4505 u8 reserved_at_60[0x20]; 4506 4507 u8 opt_param_mask[0x20]; 4508 4509 u8 reserved_at_a0[0x20]; 4510 4511 struct mlx5_ifc_qpc_bits qpc; 4512 4513 u8 reserved_at_800[0x80]; 4514 }; 4515 4516 struct mlx5_ifc_sqd2rts_qp_out_bits { 4517 u8 status[0x8]; 4518 u8 reserved_at_8[0x18]; 4519 4520 u8 syndrome[0x20]; 4521 4522 u8 reserved_at_40[0x40]; 4523 }; 4524 4525 struct mlx5_ifc_sqd2rts_qp_in_bits { 4526 u8 opcode[0x10]; 4527 u8 uid[0x10]; 4528 4529 u8 reserved_at_20[0x10]; 4530 u8 op_mod[0x10]; 4531 4532 u8 reserved_at_40[0x8]; 4533 u8 qpn[0x18]; 4534 4535 u8 reserved_at_60[0x20]; 4536 4537 u8 opt_param_mask[0x20]; 4538 4539 u8 reserved_at_a0[0x20]; 4540 4541 struct mlx5_ifc_qpc_bits qpc; 4542 4543 u8 reserved_at_800[0x80]; 4544 }; 4545 4546 struct mlx5_ifc_set_roce_address_out_bits { 4547 u8 status[0x8]; 4548 u8 reserved_at_8[0x18]; 4549 4550 u8 syndrome[0x20]; 4551 4552 u8 reserved_at_40[0x40]; 4553 }; 4554 4555 struct mlx5_ifc_set_roce_address_in_bits { 4556 u8 opcode[0x10]; 4557 u8 reserved_at_10[0x10]; 4558 4559 u8 reserved_at_20[0x10]; 4560 u8 op_mod[0x10]; 4561 4562 u8 roce_address_index[0x10]; 4563 u8 reserved_at_50[0xc]; 4564 u8 vhca_port_num[0x4]; 4565 4566 u8 reserved_at_60[0x20]; 4567 4568 struct mlx5_ifc_roce_addr_layout_bits roce_address; 4569 }; 4570 4571 struct mlx5_ifc_set_mad_demux_out_bits { 4572 u8 status[0x8]; 4573 u8 reserved_at_8[0x18]; 4574 4575 u8 syndrome[0x20]; 4576 4577 u8 reserved_at_40[0x40]; 4578 }; 4579 4580 enum { 4581 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0, 4582 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2, 4583 }; 4584 4585 struct mlx5_ifc_set_mad_demux_in_bits { 4586 u8 opcode[0x10]; 4587 u8 reserved_at_10[0x10]; 4588 4589 u8 reserved_at_20[0x10]; 4590 u8 op_mod[0x10]; 4591 4592 u8 reserved_at_40[0x20]; 4593 4594 u8 reserved_at_60[0x6]; 4595 u8 demux_mode[0x2]; 4596 u8 reserved_at_68[0x18]; 4597 }; 4598 4599 struct mlx5_ifc_set_l2_table_entry_out_bits { 4600 u8 status[0x8]; 4601 u8 reserved_at_8[0x18]; 4602 4603 u8 syndrome[0x20]; 4604 4605 u8 reserved_at_40[0x40]; 4606 }; 4607 4608 struct mlx5_ifc_set_l2_table_entry_in_bits { 4609 u8 opcode[0x10]; 4610 u8 reserved_at_10[0x10]; 4611 4612 u8 reserved_at_20[0x10]; 4613 u8 op_mod[0x10]; 4614 4615 u8 reserved_at_40[0x60]; 4616 4617 u8 reserved_at_a0[0x8]; 4618 u8 table_index[0x18]; 4619 4620 u8 reserved_at_c0[0x20]; 4621 4622 u8 reserved_at_e0[0x13]; 4623 u8 vlan_valid[0x1]; 4624 u8 vlan[0xc]; 4625 4626 struct mlx5_ifc_mac_address_layout_bits mac_address; 4627 4628 u8 reserved_at_140[0xc0]; 4629 }; 4630 4631 struct mlx5_ifc_set_issi_out_bits { 4632 u8 status[0x8]; 4633 u8 reserved_at_8[0x18]; 4634 4635 u8 syndrome[0x20]; 4636 4637 u8 reserved_at_40[0x40]; 4638 }; 4639 4640 struct mlx5_ifc_set_issi_in_bits { 4641 u8 opcode[0x10]; 4642 u8 reserved_at_10[0x10]; 4643 4644 u8 reserved_at_20[0x10]; 4645 u8 op_mod[0x10]; 4646 4647 u8 reserved_at_40[0x10]; 4648 u8 current_issi[0x10]; 4649 4650 u8 reserved_at_60[0x20]; 4651 }; 4652 4653 struct mlx5_ifc_set_hca_cap_out_bits { 4654 u8 status[0x8]; 4655 u8 reserved_at_8[0x18]; 4656 4657 u8 syndrome[0x20]; 4658 4659 u8 reserved_at_40[0x40]; 4660 }; 4661 4662 struct mlx5_ifc_set_hca_cap_in_bits { 4663 u8 opcode[0x10]; 4664 u8 reserved_at_10[0x10]; 4665 4666 u8 reserved_at_20[0x10]; 4667 u8 op_mod[0x10]; 4668 4669 u8 other_function[0x1]; 4670 u8 reserved_at_41[0xf]; 4671 u8 function_id[0x10]; 4672 4673 u8 reserved_at_60[0x20]; 4674 4675 union mlx5_ifc_hca_cap_union_bits capability; 4676 }; 4677 4678 enum { 4679 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0, 4680 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1, 4681 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2, 4682 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3, 4683 MLX5_SET_FTE_MODIFY_ENABLE_MASK_IPSEC_OBJ_ID = 0x4 4684 }; 4685 4686 struct mlx5_ifc_set_fte_out_bits { 4687 u8 status[0x8]; 4688 u8 reserved_at_8[0x18]; 4689 4690 u8 syndrome[0x20]; 4691 4692 u8 reserved_at_40[0x40]; 4693 }; 4694 4695 struct mlx5_ifc_set_fte_in_bits { 4696 u8 opcode[0x10]; 4697 u8 reserved_at_10[0x10]; 4698 4699 u8 reserved_at_20[0x10]; 4700 u8 op_mod[0x10]; 4701 4702 u8 other_vport[0x1]; 4703 u8 reserved_at_41[0xf]; 4704 u8 vport_number[0x10]; 4705 4706 u8 reserved_at_60[0x20]; 4707 4708 u8 table_type[0x8]; 4709 u8 reserved_at_88[0x18]; 4710 4711 u8 reserved_at_a0[0x8]; 4712 u8 table_id[0x18]; 4713 4714 u8 ignore_flow_level[0x1]; 4715 u8 reserved_at_c1[0x17]; 4716 u8 modify_enable_mask[0x8]; 4717 4718 u8 reserved_at_e0[0x20]; 4719 4720 u8 flow_index[0x20]; 4721 4722 u8 reserved_at_120[0xe0]; 4723 4724 struct mlx5_ifc_flow_context_bits flow_context; 4725 }; 4726 4727 struct mlx5_ifc_rts2rts_qp_out_bits { 4728 u8 status[0x8]; 4729 u8 reserved_at_8[0x18]; 4730 4731 u8 syndrome[0x20]; 4732 4733 u8 reserved_at_40[0x20]; 4734 u8 ece[0x20]; 4735 }; 4736 4737 struct mlx5_ifc_rts2rts_qp_in_bits { 4738 u8 opcode[0x10]; 4739 u8 uid[0x10]; 4740 4741 u8 reserved_at_20[0x10]; 4742 u8 op_mod[0x10]; 4743 4744 u8 reserved_at_40[0x8]; 4745 u8 qpn[0x18]; 4746 4747 u8 reserved_at_60[0x20]; 4748 4749 u8 opt_param_mask[0x20]; 4750 4751 u8 ece[0x20]; 4752 4753 struct mlx5_ifc_qpc_bits qpc; 4754 4755 u8 reserved_at_800[0x80]; 4756 }; 4757 4758 struct mlx5_ifc_rtr2rts_qp_out_bits { 4759 u8 status[0x8]; 4760 u8 reserved_at_8[0x18]; 4761 4762 u8 syndrome[0x20]; 4763 4764 u8 reserved_at_40[0x20]; 4765 u8 ece[0x20]; 4766 }; 4767 4768 struct mlx5_ifc_rtr2rts_qp_in_bits { 4769 u8 opcode[0x10]; 4770 u8 uid[0x10]; 4771 4772 u8 reserved_at_20[0x10]; 4773 u8 op_mod[0x10]; 4774 4775 u8 reserved_at_40[0x8]; 4776 u8 qpn[0x18]; 4777 4778 u8 reserved_at_60[0x20]; 4779 4780 u8 opt_param_mask[0x20]; 4781 4782 u8 ece[0x20]; 4783 4784 struct mlx5_ifc_qpc_bits qpc; 4785 4786 u8 reserved_at_800[0x80]; 4787 }; 4788 4789 struct mlx5_ifc_rst2init_qp_out_bits { 4790 u8 status[0x8]; 4791 u8 reserved_at_8[0x18]; 4792 4793 u8 syndrome[0x20]; 4794 4795 u8 reserved_at_40[0x20]; 4796 u8 ece[0x20]; 4797 }; 4798 4799 struct mlx5_ifc_rst2init_qp_in_bits { 4800 u8 opcode[0x10]; 4801 u8 uid[0x10]; 4802 4803 u8 reserved_at_20[0x10]; 4804 u8 op_mod[0x10]; 4805 4806 u8 reserved_at_40[0x8]; 4807 u8 qpn[0x18]; 4808 4809 u8 reserved_at_60[0x20]; 4810 4811 u8 opt_param_mask[0x20]; 4812 4813 u8 ece[0x20]; 4814 4815 struct mlx5_ifc_qpc_bits qpc; 4816 4817 u8 reserved_at_800[0x80]; 4818 }; 4819 4820 struct mlx5_ifc_query_xrq_out_bits { 4821 u8 status[0x8]; 4822 u8 reserved_at_8[0x18]; 4823 4824 u8 syndrome[0x20]; 4825 4826 u8 reserved_at_40[0x40]; 4827 4828 struct mlx5_ifc_xrqc_bits xrq_context; 4829 }; 4830 4831 struct mlx5_ifc_query_xrq_in_bits { 4832 u8 opcode[0x10]; 4833 u8 reserved_at_10[0x10]; 4834 4835 u8 reserved_at_20[0x10]; 4836 u8 op_mod[0x10]; 4837 4838 u8 reserved_at_40[0x8]; 4839 u8 xrqn[0x18]; 4840 4841 u8 reserved_at_60[0x20]; 4842 }; 4843 4844 struct mlx5_ifc_query_xrc_srq_out_bits { 4845 u8 status[0x8]; 4846 u8 reserved_at_8[0x18]; 4847 4848 u8 syndrome[0x20]; 4849 4850 u8 reserved_at_40[0x40]; 4851 4852 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 4853 4854 u8 reserved_at_280[0x600]; 4855 4856 u8 pas[][0x40]; 4857 }; 4858 4859 struct mlx5_ifc_query_xrc_srq_in_bits { 4860 u8 opcode[0x10]; 4861 u8 reserved_at_10[0x10]; 4862 4863 u8 reserved_at_20[0x10]; 4864 u8 op_mod[0x10]; 4865 4866 u8 reserved_at_40[0x8]; 4867 u8 xrc_srqn[0x18]; 4868 4869 u8 reserved_at_60[0x20]; 4870 }; 4871 4872 enum { 4873 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0, 4874 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1, 4875 }; 4876 4877 struct mlx5_ifc_query_vport_state_out_bits { 4878 u8 status[0x8]; 4879 u8 reserved_at_8[0x18]; 4880 4881 u8 syndrome[0x20]; 4882 4883 u8 reserved_at_40[0x20]; 4884 4885 u8 reserved_at_60[0x18]; 4886 u8 admin_state[0x4]; 4887 u8 state[0x4]; 4888 }; 4889 4890 enum { 4891 MLX5_VPORT_STATE_OP_MOD_VNIC_VPORT = 0x0, 4892 MLX5_VPORT_STATE_OP_MOD_ESW_VPORT = 0x1, 4893 MLX5_VPORT_STATE_OP_MOD_UPLINK = 0x2, 4894 }; 4895 4896 struct mlx5_ifc_arm_monitor_counter_in_bits { 4897 u8 opcode[0x10]; 4898 u8 uid[0x10]; 4899 4900 u8 reserved_at_20[0x10]; 4901 u8 op_mod[0x10]; 4902 4903 u8 reserved_at_40[0x20]; 4904 4905 u8 reserved_at_60[0x20]; 4906 }; 4907 4908 struct mlx5_ifc_arm_monitor_counter_out_bits { 4909 u8 status[0x8]; 4910 u8 reserved_at_8[0x18]; 4911 4912 u8 syndrome[0x20]; 4913 4914 u8 reserved_at_40[0x40]; 4915 }; 4916 4917 enum { 4918 MLX5_QUERY_MONITOR_CNT_TYPE_PPCNT = 0x0, 4919 MLX5_QUERY_MONITOR_CNT_TYPE_Q_COUNTER = 0x1, 4920 }; 4921 4922 enum mlx5_monitor_counter_ppcnt { 4923 MLX5_QUERY_MONITOR_PPCNT_IN_RANGE_LENGTH_ERRORS = 0x0, 4924 MLX5_QUERY_MONITOR_PPCNT_OUT_OF_RANGE_LENGTH_FIELD = 0x1, 4925 MLX5_QUERY_MONITOR_PPCNT_FRAME_TOO_LONG_ERRORS = 0x2, 4926 MLX5_QUERY_MONITOR_PPCNT_FRAME_CHECK_SEQUENCE_ERRORS = 0x3, 4927 MLX5_QUERY_MONITOR_PPCNT_ALIGNMENT_ERRORS = 0x4, 4928 MLX5_QUERY_MONITOR_PPCNT_IF_OUT_DISCARDS = 0x5, 4929 }; 4930 4931 enum { 4932 MLX5_QUERY_MONITOR_Q_COUNTER_RX_OUT_OF_BUFFER = 0x4, 4933 }; 4934 4935 struct mlx5_ifc_monitor_counter_output_bits { 4936 u8 reserved_at_0[0x4]; 4937 u8 type[0x4]; 4938 u8 reserved_at_8[0x8]; 4939 u8 counter[0x10]; 4940 4941 u8 counter_group_id[0x20]; 4942 }; 4943 4944 #define MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 (6) 4945 #define MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1 (1) 4946 #define MLX5_CMD_SET_MONITOR_NUM_COUNTER (MLX5_CMD_SET_MONITOR_NUM_PPCNT_COUNTER_SET1 +\ 4947 MLX5_CMD_SET_MONITOR_NUM_Q_COUNTERS_SET1) 4948 4949 struct mlx5_ifc_set_monitor_counter_in_bits { 4950 u8 opcode[0x10]; 4951 u8 uid[0x10]; 4952 4953 u8 reserved_at_20[0x10]; 4954 u8 op_mod[0x10]; 4955 4956 u8 reserved_at_40[0x10]; 4957 u8 num_of_counters[0x10]; 4958 4959 u8 reserved_at_60[0x20]; 4960 4961 struct mlx5_ifc_monitor_counter_output_bits monitor_counter[MLX5_CMD_SET_MONITOR_NUM_COUNTER]; 4962 }; 4963 4964 struct mlx5_ifc_set_monitor_counter_out_bits { 4965 u8 status[0x8]; 4966 u8 reserved_at_8[0x18]; 4967 4968 u8 syndrome[0x20]; 4969 4970 u8 reserved_at_40[0x40]; 4971 }; 4972 4973 struct mlx5_ifc_query_vport_state_in_bits { 4974 u8 opcode[0x10]; 4975 u8 reserved_at_10[0x10]; 4976 4977 u8 reserved_at_20[0x10]; 4978 u8 op_mod[0x10]; 4979 4980 u8 other_vport[0x1]; 4981 u8 reserved_at_41[0xf]; 4982 u8 vport_number[0x10]; 4983 4984 u8 reserved_at_60[0x20]; 4985 }; 4986 4987 struct mlx5_ifc_query_vnic_env_out_bits { 4988 u8 status[0x8]; 4989 u8 reserved_at_8[0x18]; 4990 4991 u8 syndrome[0x20]; 4992 4993 u8 reserved_at_40[0x40]; 4994 4995 struct mlx5_ifc_vnic_diagnostic_statistics_bits vport_env; 4996 }; 4997 4998 enum { 4999 MLX5_QUERY_VNIC_ENV_IN_OP_MOD_VPORT_DIAG_STATISTICS = 0x0, 5000 }; 5001 5002 struct mlx5_ifc_query_vnic_env_in_bits { 5003 u8 opcode[0x10]; 5004 u8 reserved_at_10[0x10]; 5005 5006 u8 reserved_at_20[0x10]; 5007 u8 op_mod[0x10]; 5008 5009 u8 other_vport[0x1]; 5010 u8 reserved_at_41[0xf]; 5011 u8 vport_number[0x10]; 5012 5013 u8 reserved_at_60[0x20]; 5014 }; 5015 5016 struct mlx5_ifc_query_vport_counter_out_bits { 5017 u8 status[0x8]; 5018 u8 reserved_at_8[0x18]; 5019 5020 u8 syndrome[0x20]; 5021 5022 u8 reserved_at_40[0x40]; 5023 5024 struct mlx5_ifc_traffic_counter_bits received_errors; 5025 5026 struct mlx5_ifc_traffic_counter_bits transmit_errors; 5027 5028 struct mlx5_ifc_traffic_counter_bits received_ib_unicast; 5029 5030 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast; 5031 5032 struct mlx5_ifc_traffic_counter_bits received_ib_multicast; 5033 5034 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast; 5035 5036 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast; 5037 5038 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast; 5039 5040 struct mlx5_ifc_traffic_counter_bits received_eth_unicast; 5041 5042 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast; 5043 5044 struct mlx5_ifc_traffic_counter_bits received_eth_multicast; 5045 5046 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast; 5047 5048 u8 reserved_at_680[0xa00]; 5049 }; 5050 5051 enum { 5052 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0, 5053 }; 5054 5055 struct mlx5_ifc_query_vport_counter_in_bits { 5056 u8 opcode[0x10]; 5057 u8 reserved_at_10[0x10]; 5058 5059 u8 reserved_at_20[0x10]; 5060 u8 op_mod[0x10]; 5061 5062 u8 other_vport[0x1]; 5063 u8 reserved_at_41[0xb]; 5064 u8 port_num[0x4]; 5065 u8 vport_number[0x10]; 5066 5067 u8 reserved_at_60[0x60]; 5068 5069 u8 clear[0x1]; 5070 u8 reserved_at_c1[0x1f]; 5071 5072 u8 reserved_at_e0[0x20]; 5073 }; 5074 5075 struct mlx5_ifc_query_tis_out_bits { 5076 u8 status[0x8]; 5077 u8 reserved_at_8[0x18]; 5078 5079 u8 syndrome[0x20]; 5080 5081 u8 reserved_at_40[0x40]; 5082 5083 struct mlx5_ifc_tisc_bits tis_context; 5084 }; 5085 5086 struct mlx5_ifc_query_tis_in_bits { 5087 u8 opcode[0x10]; 5088 u8 reserved_at_10[0x10]; 5089 5090 u8 reserved_at_20[0x10]; 5091 u8 op_mod[0x10]; 5092 5093 u8 reserved_at_40[0x8]; 5094 u8 tisn[0x18]; 5095 5096 u8 reserved_at_60[0x20]; 5097 }; 5098 5099 struct mlx5_ifc_query_tir_out_bits { 5100 u8 status[0x8]; 5101 u8 reserved_at_8[0x18]; 5102 5103 u8 syndrome[0x20]; 5104 5105 u8 reserved_at_40[0xc0]; 5106 5107 struct mlx5_ifc_tirc_bits tir_context; 5108 }; 5109 5110 struct mlx5_ifc_query_tir_in_bits { 5111 u8 opcode[0x10]; 5112 u8 reserved_at_10[0x10]; 5113 5114 u8 reserved_at_20[0x10]; 5115 u8 op_mod[0x10]; 5116 5117 u8 reserved_at_40[0x8]; 5118 u8 tirn[0x18]; 5119 5120 u8 reserved_at_60[0x20]; 5121 }; 5122 5123 struct mlx5_ifc_query_srq_out_bits { 5124 u8 status[0x8]; 5125 u8 reserved_at_8[0x18]; 5126 5127 u8 syndrome[0x20]; 5128 5129 u8 reserved_at_40[0x40]; 5130 5131 struct mlx5_ifc_srqc_bits srq_context_entry; 5132 5133 u8 reserved_at_280[0x600]; 5134 5135 u8 pas[][0x40]; 5136 }; 5137 5138 struct mlx5_ifc_query_srq_in_bits { 5139 u8 opcode[0x10]; 5140 u8 reserved_at_10[0x10]; 5141 5142 u8 reserved_at_20[0x10]; 5143 u8 op_mod[0x10]; 5144 5145 u8 reserved_at_40[0x8]; 5146 u8 srqn[0x18]; 5147 5148 u8 reserved_at_60[0x20]; 5149 }; 5150 5151 struct mlx5_ifc_query_sq_out_bits { 5152 u8 status[0x8]; 5153 u8 reserved_at_8[0x18]; 5154 5155 u8 syndrome[0x20]; 5156 5157 u8 reserved_at_40[0xc0]; 5158 5159 struct mlx5_ifc_sqc_bits sq_context; 5160 }; 5161 5162 struct mlx5_ifc_query_sq_in_bits { 5163 u8 opcode[0x10]; 5164 u8 reserved_at_10[0x10]; 5165 5166 u8 reserved_at_20[0x10]; 5167 u8 op_mod[0x10]; 5168 5169 u8 reserved_at_40[0x8]; 5170 u8 sqn[0x18]; 5171 5172 u8 reserved_at_60[0x20]; 5173 }; 5174 5175 struct mlx5_ifc_query_special_contexts_out_bits { 5176 u8 status[0x8]; 5177 u8 reserved_at_8[0x18]; 5178 5179 u8 syndrome[0x20]; 5180 5181 u8 dump_fill_mkey[0x20]; 5182 5183 u8 resd_lkey[0x20]; 5184 5185 u8 null_mkey[0x20]; 5186 5187 u8 reserved_at_a0[0x60]; 5188 }; 5189 5190 struct mlx5_ifc_query_special_contexts_in_bits { 5191 u8 opcode[0x10]; 5192 u8 reserved_at_10[0x10]; 5193 5194 u8 reserved_at_20[0x10]; 5195 u8 op_mod[0x10]; 5196 5197 u8 reserved_at_40[0x40]; 5198 }; 5199 5200 struct mlx5_ifc_query_scheduling_element_out_bits { 5201 u8 opcode[0x10]; 5202 u8 reserved_at_10[0x10]; 5203 5204 u8 reserved_at_20[0x10]; 5205 u8 op_mod[0x10]; 5206 5207 u8 reserved_at_40[0xc0]; 5208 5209 struct mlx5_ifc_scheduling_context_bits scheduling_context; 5210 5211 u8 reserved_at_300[0x100]; 5212 }; 5213 5214 enum { 5215 SCHEDULING_HIERARCHY_E_SWITCH = 0x2, 5216 SCHEDULING_HIERARCHY_NIC = 0x3, 5217 }; 5218 5219 struct mlx5_ifc_query_scheduling_element_in_bits { 5220 u8 opcode[0x10]; 5221 u8 reserved_at_10[0x10]; 5222 5223 u8 reserved_at_20[0x10]; 5224 u8 op_mod[0x10]; 5225 5226 u8 scheduling_hierarchy[0x8]; 5227 u8 reserved_at_48[0x18]; 5228 5229 u8 scheduling_element_id[0x20]; 5230 5231 u8 reserved_at_80[0x180]; 5232 }; 5233 5234 struct mlx5_ifc_query_rqt_out_bits { 5235 u8 status[0x8]; 5236 u8 reserved_at_8[0x18]; 5237 5238 u8 syndrome[0x20]; 5239 5240 u8 reserved_at_40[0xc0]; 5241 5242 struct mlx5_ifc_rqtc_bits rqt_context; 5243 }; 5244 5245 struct mlx5_ifc_query_rqt_in_bits { 5246 u8 opcode[0x10]; 5247 u8 reserved_at_10[0x10]; 5248 5249 u8 reserved_at_20[0x10]; 5250 u8 op_mod[0x10]; 5251 5252 u8 reserved_at_40[0x8]; 5253 u8 rqtn[0x18]; 5254 5255 u8 reserved_at_60[0x20]; 5256 }; 5257 5258 struct mlx5_ifc_query_rq_out_bits { 5259 u8 status[0x8]; 5260 u8 reserved_at_8[0x18]; 5261 5262 u8 syndrome[0x20]; 5263 5264 u8 reserved_at_40[0xc0]; 5265 5266 struct mlx5_ifc_rqc_bits rq_context; 5267 }; 5268 5269 struct mlx5_ifc_query_rq_in_bits { 5270 u8 opcode[0x10]; 5271 u8 reserved_at_10[0x10]; 5272 5273 u8 reserved_at_20[0x10]; 5274 u8 op_mod[0x10]; 5275 5276 u8 reserved_at_40[0x8]; 5277 u8 rqn[0x18]; 5278 5279 u8 reserved_at_60[0x20]; 5280 }; 5281 5282 struct mlx5_ifc_query_roce_address_out_bits { 5283 u8 status[0x8]; 5284 u8 reserved_at_8[0x18]; 5285 5286 u8 syndrome[0x20]; 5287 5288 u8 reserved_at_40[0x40]; 5289 5290 struct mlx5_ifc_roce_addr_layout_bits roce_address; 5291 }; 5292 5293 struct mlx5_ifc_query_roce_address_in_bits { 5294 u8 opcode[0x10]; 5295 u8 reserved_at_10[0x10]; 5296 5297 u8 reserved_at_20[0x10]; 5298 u8 op_mod[0x10]; 5299 5300 u8 roce_address_index[0x10]; 5301 u8 reserved_at_50[0xc]; 5302 u8 vhca_port_num[0x4]; 5303 5304 u8 reserved_at_60[0x20]; 5305 }; 5306 5307 struct mlx5_ifc_query_rmp_out_bits { 5308 u8 status[0x8]; 5309 u8 reserved_at_8[0x18]; 5310 5311 u8 syndrome[0x20]; 5312 5313 u8 reserved_at_40[0xc0]; 5314 5315 struct mlx5_ifc_rmpc_bits rmp_context; 5316 }; 5317 5318 struct mlx5_ifc_query_rmp_in_bits { 5319 u8 opcode[0x10]; 5320 u8 reserved_at_10[0x10]; 5321 5322 u8 reserved_at_20[0x10]; 5323 u8 op_mod[0x10]; 5324 5325 u8 reserved_at_40[0x8]; 5326 u8 rmpn[0x18]; 5327 5328 u8 reserved_at_60[0x20]; 5329 }; 5330 5331 struct mlx5_ifc_query_qp_out_bits { 5332 u8 status[0x8]; 5333 u8 reserved_at_8[0x18]; 5334 5335 u8 syndrome[0x20]; 5336 5337 u8 reserved_at_40[0x40]; 5338 5339 u8 opt_param_mask[0x20]; 5340 5341 u8 ece[0x20]; 5342 5343 struct mlx5_ifc_qpc_bits qpc; 5344 5345 u8 reserved_at_800[0x80]; 5346 5347 u8 pas[][0x40]; 5348 }; 5349 5350 struct mlx5_ifc_query_qp_in_bits { 5351 u8 opcode[0x10]; 5352 u8 reserved_at_10[0x10]; 5353 5354 u8 reserved_at_20[0x10]; 5355 u8 op_mod[0x10]; 5356 5357 u8 reserved_at_40[0x8]; 5358 u8 qpn[0x18]; 5359 5360 u8 reserved_at_60[0x20]; 5361 }; 5362 5363 struct mlx5_ifc_query_q_counter_out_bits { 5364 u8 status[0x8]; 5365 u8 reserved_at_8[0x18]; 5366 5367 u8 syndrome[0x20]; 5368 5369 u8 reserved_at_40[0x40]; 5370 5371 u8 rx_write_requests[0x20]; 5372 5373 u8 reserved_at_a0[0x20]; 5374 5375 u8 rx_read_requests[0x20]; 5376 5377 u8 reserved_at_e0[0x20]; 5378 5379 u8 rx_atomic_requests[0x20]; 5380 5381 u8 reserved_at_120[0x20]; 5382 5383 u8 rx_dct_connect[0x20]; 5384 5385 u8 reserved_at_160[0x20]; 5386 5387 u8 out_of_buffer[0x20]; 5388 5389 u8 reserved_at_1a0[0x20]; 5390 5391 u8 out_of_sequence[0x20]; 5392 5393 u8 reserved_at_1e0[0x20]; 5394 5395 u8 duplicate_request[0x20]; 5396 5397 u8 reserved_at_220[0x20]; 5398 5399 u8 rnr_nak_retry_err[0x20]; 5400 5401 u8 reserved_at_260[0x20]; 5402 5403 u8 packet_seq_err[0x20]; 5404 5405 u8 reserved_at_2a0[0x20]; 5406 5407 u8 implied_nak_seq_err[0x20]; 5408 5409 u8 reserved_at_2e0[0x20]; 5410 5411 u8 local_ack_timeout_err[0x20]; 5412 5413 u8 reserved_at_320[0xa0]; 5414 5415 u8 resp_local_length_error[0x20]; 5416 5417 u8 req_local_length_error[0x20]; 5418 5419 u8 resp_local_qp_error[0x20]; 5420 5421 u8 local_operation_error[0x20]; 5422 5423 u8 resp_local_protection[0x20]; 5424 5425 u8 req_local_protection[0x20]; 5426 5427 u8 resp_cqe_error[0x20]; 5428 5429 u8 req_cqe_error[0x20]; 5430 5431 u8 req_mw_binding[0x20]; 5432 5433 u8 req_bad_response[0x20]; 5434 5435 u8 req_remote_invalid_request[0x20]; 5436 5437 u8 resp_remote_invalid_request[0x20]; 5438 5439 u8 req_remote_access_errors[0x20]; 5440 5441 u8 resp_remote_access_errors[0x20]; 5442 5443 u8 req_remote_operation_errors[0x20]; 5444 5445 u8 req_transport_retries_exceeded[0x20]; 5446 5447 u8 cq_overflow[0x20]; 5448 5449 u8 resp_cqe_flush_error[0x20]; 5450 5451 u8 req_cqe_flush_error[0x20]; 5452 5453 u8 reserved_at_620[0x20]; 5454 5455 u8 roce_adp_retrans[0x20]; 5456 5457 u8 roce_adp_retrans_to[0x20]; 5458 5459 u8 roce_slow_restart[0x20]; 5460 5461 u8 roce_slow_restart_cnps[0x20]; 5462 5463 u8 roce_slow_restart_trans[0x20]; 5464 5465 u8 reserved_at_6e0[0x120]; 5466 }; 5467 5468 struct mlx5_ifc_query_q_counter_in_bits { 5469 u8 opcode[0x10]; 5470 u8 reserved_at_10[0x10]; 5471 5472 u8 reserved_at_20[0x10]; 5473 u8 op_mod[0x10]; 5474 5475 u8 reserved_at_40[0x80]; 5476 5477 u8 clear[0x1]; 5478 u8 reserved_at_c1[0x1f]; 5479 5480 u8 reserved_at_e0[0x18]; 5481 u8 counter_set_id[0x8]; 5482 }; 5483 5484 struct mlx5_ifc_query_pages_out_bits { 5485 u8 status[0x8]; 5486 u8 reserved_at_8[0x18]; 5487 5488 u8 syndrome[0x20]; 5489 5490 u8 embedded_cpu_function[0x1]; 5491 u8 reserved_at_41[0xf]; 5492 u8 function_id[0x10]; 5493 5494 u8 num_pages[0x20]; 5495 }; 5496 5497 enum { 5498 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1, 5499 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2, 5500 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3, 5501 }; 5502 5503 struct mlx5_ifc_query_pages_in_bits { 5504 u8 opcode[0x10]; 5505 u8 reserved_at_10[0x10]; 5506 5507 u8 reserved_at_20[0x10]; 5508 u8 op_mod[0x10]; 5509 5510 u8 embedded_cpu_function[0x1]; 5511 u8 reserved_at_41[0xf]; 5512 u8 function_id[0x10]; 5513 5514 u8 reserved_at_60[0x20]; 5515 }; 5516 5517 struct mlx5_ifc_query_nic_vport_context_out_bits { 5518 u8 status[0x8]; 5519 u8 reserved_at_8[0x18]; 5520 5521 u8 syndrome[0x20]; 5522 5523 u8 reserved_at_40[0x40]; 5524 5525 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 5526 }; 5527 5528 struct mlx5_ifc_query_nic_vport_context_in_bits { 5529 u8 opcode[0x10]; 5530 u8 reserved_at_10[0x10]; 5531 5532 u8 reserved_at_20[0x10]; 5533 u8 op_mod[0x10]; 5534 5535 u8 other_vport[0x1]; 5536 u8 reserved_at_41[0xf]; 5537 u8 vport_number[0x10]; 5538 5539 u8 reserved_at_60[0x5]; 5540 u8 allowed_list_type[0x3]; 5541 u8 reserved_at_68[0x18]; 5542 }; 5543 5544 struct mlx5_ifc_query_mkey_out_bits { 5545 u8 status[0x8]; 5546 u8 reserved_at_8[0x18]; 5547 5548 u8 syndrome[0x20]; 5549 5550 u8 reserved_at_40[0x40]; 5551 5552 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 5553 5554 u8 reserved_at_280[0x600]; 5555 5556 u8 bsf0_klm0_pas_mtt0_1[16][0x8]; 5557 5558 u8 bsf1_klm1_pas_mtt2_3[16][0x8]; 5559 }; 5560 5561 struct mlx5_ifc_query_mkey_in_bits { 5562 u8 opcode[0x10]; 5563 u8 reserved_at_10[0x10]; 5564 5565 u8 reserved_at_20[0x10]; 5566 u8 op_mod[0x10]; 5567 5568 u8 reserved_at_40[0x8]; 5569 u8 mkey_index[0x18]; 5570 5571 u8 pg_access[0x1]; 5572 u8 reserved_at_61[0x1f]; 5573 }; 5574 5575 struct mlx5_ifc_query_mad_demux_out_bits { 5576 u8 status[0x8]; 5577 u8 reserved_at_8[0x18]; 5578 5579 u8 syndrome[0x20]; 5580 5581 u8 reserved_at_40[0x40]; 5582 5583 u8 mad_dumux_parameters_block[0x20]; 5584 }; 5585 5586 struct mlx5_ifc_query_mad_demux_in_bits { 5587 u8 opcode[0x10]; 5588 u8 reserved_at_10[0x10]; 5589 5590 u8 reserved_at_20[0x10]; 5591 u8 op_mod[0x10]; 5592 5593 u8 reserved_at_40[0x40]; 5594 }; 5595 5596 struct mlx5_ifc_query_l2_table_entry_out_bits { 5597 u8 status[0x8]; 5598 u8 reserved_at_8[0x18]; 5599 5600 u8 syndrome[0x20]; 5601 5602 u8 reserved_at_40[0xa0]; 5603 5604 u8 reserved_at_e0[0x13]; 5605 u8 vlan_valid[0x1]; 5606 u8 vlan[0xc]; 5607 5608 struct mlx5_ifc_mac_address_layout_bits mac_address; 5609 5610 u8 reserved_at_140[0xc0]; 5611 }; 5612 5613 struct mlx5_ifc_query_l2_table_entry_in_bits { 5614 u8 opcode[0x10]; 5615 u8 reserved_at_10[0x10]; 5616 5617 u8 reserved_at_20[0x10]; 5618 u8 op_mod[0x10]; 5619 5620 u8 reserved_at_40[0x60]; 5621 5622 u8 reserved_at_a0[0x8]; 5623 u8 table_index[0x18]; 5624 5625 u8 reserved_at_c0[0x140]; 5626 }; 5627 5628 struct mlx5_ifc_query_issi_out_bits { 5629 u8 status[0x8]; 5630 u8 reserved_at_8[0x18]; 5631 5632 u8 syndrome[0x20]; 5633 5634 u8 reserved_at_40[0x10]; 5635 u8 current_issi[0x10]; 5636 5637 u8 reserved_at_60[0xa0]; 5638 5639 u8 reserved_at_100[76][0x8]; 5640 u8 supported_issi_dw0[0x20]; 5641 }; 5642 5643 struct mlx5_ifc_query_issi_in_bits { 5644 u8 opcode[0x10]; 5645 u8 reserved_at_10[0x10]; 5646 5647 u8 reserved_at_20[0x10]; 5648 u8 op_mod[0x10]; 5649 5650 u8 reserved_at_40[0x40]; 5651 }; 5652 5653 struct mlx5_ifc_set_driver_version_out_bits { 5654 u8 status[0x8]; 5655 u8 reserved_0[0x18]; 5656 5657 u8 syndrome[0x20]; 5658 u8 reserved_1[0x40]; 5659 }; 5660 5661 struct mlx5_ifc_set_driver_version_in_bits { 5662 u8 opcode[0x10]; 5663 u8 reserved_0[0x10]; 5664 5665 u8 reserved_1[0x10]; 5666 u8 op_mod[0x10]; 5667 5668 u8 reserved_2[0x40]; 5669 u8 driver_version[64][0x8]; 5670 }; 5671 5672 struct mlx5_ifc_query_hca_vport_pkey_out_bits { 5673 u8 status[0x8]; 5674 u8 reserved_at_8[0x18]; 5675 5676 u8 syndrome[0x20]; 5677 5678 u8 reserved_at_40[0x40]; 5679 5680 struct mlx5_ifc_pkey_bits pkey[]; 5681 }; 5682 5683 struct mlx5_ifc_query_hca_vport_pkey_in_bits { 5684 u8 opcode[0x10]; 5685 u8 reserved_at_10[0x10]; 5686 5687 u8 reserved_at_20[0x10]; 5688 u8 op_mod[0x10]; 5689 5690 u8 other_vport[0x1]; 5691 u8 reserved_at_41[0xb]; 5692 u8 port_num[0x4]; 5693 u8 vport_number[0x10]; 5694 5695 u8 reserved_at_60[0x10]; 5696 u8 pkey_index[0x10]; 5697 }; 5698 5699 enum { 5700 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0, 5701 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1, 5702 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2, 5703 }; 5704 5705 struct mlx5_ifc_query_hca_vport_gid_out_bits { 5706 u8 status[0x8]; 5707 u8 reserved_at_8[0x18]; 5708 5709 u8 syndrome[0x20]; 5710 5711 u8 reserved_at_40[0x20]; 5712 5713 u8 gids_num[0x10]; 5714 u8 reserved_at_70[0x10]; 5715 5716 struct mlx5_ifc_array128_auto_bits gid[]; 5717 }; 5718 5719 struct mlx5_ifc_query_hca_vport_gid_in_bits { 5720 u8 opcode[0x10]; 5721 u8 reserved_at_10[0x10]; 5722 5723 u8 reserved_at_20[0x10]; 5724 u8 op_mod[0x10]; 5725 5726 u8 other_vport[0x1]; 5727 u8 reserved_at_41[0xb]; 5728 u8 port_num[0x4]; 5729 u8 vport_number[0x10]; 5730 5731 u8 reserved_at_60[0x10]; 5732 u8 gid_index[0x10]; 5733 }; 5734 5735 struct mlx5_ifc_query_hca_vport_context_out_bits { 5736 u8 status[0x8]; 5737 u8 reserved_at_8[0x18]; 5738 5739 u8 syndrome[0x20]; 5740 5741 u8 reserved_at_40[0x40]; 5742 5743 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 5744 }; 5745 5746 struct mlx5_ifc_query_hca_vport_context_in_bits { 5747 u8 opcode[0x10]; 5748 u8 reserved_at_10[0x10]; 5749 5750 u8 reserved_at_20[0x10]; 5751 u8 op_mod[0x10]; 5752 5753 u8 other_vport[0x1]; 5754 u8 reserved_at_41[0xb]; 5755 u8 port_num[0x4]; 5756 u8 vport_number[0x10]; 5757 5758 u8 reserved_at_60[0x20]; 5759 }; 5760 5761 struct mlx5_ifc_query_hca_cap_out_bits { 5762 u8 status[0x8]; 5763 u8 reserved_at_8[0x18]; 5764 5765 u8 syndrome[0x20]; 5766 5767 u8 reserved_at_40[0x40]; 5768 5769 union mlx5_ifc_hca_cap_union_bits capability; 5770 }; 5771 5772 struct mlx5_ifc_query_hca_cap_in_bits { 5773 u8 opcode[0x10]; 5774 u8 reserved_at_10[0x10]; 5775 5776 u8 reserved_at_20[0x10]; 5777 u8 op_mod[0x10]; 5778 5779 u8 other_function[0x1]; 5780 u8 reserved_at_41[0xf]; 5781 u8 function_id[0x10]; 5782 5783 u8 reserved_at_60[0x20]; 5784 }; 5785 5786 struct mlx5_ifc_other_hca_cap_bits { 5787 u8 roce[0x1]; 5788 u8 reserved_at_1[0x27f]; 5789 }; 5790 5791 struct mlx5_ifc_query_other_hca_cap_out_bits { 5792 u8 status[0x8]; 5793 u8 reserved_at_8[0x18]; 5794 5795 u8 syndrome[0x20]; 5796 5797 u8 reserved_at_40[0x40]; 5798 5799 struct mlx5_ifc_other_hca_cap_bits other_capability; 5800 }; 5801 5802 struct mlx5_ifc_query_other_hca_cap_in_bits { 5803 u8 opcode[0x10]; 5804 u8 reserved_at_10[0x10]; 5805 5806 u8 reserved_at_20[0x10]; 5807 u8 op_mod[0x10]; 5808 5809 u8 reserved_at_40[0x10]; 5810 u8 function_id[0x10]; 5811 5812 u8 reserved_at_60[0x20]; 5813 }; 5814 5815 struct mlx5_ifc_modify_other_hca_cap_out_bits { 5816 u8 status[0x8]; 5817 u8 reserved_at_8[0x18]; 5818 5819 u8 syndrome[0x20]; 5820 5821 u8 reserved_at_40[0x40]; 5822 }; 5823 5824 struct mlx5_ifc_modify_other_hca_cap_in_bits { 5825 u8 opcode[0x10]; 5826 u8 reserved_at_10[0x10]; 5827 5828 u8 reserved_at_20[0x10]; 5829 u8 op_mod[0x10]; 5830 5831 u8 reserved_at_40[0x10]; 5832 u8 function_id[0x10]; 5833 u8 field_select[0x20]; 5834 5835 struct mlx5_ifc_other_hca_cap_bits other_capability; 5836 }; 5837 5838 struct mlx5_ifc_flow_table_context_bits { 5839 u8 reformat_en[0x1]; 5840 u8 decap_en[0x1]; 5841 u8 sw_owner[0x1]; 5842 u8 termination_table[0x1]; 5843 u8 table_miss_action[0x4]; 5844 u8 level[0x8]; 5845 u8 reserved_at_10[0x8]; 5846 u8 log_size[0x8]; 5847 5848 u8 reserved_at_20[0x8]; 5849 u8 table_miss_id[0x18]; 5850 5851 u8 reserved_at_40[0x8]; 5852 u8 lag_master_next_table_id[0x18]; 5853 5854 u8 reserved_at_60[0x60]; 5855 5856 u8 sw_owner_icm_root_1[0x40]; 5857 5858 u8 sw_owner_icm_root_0[0x40]; 5859 5860 }; 5861 5862 struct mlx5_ifc_query_flow_table_out_bits { 5863 u8 status[0x8]; 5864 u8 reserved_at_8[0x18]; 5865 5866 u8 syndrome[0x20]; 5867 5868 u8 reserved_at_40[0x80]; 5869 5870 struct mlx5_ifc_flow_table_context_bits flow_table_context; 5871 }; 5872 5873 struct mlx5_ifc_query_flow_table_in_bits { 5874 u8 opcode[0x10]; 5875 u8 reserved_at_10[0x10]; 5876 5877 u8 reserved_at_20[0x10]; 5878 u8 op_mod[0x10]; 5879 5880 u8 reserved_at_40[0x40]; 5881 5882 u8 table_type[0x8]; 5883 u8 reserved_at_88[0x18]; 5884 5885 u8 reserved_at_a0[0x8]; 5886 u8 table_id[0x18]; 5887 5888 u8 reserved_at_c0[0x140]; 5889 }; 5890 5891 struct mlx5_ifc_query_fte_out_bits { 5892 u8 status[0x8]; 5893 u8 reserved_at_8[0x18]; 5894 5895 u8 syndrome[0x20]; 5896 5897 u8 reserved_at_40[0x1c0]; 5898 5899 struct mlx5_ifc_flow_context_bits flow_context; 5900 }; 5901 5902 struct mlx5_ifc_query_fte_in_bits { 5903 u8 opcode[0x10]; 5904 u8 reserved_at_10[0x10]; 5905 5906 u8 reserved_at_20[0x10]; 5907 u8 op_mod[0x10]; 5908 5909 u8 reserved_at_40[0x40]; 5910 5911 u8 table_type[0x8]; 5912 u8 reserved_at_88[0x18]; 5913 5914 u8 reserved_at_a0[0x8]; 5915 u8 table_id[0x18]; 5916 5917 u8 reserved_at_c0[0x40]; 5918 5919 u8 flow_index[0x20]; 5920 5921 u8 reserved_at_120[0xe0]; 5922 }; 5923 5924 struct mlx5_ifc_match_definer_format_0_bits { 5925 u8 reserved_at_0[0x100]; 5926 5927 u8 metadata_reg_c_0[0x20]; 5928 5929 u8 metadata_reg_c_1[0x20]; 5930 5931 u8 outer_dmac_47_16[0x20]; 5932 5933 u8 outer_dmac_15_0[0x10]; 5934 u8 outer_ethertype[0x10]; 5935 5936 u8 reserved_at_180[0x1]; 5937 u8 sx_sniffer[0x1]; 5938 u8 functional_lb[0x1]; 5939 u8 outer_ip_frag[0x1]; 5940 u8 outer_qp_type[0x2]; 5941 u8 outer_encap_type[0x2]; 5942 u8 port_number[0x2]; 5943 u8 outer_l3_type[0x2]; 5944 u8 outer_l4_type[0x2]; 5945 u8 outer_first_vlan_type[0x2]; 5946 u8 outer_first_vlan_prio[0x3]; 5947 u8 outer_first_vlan_cfi[0x1]; 5948 u8 outer_first_vlan_vid[0xc]; 5949 5950 u8 outer_l4_type_ext[0x4]; 5951 u8 reserved_at_1a4[0x2]; 5952 u8 outer_ipsec_layer[0x2]; 5953 u8 outer_l2_type[0x2]; 5954 u8 force_lb[0x1]; 5955 u8 outer_l2_ok[0x1]; 5956 u8 outer_l3_ok[0x1]; 5957 u8 outer_l4_ok[0x1]; 5958 u8 outer_second_vlan_type[0x2]; 5959 u8 outer_second_vlan_prio[0x3]; 5960 u8 outer_second_vlan_cfi[0x1]; 5961 u8 outer_second_vlan_vid[0xc]; 5962 5963 u8 outer_smac_47_16[0x20]; 5964 5965 u8 outer_smac_15_0[0x10]; 5966 u8 inner_ipv4_checksum_ok[0x1]; 5967 u8 inner_l4_checksum_ok[0x1]; 5968 u8 outer_ipv4_checksum_ok[0x1]; 5969 u8 outer_l4_checksum_ok[0x1]; 5970 u8 inner_l3_ok[0x1]; 5971 u8 inner_l4_ok[0x1]; 5972 u8 outer_l3_ok_duplicate[0x1]; 5973 u8 outer_l4_ok_duplicate[0x1]; 5974 u8 outer_tcp_cwr[0x1]; 5975 u8 outer_tcp_ece[0x1]; 5976 u8 outer_tcp_urg[0x1]; 5977 u8 outer_tcp_ack[0x1]; 5978 u8 outer_tcp_psh[0x1]; 5979 u8 outer_tcp_rst[0x1]; 5980 u8 outer_tcp_syn[0x1]; 5981 u8 outer_tcp_fin[0x1]; 5982 }; 5983 5984 struct mlx5_ifc_match_definer_format_22_bits { 5985 u8 reserved_at_0[0x100]; 5986 5987 u8 outer_ip_src_addr[0x20]; 5988 5989 u8 outer_ip_dest_addr[0x20]; 5990 5991 u8 outer_l4_sport[0x10]; 5992 u8 outer_l4_dport[0x10]; 5993 5994 u8 reserved_at_160[0x1]; 5995 u8 sx_sniffer[0x1]; 5996 u8 functional_lb[0x1]; 5997 u8 outer_ip_frag[0x1]; 5998 u8 outer_qp_type[0x2]; 5999 u8 outer_encap_type[0x2]; 6000 u8 port_number[0x2]; 6001 u8 outer_l3_type[0x2]; 6002 u8 outer_l4_type[0x2]; 6003 u8 outer_first_vlan_type[0x2]; 6004 u8 outer_first_vlan_prio[0x3]; 6005 u8 outer_first_vlan_cfi[0x1]; 6006 u8 outer_first_vlan_vid[0xc]; 6007 6008 u8 metadata_reg_c_0[0x20]; 6009 6010 u8 outer_dmac_47_16[0x20]; 6011 6012 u8 outer_smac_47_16[0x20]; 6013 6014 u8 outer_smac_15_0[0x10]; 6015 u8 outer_dmac_15_0[0x10]; 6016 }; 6017 6018 struct mlx5_ifc_match_definer_format_23_bits { 6019 u8 reserved_at_0[0x100]; 6020 6021 u8 inner_ip_src_addr[0x20]; 6022 6023 u8 inner_ip_dest_addr[0x20]; 6024 6025 u8 inner_l4_sport[0x10]; 6026 u8 inner_l4_dport[0x10]; 6027 6028 u8 reserved_at_160[0x1]; 6029 u8 sx_sniffer[0x1]; 6030 u8 functional_lb[0x1]; 6031 u8 inner_ip_frag[0x1]; 6032 u8 inner_qp_type[0x2]; 6033 u8 inner_encap_type[0x2]; 6034 u8 port_number[0x2]; 6035 u8 inner_l3_type[0x2]; 6036 u8 inner_l4_type[0x2]; 6037 u8 inner_first_vlan_type[0x2]; 6038 u8 inner_first_vlan_prio[0x3]; 6039 u8 inner_first_vlan_cfi[0x1]; 6040 u8 inner_first_vlan_vid[0xc]; 6041 6042 u8 tunnel_header_0[0x20]; 6043 6044 u8 inner_dmac_47_16[0x20]; 6045 6046 u8 inner_smac_47_16[0x20]; 6047 6048 u8 inner_smac_15_0[0x10]; 6049 u8 inner_dmac_15_0[0x10]; 6050 }; 6051 6052 struct mlx5_ifc_match_definer_format_29_bits { 6053 u8 reserved_at_0[0xc0]; 6054 6055 u8 outer_ip_dest_addr[0x80]; 6056 6057 u8 outer_ip_src_addr[0x80]; 6058 6059 u8 outer_l4_sport[0x10]; 6060 u8 outer_l4_dport[0x10]; 6061 6062 u8 reserved_at_1e0[0x20]; 6063 }; 6064 6065 struct mlx5_ifc_match_definer_format_30_bits { 6066 u8 reserved_at_0[0xa0]; 6067 6068 u8 outer_ip_dest_addr[0x80]; 6069 6070 u8 outer_ip_src_addr[0x80]; 6071 6072 u8 outer_dmac_47_16[0x20]; 6073 6074 u8 outer_smac_47_16[0x20]; 6075 6076 u8 outer_smac_15_0[0x10]; 6077 u8 outer_dmac_15_0[0x10]; 6078 }; 6079 6080 struct mlx5_ifc_match_definer_format_31_bits { 6081 u8 reserved_at_0[0xc0]; 6082 6083 u8 inner_ip_dest_addr[0x80]; 6084 6085 u8 inner_ip_src_addr[0x80]; 6086 6087 u8 inner_l4_sport[0x10]; 6088 u8 inner_l4_dport[0x10]; 6089 6090 u8 reserved_at_1e0[0x20]; 6091 }; 6092 6093 struct mlx5_ifc_match_definer_format_32_bits { 6094 u8 reserved_at_0[0xa0]; 6095 6096 u8 inner_ip_dest_addr[0x80]; 6097 6098 u8 inner_ip_src_addr[0x80]; 6099 6100 u8 inner_dmac_47_16[0x20]; 6101 6102 u8 inner_smac_47_16[0x20]; 6103 6104 u8 inner_smac_15_0[0x10]; 6105 u8 inner_dmac_15_0[0x10]; 6106 }; 6107 6108 struct mlx5_ifc_match_definer_bits { 6109 u8 modify_field_select[0x40]; 6110 6111 u8 reserved_at_40[0x40]; 6112 6113 u8 reserved_at_80[0x10]; 6114 u8 format_id[0x10]; 6115 6116 u8 reserved_at_a0[0x160]; 6117 6118 u8 match_mask[16][0x20]; 6119 }; 6120 6121 struct mlx5_ifc_general_obj_in_cmd_hdr_bits { 6122 u8 opcode[0x10]; 6123 u8 uid[0x10]; 6124 6125 u8 vhca_tunnel_id[0x10]; 6126 u8 obj_type[0x10]; 6127 6128 u8 obj_id[0x20]; 6129 6130 u8 reserved_at_60[0x3]; 6131 u8 log_obj_range[0x5]; 6132 u8 reserved_at_68[0x18]; 6133 }; 6134 6135 struct mlx5_ifc_general_obj_out_cmd_hdr_bits { 6136 u8 status[0x8]; 6137 u8 reserved_at_8[0x18]; 6138 6139 u8 syndrome[0x20]; 6140 6141 u8 obj_id[0x20]; 6142 6143 u8 reserved_at_60[0x20]; 6144 }; 6145 6146 struct mlx5_ifc_create_match_definer_in_bits { 6147 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 6148 6149 struct mlx5_ifc_match_definer_bits obj_context; 6150 }; 6151 6152 struct mlx5_ifc_create_match_definer_out_bits { 6153 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 6154 }; 6155 6156 enum { 6157 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 6158 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 6159 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 6160 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 6161 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_3 = 0x4, 6162 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_4 = 0x5, 6163 MLX5_QUERY_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_5 = 0x6, 6164 }; 6165 6166 struct mlx5_ifc_query_flow_group_out_bits { 6167 u8 status[0x8]; 6168 u8 reserved_at_8[0x18]; 6169 6170 u8 syndrome[0x20]; 6171 6172 u8 reserved_at_40[0xa0]; 6173 6174 u8 start_flow_index[0x20]; 6175 6176 u8 reserved_at_100[0x20]; 6177 6178 u8 end_flow_index[0x20]; 6179 6180 u8 reserved_at_140[0xa0]; 6181 6182 u8 reserved_at_1e0[0x18]; 6183 u8 match_criteria_enable[0x8]; 6184 6185 struct mlx5_ifc_fte_match_param_bits match_criteria; 6186 6187 u8 reserved_at_1200[0xe00]; 6188 }; 6189 6190 struct mlx5_ifc_query_flow_group_in_bits { 6191 u8 opcode[0x10]; 6192 u8 reserved_at_10[0x10]; 6193 6194 u8 reserved_at_20[0x10]; 6195 u8 op_mod[0x10]; 6196 6197 u8 reserved_at_40[0x40]; 6198 6199 u8 table_type[0x8]; 6200 u8 reserved_at_88[0x18]; 6201 6202 u8 reserved_at_a0[0x8]; 6203 u8 table_id[0x18]; 6204 6205 u8 group_id[0x20]; 6206 6207 u8 reserved_at_e0[0x120]; 6208 }; 6209 6210 struct mlx5_ifc_query_flow_counter_out_bits { 6211 u8 status[0x8]; 6212 u8 reserved_at_8[0x18]; 6213 6214 u8 syndrome[0x20]; 6215 6216 u8 reserved_at_40[0x40]; 6217 6218 struct mlx5_ifc_traffic_counter_bits flow_statistics[]; 6219 }; 6220 6221 struct mlx5_ifc_query_flow_counter_in_bits { 6222 u8 opcode[0x10]; 6223 u8 reserved_at_10[0x10]; 6224 6225 u8 reserved_at_20[0x10]; 6226 u8 op_mod[0x10]; 6227 6228 u8 reserved_at_40[0x80]; 6229 6230 u8 clear[0x1]; 6231 u8 reserved_at_c1[0xf]; 6232 u8 num_of_counters[0x10]; 6233 6234 u8 flow_counter_id[0x20]; 6235 }; 6236 6237 struct mlx5_ifc_query_esw_vport_context_out_bits { 6238 u8 status[0x8]; 6239 u8 reserved_at_8[0x18]; 6240 6241 u8 syndrome[0x20]; 6242 6243 u8 reserved_at_40[0x40]; 6244 6245 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 6246 }; 6247 6248 struct mlx5_ifc_query_esw_vport_context_in_bits { 6249 u8 opcode[0x10]; 6250 u8 reserved_at_10[0x10]; 6251 6252 u8 reserved_at_20[0x10]; 6253 u8 op_mod[0x10]; 6254 6255 u8 other_vport[0x1]; 6256 u8 reserved_at_41[0xf]; 6257 u8 vport_number[0x10]; 6258 6259 u8 reserved_at_60[0x20]; 6260 }; 6261 6262 struct mlx5_ifc_modify_esw_vport_context_out_bits { 6263 u8 status[0x8]; 6264 u8 reserved_at_8[0x18]; 6265 6266 u8 syndrome[0x20]; 6267 6268 u8 reserved_at_40[0x40]; 6269 }; 6270 6271 struct mlx5_ifc_esw_vport_context_fields_select_bits { 6272 u8 reserved_at_0[0x1b]; 6273 u8 fdb_to_vport_reg_c_id[0x1]; 6274 u8 vport_cvlan_insert[0x1]; 6275 u8 vport_svlan_insert[0x1]; 6276 u8 vport_cvlan_strip[0x1]; 6277 u8 vport_svlan_strip[0x1]; 6278 }; 6279 6280 struct mlx5_ifc_modify_esw_vport_context_in_bits { 6281 u8 opcode[0x10]; 6282 u8 reserved_at_10[0x10]; 6283 6284 u8 reserved_at_20[0x10]; 6285 u8 op_mod[0x10]; 6286 6287 u8 other_vport[0x1]; 6288 u8 reserved_at_41[0xf]; 6289 u8 vport_number[0x10]; 6290 6291 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select; 6292 6293 struct mlx5_ifc_esw_vport_context_bits esw_vport_context; 6294 }; 6295 6296 struct mlx5_ifc_query_eq_out_bits { 6297 u8 status[0x8]; 6298 u8 reserved_at_8[0x18]; 6299 6300 u8 syndrome[0x20]; 6301 6302 u8 reserved_at_40[0x40]; 6303 6304 struct mlx5_ifc_eqc_bits eq_context_entry; 6305 6306 u8 reserved_at_280[0x40]; 6307 6308 u8 event_bitmask[0x40]; 6309 6310 u8 reserved_at_300[0x580]; 6311 6312 u8 pas[][0x40]; 6313 }; 6314 6315 struct mlx5_ifc_query_eq_in_bits { 6316 u8 opcode[0x10]; 6317 u8 reserved_at_10[0x10]; 6318 6319 u8 reserved_at_20[0x10]; 6320 u8 op_mod[0x10]; 6321 6322 u8 reserved_at_40[0x18]; 6323 u8 eq_number[0x8]; 6324 6325 u8 reserved_at_60[0x20]; 6326 }; 6327 6328 struct mlx5_ifc_packet_reformat_context_in_bits { 6329 u8 reformat_type[0x8]; 6330 u8 reserved_at_8[0x4]; 6331 u8 reformat_param_0[0x4]; 6332 u8 reserved_at_10[0x6]; 6333 u8 reformat_data_size[0xa]; 6334 6335 u8 reformat_param_1[0x8]; 6336 u8 reserved_at_28[0x8]; 6337 u8 reformat_data[2][0x8]; 6338 6339 u8 more_reformat_data[][0x8]; 6340 }; 6341 6342 struct mlx5_ifc_query_packet_reformat_context_out_bits { 6343 u8 status[0x8]; 6344 u8 reserved_at_8[0x18]; 6345 6346 u8 syndrome[0x20]; 6347 6348 u8 reserved_at_40[0xa0]; 6349 6350 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context[]; 6351 }; 6352 6353 struct mlx5_ifc_query_packet_reformat_context_in_bits { 6354 u8 opcode[0x10]; 6355 u8 reserved_at_10[0x10]; 6356 6357 u8 reserved_at_20[0x10]; 6358 u8 op_mod[0x10]; 6359 6360 u8 packet_reformat_id[0x20]; 6361 6362 u8 reserved_at_60[0xa0]; 6363 }; 6364 6365 struct mlx5_ifc_alloc_packet_reformat_context_out_bits { 6366 u8 status[0x8]; 6367 u8 reserved_at_8[0x18]; 6368 6369 u8 syndrome[0x20]; 6370 6371 u8 packet_reformat_id[0x20]; 6372 6373 u8 reserved_at_60[0x20]; 6374 }; 6375 6376 enum { 6377 MLX5_REFORMAT_CONTEXT_ANCHOR_MAC_START = 0x1, 6378 MLX5_REFORMAT_CONTEXT_ANCHOR_IP_START = 0x7, 6379 MLX5_REFORMAT_CONTEXT_ANCHOR_TCP_UDP_START = 0x9, 6380 }; 6381 6382 enum mlx5_reformat_ctx_type { 6383 MLX5_REFORMAT_TYPE_L2_TO_VXLAN = 0x0, 6384 MLX5_REFORMAT_TYPE_L2_TO_NVGRE = 0x1, 6385 MLX5_REFORMAT_TYPE_L2_TO_L2_TUNNEL = 0x2, 6386 MLX5_REFORMAT_TYPE_L3_TUNNEL_TO_L2 = 0x3, 6387 MLX5_REFORMAT_TYPE_L2_TO_L3_TUNNEL = 0x4, 6388 MLX5_REFORMAT_TYPE_INSERT_HDR = 0xf, 6389 MLX5_REFORMAT_TYPE_REMOVE_HDR = 0x10, 6390 MLX5_REFORMAT_TYPE_ADD_MACSEC = 0x11, 6391 MLX5_REFORMAT_TYPE_DEL_MACSEC = 0x12, 6392 }; 6393 6394 struct mlx5_ifc_alloc_packet_reformat_context_in_bits { 6395 u8 opcode[0x10]; 6396 u8 reserved_at_10[0x10]; 6397 6398 u8 reserved_at_20[0x10]; 6399 u8 op_mod[0x10]; 6400 6401 u8 reserved_at_40[0xa0]; 6402 6403 struct mlx5_ifc_packet_reformat_context_in_bits packet_reformat_context; 6404 }; 6405 6406 struct mlx5_ifc_dealloc_packet_reformat_context_out_bits { 6407 u8 status[0x8]; 6408 u8 reserved_at_8[0x18]; 6409 6410 u8 syndrome[0x20]; 6411 6412 u8 reserved_at_40[0x40]; 6413 }; 6414 6415 struct mlx5_ifc_dealloc_packet_reformat_context_in_bits { 6416 u8 opcode[0x10]; 6417 u8 reserved_at_10[0x10]; 6418 6419 u8 reserved_20[0x10]; 6420 u8 op_mod[0x10]; 6421 6422 u8 packet_reformat_id[0x20]; 6423 6424 u8 reserved_60[0x20]; 6425 }; 6426 6427 struct mlx5_ifc_set_action_in_bits { 6428 u8 action_type[0x4]; 6429 u8 field[0xc]; 6430 u8 reserved_at_10[0x3]; 6431 u8 offset[0x5]; 6432 u8 reserved_at_18[0x3]; 6433 u8 length[0x5]; 6434 6435 u8 data[0x20]; 6436 }; 6437 6438 struct mlx5_ifc_add_action_in_bits { 6439 u8 action_type[0x4]; 6440 u8 field[0xc]; 6441 u8 reserved_at_10[0x10]; 6442 6443 u8 data[0x20]; 6444 }; 6445 6446 struct mlx5_ifc_copy_action_in_bits { 6447 u8 action_type[0x4]; 6448 u8 src_field[0xc]; 6449 u8 reserved_at_10[0x3]; 6450 u8 src_offset[0x5]; 6451 u8 reserved_at_18[0x3]; 6452 u8 length[0x5]; 6453 6454 u8 reserved_at_20[0x4]; 6455 u8 dst_field[0xc]; 6456 u8 reserved_at_30[0x3]; 6457 u8 dst_offset[0x5]; 6458 u8 reserved_at_38[0x8]; 6459 }; 6460 6461 union mlx5_ifc_set_add_copy_action_in_auto_bits { 6462 struct mlx5_ifc_set_action_in_bits set_action_in; 6463 struct mlx5_ifc_add_action_in_bits add_action_in; 6464 struct mlx5_ifc_copy_action_in_bits copy_action_in; 6465 u8 reserved_at_0[0x40]; 6466 }; 6467 6468 enum { 6469 MLX5_ACTION_TYPE_SET = 0x1, 6470 MLX5_ACTION_TYPE_ADD = 0x2, 6471 MLX5_ACTION_TYPE_COPY = 0x3, 6472 }; 6473 6474 enum { 6475 MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16 = 0x1, 6476 MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0 = 0x2, 6477 MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE = 0x3, 6478 MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16 = 0x4, 6479 MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0 = 0x5, 6480 MLX5_ACTION_IN_FIELD_OUT_IP_DSCP = 0x6, 6481 MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS = 0x7, 6482 MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT = 0x8, 6483 MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT = 0x9, 6484 MLX5_ACTION_IN_FIELD_OUT_IP_TTL = 0xa, 6485 MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT = 0xb, 6486 MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT = 0xc, 6487 MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96 = 0xd, 6488 MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64 = 0xe, 6489 MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32 = 0xf, 6490 MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0 = 0x10, 6491 MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96 = 0x11, 6492 MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64 = 0x12, 6493 MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32 = 0x13, 6494 MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0 = 0x14, 6495 MLX5_ACTION_IN_FIELD_OUT_SIPV4 = 0x15, 6496 MLX5_ACTION_IN_FIELD_OUT_DIPV4 = 0x16, 6497 MLX5_ACTION_IN_FIELD_OUT_FIRST_VID = 0x17, 6498 MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47, 6499 MLX5_ACTION_IN_FIELD_METADATA_REG_A = 0x49, 6500 MLX5_ACTION_IN_FIELD_METADATA_REG_B = 0x50, 6501 MLX5_ACTION_IN_FIELD_METADATA_REG_C_0 = 0x51, 6502 MLX5_ACTION_IN_FIELD_METADATA_REG_C_1 = 0x52, 6503 MLX5_ACTION_IN_FIELD_METADATA_REG_C_2 = 0x53, 6504 MLX5_ACTION_IN_FIELD_METADATA_REG_C_3 = 0x54, 6505 MLX5_ACTION_IN_FIELD_METADATA_REG_C_4 = 0x55, 6506 MLX5_ACTION_IN_FIELD_METADATA_REG_C_5 = 0x56, 6507 MLX5_ACTION_IN_FIELD_METADATA_REG_C_6 = 0x57, 6508 MLX5_ACTION_IN_FIELD_METADATA_REG_C_7 = 0x58, 6509 MLX5_ACTION_IN_FIELD_OUT_TCP_SEQ_NUM = 0x59, 6510 MLX5_ACTION_IN_FIELD_OUT_TCP_ACK_NUM = 0x5B, 6511 MLX5_ACTION_IN_FIELD_IPSEC_SYNDROME = 0x5D, 6512 MLX5_ACTION_IN_FIELD_OUT_EMD_47_32 = 0x6F, 6513 MLX5_ACTION_IN_FIELD_OUT_EMD_31_0 = 0x70, 6514 }; 6515 6516 struct mlx5_ifc_alloc_modify_header_context_out_bits { 6517 u8 status[0x8]; 6518 u8 reserved_at_8[0x18]; 6519 6520 u8 syndrome[0x20]; 6521 6522 u8 modify_header_id[0x20]; 6523 6524 u8 reserved_at_60[0x20]; 6525 }; 6526 6527 struct mlx5_ifc_alloc_modify_header_context_in_bits { 6528 u8 opcode[0x10]; 6529 u8 reserved_at_10[0x10]; 6530 6531 u8 reserved_at_20[0x10]; 6532 u8 op_mod[0x10]; 6533 6534 u8 reserved_at_40[0x20]; 6535 6536 u8 table_type[0x8]; 6537 u8 reserved_at_68[0x10]; 6538 u8 num_of_actions[0x8]; 6539 6540 union mlx5_ifc_set_add_copy_action_in_auto_bits actions[]; 6541 }; 6542 6543 struct mlx5_ifc_dealloc_modify_header_context_out_bits { 6544 u8 status[0x8]; 6545 u8 reserved_at_8[0x18]; 6546 6547 u8 syndrome[0x20]; 6548 6549 u8 reserved_at_40[0x40]; 6550 }; 6551 6552 struct mlx5_ifc_dealloc_modify_header_context_in_bits { 6553 u8 opcode[0x10]; 6554 u8 reserved_at_10[0x10]; 6555 6556 u8 reserved_at_20[0x10]; 6557 u8 op_mod[0x10]; 6558 6559 u8 modify_header_id[0x20]; 6560 6561 u8 reserved_at_60[0x20]; 6562 }; 6563 6564 struct mlx5_ifc_query_modify_header_context_in_bits { 6565 u8 opcode[0x10]; 6566 u8 uid[0x10]; 6567 6568 u8 reserved_at_20[0x10]; 6569 u8 op_mod[0x10]; 6570 6571 u8 modify_header_id[0x20]; 6572 6573 u8 reserved_at_60[0xa0]; 6574 }; 6575 6576 struct mlx5_ifc_query_dct_out_bits { 6577 u8 status[0x8]; 6578 u8 reserved_at_8[0x18]; 6579 6580 u8 syndrome[0x20]; 6581 6582 u8 reserved_at_40[0x40]; 6583 6584 struct mlx5_ifc_dctc_bits dct_context_entry; 6585 6586 u8 reserved_at_280[0x180]; 6587 }; 6588 6589 struct mlx5_ifc_query_dct_in_bits { 6590 u8 opcode[0x10]; 6591 u8 reserved_at_10[0x10]; 6592 6593 u8 reserved_at_20[0x10]; 6594 u8 op_mod[0x10]; 6595 6596 u8 reserved_at_40[0x8]; 6597 u8 dctn[0x18]; 6598 6599 u8 reserved_at_60[0x20]; 6600 }; 6601 6602 struct mlx5_ifc_query_cq_out_bits { 6603 u8 status[0x8]; 6604 u8 reserved_at_8[0x18]; 6605 6606 u8 syndrome[0x20]; 6607 6608 u8 reserved_at_40[0x40]; 6609 6610 struct mlx5_ifc_cqc_bits cq_context; 6611 6612 u8 reserved_at_280[0x600]; 6613 6614 u8 pas[][0x40]; 6615 }; 6616 6617 struct mlx5_ifc_query_cq_in_bits { 6618 u8 opcode[0x10]; 6619 u8 reserved_at_10[0x10]; 6620 6621 u8 reserved_at_20[0x10]; 6622 u8 op_mod[0x10]; 6623 6624 u8 reserved_at_40[0x8]; 6625 u8 cqn[0x18]; 6626 6627 u8 reserved_at_60[0x20]; 6628 }; 6629 6630 struct mlx5_ifc_query_cong_status_out_bits { 6631 u8 status[0x8]; 6632 u8 reserved_at_8[0x18]; 6633 6634 u8 syndrome[0x20]; 6635 6636 u8 reserved_at_40[0x20]; 6637 6638 u8 enable[0x1]; 6639 u8 tag_enable[0x1]; 6640 u8 reserved_at_62[0x1e]; 6641 }; 6642 6643 struct mlx5_ifc_query_cong_status_in_bits { 6644 u8 opcode[0x10]; 6645 u8 reserved_at_10[0x10]; 6646 6647 u8 reserved_at_20[0x10]; 6648 u8 op_mod[0x10]; 6649 6650 u8 reserved_at_40[0x18]; 6651 u8 priority[0x4]; 6652 u8 cong_protocol[0x4]; 6653 6654 u8 reserved_at_60[0x20]; 6655 }; 6656 6657 struct mlx5_ifc_query_cong_statistics_out_bits { 6658 u8 status[0x8]; 6659 u8 reserved_at_8[0x18]; 6660 6661 u8 syndrome[0x20]; 6662 6663 u8 reserved_at_40[0x40]; 6664 6665 u8 rp_cur_flows[0x20]; 6666 6667 u8 sum_flows[0x20]; 6668 6669 u8 rp_cnp_ignored_high[0x20]; 6670 6671 u8 rp_cnp_ignored_low[0x20]; 6672 6673 u8 rp_cnp_handled_high[0x20]; 6674 6675 u8 rp_cnp_handled_low[0x20]; 6676 6677 u8 reserved_at_140[0x100]; 6678 6679 u8 time_stamp_high[0x20]; 6680 6681 u8 time_stamp_low[0x20]; 6682 6683 u8 accumulators_period[0x20]; 6684 6685 u8 np_ecn_marked_roce_packets_high[0x20]; 6686 6687 u8 np_ecn_marked_roce_packets_low[0x20]; 6688 6689 u8 np_cnp_sent_high[0x20]; 6690 6691 u8 np_cnp_sent_low[0x20]; 6692 6693 u8 reserved_at_320[0x560]; 6694 }; 6695 6696 struct mlx5_ifc_query_cong_statistics_in_bits { 6697 u8 opcode[0x10]; 6698 u8 reserved_at_10[0x10]; 6699 6700 u8 reserved_at_20[0x10]; 6701 u8 op_mod[0x10]; 6702 6703 u8 clear[0x1]; 6704 u8 reserved_at_41[0x1f]; 6705 6706 u8 reserved_at_60[0x20]; 6707 }; 6708 6709 struct mlx5_ifc_query_cong_params_out_bits { 6710 u8 status[0x8]; 6711 u8 reserved_at_8[0x18]; 6712 6713 u8 syndrome[0x20]; 6714 6715 u8 reserved_at_40[0x40]; 6716 6717 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 6718 }; 6719 6720 struct mlx5_ifc_query_cong_params_in_bits { 6721 u8 opcode[0x10]; 6722 u8 reserved_at_10[0x10]; 6723 6724 u8 reserved_at_20[0x10]; 6725 u8 op_mod[0x10]; 6726 6727 u8 reserved_at_40[0x1c]; 6728 u8 cong_protocol[0x4]; 6729 6730 u8 reserved_at_60[0x20]; 6731 }; 6732 6733 struct mlx5_ifc_query_adapter_out_bits { 6734 u8 status[0x8]; 6735 u8 reserved_at_8[0x18]; 6736 6737 u8 syndrome[0x20]; 6738 6739 u8 reserved_at_40[0x40]; 6740 6741 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct; 6742 }; 6743 6744 struct mlx5_ifc_query_adapter_in_bits { 6745 u8 opcode[0x10]; 6746 u8 reserved_at_10[0x10]; 6747 6748 u8 reserved_at_20[0x10]; 6749 u8 op_mod[0x10]; 6750 6751 u8 reserved_at_40[0x40]; 6752 }; 6753 6754 struct mlx5_ifc_qp_2rst_out_bits { 6755 u8 status[0x8]; 6756 u8 reserved_at_8[0x18]; 6757 6758 u8 syndrome[0x20]; 6759 6760 u8 reserved_at_40[0x40]; 6761 }; 6762 6763 struct mlx5_ifc_qp_2rst_in_bits { 6764 u8 opcode[0x10]; 6765 u8 uid[0x10]; 6766 6767 u8 reserved_at_20[0x10]; 6768 u8 op_mod[0x10]; 6769 6770 u8 reserved_at_40[0x8]; 6771 u8 qpn[0x18]; 6772 6773 u8 reserved_at_60[0x20]; 6774 }; 6775 6776 struct mlx5_ifc_qp_2err_out_bits { 6777 u8 status[0x8]; 6778 u8 reserved_at_8[0x18]; 6779 6780 u8 syndrome[0x20]; 6781 6782 u8 reserved_at_40[0x40]; 6783 }; 6784 6785 struct mlx5_ifc_qp_2err_in_bits { 6786 u8 opcode[0x10]; 6787 u8 uid[0x10]; 6788 6789 u8 reserved_at_20[0x10]; 6790 u8 op_mod[0x10]; 6791 6792 u8 reserved_at_40[0x8]; 6793 u8 qpn[0x18]; 6794 6795 u8 reserved_at_60[0x20]; 6796 }; 6797 6798 struct mlx5_ifc_page_fault_resume_out_bits { 6799 u8 status[0x8]; 6800 u8 reserved_at_8[0x18]; 6801 6802 u8 syndrome[0x20]; 6803 6804 u8 reserved_at_40[0x40]; 6805 }; 6806 6807 struct mlx5_ifc_page_fault_resume_in_bits { 6808 u8 opcode[0x10]; 6809 u8 reserved_at_10[0x10]; 6810 6811 u8 reserved_at_20[0x10]; 6812 u8 op_mod[0x10]; 6813 6814 u8 error[0x1]; 6815 u8 reserved_at_41[0x4]; 6816 u8 page_fault_type[0x3]; 6817 u8 wq_number[0x18]; 6818 6819 u8 reserved_at_60[0x8]; 6820 u8 token[0x18]; 6821 }; 6822 6823 struct mlx5_ifc_nop_out_bits { 6824 u8 status[0x8]; 6825 u8 reserved_at_8[0x18]; 6826 6827 u8 syndrome[0x20]; 6828 6829 u8 reserved_at_40[0x40]; 6830 }; 6831 6832 struct mlx5_ifc_nop_in_bits { 6833 u8 opcode[0x10]; 6834 u8 reserved_at_10[0x10]; 6835 6836 u8 reserved_at_20[0x10]; 6837 u8 op_mod[0x10]; 6838 6839 u8 reserved_at_40[0x40]; 6840 }; 6841 6842 struct mlx5_ifc_modify_vport_state_out_bits { 6843 u8 status[0x8]; 6844 u8 reserved_at_8[0x18]; 6845 6846 u8 syndrome[0x20]; 6847 6848 u8 reserved_at_40[0x40]; 6849 }; 6850 6851 struct mlx5_ifc_modify_vport_state_in_bits { 6852 u8 opcode[0x10]; 6853 u8 reserved_at_10[0x10]; 6854 6855 u8 reserved_at_20[0x10]; 6856 u8 op_mod[0x10]; 6857 6858 u8 other_vport[0x1]; 6859 u8 reserved_at_41[0xf]; 6860 u8 vport_number[0x10]; 6861 6862 u8 reserved_at_60[0x18]; 6863 u8 admin_state[0x4]; 6864 u8 reserved_at_7c[0x4]; 6865 }; 6866 6867 struct mlx5_ifc_modify_tis_out_bits { 6868 u8 status[0x8]; 6869 u8 reserved_at_8[0x18]; 6870 6871 u8 syndrome[0x20]; 6872 6873 u8 reserved_at_40[0x40]; 6874 }; 6875 6876 struct mlx5_ifc_modify_tis_bitmask_bits { 6877 u8 reserved_at_0[0x20]; 6878 6879 u8 reserved_at_20[0x1d]; 6880 u8 lag_tx_port_affinity[0x1]; 6881 u8 strict_lag_tx_port_affinity[0x1]; 6882 u8 prio[0x1]; 6883 }; 6884 6885 struct mlx5_ifc_modify_tis_in_bits { 6886 u8 opcode[0x10]; 6887 u8 uid[0x10]; 6888 6889 u8 reserved_at_20[0x10]; 6890 u8 op_mod[0x10]; 6891 6892 u8 reserved_at_40[0x8]; 6893 u8 tisn[0x18]; 6894 6895 u8 reserved_at_60[0x20]; 6896 6897 struct mlx5_ifc_modify_tis_bitmask_bits bitmask; 6898 6899 u8 reserved_at_c0[0x40]; 6900 6901 struct mlx5_ifc_tisc_bits ctx; 6902 }; 6903 6904 struct mlx5_ifc_modify_tir_bitmask_bits { 6905 u8 reserved_at_0[0x20]; 6906 6907 u8 reserved_at_20[0x1b]; 6908 u8 self_lb_en[0x1]; 6909 u8 reserved_at_3c[0x1]; 6910 u8 hash[0x1]; 6911 u8 reserved_at_3e[0x1]; 6912 u8 packet_merge[0x1]; 6913 }; 6914 6915 struct mlx5_ifc_modify_tir_out_bits { 6916 u8 status[0x8]; 6917 u8 reserved_at_8[0x18]; 6918 6919 u8 syndrome[0x20]; 6920 6921 u8 reserved_at_40[0x40]; 6922 }; 6923 6924 struct mlx5_ifc_modify_tir_in_bits { 6925 u8 opcode[0x10]; 6926 u8 uid[0x10]; 6927 6928 u8 reserved_at_20[0x10]; 6929 u8 op_mod[0x10]; 6930 6931 u8 reserved_at_40[0x8]; 6932 u8 tirn[0x18]; 6933 6934 u8 reserved_at_60[0x20]; 6935 6936 struct mlx5_ifc_modify_tir_bitmask_bits bitmask; 6937 6938 u8 reserved_at_c0[0x40]; 6939 6940 struct mlx5_ifc_tirc_bits ctx; 6941 }; 6942 6943 struct mlx5_ifc_modify_sq_out_bits { 6944 u8 status[0x8]; 6945 u8 reserved_at_8[0x18]; 6946 6947 u8 syndrome[0x20]; 6948 6949 u8 reserved_at_40[0x40]; 6950 }; 6951 6952 struct mlx5_ifc_modify_sq_in_bits { 6953 u8 opcode[0x10]; 6954 u8 uid[0x10]; 6955 6956 u8 reserved_at_20[0x10]; 6957 u8 op_mod[0x10]; 6958 6959 u8 sq_state[0x4]; 6960 u8 reserved_at_44[0x4]; 6961 u8 sqn[0x18]; 6962 6963 u8 reserved_at_60[0x20]; 6964 6965 u8 modify_bitmask[0x40]; 6966 6967 u8 reserved_at_c0[0x40]; 6968 6969 struct mlx5_ifc_sqc_bits ctx; 6970 }; 6971 6972 struct mlx5_ifc_modify_scheduling_element_out_bits { 6973 u8 status[0x8]; 6974 u8 reserved_at_8[0x18]; 6975 6976 u8 syndrome[0x20]; 6977 6978 u8 reserved_at_40[0x1c0]; 6979 }; 6980 6981 enum { 6982 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1, 6983 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2, 6984 }; 6985 6986 struct mlx5_ifc_modify_scheduling_element_in_bits { 6987 u8 opcode[0x10]; 6988 u8 reserved_at_10[0x10]; 6989 6990 u8 reserved_at_20[0x10]; 6991 u8 op_mod[0x10]; 6992 6993 u8 scheduling_hierarchy[0x8]; 6994 u8 reserved_at_48[0x18]; 6995 6996 u8 scheduling_element_id[0x20]; 6997 6998 u8 reserved_at_80[0x20]; 6999 7000 u8 modify_bitmask[0x20]; 7001 7002 u8 reserved_at_c0[0x40]; 7003 7004 struct mlx5_ifc_scheduling_context_bits scheduling_context; 7005 7006 u8 reserved_at_300[0x100]; 7007 }; 7008 7009 struct mlx5_ifc_modify_rqt_out_bits { 7010 u8 status[0x8]; 7011 u8 reserved_at_8[0x18]; 7012 7013 u8 syndrome[0x20]; 7014 7015 u8 reserved_at_40[0x40]; 7016 }; 7017 7018 struct mlx5_ifc_rqt_bitmask_bits { 7019 u8 reserved_at_0[0x20]; 7020 7021 u8 reserved_at_20[0x1f]; 7022 u8 rqn_list[0x1]; 7023 }; 7024 7025 struct mlx5_ifc_modify_rqt_in_bits { 7026 u8 opcode[0x10]; 7027 u8 uid[0x10]; 7028 7029 u8 reserved_at_20[0x10]; 7030 u8 op_mod[0x10]; 7031 7032 u8 reserved_at_40[0x8]; 7033 u8 rqtn[0x18]; 7034 7035 u8 reserved_at_60[0x20]; 7036 7037 struct mlx5_ifc_rqt_bitmask_bits bitmask; 7038 7039 u8 reserved_at_c0[0x40]; 7040 7041 struct mlx5_ifc_rqtc_bits ctx; 7042 }; 7043 7044 struct mlx5_ifc_modify_rq_out_bits { 7045 u8 status[0x8]; 7046 u8 reserved_at_8[0x18]; 7047 7048 u8 syndrome[0x20]; 7049 7050 u8 reserved_at_40[0x40]; 7051 }; 7052 7053 enum { 7054 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1, 7055 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2, 7056 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3, 7057 }; 7058 7059 struct mlx5_ifc_modify_rq_in_bits { 7060 u8 opcode[0x10]; 7061 u8 uid[0x10]; 7062 7063 u8 reserved_at_20[0x10]; 7064 u8 op_mod[0x10]; 7065 7066 u8 rq_state[0x4]; 7067 u8 reserved_at_44[0x4]; 7068 u8 rqn[0x18]; 7069 7070 u8 reserved_at_60[0x20]; 7071 7072 u8 modify_bitmask[0x40]; 7073 7074 u8 reserved_at_c0[0x40]; 7075 7076 struct mlx5_ifc_rqc_bits ctx; 7077 }; 7078 7079 struct mlx5_ifc_modify_rmp_out_bits { 7080 u8 status[0x8]; 7081 u8 reserved_at_8[0x18]; 7082 7083 u8 syndrome[0x20]; 7084 7085 u8 reserved_at_40[0x40]; 7086 }; 7087 7088 struct mlx5_ifc_rmp_bitmask_bits { 7089 u8 reserved_at_0[0x20]; 7090 7091 u8 reserved_at_20[0x1f]; 7092 u8 lwm[0x1]; 7093 }; 7094 7095 struct mlx5_ifc_modify_rmp_in_bits { 7096 u8 opcode[0x10]; 7097 u8 uid[0x10]; 7098 7099 u8 reserved_at_20[0x10]; 7100 u8 op_mod[0x10]; 7101 7102 u8 rmp_state[0x4]; 7103 u8 reserved_at_44[0x4]; 7104 u8 rmpn[0x18]; 7105 7106 u8 reserved_at_60[0x20]; 7107 7108 struct mlx5_ifc_rmp_bitmask_bits bitmask; 7109 7110 u8 reserved_at_c0[0x40]; 7111 7112 struct mlx5_ifc_rmpc_bits ctx; 7113 }; 7114 7115 struct mlx5_ifc_modify_nic_vport_context_out_bits { 7116 u8 status[0x8]; 7117 u8 reserved_at_8[0x18]; 7118 7119 u8 syndrome[0x20]; 7120 7121 u8 reserved_at_40[0x40]; 7122 }; 7123 7124 struct mlx5_ifc_modify_nic_vport_field_select_bits { 7125 u8 reserved_at_0[0x12]; 7126 u8 affiliation[0x1]; 7127 u8 reserved_at_13[0x1]; 7128 u8 disable_uc_local_lb[0x1]; 7129 u8 disable_mc_local_lb[0x1]; 7130 u8 node_guid[0x1]; 7131 u8 port_guid[0x1]; 7132 u8 min_inline[0x1]; 7133 u8 mtu[0x1]; 7134 u8 change_event[0x1]; 7135 u8 promisc[0x1]; 7136 u8 permanent_address[0x1]; 7137 u8 addresses_list[0x1]; 7138 u8 roce_en[0x1]; 7139 u8 reserved_at_1f[0x1]; 7140 }; 7141 7142 struct mlx5_ifc_modify_nic_vport_context_in_bits { 7143 u8 opcode[0x10]; 7144 u8 reserved_at_10[0x10]; 7145 7146 u8 reserved_at_20[0x10]; 7147 u8 op_mod[0x10]; 7148 7149 u8 other_vport[0x1]; 7150 u8 reserved_at_41[0xf]; 7151 u8 vport_number[0x10]; 7152 7153 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select; 7154 7155 u8 reserved_at_80[0x780]; 7156 7157 struct mlx5_ifc_nic_vport_context_bits nic_vport_context; 7158 }; 7159 7160 struct mlx5_ifc_modify_hca_vport_context_out_bits { 7161 u8 status[0x8]; 7162 u8 reserved_at_8[0x18]; 7163 7164 u8 syndrome[0x20]; 7165 7166 u8 reserved_at_40[0x40]; 7167 }; 7168 7169 struct mlx5_ifc_modify_hca_vport_context_in_bits { 7170 u8 opcode[0x10]; 7171 u8 reserved_at_10[0x10]; 7172 7173 u8 reserved_at_20[0x10]; 7174 u8 op_mod[0x10]; 7175 7176 u8 other_vport[0x1]; 7177 u8 reserved_at_41[0xb]; 7178 u8 port_num[0x4]; 7179 u8 vport_number[0x10]; 7180 7181 u8 reserved_at_60[0x20]; 7182 7183 struct mlx5_ifc_hca_vport_context_bits hca_vport_context; 7184 }; 7185 7186 struct mlx5_ifc_modify_cq_out_bits { 7187 u8 status[0x8]; 7188 u8 reserved_at_8[0x18]; 7189 7190 u8 syndrome[0x20]; 7191 7192 u8 reserved_at_40[0x40]; 7193 }; 7194 7195 enum { 7196 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0, 7197 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1, 7198 }; 7199 7200 struct mlx5_ifc_modify_cq_in_bits { 7201 u8 opcode[0x10]; 7202 u8 uid[0x10]; 7203 7204 u8 reserved_at_20[0x10]; 7205 u8 op_mod[0x10]; 7206 7207 u8 reserved_at_40[0x8]; 7208 u8 cqn[0x18]; 7209 7210 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select; 7211 7212 struct mlx5_ifc_cqc_bits cq_context; 7213 7214 u8 reserved_at_280[0x60]; 7215 7216 u8 cq_umem_valid[0x1]; 7217 u8 reserved_at_2e1[0x1f]; 7218 7219 u8 reserved_at_300[0x580]; 7220 7221 u8 pas[][0x40]; 7222 }; 7223 7224 struct mlx5_ifc_modify_cong_status_out_bits { 7225 u8 status[0x8]; 7226 u8 reserved_at_8[0x18]; 7227 7228 u8 syndrome[0x20]; 7229 7230 u8 reserved_at_40[0x40]; 7231 }; 7232 7233 struct mlx5_ifc_modify_cong_status_in_bits { 7234 u8 opcode[0x10]; 7235 u8 reserved_at_10[0x10]; 7236 7237 u8 reserved_at_20[0x10]; 7238 u8 op_mod[0x10]; 7239 7240 u8 reserved_at_40[0x18]; 7241 u8 priority[0x4]; 7242 u8 cong_protocol[0x4]; 7243 7244 u8 enable[0x1]; 7245 u8 tag_enable[0x1]; 7246 u8 reserved_at_62[0x1e]; 7247 }; 7248 7249 struct mlx5_ifc_modify_cong_params_out_bits { 7250 u8 status[0x8]; 7251 u8 reserved_at_8[0x18]; 7252 7253 u8 syndrome[0x20]; 7254 7255 u8 reserved_at_40[0x40]; 7256 }; 7257 7258 struct mlx5_ifc_modify_cong_params_in_bits { 7259 u8 opcode[0x10]; 7260 u8 reserved_at_10[0x10]; 7261 7262 u8 reserved_at_20[0x10]; 7263 u8 op_mod[0x10]; 7264 7265 u8 reserved_at_40[0x1c]; 7266 u8 cong_protocol[0x4]; 7267 7268 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select; 7269 7270 u8 reserved_at_80[0x80]; 7271 7272 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; 7273 }; 7274 7275 struct mlx5_ifc_manage_pages_out_bits { 7276 u8 status[0x8]; 7277 u8 reserved_at_8[0x18]; 7278 7279 u8 syndrome[0x20]; 7280 7281 u8 output_num_entries[0x20]; 7282 7283 u8 reserved_at_60[0x20]; 7284 7285 u8 pas[][0x40]; 7286 }; 7287 7288 enum { 7289 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0, 7290 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1, 7291 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2, 7292 }; 7293 7294 struct mlx5_ifc_manage_pages_in_bits { 7295 u8 opcode[0x10]; 7296 u8 reserved_at_10[0x10]; 7297 7298 u8 reserved_at_20[0x10]; 7299 u8 op_mod[0x10]; 7300 7301 u8 embedded_cpu_function[0x1]; 7302 u8 reserved_at_41[0xf]; 7303 u8 function_id[0x10]; 7304 7305 u8 input_num_entries[0x20]; 7306 7307 u8 pas[][0x40]; 7308 }; 7309 7310 struct mlx5_ifc_mad_ifc_out_bits { 7311 u8 status[0x8]; 7312 u8 reserved_at_8[0x18]; 7313 7314 u8 syndrome[0x20]; 7315 7316 u8 reserved_at_40[0x40]; 7317 7318 u8 response_mad_packet[256][0x8]; 7319 }; 7320 7321 struct mlx5_ifc_mad_ifc_in_bits { 7322 u8 opcode[0x10]; 7323 u8 reserved_at_10[0x10]; 7324 7325 u8 reserved_at_20[0x10]; 7326 u8 op_mod[0x10]; 7327 7328 u8 remote_lid[0x10]; 7329 u8 reserved_at_50[0x8]; 7330 u8 port[0x8]; 7331 7332 u8 reserved_at_60[0x20]; 7333 7334 u8 mad[256][0x8]; 7335 }; 7336 7337 struct mlx5_ifc_init_hca_out_bits { 7338 u8 status[0x8]; 7339 u8 reserved_at_8[0x18]; 7340 7341 u8 syndrome[0x20]; 7342 7343 u8 reserved_at_40[0x40]; 7344 }; 7345 7346 struct mlx5_ifc_init_hca_in_bits { 7347 u8 opcode[0x10]; 7348 u8 reserved_at_10[0x10]; 7349 7350 u8 reserved_at_20[0x10]; 7351 u8 op_mod[0x10]; 7352 7353 u8 reserved_at_40[0x20]; 7354 7355 u8 reserved_at_60[0x2]; 7356 u8 sw_vhca_id[0xe]; 7357 u8 reserved_at_70[0x10]; 7358 7359 u8 sw_owner_id[4][0x20]; 7360 }; 7361 7362 struct mlx5_ifc_init2rtr_qp_out_bits { 7363 u8 status[0x8]; 7364 u8 reserved_at_8[0x18]; 7365 7366 u8 syndrome[0x20]; 7367 7368 u8 reserved_at_40[0x20]; 7369 u8 ece[0x20]; 7370 }; 7371 7372 struct mlx5_ifc_init2rtr_qp_in_bits { 7373 u8 opcode[0x10]; 7374 u8 uid[0x10]; 7375 7376 u8 reserved_at_20[0x10]; 7377 u8 op_mod[0x10]; 7378 7379 u8 reserved_at_40[0x8]; 7380 u8 qpn[0x18]; 7381 7382 u8 reserved_at_60[0x20]; 7383 7384 u8 opt_param_mask[0x20]; 7385 7386 u8 ece[0x20]; 7387 7388 struct mlx5_ifc_qpc_bits qpc; 7389 7390 u8 reserved_at_800[0x80]; 7391 }; 7392 7393 struct mlx5_ifc_init2init_qp_out_bits { 7394 u8 status[0x8]; 7395 u8 reserved_at_8[0x18]; 7396 7397 u8 syndrome[0x20]; 7398 7399 u8 reserved_at_40[0x20]; 7400 u8 ece[0x20]; 7401 }; 7402 7403 struct mlx5_ifc_init2init_qp_in_bits { 7404 u8 opcode[0x10]; 7405 u8 uid[0x10]; 7406 7407 u8 reserved_at_20[0x10]; 7408 u8 op_mod[0x10]; 7409 7410 u8 reserved_at_40[0x8]; 7411 u8 qpn[0x18]; 7412 7413 u8 reserved_at_60[0x20]; 7414 7415 u8 opt_param_mask[0x20]; 7416 7417 u8 ece[0x20]; 7418 7419 struct mlx5_ifc_qpc_bits qpc; 7420 7421 u8 reserved_at_800[0x80]; 7422 }; 7423 7424 struct mlx5_ifc_get_dropped_packet_log_out_bits { 7425 u8 status[0x8]; 7426 u8 reserved_at_8[0x18]; 7427 7428 u8 syndrome[0x20]; 7429 7430 u8 reserved_at_40[0x40]; 7431 7432 u8 packet_headers_log[128][0x8]; 7433 7434 u8 packet_syndrome[64][0x8]; 7435 }; 7436 7437 struct mlx5_ifc_get_dropped_packet_log_in_bits { 7438 u8 opcode[0x10]; 7439 u8 reserved_at_10[0x10]; 7440 7441 u8 reserved_at_20[0x10]; 7442 u8 op_mod[0x10]; 7443 7444 u8 reserved_at_40[0x40]; 7445 }; 7446 7447 struct mlx5_ifc_gen_eqe_in_bits { 7448 u8 opcode[0x10]; 7449 u8 reserved_at_10[0x10]; 7450 7451 u8 reserved_at_20[0x10]; 7452 u8 op_mod[0x10]; 7453 7454 u8 reserved_at_40[0x18]; 7455 u8 eq_number[0x8]; 7456 7457 u8 reserved_at_60[0x20]; 7458 7459 u8 eqe[64][0x8]; 7460 }; 7461 7462 struct mlx5_ifc_gen_eq_out_bits { 7463 u8 status[0x8]; 7464 u8 reserved_at_8[0x18]; 7465 7466 u8 syndrome[0x20]; 7467 7468 u8 reserved_at_40[0x40]; 7469 }; 7470 7471 struct mlx5_ifc_enable_hca_out_bits { 7472 u8 status[0x8]; 7473 u8 reserved_at_8[0x18]; 7474 7475 u8 syndrome[0x20]; 7476 7477 u8 reserved_at_40[0x20]; 7478 }; 7479 7480 struct mlx5_ifc_enable_hca_in_bits { 7481 u8 opcode[0x10]; 7482 u8 reserved_at_10[0x10]; 7483 7484 u8 reserved_at_20[0x10]; 7485 u8 op_mod[0x10]; 7486 7487 u8 embedded_cpu_function[0x1]; 7488 u8 reserved_at_41[0xf]; 7489 u8 function_id[0x10]; 7490 7491 u8 reserved_at_60[0x20]; 7492 }; 7493 7494 struct mlx5_ifc_drain_dct_out_bits { 7495 u8 status[0x8]; 7496 u8 reserved_at_8[0x18]; 7497 7498 u8 syndrome[0x20]; 7499 7500 u8 reserved_at_40[0x40]; 7501 }; 7502 7503 struct mlx5_ifc_drain_dct_in_bits { 7504 u8 opcode[0x10]; 7505 u8 uid[0x10]; 7506 7507 u8 reserved_at_20[0x10]; 7508 u8 op_mod[0x10]; 7509 7510 u8 reserved_at_40[0x8]; 7511 u8 dctn[0x18]; 7512 7513 u8 reserved_at_60[0x20]; 7514 }; 7515 7516 struct mlx5_ifc_disable_hca_out_bits { 7517 u8 status[0x8]; 7518 u8 reserved_at_8[0x18]; 7519 7520 u8 syndrome[0x20]; 7521 7522 u8 reserved_at_40[0x20]; 7523 }; 7524 7525 struct mlx5_ifc_disable_hca_in_bits { 7526 u8 opcode[0x10]; 7527 u8 reserved_at_10[0x10]; 7528 7529 u8 reserved_at_20[0x10]; 7530 u8 op_mod[0x10]; 7531 7532 u8 embedded_cpu_function[0x1]; 7533 u8 reserved_at_41[0xf]; 7534 u8 function_id[0x10]; 7535 7536 u8 reserved_at_60[0x20]; 7537 }; 7538 7539 struct mlx5_ifc_detach_from_mcg_out_bits { 7540 u8 status[0x8]; 7541 u8 reserved_at_8[0x18]; 7542 7543 u8 syndrome[0x20]; 7544 7545 u8 reserved_at_40[0x40]; 7546 }; 7547 7548 struct mlx5_ifc_detach_from_mcg_in_bits { 7549 u8 opcode[0x10]; 7550 u8 uid[0x10]; 7551 7552 u8 reserved_at_20[0x10]; 7553 u8 op_mod[0x10]; 7554 7555 u8 reserved_at_40[0x8]; 7556 u8 qpn[0x18]; 7557 7558 u8 reserved_at_60[0x20]; 7559 7560 u8 multicast_gid[16][0x8]; 7561 }; 7562 7563 struct mlx5_ifc_destroy_xrq_out_bits { 7564 u8 status[0x8]; 7565 u8 reserved_at_8[0x18]; 7566 7567 u8 syndrome[0x20]; 7568 7569 u8 reserved_at_40[0x40]; 7570 }; 7571 7572 struct mlx5_ifc_destroy_xrq_in_bits { 7573 u8 opcode[0x10]; 7574 u8 uid[0x10]; 7575 7576 u8 reserved_at_20[0x10]; 7577 u8 op_mod[0x10]; 7578 7579 u8 reserved_at_40[0x8]; 7580 u8 xrqn[0x18]; 7581 7582 u8 reserved_at_60[0x20]; 7583 }; 7584 7585 struct mlx5_ifc_destroy_xrc_srq_out_bits { 7586 u8 status[0x8]; 7587 u8 reserved_at_8[0x18]; 7588 7589 u8 syndrome[0x20]; 7590 7591 u8 reserved_at_40[0x40]; 7592 }; 7593 7594 struct mlx5_ifc_destroy_xrc_srq_in_bits { 7595 u8 opcode[0x10]; 7596 u8 uid[0x10]; 7597 7598 u8 reserved_at_20[0x10]; 7599 u8 op_mod[0x10]; 7600 7601 u8 reserved_at_40[0x8]; 7602 u8 xrc_srqn[0x18]; 7603 7604 u8 reserved_at_60[0x20]; 7605 }; 7606 7607 struct mlx5_ifc_destroy_tis_out_bits { 7608 u8 status[0x8]; 7609 u8 reserved_at_8[0x18]; 7610 7611 u8 syndrome[0x20]; 7612 7613 u8 reserved_at_40[0x40]; 7614 }; 7615 7616 struct mlx5_ifc_destroy_tis_in_bits { 7617 u8 opcode[0x10]; 7618 u8 uid[0x10]; 7619 7620 u8 reserved_at_20[0x10]; 7621 u8 op_mod[0x10]; 7622 7623 u8 reserved_at_40[0x8]; 7624 u8 tisn[0x18]; 7625 7626 u8 reserved_at_60[0x20]; 7627 }; 7628 7629 struct mlx5_ifc_destroy_tir_out_bits { 7630 u8 status[0x8]; 7631 u8 reserved_at_8[0x18]; 7632 7633 u8 syndrome[0x20]; 7634 7635 u8 reserved_at_40[0x40]; 7636 }; 7637 7638 struct mlx5_ifc_destroy_tir_in_bits { 7639 u8 opcode[0x10]; 7640 u8 uid[0x10]; 7641 7642 u8 reserved_at_20[0x10]; 7643 u8 op_mod[0x10]; 7644 7645 u8 reserved_at_40[0x8]; 7646 u8 tirn[0x18]; 7647 7648 u8 reserved_at_60[0x20]; 7649 }; 7650 7651 struct mlx5_ifc_destroy_srq_out_bits { 7652 u8 status[0x8]; 7653 u8 reserved_at_8[0x18]; 7654 7655 u8 syndrome[0x20]; 7656 7657 u8 reserved_at_40[0x40]; 7658 }; 7659 7660 struct mlx5_ifc_destroy_srq_in_bits { 7661 u8 opcode[0x10]; 7662 u8 uid[0x10]; 7663 7664 u8 reserved_at_20[0x10]; 7665 u8 op_mod[0x10]; 7666 7667 u8 reserved_at_40[0x8]; 7668 u8 srqn[0x18]; 7669 7670 u8 reserved_at_60[0x20]; 7671 }; 7672 7673 struct mlx5_ifc_destroy_sq_out_bits { 7674 u8 status[0x8]; 7675 u8 reserved_at_8[0x18]; 7676 7677 u8 syndrome[0x20]; 7678 7679 u8 reserved_at_40[0x40]; 7680 }; 7681 7682 struct mlx5_ifc_destroy_sq_in_bits { 7683 u8 opcode[0x10]; 7684 u8 uid[0x10]; 7685 7686 u8 reserved_at_20[0x10]; 7687 u8 op_mod[0x10]; 7688 7689 u8 reserved_at_40[0x8]; 7690 u8 sqn[0x18]; 7691 7692 u8 reserved_at_60[0x20]; 7693 }; 7694 7695 struct mlx5_ifc_destroy_scheduling_element_out_bits { 7696 u8 status[0x8]; 7697 u8 reserved_at_8[0x18]; 7698 7699 u8 syndrome[0x20]; 7700 7701 u8 reserved_at_40[0x1c0]; 7702 }; 7703 7704 struct mlx5_ifc_destroy_scheduling_element_in_bits { 7705 u8 opcode[0x10]; 7706 u8 reserved_at_10[0x10]; 7707 7708 u8 reserved_at_20[0x10]; 7709 u8 op_mod[0x10]; 7710 7711 u8 scheduling_hierarchy[0x8]; 7712 u8 reserved_at_48[0x18]; 7713 7714 u8 scheduling_element_id[0x20]; 7715 7716 u8 reserved_at_80[0x180]; 7717 }; 7718 7719 struct mlx5_ifc_destroy_rqt_out_bits { 7720 u8 status[0x8]; 7721 u8 reserved_at_8[0x18]; 7722 7723 u8 syndrome[0x20]; 7724 7725 u8 reserved_at_40[0x40]; 7726 }; 7727 7728 struct mlx5_ifc_destroy_rqt_in_bits { 7729 u8 opcode[0x10]; 7730 u8 uid[0x10]; 7731 7732 u8 reserved_at_20[0x10]; 7733 u8 op_mod[0x10]; 7734 7735 u8 reserved_at_40[0x8]; 7736 u8 rqtn[0x18]; 7737 7738 u8 reserved_at_60[0x20]; 7739 }; 7740 7741 struct mlx5_ifc_destroy_rq_out_bits { 7742 u8 status[0x8]; 7743 u8 reserved_at_8[0x18]; 7744 7745 u8 syndrome[0x20]; 7746 7747 u8 reserved_at_40[0x40]; 7748 }; 7749 7750 struct mlx5_ifc_destroy_rq_in_bits { 7751 u8 opcode[0x10]; 7752 u8 uid[0x10]; 7753 7754 u8 reserved_at_20[0x10]; 7755 u8 op_mod[0x10]; 7756 7757 u8 reserved_at_40[0x8]; 7758 u8 rqn[0x18]; 7759 7760 u8 reserved_at_60[0x20]; 7761 }; 7762 7763 struct mlx5_ifc_set_delay_drop_params_in_bits { 7764 u8 opcode[0x10]; 7765 u8 reserved_at_10[0x10]; 7766 7767 u8 reserved_at_20[0x10]; 7768 u8 op_mod[0x10]; 7769 7770 u8 reserved_at_40[0x20]; 7771 7772 u8 reserved_at_60[0x10]; 7773 u8 delay_drop_timeout[0x10]; 7774 }; 7775 7776 struct mlx5_ifc_set_delay_drop_params_out_bits { 7777 u8 status[0x8]; 7778 u8 reserved_at_8[0x18]; 7779 7780 u8 syndrome[0x20]; 7781 7782 u8 reserved_at_40[0x40]; 7783 }; 7784 7785 struct mlx5_ifc_destroy_rmp_out_bits { 7786 u8 status[0x8]; 7787 u8 reserved_at_8[0x18]; 7788 7789 u8 syndrome[0x20]; 7790 7791 u8 reserved_at_40[0x40]; 7792 }; 7793 7794 struct mlx5_ifc_destroy_rmp_in_bits { 7795 u8 opcode[0x10]; 7796 u8 uid[0x10]; 7797 7798 u8 reserved_at_20[0x10]; 7799 u8 op_mod[0x10]; 7800 7801 u8 reserved_at_40[0x8]; 7802 u8 rmpn[0x18]; 7803 7804 u8 reserved_at_60[0x20]; 7805 }; 7806 7807 struct mlx5_ifc_destroy_qp_out_bits { 7808 u8 status[0x8]; 7809 u8 reserved_at_8[0x18]; 7810 7811 u8 syndrome[0x20]; 7812 7813 u8 reserved_at_40[0x40]; 7814 }; 7815 7816 struct mlx5_ifc_destroy_qp_in_bits { 7817 u8 opcode[0x10]; 7818 u8 uid[0x10]; 7819 7820 u8 reserved_at_20[0x10]; 7821 u8 op_mod[0x10]; 7822 7823 u8 reserved_at_40[0x8]; 7824 u8 qpn[0x18]; 7825 7826 u8 reserved_at_60[0x20]; 7827 }; 7828 7829 struct mlx5_ifc_destroy_psv_out_bits { 7830 u8 status[0x8]; 7831 u8 reserved_at_8[0x18]; 7832 7833 u8 syndrome[0x20]; 7834 7835 u8 reserved_at_40[0x40]; 7836 }; 7837 7838 struct mlx5_ifc_destroy_psv_in_bits { 7839 u8 opcode[0x10]; 7840 u8 reserved_at_10[0x10]; 7841 7842 u8 reserved_at_20[0x10]; 7843 u8 op_mod[0x10]; 7844 7845 u8 reserved_at_40[0x8]; 7846 u8 psvn[0x18]; 7847 7848 u8 reserved_at_60[0x20]; 7849 }; 7850 7851 struct mlx5_ifc_destroy_mkey_out_bits { 7852 u8 status[0x8]; 7853 u8 reserved_at_8[0x18]; 7854 7855 u8 syndrome[0x20]; 7856 7857 u8 reserved_at_40[0x40]; 7858 }; 7859 7860 struct mlx5_ifc_destroy_mkey_in_bits { 7861 u8 opcode[0x10]; 7862 u8 uid[0x10]; 7863 7864 u8 reserved_at_20[0x10]; 7865 u8 op_mod[0x10]; 7866 7867 u8 reserved_at_40[0x8]; 7868 u8 mkey_index[0x18]; 7869 7870 u8 reserved_at_60[0x20]; 7871 }; 7872 7873 struct mlx5_ifc_destroy_flow_table_out_bits { 7874 u8 status[0x8]; 7875 u8 reserved_at_8[0x18]; 7876 7877 u8 syndrome[0x20]; 7878 7879 u8 reserved_at_40[0x40]; 7880 }; 7881 7882 struct mlx5_ifc_destroy_flow_table_in_bits { 7883 u8 opcode[0x10]; 7884 u8 reserved_at_10[0x10]; 7885 7886 u8 reserved_at_20[0x10]; 7887 u8 op_mod[0x10]; 7888 7889 u8 other_vport[0x1]; 7890 u8 reserved_at_41[0xf]; 7891 u8 vport_number[0x10]; 7892 7893 u8 reserved_at_60[0x20]; 7894 7895 u8 table_type[0x8]; 7896 u8 reserved_at_88[0x18]; 7897 7898 u8 reserved_at_a0[0x8]; 7899 u8 table_id[0x18]; 7900 7901 u8 reserved_at_c0[0x140]; 7902 }; 7903 7904 struct mlx5_ifc_destroy_flow_group_out_bits { 7905 u8 status[0x8]; 7906 u8 reserved_at_8[0x18]; 7907 7908 u8 syndrome[0x20]; 7909 7910 u8 reserved_at_40[0x40]; 7911 }; 7912 7913 struct mlx5_ifc_destroy_flow_group_in_bits { 7914 u8 opcode[0x10]; 7915 u8 reserved_at_10[0x10]; 7916 7917 u8 reserved_at_20[0x10]; 7918 u8 op_mod[0x10]; 7919 7920 u8 other_vport[0x1]; 7921 u8 reserved_at_41[0xf]; 7922 u8 vport_number[0x10]; 7923 7924 u8 reserved_at_60[0x20]; 7925 7926 u8 table_type[0x8]; 7927 u8 reserved_at_88[0x18]; 7928 7929 u8 reserved_at_a0[0x8]; 7930 u8 table_id[0x18]; 7931 7932 u8 group_id[0x20]; 7933 7934 u8 reserved_at_e0[0x120]; 7935 }; 7936 7937 struct mlx5_ifc_destroy_eq_out_bits { 7938 u8 status[0x8]; 7939 u8 reserved_at_8[0x18]; 7940 7941 u8 syndrome[0x20]; 7942 7943 u8 reserved_at_40[0x40]; 7944 }; 7945 7946 struct mlx5_ifc_destroy_eq_in_bits { 7947 u8 opcode[0x10]; 7948 u8 reserved_at_10[0x10]; 7949 7950 u8 reserved_at_20[0x10]; 7951 u8 op_mod[0x10]; 7952 7953 u8 reserved_at_40[0x18]; 7954 u8 eq_number[0x8]; 7955 7956 u8 reserved_at_60[0x20]; 7957 }; 7958 7959 struct mlx5_ifc_destroy_dct_out_bits { 7960 u8 status[0x8]; 7961 u8 reserved_at_8[0x18]; 7962 7963 u8 syndrome[0x20]; 7964 7965 u8 reserved_at_40[0x40]; 7966 }; 7967 7968 struct mlx5_ifc_destroy_dct_in_bits { 7969 u8 opcode[0x10]; 7970 u8 uid[0x10]; 7971 7972 u8 reserved_at_20[0x10]; 7973 u8 op_mod[0x10]; 7974 7975 u8 reserved_at_40[0x8]; 7976 u8 dctn[0x18]; 7977 7978 u8 reserved_at_60[0x20]; 7979 }; 7980 7981 struct mlx5_ifc_destroy_cq_out_bits { 7982 u8 status[0x8]; 7983 u8 reserved_at_8[0x18]; 7984 7985 u8 syndrome[0x20]; 7986 7987 u8 reserved_at_40[0x40]; 7988 }; 7989 7990 struct mlx5_ifc_destroy_cq_in_bits { 7991 u8 opcode[0x10]; 7992 u8 uid[0x10]; 7993 7994 u8 reserved_at_20[0x10]; 7995 u8 op_mod[0x10]; 7996 7997 u8 reserved_at_40[0x8]; 7998 u8 cqn[0x18]; 7999 8000 u8 reserved_at_60[0x20]; 8001 }; 8002 8003 struct mlx5_ifc_delete_vxlan_udp_dport_out_bits { 8004 u8 status[0x8]; 8005 u8 reserved_at_8[0x18]; 8006 8007 u8 syndrome[0x20]; 8008 8009 u8 reserved_at_40[0x40]; 8010 }; 8011 8012 struct mlx5_ifc_delete_vxlan_udp_dport_in_bits { 8013 u8 opcode[0x10]; 8014 u8 reserved_at_10[0x10]; 8015 8016 u8 reserved_at_20[0x10]; 8017 u8 op_mod[0x10]; 8018 8019 u8 reserved_at_40[0x20]; 8020 8021 u8 reserved_at_60[0x10]; 8022 u8 vxlan_udp_port[0x10]; 8023 }; 8024 8025 struct mlx5_ifc_delete_l2_table_entry_out_bits { 8026 u8 status[0x8]; 8027 u8 reserved_at_8[0x18]; 8028 8029 u8 syndrome[0x20]; 8030 8031 u8 reserved_at_40[0x40]; 8032 }; 8033 8034 struct mlx5_ifc_delete_l2_table_entry_in_bits { 8035 u8 opcode[0x10]; 8036 u8 reserved_at_10[0x10]; 8037 8038 u8 reserved_at_20[0x10]; 8039 u8 op_mod[0x10]; 8040 8041 u8 reserved_at_40[0x60]; 8042 8043 u8 reserved_at_a0[0x8]; 8044 u8 table_index[0x18]; 8045 8046 u8 reserved_at_c0[0x140]; 8047 }; 8048 8049 struct mlx5_ifc_delete_fte_out_bits { 8050 u8 status[0x8]; 8051 u8 reserved_at_8[0x18]; 8052 8053 u8 syndrome[0x20]; 8054 8055 u8 reserved_at_40[0x40]; 8056 }; 8057 8058 struct mlx5_ifc_delete_fte_in_bits { 8059 u8 opcode[0x10]; 8060 u8 reserved_at_10[0x10]; 8061 8062 u8 reserved_at_20[0x10]; 8063 u8 op_mod[0x10]; 8064 8065 u8 other_vport[0x1]; 8066 u8 reserved_at_41[0xf]; 8067 u8 vport_number[0x10]; 8068 8069 u8 reserved_at_60[0x20]; 8070 8071 u8 table_type[0x8]; 8072 u8 reserved_at_88[0x18]; 8073 8074 u8 reserved_at_a0[0x8]; 8075 u8 table_id[0x18]; 8076 8077 u8 reserved_at_c0[0x40]; 8078 8079 u8 flow_index[0x20]; 8080 8081 u8 reserved_at_120[0xe0]; 8082 }; 8083 8084 struct mlx5_ifc_dealloc_xrcd_out_bits { 8085 u8 status[0x8]; 8086 u8 reserved_at_8[0x18]; 8087 8088 u8 syndrome[0x20]; 8089 8090 u8 reserved_at_40[0x40]; 8091 }; 8092 8093 struct mlx5_ifc_dealloc_xrcd_in_bits { 8094 u8 opcode[0x10]; 8095 u8 uid[0x10]; 8096 8097 u8 reserved_at_20[0x10]; 8098 u8 op_mod[0x10]; 8099 8100 u8 reserved_at_40[0x8]; 8101 u8 xrcd[0x18]; 8102 8103 u8 reserved_at_60[0x20]; 8104 }; 8105 8106 struct mlx5_ifc_dealloc_uar_out_bits { 8107 u8 status[0x8]; 8108 u8 reserved_at_8[0x18]; 8109 8110 u8 syndrome[0x20]; 8111 8112 u8 reserved_at_40[0x40]; 8113 }; 8114 8115 struct mlx5_ifc_dealloc_uar_in_bits { 8116 u8 opcode[0x10]; 8117 u8 uid[0x10]; 8118 8119 u8 reserved_at_20[0x10]; 8120 u8 op_mod[0x10]; 8121 8122 u8 reserved_at_40[0x8]; 8123 u8 uar[0x18]; 8124 8125 u8 reserved_at_60[0x20]; 8126 }; 8127 8128 struct mlx5_ifc_dealloc_transport_domain_out_bits { 8129 u8 status[0x8]; 8130 u8 reserved_at_8[0x18]; 8131 8132 u8 syndrome[0x20]; 8133 8134 u8 reserved_at_40[0x40]; 8135 }; 8136 8137 struct mlx5_ifc_dealloc_transport_domain_in_bits { 8138 u8 opcode[0x10]; 8139 u8 uid[0x10]; 8140 8141 u8 reserved_at_20[0x10]; 8142 u8 op_mod[0x10]; 8143 8144 u8 reserved_at_40[0x8]; 8145 u8 transport_domain[0x18]; 8146 8147 u8 reserved_at_60[0x20]; 8148 }; 8149 8150 struct mlx5_ifc_dealloc_q_counter_out_bits { 8151 u8 status[0x8]; 8152 u8 reserved_at_8[0x18]; 8153 8154 u8 syndrome[0x20]; 8155 8156 u8 reserved_at_40[0x40]; 8157 }; 8158 8159 struct mlx5_ifc_dealloc_q_counter_in_bits { 8160 u8 opcode[0x10]; 8161 u8 reserved_at_10[0x10]; 8162 8163 u8 reserved_at_20[0x10]; 8164 u8 op_mod[0x10]; 8165 8166 u8 reserved_at_40[0x18]; 8167 u8 counter_set_id[0x8]; 8168 8169 u8 reserved_at_60[0x20]; 8170 }; 8171 8172 struct mlx5_ifc_dealloc_pd_out_bits { 8173 u8 status[0x8]; 8174 u8 reserved_at_8[0x18]; 8175 8176 u8 syndrome[0x20]; 8177 8178 u8 reserved_at_40[0x40]; 8179 }; 8180 8181 struct mlx5_ifc_dealloc_pd_in_bits { 8182 u8 opcode[0x10]; 8183 u8 uid[0x10]; 8184 8185 u8 reserved_at_20[0x10]; 8186 u8 op_mod[0x10]; 8187 8188 u8 reserved_at_40[0x8]; 8189 u8 pd[0x18]; 8190 8191 u8 reserved_at_60[0x20]; 8192 }; 8193 8194 struct mlx5_ifc_dealloc_flow_counter_out_bits { 8195 u8 status[0x8]; 8196 u8 reserved_at_8[0x18]; 8197 8198 u8 syndrome[0x20]; 8199 8200 u8 reserved_at_40[0x40]; 8201 }; 8202 8203 struct mlx5_ifc_dealloc_flow_counter_in_bits { 8204 u8 opcode[0x10]; 8205 u8 reserved_at_10[0x10]; 8206 8207 u8 reserved_at_20[0x10]; 8208 u8 op_mod[0x10]; 8209 8210 u8 flow_counter_id[0x20]; 8211 8212 u8 reserved_at_60[0x20]; 8213 }; 8214 8215 struct mlx5_ifc_create_xrq_out_bits { 8216 u8 status[0x8]; 8217 u8 reserved_at_8[0x18]; 8218 8219 u8 syndrome[0x20]; 8220 8221 u8 reserved_at_40[0x8]; 8222 u8 xrqn[0x18]; 8223 8224 u8 reserved_at_60[0x20]; 8225 }; 8226 8227 struct mlx5_ifc_create_xrq_in_bits { 8228 u8 opcode[0x10]; 8229 u8 uid[0x10]; 8230 8231 u8 reserved_at_20[0x10]; 8232 u8 op_mod[0x10]; 8233 8234 u8 reserved_at_40[0x40]; 8235 8236 struct mlx5_ifc_xrqc_bits xrq_context; 8237 }; 8238 8239 struct mlx5_ifc_create_xrc_srq_out_bits { 8240 u8 status[0x8]; 8241 u8 reserved_at_8[0x18]; 8242 8243 u8 syndrome[0x20]; 8244 8245 u8 reserved_at_40[0x8]; 8246 u8 xrc_srqn[0x18]; 8247 8248 u8 reserved_at_60[0x20]; 8249 }; 8250 8251 struct mlx5_ifc_create_xrc_srq_in_bits { 8252 u8 opcode[0x10]; 8253 u8 uid[0x10]; 8254 8255 u8 reserved_at_20[0x10]; 8256 u8 op_mod[0x10]; 8257 8258 u8 reserved_at_40[0x40]; 8259 8260 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; 8261 8262 u8 reserved_at_280[0x60]; 8263 8264 u8 xrc_srq_umem_valid[0x1]; 8265 u8 reserved_at_2e1[0x1f]; 8266 8267 u8 reserved_at_300[0x580]; 8268 8269 u8 pas[][0x40]; 8270 }; 8271 8272 struct mlx5_ifc_create_tis_out_bits { 8273 u8 status[0x8]; 8274 u8 reserved_at_8[0x18]; 8275 8276 u8 syndrome[0x20]; 8277 8278 u8 reserved_at_40[0x8]; 8279 u8 tisn[0x18]; 8280 8281 u8 reserved_at_60[0x20]; 8282 }; 8283 8284 struct mlx5_ifc_create_tis_in_bits { 8285 u8 opcode[0x10]; 8286 u8 uid[0x10]; 8287 8288 u8 reserved_at_20[0x10]; 8289 u8 op_mod[0x10]; 8290 8291 u8 reserved_at_40[0xc0]; 8292 8293 struct mlx5_ifc_tisc_bits ctx; 8294 }; 8295 8296 struct mlx5_ifc_create_tir_out_bits { 8297 u8 status[0x8]; 8298 u8 icm_address_63_40[0x18]; 8299 8300 u8 syndrome[0x20]; 8301 8302 u8 icm_address_39_32[0x8]; 8303 u8 tirn[0x18]; 8304 8305 u8 icm_address_31_0[0x20]; 8306 }; 8307 8308 struct mlx5_ifc_create_tir_in_bits { 8309 u8 opcode[0x10]; 8310 u8 uid[0x10]; 8311 8312 u8 reserved_at_20[0x10]; 8313 u8 op_mod[0x10]; 8314 8315 u8 reserved_at_40[0xc0]; 8316 8317 struct mlx5_ifc_tirc_bits ctx; 8318 }; 8319 8320 struct mlx5_ifc_create_srq_out_bits { 8321 u8 status[0x8]; 8322 u8 reserved_at_8[0x18]; 8323 8324 u8 syndrome[0x20]; 8325 8326 u8 reserved_at_40[0x8]; 8327 u8 srqn[0x18]; 8328 8329 u8 reserved_at_60[0x20]; 8330 }; 8331 8332 struct mlx5_ifc_create_srq_in_bits { 8333 u8 opcode[0x10]; 8334 u8 uid[0x10]; 8335 8336 u8 reserved_at_20[0x10]; 8337 u8 op_mod[0x10]; 8338 8339 u8 reserved_at_40[0x40]; 8340 8341 struct mlx5_ifc_srqc_bits srq_context_entry; 8342 8343 u8 reserved_at_280[0x600]; 8344 8345 u8 pas[][0x40]; 8346 }; 8347 8348 struct mlx5_ifc_create_sq_out_bits { 8349 u8 status[0x8]; 8350 u8 reserved_at_8[0x18]; 8351 8352 u8 syndrome[0x20]; 8353 8354 u8 reserved_at_40[0x8]; 8355 u8 sqn[0x18]; 8356 8357 u8 reserved_at_60[0x20]; 8358 }; 8359 8360 struct mlx5_ifc_create_sq_in_bits { 8361 u8 opcode[0x10]; 8362 u8 uid[0x10]; 8363 8364 u8 reserved_at_20[0x10]; 8365 u8 op_mod[0x10]; 8366 8367 u8 reserved_at_40[0xc0]; 8368 8369 struct mlx5_ifc_sqc_bits ctx; 8370 }; 8371 8372 struct mlx5_ifc_create_scheduling_element_out_bits { 8373 u8 status[0x8]; 8374 u8 reserved_at_8[0x18]; 8375 8376 u8 syndrome[0x20]; 8377 8378 u8 reserved_at_40[0x40]; 8379 8380 u8 scheduling_element_id[0x20]; 8381 8382 u8 reserved_at_a0[0x160]; 8383 }; 8384 8385 struct mlx5_ifc_create_scheduling_element_in_bits { 8386 u8 opcode[0x10]; 8387 u8 reserved_at_10[0x10]; 8388 8389 u8 reserved_at_20[0x10]; 8390 u8 op_mod[0x10]; 8391 8392 u8 scheduling_hierarchy[0x8]; 8393 u8 reserved_at_48[0x18]; 8394 8395 u8 reserved_at_60[0xa0]; 8396 8397 struct mlx5_ifc_scheduling_context_bits scheduling_context; 8398 8399 u8 reserved_at_300[0x100]; 8400 }; 8401 8402 struct mlx5_ifc_create_rqt_out_bits { 8403 u8 status[0x8]; 8404 u8 reserved_at_8[0x18]; 8405 8406 u8 syndrome[0x20]; 8407 8408 u8 reserved_at_40[0x8]; 8409 u8 rqtn[0x18]; 8410 8411 u8 reserved_at_60[0x20]; 8412 }; 8413 8414 struct mlx5_ifc_create_rqt_in_bits { 8415 u8 opcode[0x10]; 8416 u8 uid[0x10]; 8417 8418 u8 reserved_at_20[0x10]; 8419 u8 op_mod[0x10]; 8420 8421 u8 reserved_at_40[0xc0]; 8422 8423 struct mlx5_ifc_rqtc_bits rqt_context; 8424 }; 8425 8426 struct mlx5_ifc_create_rq_out_bits { 8427 u8 status[0x8]; 8428 u8 reserved_at_8[0x18]; 8429 8430 u8 syndrome[0x20]; 8431 8432 u8 reserved_at_40[0x8]; 8433 u8 rqn[0x18]; 8434 8435 u8 reserved_at_60[0x20]; 8436 }; 8437 8438 struct mlx5_ifc_create_rq_in_bits { 8439 u8 opcode[0x10]; 8440 u8 uid[0x10]; 8441 8442 u8 reserved_at_20[0x10]; 8443 u8 op_mod[0x10]; 8444 8445 u8 reserved_at_40[0xc0]; 8446 8447 struct mlx5_ifc_rqc_bits ctx; 8448 }; 8449 8450 struct mlx5_ifc_create_rmp_out_bits { 8451 u8 status[0x8]; 8452 u8 reserved_at_8[0x18]; 8453 8454 u8 syndrome[0x20]; 8455 8456 u8 reserved_at_40[0x8]; 8457 u8 rmpn[0x18]; 8458 8459 u8 reserved_at_60[0x20]; 8460 }; 8461 8462 struct mlx5_ifc_create_rmp_in_bits { 8463 u8 opcode[0x10]; 8464 u8 uid[0x10]; 8465 8466 u8 reserved_at_20[0x10]; 8467 u8 op_mod[0x10]; 8468 8469 u8 reserved_at_40[0xc0]; 8470 8471 struct mlx5_ifc_rmpc_bits ctx; 8472 }; 8473 8474 struct mlx5_ifc_create_qp_out_bits { 8475 u8 status[0x8]; 8476 u8 reserved_at_8[0x18]; 8477 8478 u8 syndrome[0x20]; 8479 8480 u8 reserved_at_40[0x8]; 8481 u8 qpn[0x18]; 8482 8483 u8 ece[0x20]; 8484 }; 8485 8486 struct mlx5_ifc_create_qp_in_bits { 8487 u8 opcode[0x10]; 8488 u8 uid[0x10]; 8489 8490 u8 reserved_at_20[0x10]; 8491 u8 op_mod[0x10]; 8492 8493 u8 reserved_at_40[0x8]; 8494 u8 input_qpn[0x18]; 8495 8496 u8 reserved_at_60[0x20]; 8497 u8 opt_param_mask[0x20]; 8498 8499 u8 ece[0x20]; 8500 8501 struct mlx5_ifc_qpc_bits qpc; 8502 8503 u8 reserved_at_800[0x60]; 8504 8505 u8 wq_umem_valid[0x1]; 8506 u8 reserved_at_861[0x1f]; 8507 8508 u8 pas[][0x40]; 8509 }; 8510 8511 struct mlx5_ifc_create_psv_out_bits { 8512 u8 status[0x8]; 8513 u8 reserved_at_8[0x18]; 8514 8515 u8 syndrome[0x20]; 8516 8517 u8 reserved_at_40[0x40]; 8518 8519 u8 reserved_at_80[0x8]; 8520 u8 psv0_index[0x18]; 8521 8522 u8 reserved_at_a0[0x8]; 8523 u8 psv1_index[0x18]; 8524 8525 u8 reserved_at_c0[0x8]; 8526 u8 psv2_index[0x18]; 8527 8528 u8 reserved_at_e0[0x8]; 8529 u8 psv3_index[0x18]; 8530 }; 8531 8532 struct mlx5_ifc_create_psv_in_bits { 8533 u8 opcode[0x10]; 8534 u8 reserved_at_10[0x10]; 8535 8536 u8 reserved_at_20[0x10]; 8537 u8 op_mod[0x10]; 8538 8539 u8 num_psv[0x4]; 8540 u8 reserved_at_44[0x4]; 8541 u8 pd[0x18]; 8542 8543 u8 reserved_at_60[0x20]; 8544 }; 8545 8546 struct mlx5_ifc_create_mkey_out_bits { 8547 u8 status[0x8]; 8548 u8 reserved_at_8[0x18]; 8549 8550 u8 syndrome[0x20]; 8551 8552 u8 reserved_at_40[0x8]; 8553 u8 mkey_index[0x18]; 8554 8555 u8 reserved_at_60[0x20]; 8556 }; 8557 8558 struct mlx5_ifc_create_mkey_in_bits { 8559 u8 opcode[0x10]; 8560 u8 uid[0x10]; 8561 8562 u8 reserved_at_20[0x10]; 8563 u8 op_mod[0x10]; 8564 8565 u8 reserved_at_40[0x20]; 8566 8567 u8 pg_access[0x1]; 8568 u8 mkey_umem_valid[0x1]; 8569 u8 reserved_at_62[0x1e]; 8570 8571 struct mlx5_ifc_mkc_bits memory_key_mkey_entry; 8572 8573 u8 reserved_at_280[0x80]; 8574 8575 u8 translations_octword_actual_size[0x20]; 8576 8577 u8 reserved_at_320[0x560]; 8578 8579 u8 klm_pas_mtt[][0x20]; 8580 }; 8581 8582 enum { 8583 MLX5_FLOW_TABLE_TYPE_NIC_RX = 0x0, 8584 MLX5_FLOW_TABLE_TYPE_NIC_TX = 0x1, 8585 MLX5_FLOW_TABLE_TYPE_ESW_EGRESS_ACL = 0x2, 8586 MLX5_FLOW_TABLE_TYPE_ESW_INGRESS_ACL = 0x3, 8587 MLX5_FLOW_TABLE_TYPE_FDB = 0X4, 8588 MLX5_FLOW_TABLE_TYPE_SNIFFER_RX = 0X5, 8589 MLX5_FLOW_TABLE_TYPE_SNIFFER_TX = 0X6, 8590 }; 8591 8592 struct mlx5_ifc_create_flow_table_out_bits { 8593 u8 status[0x8]; 8594 u8 icm_address_63_40[0x18]; 8595 8596 u8 syndrome[0x20]; 8597 8598 u8 icm_address_39_32[0x8]; 8599 u8 table_id[0x18]; 8600 8601 u8 icm_address_31_0[0x20]; 8602 }; 8603 8604 struct mlx5_ifc_create_flow_table_in_bits { 8605 u8 opcode[0x10]; 8606 u8 uid[0x10]; 8607 8608 u8 reserved_at_20[0x10]; 8609 u8 op_mod[0x10]; 8610 8611 u8 other_vport[0x1]; 8612 u8 reserved_at_41[0xf]; 8613 u8 vport_number[0x10]; 8614 8615 u8 reserved_at_60[0x20]; 8616 8617 u8 table_type[0x8]; 8618 u8 reserved_at_88[0x18]; 8619 8620 u8 reserved_at_a0[0x20]; 8621 8622 struct mlx5_ifc_flow_table_context_bits flow_table_context; 8623 }; 8624 8625 struct mlx5_ifc_create_flow_group_out_bits { 8626 u8 status[0x8]; 8627 u8 reserved_at_8[0x18]; 8628 8629 u8 syndrome[0x20]; 8630 8631 u8 reserved_at_40[0x8]; 8632 u8 group_id[0x18]; 8633 8634 u8 reserved_at_60[0x20]; 8635 }; 8636 8637 enum { 8638 MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_TCAM_SUBTABLE = 0x0, 8639 MLX5_CREATE_FLOW_GROUP_IN_GROUP_TYPE_HASH_SPLIT = 0x1, 8640 }; 8641 8642 enum { 8643 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, 8644 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, 8645 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, 8646 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS_2 = 0x3, 8647 }; 8648 8649 struct mlx5_ifc_create_flow_group_in_bits { 8650 u8 opcode[0x10]; 8651 u8 reserved_at_10[0x10]; 8652 8653 u8 reserved_at_20[0x10]; 8654 u8 op_mod[0x10]; 8655 8656 u8 other_vport[0x1]; 8657 u8 reserved_at_41[0xf]; 8658 u8 vport_number[0x10]; 8659 8660 u8 reserved_at_60[0x20]; 8661 8662 u8 table_type[0x8]; 8663 u8 reserved_at_88[0x4]; 8664 u8 group_type[0x4]; 8665 u8 reserved_at_90[0x10]; 8666 8667 u8 reserved_at_a0[0x8]; 8668 u8 table_id[0x18]; 8669 8670 u8 source_eswitch_owner_vhca_id_valid[0x1]; 8671 8672 u8 reserved_at_c1[0x1f]; 8673 8674 u8 start_flow_index[0x20]; 8675 8676 u8 reserved_at_100[0x20]; 8677 8678 u8 end_flow_index[0x20]; 8679 8680 u8 reserved_at_140[0x10]; 8681 u8 match_definer_id[0x10]; 8682 8683 u8 reserved_at_160[0x80]; 8684 8685 u8 reserved_at_1e0[0x18]; 8686 u8 match_criteria_enable[0x8]; 8687 8688 struct mlx5_ifc_fte_match_param_bits match_criteria; 8689 8690 u8 reserved_at_1200[0xe00]; 8691 }; 8692 8693 struct mlx5_ifc_create_eq_out_bits { 8694 u8 status[0x8]; 8695 u8 reserved_at_8[0x18]; 8696 8697 u8 syndrome[0x20]; 8698 8699 u8 reserved_at_40[0x18]; 8700 u8 eq_number[0x8]; 8701 8702 u8 reserved_at_60[0x20]; 8703 }; 8704 8705 struct mlx5_ifc_create_eq_in_bits { 8706 u8 opcode[0x10]; 8707 u8 uid[0x10]; 8708 8709 u8 reserved_at_20[0x10]; 8710 u8 op_mod[0x10]; 8711 8712 u8 reserved_at_40[0x40]; 8713 8714 struct mlx5_ifc_eqc_bits eq_context_entry; 8715 8716 u8 reserved_at_280[0x40]; 8717 8718 u8 event_bitmask[4][0x40]; 8719 8720 u8 reserved_at_3c0[0x4c0]; 8721 8722 u8 pas[][0x40]; 8723 }; 8724 8725 struct mlx5_ifc_create_dct_out_bits { 8726 u8 status[0x8]; 8727 u8 reserved_at_8[0x18]; 8728 8729 u8 syndrome[0x20]; 8730 8731 u8 reserved_at_40[0x8]; 8732 u8 dctn[0x18]; 8733 8734 u8 ece[0x20]; 8735 }; 8736 8737 struct mlx5_ifc_create_dct_in_bits { 8738 u8 opcode[0x10]; 8739 u8 uid[0x10]; 8740 8741 u8 reserved_at_20[0x10]; 8742 u8 op_mod[0x10]; 8743 8744 u8 reserved_at_40[0x40]; 8745 8746 struct mlx5_ifc_dctc_bits dct_context_entry; 8747 8748 u8 reserved_at_280[0x180]; 8749 }; 8750 8751 struct mlx5_ifc_create_cq_out_bits { 8752 u8 status[0x8]; 8753 u8 reserved_at_8[0x18]; 8754 8755 u8 syndrome[0x20]; 8756 8757 u8 reserved_at_40[0x8]; 8758 u8 cqn[0x18]; 8759 8760 u8 reserved_at_60[0x20]; 8761 }; 8762 8763 struct mlx5_ifc_create_cq_in_bits { 8764 u8 opcode[0x10]; 8765 u8 uid[0x10]; 8766 8767 u8 reserved_at_20[0x10]; 8768 u8 op_mod[0x10]; 8769 8770 u8 reserved_at_40[0x40]; 8771 8772 struct mlx5_ifc_cqc_bits cq_context; 8773 8774 u8 reserved_at_280[0x60]; 8775 8776 u8 cq_umem_valid[0x1]; 8777 u8 reserved_at_2e1[0x59f]; 8778 8779 u8 pas[][0x40]; 8780 }; 8781 8782 struct mlx5_ifc_config_int_moderation_out_bits { 8783 u8 status[0x8]; 8784 u8 reserved_at_8[0x18]; 8785 8786 u8 syndrome[0x20]; 8787 8788 u8 reserved_at_40[0x4]; 8789 u8 min_delay[0xc]; 8790 u8 int_vector[0x10]; 8791 8792 u8 reserved_at_60[0x20]; 8793 }; 8794 8795 enum { 8796 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0, 8797 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1, 8798 }; 8799 8800 struct mlx5_ifc_config_int_moderation_in_bits { 8801 u8 opcode[0x10]; 8802 u8 reserved_at_10[0x10]; 8803 8804 u8 reserved_at_20[0x10]; 8805 u8 op_mod[0x10]; 8806 8807 u8 reserved_at_40[0x4]; 8808 u8 min_delay[0xc]; 8809 u8 int_vector[0x10]; 8810 8811 u8 reserved_at_60[0x20]; 8812 }; 8813 8814 struct mlx5_ifc_attach_to_mcg_out_bits { 8815 u8 status[0x8]; 8816 u8 reserved_at_8[0x18]; 8817 8818 u8 syndrome[0x20]; 8819 8820 u8 reserved_at_40[0x40]; 8821 }; 8822 8823 struct mlx5_ifc_attach_to_mcg_in_bits { 8824 u8 opcode[0x10]; 8825 u8 uid[0x10]; 8826 8827 u8 reserved_at_20[0x10]; 8828 u8 op_mod[0x10]; 8829 8830 u8 reserved_at_40[0x8]; 8831 u8 qpn[0x18]; 8832 8833 u8 reserved_at_60[0x20]; 8834 8835 u8 multicast_gid[16][0x8]; 8836 }; 8837 8838 struct mlx5_ifc_arm_xrq_out_bits { 8839 u8 status[0x8]; 8840 u8 reserved_at_8[0x18]; 8841 8842 u8 syndrome[0x20]; 8843 8844 u8 reserved_at_40[0x40]; 8845 }; 8846 8847 struct mlx5_ifc_arm_xrq_in_bits { 8848 u8 opcode[0x10]; 8849 u8 reserved_at_10[0x10]; 8850 8851 u8 reserved_at_20[0x10]; 8852 u8 op_mod[0x10]; 8853 8854 u8 reserved_at_40[0x8]; 8855 u8 xrqn[0x18]; 8856 8857 u8 reserved_at_60[0x10]; 8858 u8 lwm[0x10]; 8859 }; 8860 8861 struct mlx5_ifc_arm_xrc_srq_out_bits { 8862 u8 status[0x8]; 8863 u8 reserved_at_8[0x18]; 8864 8865 u8 syndrome[0x20]; 8866 8867 u8 reserved_at_40[0x40]; 8868 }; 8869 8870 enum { 8871 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1, 8872 }; 8873 8874 struct mlx5_ifc_arm_xrc_srq_in_bits { 8875 u8 opcode[0x10]; 8876 u8 uid[0x10]; 8877 8878 u8 reserved_at_20[0x10]; 8879 u8 op_mod[0x10]; 8880 8881 u8 reserved_at_40[0x8]; 8882 u8 xrc_srqn[0x18]; 8883 8884 u8 reserved_at_60[0x10]; 8885 u8 lwm[0x10]; 8886 }; 8887 8888 struct mlx5_ifc_arm_rq_out_bits { 8889 u8 status[0x8]; 8890 u8 reserved_at_8[0x18]; 8891 8892 u8 syndrome[0x20]; 8893 8894 u8 reserved_at_40[0x40]; 8895 }; 8896 8897 enum { 8898 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1, 8899 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2, 8900 }; 8901 8902 struct mlx5_ifc_arm_rq_in_bits { 8903 u8 opcode[0x10]; 8904 u8 uid[0x10]; 8905 8906 u8 reserved_at_20[0x10]; 8907 u8 op_mod[0x10]; 8908 8909 u8 reserved_at_40[0x8]; 8910 u8 srq_number[0x18]; 8911 8912 u8 reserved_at_60[0x10]; 8913 u8 lwm[0x10]; 8914 }; 8915 8916 struct mlx5_ifc_arm_dct_out_bits { 8917 u8 status[0x8]; 8918 u8 reserved_at_8[0x18]; 8919 8920 u8 syndrome[0x20]; 8921 8922 u8 reserved_at_40[0x40]; 8923 }; 8924 8925 struct mlx5_ifc_arm_dct_in_bits { 8926 u8 opcode[0x10]; 8927 u8 reserved_at_10[0x10]; 8928 8929 u8 reserved_at_20[0x10]; 8930 u8 op_mod[0x10]; 8931 8932 u8 reserved_at_40[0x8]; 8933 u8 dct_number[0x18]; 8934 8935 u8 reserved_at_60[0x20]; 8936 }; 8937 8938 struct mlx5_ifc_alloc_xrcd_out_bits { 8939 u8 status[0x8]; 8940 u8 reserved_at_8[0x18]; 8941 8942 u8 syndrome[0x20]; 8943 8944 u8 reserved_at_40[0x8]; 8945 u8 xrcd[0x18]; 8946 8947 u8 reserved_at_60[0x20]; 8948 }; 8949 8950 struct mlx5_ifc_alloc_xrcd_in_bits { 8951 u8 opcode[0x10]; 8952 u8 uid[0x10]; 8953 8954 u8 reserved_at_20[0x10]; 8955 u8 op_mod[0x10]; 8956 8957 u8 reserved_at_40[0x40]; 8958 }; 8959 8960 struct mlx5_ifc_alloc_uar_out_bits { 8961 u8 status[0x8]; 8962 u8 reserved_at_8[0x18]; 8963 8964 u8 syndrome[0x20]; 8965 8966 u8 reserved_at_40[0x8]; 8967 u8 uar[0x18]; 8968 8969 u8 reserved_at_60[0x20]; 8970 }; 8971 8972 struct mlx5_ifc_alloc_uar_in_bits { 8973 u8 opcode[0x10]; 8974 u8 uid[0x10]; 8975 8976 u8 reserved_at_20[0x10]; 8977 u8 op_mod[0x10]; 8978 8979 u8 reserved_at_40[0x40]; 8980 }; 8981 8982 struct mlx5_ifc_alloc_transport_domain_out_bits { 8983 u8 status[0x8]; 8984 u8 reserved_at_8[0x18]; 8985 8986 u8 syndrome[0x20]; 8987 8988 u8 reserved_at_40[0x8]; 8989 u8 transport_domain[0x18]; 8990 8991 u8 reserved_at_60[0x20]; 8992 }; 8993 8994 struct mlx5_ifc_alloc_transport_domain_in_bits { 8995 u8 opcode[0x10]; 8996 u8 uid[0x10]; 8997 8998 u8 reserved_at_20[0x10]; 8999 u8 op_mod[0x10]; 9000 9001 u8 reserved_at_40[0x40]; 9002 }; 9003 9004 struct mlx5_ifc_alloc_q_counter_out_bits { 9005 u8 status[0x8]; 9006 u8 reserved_at_8[0x18]; 9007 9008 u8 syndrome[0x20]; 9009 9010 u8 reserved_at_40[0x18]; 9011 u8 counter_set_id[0x8]; 9012 9013 u8 reserved_at_60[0x20]; 9014 }; 9015 9016 struct mlx5_ifc_alloc_q_counter_in_bits { 9017 u8 opcode[0x10]; 9018 u8 uid[0x10]; 9019 9020 u8 reserved_at_20[0x10]; 9021 u8 op_mod[0x10]; 9022 9023 u8 reserved_at_40[0x40]; 9024 }; 9025 9026 struct mlx5_ifc_alloc_pd_out_bits { 9027 u8 status[0x8]; 9028 u8 reserved_at_8[0x18]; 9029 9030 u8 syndrome[0x20]; 9031 9032 u8 reserved_at_40[0x8]; 9033 u8 pd[0x18]; 9034 9035 u8 reserved_at_60[0x20]; 9036 }; 9037 9038 struct mlx5_ifc_alloc_pd_in_bits { 9039 u8 opcode[0x10]; 9040 u8 uid[0x10]; 9041 9042 u8 reserved_at_20[0x10]; 9043 u8 op_mod[0x10]; 9044 9045 u8 reserved_at_40[0x40]; 9046 }; 9047 9048 struct mlx5_ifc_alloc_flow_counter_out_bits { 9049 u8 status[0x8]; 9050 u8 reserved_at_8[0x18]; 9051 9052 u8 syndrome[0x20]; 9053 9054 u8 flow_counter_id[0x20]; 9055 9056 u8 reserved_at_60[0x20]; 9057 }; 9058 9059 struct mlx5_ifc_alloc_flow_counter_in_bits { 9060 u8 opcode[0x10]; 9061 u8 reserved_at_10[0x10]; 9062 9063 u8 reserved_at_20[0x10]; 9064 u8 op_mod[0x10]; 9065 9066 u8 reserved_at_40[0x38]; 9067 u8 flow_counter_bulk[0x8]; 9068 }; 9069 9070 struct mlx5_ifc_add_vxlan_udp_dport_out_bits { 9071 u8 status[0x8]; 9072 u8 reserved_at_8[0x18]; 9073 9074 u8 syndrome[0x20]; 9075 9076 u8 reserved_at_40[0x40]; 9077 }; 9078 9079 struct mlx5_ifc_add_vxlan_udp_dport_in_bits { 9080 u8 opcode[0x10]; 9081 u8 reserved_at_10[0x10]; 9082 9083 u8 reserved_at_20[0x10]; 9084 u8 op_mod[0x10]; 9085 9086 u8 reserved_at_40[0x20]; 9087 9088 u8 reserved_at_60[0x10]; 9089 u8 vxlan_udp_port[0x10]; 9090 }; 9091 9092 struct mlx5_ifc_set_pp_rate_limit_out_bits { 9093 u8 status[0x8]; 9094 u8 reserved_at_8[0x18]; 9095 9096 u8 syndrome[0x20]; 9097 9098 u8 reserved_at_40[0x40]; 9099 }; 9100 9101 struct mlx5_ifc_set_pp_rate_limit_context_bits { 9102 u8 rate_limit[0x20]; 9103 9104 u8 burst_upper_bound[0x20]; 9105 9106 u8 reserved_at_40[0x10]; 9107 u8 typical_packet_size[0x10]; 9108 9109 u8 reserved_at_60[0x120]; 9110 }; 9111 9112 struct mlx5_ifc_set_pp_rate_limit_in_bits { 9113 u8 opcode[0x10]; 9114 u8 uid[0x10]; 9115 9116 u8 reserved_at_20[0x10]; 9117 u8 op_mod[0x10]; 9118 9119 u8 reserved_at_40[0x10]; 9120 u8 rate_limit_index[0x10]; 9121 9122 u8 reserved_at_60[0x20]; 9123 9124 struct mlx5_ifc_set_pp_rate_limit_context_bits ctx; 9125 }; 9126 9127 struct mlx5_ifc_access_register_out_bits { 9128 u8 status[0x8]; 9129 u8 reserved_at_8[0x18]; 9130 9131 u8 syndrome[0x20]; 9132 9133 u8 reserved_at_40[0x40]; 9134 9135 u8 register_data[][0x20]; 9136 }; 9137 9138 enum { 9139 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0, 9140 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1, 9141 }; 9142 9143 struct mlx5_ifc_access_register_in_bits { 9144 u8 opcode[0x10]; 9145 u8 reserved_at_10[0x10]; 9146 9147 u8 reserved_at_20[0x10]; 9148 u8 op_mod[0x10]; 9149 9150 u8 reserved_at_40[0x10]; 9151 u8 register_id[0x10]; 9152 9153 u8 argument[0x20]; 9154 9155 u8 register_data[][0x20]; 9156 }; 9157 9158 struct mlx5_ifc_sltp_reg_bits { 9159 u8 status[0x4]; 9160 u8 version[0x4]; 9161 u8 local_port[0x8]; 9162 u8 pnat[0x2]; 9163 u8 reserved_at_12[0x2]; 9164 u8 lane[0x4]; 9165 u8 reserved_at_18[0x8]; 9166 9167 u8 reserved_at_20[0x20]; 9168 9169 u8 reserved_at_40[0x7]; 9170 u8 polarity[0x1]; 9171 u8 ob_tap0[0x8]; 9172 u8 ob_tap1[0x8]; 9173 u8 ob_tap2[0x8]; 9174 9175 u8 reserved_at_60[0xc]; 9176 u8 ob_preemp_mode[0x4]; 9177 u8 ob_reg[0x8]; 9178 u8 ob_bias[0x8]; 9179 9180 u8 reserved_at_80[0x20]; 9181 }; 9182 9183 struct mlx5_ifc_slrg_reg_bits { 9184 u8 status[0x4]; 9185 u8 version[0x4]; 9186 u8 local_port[0x8]; 9187 u8 pnat[0x2]; 9188 u8 reserved_at_12[0x2]; 9189 u8 lane[0x4]; 9190 u8 reserved_at_18[0x8]; 9191 9192 u8 time_to_link_up[0x10]; 9193 u8 reserved_at_30[0xc]; 9194 u8 grade_lane_speed[0x4]; 9195 9196 u8 grade_version[0x8]; 9197 u8 grade[0x18]; 9198 9199 u8 reserved_at_60[0x4]; 9200 u8 height_grade_type[0x4]; 9201 u8 height_grade[0x18]; 9202 9203 u8 height_dz[0x10]; 9204 u8 height_dv[0x10]; 9205 9206 u8 reserved_at_a0[0x10]; 9207 u8 height_sigma[0x10]; 9208 9209 u8 reserved_at_c0[0x20]; 9210 9211 u8 reserved_at_e0[0x4]; 9212 u8 phase_grade_type[0x4]; 9213 u8 phase_grade[0x18]; 9214 9215 u8 reserved_at_100[0x8]; 9216 u8 phase_eo_pos[0x8]; 9217 u8 reserved_at_110[0x8]; 9218 u8 phase_eo_neg[0x8]; 9219 9220 u8 ffe_set_tested[0x10]; 9221 u8 test_errors_per_lane[0x10]; 9222 }; 9223 9224 struct mlx5_ifc_pvlc_reg_bits { 9225 u8 reserved_at_0[0x8]; 9226 u8 local_port[0x8]; 9227 u8 reserved_at_10[0x10]; 9228 9229 u8 reserved_at_20[0x1c]; 9230 u8 vl_hw_cap[0x4]; 9231 9232 u8 reserved_at_40[0x1c]; 9233 u8 vl_admin[0x4]; 9234 9235 u8 reserved_at_60[0x1c]; 9236 u8 vl_operational[0x4]; 9237 }; 9238 9239 struct mlx5_ifc_pude_reg_bits { 9240 u8 swid[0x8]; 9241 u8 local_port[0x8]; 9242 u8 reserved_at_10[0x4]; 9243 u8 admin_status[0x4]; 9244 u8 reserved_at_18[0x4]; 9245 u8 oper_status[0x4]; 9246 9247 u8 reserved_at_20[0x60]; 9248 }; 9249 9250 struct mlx5_ifc_ptys_reg_bits { 9251 u8 reserved_at_0[0x1]; 9252 u8 an_disable_admin[0x1]; 9253 u8 an_disable_cap[0x1]; 9254 u8 reserved_at_3[0x5]; 9255 u8 local_port[0x8]; 9256 u8 reserved_at_10[0xd]; 9257 u8 proto_mask[0x3]; 9258 9259 u8 an_status[0x4]; 9260 u8 reserved_at_24[0xc]; 9261 u8 data_rate_oper[0x10]; 9262 9263 u8 ext_eth_proto_capability[0x20]; 9264 9265 u8 eth_proto_capability[0x20]; 9266 9267 u8 ib_link_width_capability[0x10]; 9268 u8 ib_proto_capability[0x10]; 9269 9270 u8 ext_eth_proto_admin[0x20]; 9271 9272 u8 eth_proto_admin[0x20]; 9273 9274 u8 ib_link_width_admin[0x10]; 9275 u8 ib_proto_admin[0x10]; 9276 9277 u8 ext_eth_proto_oper[0x20]; 9278 9279 u8 eth_proto_oper[0x20]; 9280 9281 u8 ib_link_width_oper[0x10]; 9282 u8 ib_proto_oper[0x10]; 9283 9284 u8 reserved_at_160[0x1c]; 9285 u8 connector_type[0x4]; 9286 9287 u8 eth_proto_lp_advertise[0x20]; 9288 9289 u8 reserved_at_1a0[0x60]; 9290 }; 9291 9292 struct mlx5_ifc_mlcr_reg_bits { 9293 u8 reserved_at_0[0x8]; 9294 u8 local_port[0x8]; 9295 u8 reserved_at_10[0x20]; 9296 9297 u8 beacon_duration[0x10]; 9298 u8 reserved_at_40[0x10]; 9299 9300 u8 beacon_remain[0x10]; 9301 }; 9302 9303 struct mlx5_ifc_ptas_reg_bits { 9304 u8 reserved_at_0[0x20]; 9305 9306 u8 algorithm_options[0x10]; 9307 u8 reserved_at_30[0x4]; 9308 u8 repetitions_mode[0x4]; 9309 u8 num_of_repetitions[0x8]; 9310 9311 u8 grade_version[0x8]; 9312 u8 height_grade_type[0x4]; 9313 u8 phase_grade_type[0x4]; 9314 u8 height_grade_weight[0x8]; 9315 u8 phase_grade_weight[0x8]; 9316 9317 u8 gisim_measure_bits[0x10]; 9318 u8 adaptive_tap_measure_bits[0x10]; 9319 9320 u8 ber_bath_high_error_threshold[0x10]; 9321 u8 ber_bath_mid_error_threshold[0x10]; 9322 9323 u8 ber_bath_low_error_threshold[0x10]; 9324 u8 one_ratio_high_threshold[0x10]; 9325 9326 u8 one_ratio_high_mid_threshold[0x10]; 9327 u8 one_ratio_low_mid_threshold[0x10]; 9328 9329 u8 one_ratio_low_threshold[0x10]; 9330 u8 ndeo_error_threshold[0x10]; 9331 9332 u8 mixer_offset_step_size[0x10]; 9333 u8 reserved_at_110[0x8]; 9334 u8 mix90_phase_for_voltage_bath[0x8]; 9335 9336 u8 mixer_offset_start[0x10]; 9337 u8 mixer_offset_end[0x10]; 9338 9339 u8 reserved_at_140[0x15]; 9340 u8 ber_test_time[0xb]; 9341 }; 9342 9343 struct mlx5_ifc_pspa_reg_bits { 9344 u8 swid[0x8]; 9345 u8 local_port[0x8]; 9346 u8 sub_port[0x8]; 9347 u8 reserved_at_18[0x8]; 9348 9349 u8 reserved_at_20[0x20]; 9350 }; 9351 9352 struct mlx5_ifc_pqdr_reg_bits { 9353 u8 reserved_at_0[0x8]; 9354 u8 local_port[0x8]; 9355 u8 reserved_at_10[0x5]; 9356 u8 prio[0x3]; 9357 u8 reserved_at_18[0x6]; 9358 u8 mode[0x2]; 9359 9360 u8 reserved_at_20[0x20]; 9361 9362 u8 reserved_at_40[0x10]; 9363 u8 min_threshold[0x10]; 9364 9365 u8 reserved_at_60[0x10]; 9366 u8 max_threshold[0x10]; 9367 9368 u8 reserved_at_80[0x10]; 9369 u8 mark_probability_denominator[0x10]; 9370 9371 u8 reserved_at_a0[0x60]; 9372 }; 9373 9374 struct mlx5_ifc_ppsc_reg_bits { 9375 u8 reserved_at_0[0x8]; 9376 u8 local_port[0x8]; 9377 u8 reserved_at_10[0x10]; 9378 9379 u8 reserved_at_20[0x60]; 9380 9381 u8 reserved_at_80[0x1c]; 9382 u8 wrps_admin[0x4]; 9383 9384 u8 reserved_at_a0[0x1c]; 9385 u8 wrps_status[0x4]; 9386 9387 u8 reserved_at_c0[0x8]; 9388 u8 up_threshold[0x8]; 9389 u8 reserved_at_d0[0x8]; 9390 u8 down_threshold[0x8]; 9391 9392 u8 reserved_at_e0[0x20]; 9393 9394 u8 reserved_at_100[0x1c]; 9395 u8 srps_admin[0x4]; 9396 9397 u8 reserved_at_120[0x1c]; 9398 u8 srps_status[0x4]; 9399 9400 u8 reserved_at_140[0x40]; 9401 }; 9402 9403 struct mlx5_ifc_pplr_reg_bits { 9404 u8 reserved_at_0[0x8]; 9405 u8 local_port[0x8]; 9406 u8 reserved_at_10[0x10]; 9407 9408 u8 reserved_at_20[0x8]; 9409 u8 lb_cap[0x8]; 9410 u8 reserved_at_30[0x8]; 9411 u8 lb_en[0x8]; 9412 }; 9413 9414 struct mlx5_ifc_pplm_reg_bits { 9415 u8 reserved_at_0[0x8]; 9416 u8 local_port[0x8]; 9417 u8 reserved_at_10[0x10]; 9418 9419 u8 reserved_at_20[0x20]; 9420 9421 u8 port_profile_mode[0x8]; 9422 u8 static_port_profile[0x8]; 9423 u8 active_port_profile[0x8]; 9424 u8 reserved_at_58[0x8]; 9425 9426 u8 retransmission_active[0x8]; 9427 u8 fec_mode_active[0x18]; 9428 9429 u8 rs_fec_correction_bypass_cap[0x4]; 9430 u8 reserved_at_84[0x8]; 9431 u8 fec_override_cap_56g[0x4]; 9432 u8 fec_override_cap_100g[0x4]; 9433 u8 fec_override_cap_50g[0x4]; 9434 u8 fec_override_cap_25g[0x4]; 9435 u8 fec_override_cap_10g_40g[0x4]; 9436 9437 u8 rs_fec_correction_bypass_admin[0x4]; 9438 u8 reserved_at_a4[0x8]; 9439 u8 fec_override_admin_56g[0x4]; 9440 u8 fec_override_admin_100g[0x4]; 9441 u8 fec_override_admin_50g[0x4]; 9442 u8 fec_override_admin_25g[0x4]; 9443 u8 fec_override_admin_10g_40g[0x4]; 9444 9445 u8 fec_override_cap_400g_8x[0x10]; 9446 u8 fec_override_cap_200g_4x[0x10]; 9447 9448 u8 fec_override_cap_100g_2x[0x10]; 9449 u8 fec_override_cap_50g_1x[0x10]; 9450 9451 u8 fec_override_admin_400g_8x[0x10]; 9452 u8 fec_override_admin_200g_4x[0x10]; 9453 9454 u8 fec_override_admin_100g_2x[0x10]; 9455 u8 fec_override_admin_50g_1x[0x10]; 9456 9457 u8 reserved_at_140[0x140]; 9458 }; 9459 9460 struct mlx5_ifc_ppcnt_reg_bits { 9461 u8 swid[0x8]; 9462 u8 local_port[0x8]; 9463 u8 pnat[0x2]; 9464 u8 reserved_at_12[0x8]; 9465 u8 grp[0x6]; 9466 9467 u8 clr[0x1]; 9468 u8 reserved_at_21[0x1c]; 9469 u8 prio_tc[0x3]; 9470 9471 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set; 9472 }; 9473 9474 struct mlx5_ifc_mpein_reg_bits { 9475 u8 reserved_at_0[0x2]; 9476 u8 depth[0x6]; 9477 u8 pcie_index[0x8]; 9478 u8 node[0x8]; 9479 u8 reserved_at_18[0x8]; 9480 9481 u8 capability_mask[0x20]; 9482 9483 u8 reserved_at_40[0x8]; 9484 u8 link_width_enabled[0x8]; 9485 u8 link_speed_enabled[0x10]; 9486 9487 u8 lane0_physical_position[0x8]; 9488 u8 link_width_active[0x8]; 9489 u8 link_speed_active[0x10]; 9490 9491 u8 num_of_pfs[0x10]; 9492 u8 num_of_vfs[0x10]; 9493 9494 u8 bdf0[0x10]; 9495 u8 reserved_at_b0[0x10]; 9496 9497 u8 max_read_request_size[0x4]; 9498 u8 max_payload_size[0x4]; 9499 u8 reserved_at_c8[0x5]; 9500 u8 pwr_status[0x3]; 9501 u8 port_type[0x4]; 9502 u8 reserved_at_d4[0xb]; 9503 u8 lane_reversal[0x1]; 9504 9505 u8 reserved_at_e0[0x14]; 9506 u8 pci_power[0xc]; 9507 9508 u8 reserved_at_100[0x20]; 9509 9510 u8 device_status[0x10]; 9511 u8 port_state[0x8]; 9512 u8 reserved_at_138[0x8]; 9513 9514 u8 reserved_at_140[0x10]; 9515 u8 receiver_detect_result[0x10]; 9516 9517 u8 reserved_at_160[0x20]; 9518 }; 9519 9520 struct mlx5_ifc_mpcnt_reg_bits { 9521 u8 reserved_at_0[0x8]; 9522 u8 pcie_index[0x8]; 9523 u8 reserved_at_10[0xa]; 9524 u8 grp[0x6]; 9525 9526 u8 clr[0x1]; 9527 u8 reserved_at_21[0x1f]; 9528 9529 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set; 9530 }; 9531 9532 struct mlx5_ifc_ppad_reg_bits { 9533 u8 reserved_at_0[0x3]; 9534 u8 single_mac[0x1]; 9535 u8 reserved_at_4[0x4]; 9536 u8 local_port[0x8]; 9537 u8 mac_47_32[0x10]; 9538 9539 u8 mac_31_0[0x20]; 9540 9541 u8 reserved_at_40[0x40]; 9542 }; 9543 9544 struct mlx5_ifc_pmtu_reg_bits { 9545 u8 reserved_at_0[0x8]; 9546 u8 local_port[0x8]; 9547 u8 reserved_at_10[0x10]; 9548 9549 u8 max_mtu[0x10]; 9550 u8 reserved_at_30[0x10]; 9551 9552 u8 admin_mtu[0x10]; 9553 u8 reserved_at_50[0x10]; 9554 9555 u8 oper_mtu[0x10]; 9556 u8 reserved_at_70[0x10]; 9557 }; 9558 9559 struct mlx5_ifc_pmpr_reg_bits { 9560 u8 reserved_at_0[0x8]; 9561 u8 module[0x8]; 9562 u8 reserved_at_10[0x10]; 9563 9564 u8 reserved_at_20[0x18]; 9565 u8 attenuation_5g[0x8]; 9566 9567 u8 reserved_at_40[0x18]; 9568 u8 attenuation_7g[0x8]; 9569 9570 u8 reserved_at_60[0x18]; 9571 u8 attenuation_12g[0x8]; 9572 }; 9573 9574 struct mlx5_ifc_pmpe_reg_bits { 9575 u8 reserved_at_0[0x8]; 9576 u8 module[0x8]; 9577 u8 reserved_at_10[0xc]; 9578 u8 module_status[0x4]; 9579 9580 u8 reserved_at_20[0x60]; 9581 }; 9582 9583 struct mlx5_ifc_pmpc_reg_bits { 9584 u8 module_state_updated[32][0x8]; 9585 }; 9586 9587 struct mlx5_ifc_pmlpn_reg_bits { 9588 u8 reserved_at_0[0x4]; 9589 u8 mlpn_status[0x4]; 9590 u8 local_port[0x8]; 9591 u8 reserved_at_10[0x10]; 9592 9593 u8 e[0x1]; 9594 u8 reserved_at_21[0x1f]; 9595 }; 9596 9597 struct mlx5_ifc_pmlp_reg_bits { 9598 u8 rxtx[0x1]; 9599 u8 reserved_at_1[0x7]; 9600 u8 local_port[0x8]; 9601 u8 reserved_at_10[0x8]; 9602 u8 width[0x8]; 9603 9604 u8 lane0_module_mapping[0x20]; 9605 9606 u8 lane1_module_mapping[0x20]; 9607 9608 u8 lane2_module_mapping[0x20]; 9609 9610 u8 lane3_module_mapping[0x20]; 9611 9612 u8 reserved_at_a0[0x160]; 9613 }; 9614 9615 struct mlx5_ifc_pmaos_reg_bits { 9616 u8 reserved_at_0[0x8]; 9617 u8 module[0x8]; 9618 u8 reserved_at_10[0x4]; 9619 u8 admin_status[0x4]; 9620 u8 reserved_at_18[0x4]; 9621 u8 oper_status[0x4]; 9622 9623 u8 ase[0x1]; 9624 u8 ee[0x1]; 9625 u8 reserved_at_22[0x1c]; 9626 u8 e[0x2]; 9627 9628 u8 reserved_at_40[0x40]; 9629 }; 9630 9631 struct mlx5_ifc_plpc_reg_bits { 9632 u8 reserved_at_0[0x4]; 9633 u8 profile_id[0xc]; 9634 u8 reserved_at_10[0x4]; 9635 u8 proto_mask[0x4]; 9636 u8 reserved_at_18[0x8]; 9637 9638 u8 reserved_at_20[0x10]; 9639 u8 lane_speed[0x10]; 9640 9641 u8 reserved_at_40[0x17]; 9642 u8 lpbf[0x1]; 9643 u8 fec_mode_policy[0x8]; 9644 9645 u8 retransmission_capability[0x8]; 9646 u8 fec_mode_capability[0x18]; 9647 9648 u8 retransmission_support_admin[0x8]; 9649 u8 fec_mode_support_admin[0x18]; 9650 9651 u8 retransmission_request_admin[0x8]; 9652 u8 fec_mode_request_admin[0x18]; 9653 9654 u8 reserved_at_c0[0x80]; 9655 }; 9656 9657 struct mlx5_ifc_plib_reg_bits { 9658 u8 reserved_at_0[0x8]; 9659 u8 local_port[0x8]; 9660 u8 reserved_at_10[0x8]; 9661 u8 ib_port[0x8]; 9662 9663 u8 reserved_at_20[0x60]; 9664 }; 9665 9666 struct mlx5_ifc_plbf_reg_bits { 9667 u8 reserved_at_0[0x8]; 9668 u8 local_port[0x8]; 9669 u8 reserved_at_10[0xd]; 9670 u8 lbf_mode[0x3]; 9671 9672 u8 reserved_at_20[0x20]; 9673 }; 9674 9675 struct mlx5_ifc_pipg_reg_bits { 9676 u8 reserved_at_0[0x8]; 9677 u8 local_port[0x8]; 9678 u8 reserved_at_10[0x10]; 9679 9680 u8 dic[0x1]; 9681 u8 reserved_at_21[0x19]; 9682 u8 ipg[0x4]; 9683 u8 reserved_at_3e[0x2]; 9684 }; 9685 9686 struct mlx5_ifc_pifr_reg_bits { 9687 u8 reserved_at_0[0x8]; 9688 u8 local_port[0x8]; 9689 u8 reserved_at_10[0x10]; 9690 9691 u8 reserved_at_20[0xe0]; 9692 9693 u8 port_filter[8][0x20]; 9694 9695 u8 port_filter_update_en[8][0x20]; 9696 }; 9697 9698 struct mlx5_ifc_pfcc_reg_bits { 9699 u8 reserved_at_0[0x8]; 9700 u8 local_port[0x8]; 9701 u8 reserved_at_10[0xb]; 9702 u8 ppan_mask_n[0x1]; 9703 u8 minor_stall_mask[0x1]; 9704 u8 critical_stall_mask[0x1]; 9705 u8 reserved_at_1e[0x2]; 9706 9707 u8 ppan[0x4]; 9708 u8 reserved_at_24[0x4]; 9709 u8 prio_mask_tx[0x8]; 9710 u8 reserved_at_30[0x8]; 9711 u8 prio_mask_rx[0x8]; 9712 9713 u8 pptx[0x1]; 9714 u8 aptx[0x1]; 9715 u8 pptx_mask_n[0x1]; 9716 u8 reserved_at_43[0x5]; 9717 u8 pfctx[0x8]; 9718 u8 reserved_at_50[0x10]; 9719 9720 u8 pprx[0x1]; 9721 u8 aprx[0x1]; 9722 u8 pprx_mask_n[0x1]; 9723 u8 reserved_at_63[0x5]; 9724 u8 pfcrx[0x8]; 9725 u8 reserved_at_70[0x10]; 9726 9727 u8 device_stall_minor_watermark[0x10]; 9728 u8 device_stall_critical_watermark[0x10]; 9729 9730 u8 reserved_at_a0[0x60]; 9731 }; 9732 9733 struct mlx5_ifc_pelc_reg_bits { 9734 u8 op[0x4]; 9735 u8 reserved_at_4[0x4]; 9736 u8 local_port[0x8]; 9737 u8 reserved_at_10[0x10]; 9738 9739 u8 op_admin[0x8]; 9740 u8 op_capability[0x8]; 9741 u8 op_request[0x8]; 9742 u8 op_active[0x8]; 9743 9744 u8 admin[0x40]; 9745 9746 u8 capability[0x40]; 9747 9748 u8 request[0x40]; 9749 9750 u8 active[0x40]; 9751 9752 u8 reserved_at_140[0x80]; 9753 }; 9754 9755 struct mlx5_ifc_peir_reg_bits { 9756 u8 reserved_at_0[0x8]; 9757 u8 local_port[0x8]; 9758 u8 reserved_at_10[0x10]; 9759 9760 u8 reserved_at_20[0xc]; 9761 u8 error_count[0x4]; 9762 u8 reserved_at_30[0x10]; 9763 9764 u8 reserved_at_40[0xc]; 9765 u8 lane[0x4]; 9766 u8 reserved_at_50[0x8]; 9767 u8 error_type[0x8]; 9768 }; 9769 9770 struct mlx5_ifc_mpegc_reg_bits { 9771 u8 reserved_at_0[0x30]; 9772 u8 field_select[0x10]; 9773 9774 u8 tx_overflow_sense[0x1]; 9775 u8 mark_cqe[0x1]; 9776 u8 mark_cnp[0x1]; 9777 u8 reserved_at_43[0x1b]; 9778 u8 tx_lossy_overflow_oper[0x2]; 9779 9780 u8 reserved_at_60[0x100]; 9781 }; 9782 9783 enum { 9784 MLX5_MTUTC_OPERATION_SET_TIME_IMMEDIATE = 0x1, 9785 MLX5_MTUTC_OPERATION_ADJUST_TIME = 0x2, 9786 MLX5_MTUTC_OPERATION_ADJUST_FREQ_UTC = 0x3, 9787 }; 9788 9789 struct mlx5_ifc_mtutc_reg_bits { 9790 u8 reserved_at_0[0x1c]; 9791 u8 operation[0x4]; 9792 9793 u8 freq_adjustment[0x20]; 9794 9795 u8 reserved_at_40[0x40]; 9796 9797 u8 utc_sec[0x20]; 9798 9799 u8 reserved_at_a0[0x2]; 9800 u8 utc_nsec[0x1e]; 9801 9802 u8 time_adjustment[0x20]; 9803 }; 9804 9805 struct mlx5_ifc_pcam_enhanced_features_bits { 9806 u8 reserved_at_0[0x68]; 9807 u8 fec_50G_per_lane_in_pplm[0x1]; 9808 u8 reserved_at_69[0x4]; 9809 u8 rx_icrc_encapsulated_counter[0x1]; 9810 u8 reserved_at_6e[0x4]; 9811 u8 ptys_extended_ethernet[0x1]; 9812 u8 reserved_at_73[0x3]; 9813 u8 pfcc_mask[0x1]; 9814 u8 reserved_at_77[0x3]; 9815 u8 per_lane_error_counters[0x1]; 9816 u8 rx_buffer_fullness_counters[0x1]; 9817 u8 ptys_connector_type[0x1]; 9818 u8 reserved_at_7d[0x1]; 9819 u8 ppcnt_discard_group[0x1]; 9820 u8 ppcnt_statistical_group[0x1]; 9821 }; 9822 9823 struct mlx5_ifc_pcam_regs_5000_to_507f_bits { 9824 u8 port_access_reg_cap_mask_127_to_96[0x20]; 9825 u8 port_access_reg_cap_mask_95_to_64[0x20]; 9826 9827 u8 port_access_reg_cap_mask_63_to_36[0x1c]; 9828 u8 pplm[0x1]; 9829 u8 port_access_reg_cap_mask_34_to_32[0x3]; 9830 9831 u8 port_access_reg_cap_mask_31_to_13[0x13]; 9832 u8 pbmc[0x1]; 9833 u8 pptb[0x1]; 9834 u8 port_access_reg_cap_mask_10_to_09[0x2]; 9835 u8 ppcnt[0x1]; 9836 u8 port_access_reg_cap_mask_07_to_00[0x8]; 9837 }; 9838 9839 struct mlx5_ifc_pcam_reg_bits { 9840 u8 reserved_at_0[0x8]; 9841 u8 feature_group[0x8]; 9842 u8 reserved_at_10[0x8]; 9843 u8 access_reg_group[0x8]; 9844 9845 u8 reserved_at_20[0x20]; 9846 9847 union { 9848 struct mlx5_ifc_pcam_regs_5000_to_507f_bits regs_5000_to_507f; 9849 u8 reserved_at_0[0x80]; 9850 } port_access_reg_cap_mask; 9851 9852 u8 reserved_at_c0[0x80]; 9853 9854 union { 9855 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features; 9856 u8 reserved_at_0[0x80]; 9857 } feature_cap_mask; 9858 9859 u8 reserved_at_1c0[0xc0]; 9860 }; 9861 9862 struct mlx5_ifc_mcam_enhanced_features_bits { 9863 u8 reserved_at_0[0x5d]; 9864 u8 mcia_32dwords[0x1]; 9865 u8 out_pulse_duration_ns[0x1]; 9866 u8 npps_period[0x1]; 9867 u8 reserved_at_60[0xa]; 9868 u8 reset_state[0x1]; 9869 u8 ptpcyc2realtime_modify[0x1]; 9870 u8 reserved_at_6c[0x2]; 9871 u8 pci_status_and_power[0x1]; 9872 u8 reserved_at_6f[0x5]; 9873 u8 mark_tx_action_cnp[0x1]; 9874 u8 mark_tx_action_cqe[0x1]; 9875 u8 dynamic_tx_overflow[0x1]; 9876 u8 reserved_at_77[0x4]; 9877 u8 pcie_outbound_stalled[0x1]; 9878 u8 tx_overflow_buffer_pkt[0x1]; 9879 u8 mtpps_enh_out_per_adj[0x1]; 9880 u8 mtpps_fs[0x1]; 9881 u8 pcie_performance_group[0x1]; 9882 }; 9883 9884 struct mlx5_ifc_mcam_access_reg_bits { 9885 u8 reserved_at_0[0x1c]; 9886 u8 mcda[0x1]; 9887 u8 mcc[0x1]; 9888 u8 mcqi[0x1]; 9889 u8 mcqs[0x1]; 9890 9891 u8 regs_95_to_87[0x9]; 9892 u8 mpegc[0x1]; 9893 u8 mtutc[0x1]; 9894 u8 regs_84_to_68[0x11]; 9895 u8 tracer_registers[0x4]; 9896 9897 u8 regs_63_to_46[0x12]; 9898 u8 mrtc[0x1]; 9899 u8 regs_44_to_32[0xd]; 9900 9901 u8 regs_31_to_0[0x20]; 9902 }; 9903 9904 struct mlx5_ifc_mcam_access_reg_bits1 { 9905 u8 regs_127_to_96[0x20]; 9906 9907 u8 regs_95_to_64[0x20]; 9908 9909 u8 regs_63_to_32[0x20]; 9910 9911 u8 regs_31_to_0[0x20]; 9912 }; 9913 9914 struct mlx5_ifc_mcam_access_reg_bits2 { 9915 u8 regs_127_to_99[0x1d]; 9916 u8 mirc[0x1]; 9917 u8 regs_97_to_96[0x2]; 9918 9919 u8 regs_95_to_64[0x20]; 9920 9921 u8 regs_63_to_32[0x20]; 9922 9923 u8 regs_31_to_0[0x20]; 9924 }; 9925 9926 struct mlx5_ifc_mcam_reg_bits { 9927 u8 reserved_at_0[0x8]; 9928 u8 feature_group[0x8]; 9929 u8 reserved_at_10[0x8]; 9930 u8 access_reg_group[0x8]; 9931 9932 u8 reserved_at_20[0x20]; 9933 9934 union { 9935 struct mlx5_ifc_mcam_access_reg_bits access_regs; 9936 struct mlx5_ifc_mcam_access_reg_bits1 access_regs1; 9937 struct mlx5_ifc_mcam_access_reg_bits2 access_regs2; 9938 u8 reserved_at_0[0x80]; 9939 } mng_access_reg_cap_mask; 9940 9941 u8 reserved_at_c0[0x80]; 9942 9943 union { 9944 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features; 9945 u8 reserved_at_0[0x80]; 9946 } mng_feature_cap_mask; 9947 9948 u8 reserved_at_1c0[0x80]; 9949 }; 9950 9951 struct mlx5_ifc_qcam_access_reg_cap_mask { 9952 u8 qcam_access_reg_cap_mask_127_to_20[0x6C]; 9953 u8 qpdpm[0x1]; 9954 u8 qcam_access_reg_cap_mask_18_to_4[0x0F]; 9955 u8 qdpm[0x1]; 9956 u8 qpts[0x1]; 9957 u8 qcap[0x1]; 9958 u8 qcam_access_reg_cap_mask_0[0x1]; 9959 }; 9960 9961 struct mlx5_ifc_qcam_qos_feature_cap_mask { 9962 u8 qcam_qos_feature_cap_mask_127_to_1[0x7F]; 9963 u8 qpts_trust_both[0x1]; 9964 }; 9965 9966 struct mlx5_ifc_qcam_reg_bits { 9967 u8 reserved_at_0[0x8]; 9968 u8 feature_group[0x8]; 9969 u8 reserved_at_10[0x8]; 9970 u8 access_reg_group[0x8]; 9971 u8 reserved_at_20[0x20]; 9972 9973 union { 9974 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap; 9975 u8 reserved_at_0[0x80]; 9976 } qos_access_reg_cap_mask; 9977 9978 u8 reserved_at_c0[0x80]; 9979 9980 union { 9981 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap; 9982 u8 reserved_at_0[0x80]; 9983 } qos_feature_cap_mask; 9984 9985 u8 reserved_at_1c0[0x80]; 9986 }; 9987 9988 struct mlx5_ifc_core_dump_reg_bits { 9989 u8 reserved_at_0[0x18]; 9990 u8 core_dump_type[0x8]; 9991 9992 u8 reserved_at_20[0x30]; 9993 u8 vhca_id[0x10]; 9994 9995 u8 reserved_at_60[0x8]; 9996 u8 qpn[0x18]; 9997 u8 reserved_at_80[0x180]; 9998 }; 9999 10000 struct mlx5_ifc_pcap_reg_bits { 10001 u8 reserved_at_0[0x8]; 10002 u8 local_port[0x8]; 10003 u8 reserved_at_10[0x10]; 10004 10005 u8 port_capability_mask[4][0x20]; 10006 }; 10007 10008 struct mlx5_ifc_paos_reg_bits { 10009 u8 swid[0x8]; 10010 u8 local_port[0x8]; 10011 u8 reserved_at_10[0x4]; 10012 u8 admin_status[0x4]; 10013 u8 reserved_at_18[0x4]; 10014 u8 oper_status[0x4]; 10015 10016 u8 ase[0x1]; 10017 u8 ee[0x1]; 10018 u8 reserved_at_22[0x1c]; 10019 u8 e[0x2]; 10020 10021 u8 reserved_at_40[0x40]; 10022 }; 10023 10024 struct mlx5_ifc_pamp_reg_bits { 10025 u8 reserved_at_0[0x8]; 10026 u8 opamp_group[0x8]; 10027 u8 reserved_at_10[0xc]; 10028 u8 opamp_group_type[0x4]; 10029 10030 u8 start_index[0x10]; 10031 u8 reserved_at_30[0x4]; 10032 u8 num_of_indices[0xc]; 10033 10034 u8 index_data[18][0x10]; 10035 }; 10036 10037 struct mlx5_ifc_pcmr_reg_bits { 10038 u8 reserved_at_0[0x8]; 10039 u8 local_port[0x8]; 10040 u8 reserved_at_10[0x10]; 10041 10042 u8 entropy_force_cap[0x1]; 10043 u8 entropy_calc_cap[0x1]; 10044 u8 entropy_gre_calc_cap[0x1]; 10045 u8 reserved_at_23[0xf]; 10046 u8 rx_ts_over_crc_cap[0x1]; 10047 u8 reserved_at_33[0xb]; 10048 u8 fcs_cap[0x1]; 10049 u8 reserved_at_3f[0x1]; 10050 10051 u8 entropy_force[0x1]; 10052 u8 entropy_calc[0x1]; 10053 u8 entropy_gre_calc[0x1]; 10054 u8 reserved_at_43[0xf]; 10055 u8 rx_ts_over_crc[0x1]; 10056 u8 reserved_at_53[0xb]; 10057 u8 fcs_chk[0x1]; 10058 u8 reserved_at_5f[0x1]; 10059 }; 10060 10061 struct mlx5_ifc_lane_2_module_mapping_bits { 10062 u8 reserved_at_0[0x4]; 10063 u8 rx_lane[0x4]; 10064 u8 reserved_at_8[0x4]; 10065 u8 tx_lane[0x4]; 10066 u8 reserved_at_10[0x8]; 10067 u8 module[0x8]; 10068 }; 10069 10070 struct mlx5_ifc_bufferx_reg_bits { 10071 u8 reserved_at_0[0x6]; 10072 u8 lossy[0x1]; 10073 u8 epsb[0x1]; 10074 u8 reserved_at_8[0x8]; 10075 u8 size[0x10]; 10076 10077 u8 xoff_threshold[0x10]; 10078 u8 xon_threshold[0x10]; 10079 }; 10080 10081 struct mlx5_ifc_set_node_in_bits { 10082 u8 node_description[64][0x8]; 10083 }; 10084 10085 struct mlx5_ifc_register_power_settings_bits { 10086 u8 reserved_at_0[0x18]; 10087 u8 power_settings_level[0x8]; 10088 10089 u8 reserved_at_20[0x60]; 10090 }; 10091 10092 struct mlx5_ifc_register_host_endianness_bits { 10093 u8 he[0x1]; 10094 u8 reserved_at_1[0x1f]; 10095 10096 u8 reserved_at_20[0x60]; 10097 }; 10098 10099 struct mlx5_ifc_umr_pointer_desc_argument_bits { 10100 u8 reserved_at_0[0x20]; 10101 10102 u8 mkey[0x20]; 10103 10104 u8 addressh_63_32[0x20]; 10105 10106 u8 addressl_31_0[0x20]; 10107 }; 10108 10109 struct mlx5_ifc_ud_adrs_vector_bits { 10110 u8 dc_key[0x40]; 10111 10112 u8 ext[0x1]; 10113 u8 reserved_at_41[0x7]; 10114 u8 destination_qp_dct[0x18]; 10115 10116 u8 static_rate[0x4]; 10117 u8 sl_eth_prio[0x4]; 10118 u8 fl[0x1]; 10119 u8 mlid[0x7]; 10120 u8 rlid_udp_sport[0x10]; 10121 10122 u8 reserved_at_80[0x20]; 10123 10124 u8 rmac_47_16[0x20]; 10125 10126 u8 rmac_15_0[0x10]; 10127 u8 tclass[0x8]; 10128 u8 hop_limit[0x8]; 10129 10130 u8 reserved_at_e0[0x1]; 10131 u8 grh[0x1]; 10132 u8 reserved_at_e2[0x2]; 10133 u8 src_addr_index[0x8]; 10134 u8 flow_label[0x14]; 10135 10136 u8 rgid_rip[16][0x8]; 10137 }; 10138 10139 struct mlx5_ifc_pages_req_event_bits { 10140 u8 reserved_at_0[0x10]; 10141 u8 function_id[0x10]; 10142 10143 u8 num_pages[0x20]; 10144 10145 u8 reserved_at_40[0xa0]; 10146 }; 10147 10148 struct mlx5_ifc_eqe_bits { 10149 u8 reserved_at_0[0x8]; 10150 u8 event_type[0x8]; 10151 u8 reserved_at_10[0x8]; 10152 u8 event_sub_type[0x8]; 10153 10154 u8 reserved_at_20[0xe0]; 10155 10156 union mlx5_ifc_event_auto_bits event_data; 10157 10158 u8 reserved_at_1e0[0x10]; 10159 u8 signature[0x8]; 10160 u8 reserved_at_1f8[0x7]; 10161 u8 owner[0x1]; 10162 }; 10163 10164 enum { 10165 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7, 10166 }; 10167 10168 struct mlx5_ifc_cmd_queue_entry_bits { 10169 u8 type[0x8]; 10170 u8 reserved_at_8[0x18]; 10171 10172 u8 input_length[0x20]; 10173 10174 u8 input_mailbox_pointer_63_32[0x20]; 10175 10176 u8 input_mailbox_pointer_31_9[0x17]; 10177 u8 reserved_at_77[0x9]; 10178 10179 u8 command_input_inline_data[16][0x8]; 10180 10181 u8 command_output_inline_data[16][0x8]; 10182 10183 u8 output_mailbox_pointer_63_32[0x20]; 10184 10185 u8 output_mailbox_pointer_31_9[0x17]; 10186 u8 reserved_at_1b7[0x9]; 10187 10188 u8 output_length[0x20]; 10189 10190 u8 token[0x8]; 10191 u8 signature[0x8]; 10192 u8 reserved_at_1f0[0x8]; 10193 u8 status[0x7]; 10194 u8 ownership[0x1]; 10195 }; 10196 10197 struct mlx5_ifc_cmd_out_bits { 10198 u8 status[0x8]; 10199 u8 reserved_at_8[0x18]; 10200 10201 u8 syndrome[0x20]; 10202 10203 u8 command_output[0x20]; 10204 }; 10205 10206 struct mlx5_ifc_cmd_in_bits { 10207 u8 opcode[0x10]; 10208 u8 reserved_at_10[0x10]; 10209 10210 u8 reserved_at_20[0x10]; 10211 u8 op_mod[0x10]; 10212 10213 u8 command[][0x20]; 10214 }; 10215 10216 struct mlx5_ifc_cmd_if_box_bits { 10217 u8 mailbox_data[512][0x8]; 10218 10219 u8 reserved_at_1000[0x180]; 10220 10221 u8 next_pointer_63_32[0x20]; 10222 10223 u8 next_pointer_31_10[0x16]; 10224 u8 reserved_at_11b6[0xa]; 10225 10226 u8 block_number[0x20]; 10227 10228 u8 reserved_at_11e0[0x8]; 10229 u8 token[0x8]; 10230 u8 ctrl_signature[0x8]; 10231 u8 signature[0x8]; 10232 }; 10233 10234 struct mlx5_ifc_mtt_bits { 10235 u8 ptag_63_32[0x20]; 10236 10237 u8 ptag_31_8[0x18]; 10238 u8 reserved_at_38[0x6]; 10239 u8 wr_en[0x1]; 10240 u8 rd_en[0x1]; 10241 }; 10242 10243 struct mlx5_ifc_query_wol_rol_out_bits { 10244 u8 status[0x8]; 10245 u8 reserved_at_8[0x18]; 10246 10247 u8 syndrome[0x20]; 10248 10249 u8 reserved_at_40[0x10]; 10250 u8 rol_mode[0x8]; 10251 u8 wol_mode[0x8]; 10252 10253 u8 reserved_at_60[0x20]; 10254 }; 10255 10256 struct mlx5_ifc_query_wol_rol_in_bits { 10257 u8 opcode[0x10]; 10258 u8 reserved_at_10[0x10]; 10259 10260 u8 reserved_at_20[0x10]; 10261 u8 op_mod[0x10]; 10262 10263 u8 reserved_at_40[0x40]; 10264 }; 10265 10266 struct mlx5_ifc_set_wol_rol_out_bits { 10267 u8 status[0x8]; 10268 u8 reserved_at_8[0x18]; 10269 10270 u8 syndrome[0x20]; 10271 10272 u8 reserved_at_40[0x40]; 10273 }; 10274 10275 struct mlx5_ifc_set_wol_rol_in_bits { 10276 u8 opcode[0x10]; 10277 u8 reserved_at_10[0x10]; 10278 10279 u8 reserved_at_20[0x10]; 10280 u8 op_mod[0x10]; 10281 10282 u8 rol_mode_valid[0x1]; 10283 u8 wol_mode_valid[0x1]; 10284 u8 reserved_at_42[0xe]; 10285 u8 rol_mode[0x8]; 10286 u8 wol_mode[0x8]; 10287 10288 u8 reserved_at_60[0x20]; 10289 }; 10290 10291 enum { 10292 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0, 10293 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1, 10294 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2, 10295 }; 10296 10297 enum { 10298 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0, 10299 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1, 10300 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2, 10301 }; 10302 10303 enum { 10304 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1, 10305 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7, 10306 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8, 10307 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9, 10308 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa, 10309 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb, 10310 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc, 10311 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd, 10312 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe, 10313 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf, 10314 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10, 10315 }; 10316 10317 struct mlx5_ifc_initial_seg_bits { 10318 u8 fw_rev_minor[0x10]; 10319 u8 fw_rev_major[0x10]; 10320 10321 u8 cmd_interface_rev[0x10]; 10322 u8 fw_rev_subminor[0x10]; 10323 10324 u8 reserved_at_40[0x40]; 10325 10326 u8 cmdq_phy_addr_63_32[0x20]; 10327 10328 u8 cmdq_phy_addr_31_12[0x14]; 10329 u8 reserved_at_b4[0x2]; 10330 u8 nic_interface[0x2]; 10331 u8 log_cmdq_size[0x4]; 10332 u8 log_cmdq_stride[0x4]; 10333 10334 u8 command_doorbell_vector[0x20]; 10335 10336 u8 reserved_at_e0[0xf00]; 10337 10338 u8 initializing[0x1]; 10339 u8 reserved_at_fe1[0x4]; 10340 u8 nic_interface_supported[0x3]; 10341 u8 embedded_cpu[0x1]; 10342 u8 reserved_at_fe9[0x17]; 10343 10344 struct mlx5_ifc_health_buffer_bits health_buffer; 10345 10346 u8 no_dram_nic_offset[0x20]; 10347 10348 u8 reserved_at_1220[0x6e40]; 10349 10350 u8 reserved_at_8060[0x1f]; 10351 u8 clear_int[0x1]; 10352 10353 u8 health_syndrome[0x8]; 10354 u8 health_counter[0x18]; 10355 10356 u8 reserved_at_80a0[0x17fc0]; 10357 }; 10358 10359 struct mlx5_ifc_mtpps_reg_bits { 10360 u8 reserved_at_0[0xc]; 10361 u8 cap_number_of_pps_pins[0x4]; 10362 u8 reserved_at_10[0x4]; 10363 u8 cap_max_num_of_pps_in_pins[0x4]; 10364 u8 reserved_at_18[0x4]; 10365 u8 cap_max_num_of_pps_out_pins[0x4]; 10366 10367 u8 reserved_at_20[0x13]; 10368 u8 cap_log_min_npps_period[0x5]; 10369 u8 reserved_at_38[0x3]; 10370 u8 cap_log_min_out_pulse_duration_ns[0x5]; 10371 10372 u8 reserved_at_40[0x4]; 10373 u8 cap_pin_3_mode[0x4]; 10374 u8 reserved_at_48[0x4]; 10375 u8 cap_pin_2_mode[0x4]; 10376 u8 reserved_at_50[0x4]; 10377 u8 cap_pin_1_mode[0x4]; 10378 u8 reserved_at_58[0x4]; 10379 u8 cap_pin_0_mode[0x4]; 10380 10381 u8 reserved_at_60[0x4]; 10382 u8 cap_pin_7_mode[0x4]; 10383 u8 reserved_at_68[0x4]; 10384 u8 cap_pin_6_mode[0x4]; 10385 u8 reserved_at_70[0x4]; 10386 u8 cap_pin_5_mode[0x4]; 10387 u8 reserved_at_78[0x4]; 10388 u8 cap_pin_4_mode[0x4]; 10389 10390 u8 field_select[0x20]; 10391 u8 reserved_at_a0[0x20]; 10392 10393 u8 npps_period[0x40]; 10394 10395 u8 enable[0x1]; 10396 u8 reserved_at_101[0xb]; 10397 u8 pattern[0x4]; 10398 u8 reserved_at_110[0x4]; 10399 u8 pin_mode[0x4]; 10400 u8 pin[0x8]; 10401 10402 u8 reserved_at_120[0x2]; 10403 u8 out_pulse_duration_ns[0x1e]; 10404 10405 u8 time_stamp[0x40]; 10406 10407 u8 out_pulse_duration[0x10]; 10408 u8 out_periodic_adjustment[0x10]; 10409 u8 enhanced_out_periodic_adjustment[0x20]; 10410 10411 u8 reserved_at_1c0[0x20]; 10412 }; 10413 10414 struct mlx5_ifc_mtppse_reg_bits { 10415 u8 reserved_at_0[0x18]; 10416 u8 pin[0x8]; 10417 u8 event_arm[0x1]; 10418 u8 reserved_at_21[0x1b]; 10419 u8 event_generation_mode[0x4]; 10420 u8 reserved_at_40[0x40]; 10421 }; 10422 10423 struct mlx5_ifc_mcqs_reg_bits { 10424 u8 last_index_flag[0x1]; 10425 u8 reserved_at_1[0x7]; 10426 u8 fw_device[0x8]; 10427 u8 component_index[0x10]; 10428 10429 u8 reserved_at_20[0x10]; 10430 u8 identifier[0x10]; 10431 10432 u8 reserved_at_40[0x17]; 10433 u8 component_status[0x5]; 10434 u8 component_update_state[0x4]; 10435 10436 u8 last_update_state_changer_type[0x4]; 10437 u8 last_update_state_changer_host_id[0x4]; 10438 u8 reserved_at_68[0x18]; 10439 }; 10440 10441 struct mlx5_ifc_mcqi_cap_bits { 10442 u8 supported_info_bitmask[0x20]; 10443 10444 u8 component_size[0x20]; 10445 10446 u8 max_component_size[0x20]; 10447 10448 u8 log_mcda_word_size[0x4]; 10449 u8 reserved_at_64[0xc]; 10450 u8 mcda_max_write_size[0x10]; 10451 10452 u8 rd_en[0x1]; 10453 u8 reserved_at_81[0x1]; 10454 u8 match_chip_id[0x1]; 10455 u8 match_psid[0x1]; 10456 u8 check_user_timestamp[0x1]; 10457 u8 match_base_guid_mac[0x1]; 10458 u8 reserved_at_86[0x1a]; 10459 }; 10460 10461 struct mlx5_ifc_mcqi_version_bits { 10462 u8 reserved_at_0[0x2]; 10463 u8 build_time_valid[0x1]; 10464 u8 user_defined_time_valid[0x1]; 10465 u8 reserved_at_4[0x14]; 10466 u8 version_string_length[0x8]; 10467 10468 u8 version[0x20]; 10469 10470 u8 build_time[0x40]; 10471 10472 u8 user_defined_time[0x40]; 10473 10474 u8 build_tool_version[0x20]; 10475 10476 u8 reserved_at_e0[0x20]; 10477 10478 u8 version_string[92][0x8]; 10479 }; 10480 10481 struct mlx5_ifc_mcqi_activation_method_bits { 10482 u8 pending_server_ac_power_cycle[0x1]; 10483 u8 pending_server_dc_power_cycle[0x1]; 10484 u8 pending_server_reboot[0x1]; 10485 u8 pending_fw_reset[0x1]; 10486 u8 auto_activate[0x1]; 10487 u8 all_hosts_sync[0x1]; 10488 u8 device_hw_reset[0x1]; 10489 u8 reserved_at_7[0x19]; 10490 }; 10491 10492 union mlx5_ifc_mcqi_reg_data_bits { 10493 struct mlx5_ifc_mcqi_cap_bits mcqi_caps; 10494 struct mlx5_ifc_mcqi_version_bits mcqi_version; 10495 struct mlx5_ifc_mcqi_activation_method_bits mcqi_activation_mathod; 10496 }; 10497 10498 struct mlx5_ifc_mcqi_reg_bits { 10499 u8 read_pending_component[0x1]; 10500 u8 reserved_at_1[0xf]; 10501 u8 component_index[0x10]; 10502 10503 u8 reserved_at_20[0x20]; 10504 10505 u8 reserved_at_40[0x1b]; 10506 u8 info_type[0x5]; 10507 10508 u8 info_size[0x20]; 10509 10510 u8 offset[0x20]; 10511 10512 u8 reserved_at_a0[0x10]; 10513 u8 data_size[0x10]; 10514 10515 union mlx5_ifc_mcqi_reg_data_bits data[]; 10516 }; 10517 10518 struct mlx5_ifc_mcc_reg_bits { 10519 u8 reserved_at_0[0x4]; 10520 u8 time_elapsed_since_last_cmd[0xc]; 10521 u8 reserved_at_10[0x8]; 10522 u8 instruction[0x8]; 10523 10524 u8 reserved_at_20[0x10]; 10525 u8 component_index[0x10]; 10526 10527 u8 reserved_at_40[0x8]; 10528 u8 update_handle[0x18]; 10529 10530 u8 handle_owner_type[0x4]; 10531 u8 handle_owner_host_id[0x4]; 10532 u8 reserved_at_68[0x1]; 10533 u8 control_progress[0x7]; 10534 u8 error_code[0x8]; 10535 u8 reserved_at_78[0x4]; 10536 u8 control_state[0x4]; 10537 10538 u8 component_size[0x20]; 10539 10540 u8 reserved_at_a0[0x60]; 10541 }; 10542 10543 struct mlx5_ifc_mcda_reg_bits { 10544 u8 reserved_at_0[0x8]; 10545 u8 update_handle[0x18]; 10546 10547 u8 offset[0x20]; 10548 10549 u8 reserved_at_40[0x10]; 10550 u8 size[0x10]; 10551 10552 u8 reserved_at_60[0x20]; 10553 10554 u8 data[][0x20]; 10555 }; 10556 10557 enum { 10558 MLX5_MFRL_REG_RESET_STATE_IDLE = 0, 10559 MLX5_MFRL_REG_RESET_STATE_IN_NEGOTIATION = 1, 10560 MLX5_MFRL_REG_RESET_STATE_RESET_IN_PROGRESS = 2, 10561 MLX5_MFRL_REG_RESET_STATE_TIMEOUT = 3, 10562 MLX5_MFRL_REG_RESET_STATE_NACK = 4, 10563 }; 10564 10565 enum { 10566 MLX5_MFRL_REG_RESET_TYPE_FULL_CHIP = BIT(0), 10567 MLX5_MFRL_REG_RESET_TYPE_NET_PORT_ALIVE = BIT(1), 10568 }; 10569 10570 enum { 10571 MLX5_MFRL_REG_RESET_LEVEL0 = BIT(0), 10572 MLX5_MFRL_REG_RESET_LEVEL3 = BIT(3), 10573 MLX5_MFRL_REG_RESET_LEVEL6 = BIT(6), 10574 }; 10575 10576 struct mlx5_ifc_mfrl_reg_bits { 10577 u8 reserved_at_0[0x20]; 10578 10579 u8 reserved_at_20[0x2]; 10580 u8 pci_sync_for_fw_update_start[0x1]; 10581 u8 pci_sync_for_fw_update_resp[0x2]; 10582 u8 rst_type_sel[0x3]; 10583 u8 reserved_at_28[0x4]; 10584 u8 reset_state[0x4]; 10585 u8 reset_type[0x8]; 10586 u8 reset_level[0x8]; 10587 }; 10588 10589 struct mlx5_ifc_mirc_reg_bits { 10590 u8 reserved_at_0[0x18]; 10591 u8 status_code[0x8]; 10592 10593 u8 reserved_at_20[0x20]; 10594 }; 10595 10596 struct mlx5_ifc_pddr_monitor_opcode_bits { 10597 u8 reserved_at_0[0x10]; 10598 u8 monitor_opcode[0x10]; 10599 }; 10600 10601 union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits { 10602 struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode; 10603 u8 reserved_at_0[0x20]; 10604 }; 10605 10606 enum { 10607 /* Monitor opcodes */ 10608 MLX5_PDDR_REG_TRBLSH_GROUP_OPCODE_MONITOR = 0x0, 10609 }; 10610 10611 struct mlx5_ifc_pddr_troubleshooting_page_bits { 10612 u8 reserved_at_0[0x10]; 10613 u8 group_opcode[0x10]; 10614 10615 union mlx5_ifc_pddr_troubleshooting_page_status_opcode_auto_bits status_opcode; 10616 10617 u8 reserved_at_40[0x20]; 10618 10619 u8 status_message[59][0x20]; 10620 }; 10621 10622 union mlx5_ifc_pddr_reg_page_data_auto_bits { 10623 struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page; 10624 u8 reserved_at_0[0x7c0]; 10625 }; 10626 10627 enum { 10628 MLX5_PDDR_REG_PAGE_SELECT_TROUBLESHOOTING_INFO_PAGE = 0x1, 10629 }; 10630 10631 struct mlx5_ifc_pddr_reg_bits { 10632 u8 reserved_at_0[0x8]; 10633 u8 local_port[0x8]; 10634 u8 pnat[0x2]; 10635 u8 reserved_at_12[0xe]; 10636 10637 u8 reserved_at_20[0x18]; 10638 u8 page_select[0x8]; 10639 10640 union mlx5_ifc_pddr_reg_page_data_auto_bits page_data; 10641 }; 10642 10643 struct mlx5_ifc_mrtc_reg_bits { 10644 u8 time_synced[0x1]; 10645 u8 reserved_at_1[0x1f]; 10646 10647 u8 reserved_at_20[0x20]; 10648 10649 u8 time_h[0x20]; 10650 10651 u8 time_l[0x20]; 10652 }; 10653 10654 union mlx5_ifc_ports_control_registers_document_bits { 10655 struct mlx5_ifc_bufferx_reg_bits bufferx_reg; 10656 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; 10657 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; 10658 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; 10659 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; 10660 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; 10661 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; 10662 struct mlx5_ifc_eth_per_tc_prio_grp_data_layout_bits eth_per_tc_prio_grp_data_layout; 10663 struct mlx5_ifc_eth_per_tc_congest_prio_grp_data_layout_bits eth_per_tc_congest_prio_grp_data_layout; 10664 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping; 10665 struct mlx5_ifc_pamp_reg_bits pamp_reg; 10666 struct mlx5_ifc_paos_reg_bits paos_reg; 10667 struct mlx5_ifc_pcap_reg_bits pcap_reg; 10668 struct mlx5_ifc_pddr_monitor_opcode_bits pddr_monitor_opcode; 10669 struct mlx5_ifc_pddr_reg_bits pddr_reg; 10670 struct mlx5_ifc_pddr_troubleshooting_page_bits pddr_troubleshooting_page; 10671 struct mlx5_ifc_peir_reg_bits peir_reg; 10672 struct mlx5_ifc_pelc_reg_bits pelc_reg; 10673 struct mlx5_ifc_pfcc_reg_bits pfcc_reg; 10674 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; 10675 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; 10676 struct mlx5_ifc_pifr_reg_bits pifr_reg; 10677 struct mlx5_ifc_pipg_reg_bits pipg_reg; 10678 struct mlx5_ifc_plbf_reg_bits plbf_reg; 10679 struct mlx5_ifc_plib_reg_bits plib_reg; 10680 struct mlx5_ifc_plpc_reg_bits plpc_reg; 10681 struct mlx5_ifc_pmaos_reg_bits pmaos_reg; 10682 struct mlx5_ifc_pmlp_reg_bits pmlp_reg; 10683 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg; 10684 struct mlx5_ifc_pmpc_reg_bits pmpc_reg; 10685 struct mlx5_ifc_pmpe_reg_bits pmpe_reg; 10686 struct mlx5_ifc_pmpr_reg_bits pmpr_reg; 10687 struct mlx5_ifc_pmtu_reg_bits pmtu_reg; 10688 struct mlx5_ifc_ppad_reg_bits ppad_reg; 10689 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg; 10690 struct mlx5_ifc_mpein_reg_bits mpein_reg; 10691 struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg; 10692 struct mlx5_ifc_pplm_reg_bits pplm_reg; 10693 struct mlx5_ifc_pplr_reg_bits pplr_reg; 10694 struct mlx5_ifc_ppsc_reg_bits ppsc_reg; 10695 struct mlx5_ifc_pqdr_reg_bits pqdr_reg; 10696 struct mlx5_ifc_pspa_reg_bits pspa_reg; 10697 struct mlx5_ifc_ptas_reg_bits ptas_reg; 10698 struct mlx5_ifc_ptys_reg_bits ptys_reg; 10699 struct mlx5_ifc_mlcr_reg_bits mlcr_reg; 10700 struct mlx5_ifc_pude_reg_bits pude_reg; 10701 struct mlx5_ifc_pvlc_reg_bits pvlc_reg; 10702 struct mlx5_ifc_slrg_reg_bits slrg_reg; 10703 struct mlx5_ifc_sltp_reg_bits sltp_reg; 10704 struct mlx5_ifc_mtpps_reg_bits mtpps_reg; 10705 struct mlx5_ifc_mtppse_reg_bits mtppse_reg; 10706 struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg; 10707 struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits; 10708 struct mlx5_ifc_fpga_cap_bits fpga_cap_bits; 10709 struct mlx5_ifc_mcqi_reg_bits mcqi_reg; 10710 struct mlx5_ifc_mcc_reg_bits mcc_reg; 10711 struct mlx5_ifc_mcda_reg_bits mcda_reg; 10712 struct mlx5_ifc_mirc_reg_bits mirc_reg; 10713 struct mlx5_ifc_mfrl_reg_bits mfrl_reg; 10714 struct mlx5_ifc_mtutc_reg_bits mtutc_reg; 10715 struct mlx5_ifc_mrtc_reg_bits mrtc_reg; 10716 u8 reserved_at_0[0x60e0]; 10717 }; 10718 10719 union mlx5_ifc_debug_enhancements_document_bits { 10720 struct mlx5_ifc_health_buffer_bits health_buffer; 10721 u8 reserved_at_0[0x200]; 10722 }; 10723 10724 union mlx5_ifc_uplink_pci_interface_document_bits { 10725 struct mlx5_ifc_initial_seg_bits initial_seg; 10726 u8 reserved_at_0[0x20060]; 10727 }; 10728 10729 struct mlx5_ifc_set_flow_table_root_out_bits { 10730 u8 status[0x8]; 10731 u8 reserved_at_8[0x18]; 10732 10733 u8 syndrome[0x20]; 10734 10735 u8 reserved_at_40[0x40]; 10736 }; 10737 10738 struct mlx5_ifc_set_flow_table_root_in_bits { 10739 u8 opcode[0x10]; 10740 u8 reserved_at_10[0x10]; 10741 10742 u8 reserved_at_20[0x10]; 10743 u8 op_mod[0x10]; 10744 10745 u8 other_vport[0x1]; 10746 u8 reserved_at_41[0xf]; 10747 u8 vport_number[0x10]; 10748 10749 u8 reserved_at_60[0x20]; 10750 10751 u8 table_type[0x8]; 10752 u8 reserved_at_88[0x7]; 10753 u8 table_of_other_vport[0x1]; 10754 u8 table_vport_number[0x10]; 10755 10756 u8 reserved_at_a0[0x8]; 10757 u8 table_id[0x18]; 10758 10759 u8 reserved_at_c0[0x8]; 10760 u8 underlay_qpn[0x18]; 10761 u8 table_eswitch_owner_vhca_id_valid[0x1]; 10762 u8 reserved_at_e1[0xf]; 10763 u8 table_eswitch_owner_vhca_id[0x10]; 10764 u8 reserved_at_100[0x100]; 10765 }; 10766 10767 enum { 10768 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0), 10769 MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15), 10770 }; 10771 10772 struct mlx5_ifc_modify_flow_table_out_bits { 10773 u8 status[0x8]; 10774 u8 reserved_at_8[0x18]; 10775 10776 u8 syndrome[0x20]; 10777 10778 u8 reserved_at_40[0x40]; 10779 }; 10780 10781 struct mlx5_ifc_modify_flow_table_in_bits { 10782 u8 opcode[0x10]; 10783 u8 reserved_at_10[0x10]; 10784 10785 u8 reserved_at_20[0x10]; 10786 u8 op_mod[0x10]; 10787 10788 u8 other_vport[0x1]; 10789 u8 reserved_at_41[0xf]; 10790 u8 vport_number[0x10]; 10791 10792 u8 reserved_at_60[0x10]; 10793 u8 modify_field_select[0x10]; 10794 10795 u8 table_type[0x8]; 10796 u8 reserved_at_88[0x18]; 10797 10798 u8 reserved_at_a0[0x8]; 10799 u8 table_id[0x18]; 10800 10801 struct mlx5_ifc_flow_table_context_bits flow_table_context; 10802 }; 10803 10804 struct mlx5_ifc_ets_tcn_config_reg_bits { 10805 u8 g[0x1]; 10806 u8 b[0x1]; 10807 u8 r[0x1]; 10808 u8 reserved_at_3[0x9]; 10809 u8 group[0x4]; 10810 u8 reserved_at_10[0x9]; 10811 u8 bw_allocation[0x7]; 10812 10813 u8 reserved_at_20[0xc]; 10814 u8 max_bw_units[0x4]; 10815 u8 reserved_at_30[0x8]; 10816 u8 max_bw_value[0x8]; 10817 }; 10818 10819 struct mlx5_ifc_ets_global_config_reg_bits { 10820 u8 reserved_at_0[0x2]; 10821 u8 r[0x1]; 10822 u8 reserved_at_3[0x1d]; 10823 10824 u8 reserved_at_20[0xc]; 10825 u8 max_bw_units[0x4]; 10826 u8 reserved_at_30[0x8]; 10827 u8 max_bw_value[0x8]; 10828 }; 10829 10830 struct mlx5_ifc_qetc_reg_bits { 10831 u8 reserved_at_0[0x8]; 10832 u8 port_number[0x8]; 10833 u8 reserved_at_10[0x30]; 10834 10835 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8]; 10836 struct mlx5_ifc_ets_global_config_reg_bits global_configuration; 10837 }; 10838 10839 struct mlx5_ifc_qpdpm_dscp_reg_bits { 10840 u8 e[0x1]; 10841 u8 reserved_at_01[0x0b]; 10842 u8 prio[0x04]; 10843 }; 10844 10845 struct mlx5_ifc_qpdpm_reg_bits { 10846 u8 reserved_at_0[0x8]; 10847 u8 local_port[0x8]; 10848 u8 reserved_at_10[0x10]; 10849 struct mlx5_ifc_qpdpm_dscp_reg_bits dscp[64]; 10850 }; 10851 10852 struct mlx5_ifc_qpts_reg_bits { 10853 u8 reserved_at_0[0x8]; 10854 u8 local_port[0x8]; 10855 u8 reserved_at_10[0x2d]; 10856 u8 trust_state[0x3]; 10857 }; 10858 10859 struct mlx5_ifc_pptb_reg_bits { 10860 u8 reserved_at_0[0x2]; 10861 u8 mm[0x2]; 10862 u8 reserved_at_4[0x4]; 10863 u8 local_port[0x8]; 10864 u8 reserved_at_10[0x6]; 10865 u8 cm[0x1]; 10866 u8 um[0x1]; 10867 u8 pm[0x8]; 10868 10869 u8 prio_x_buff[0x20]; 10870 10871 u8 pm_msb[0x8]; 10872 u8 reserved_at_48[0x10]; 10873 u8 ctrl_buff[0x4]; 10874 u8 untagged_buff[0x4]; 10875 }; 10876 10877 struct mlx5_ifc_sbcam_reg_bits { 10878 u8 reserved_at_0[0x8]; 10879 u8 feature_group[0x8]; 10880 u8 reserved_at_10[0x8]; 10881 u8 access_reg_group[0x8]; 10882 10883 u8 reserved_at_20[0x20]; 10884 10885 u8 sb_access_reg_cap_mask[4][0x20]; 10886 10887 u8 reserved_at_c0[0x80]; 10888 10889 u8 sb_feature_cap_mask[4][0x20]; 10890 10891 u8 reserved_at_1c0[0x40]; 10892 10893 u8 cap_total_buffer_size[0x20]; 10894 10895 u8 cap_cell_size[0x10]; 10896 u8 cap_max_pg_buffers[0x8]; 10897 u8 cap_num_pool_supported[0x8]; 10898 10899 u8 reserved_at_240[0x8]; 10900 u8 cap_sbsr_stat_size[0x8]; 10901 u8 cap_max_tclass_data[0x8]; 10902 u8 cap_max_cpu_ingress_tclass_sb[0x8]; 10903 }; 10904 10905 struct mlx5_ifc_pbmc_reg_bits { 10906 u8 reserved_at_0[0x8]; 10907 u8 local_port[0x8]; 10908 u8 reserved_at_10[0x10]; 10909 10910 u8 xoff_timer_value[0x10]; 10911 u8 xoff_refresh[0x10]; 10912 10913 u8 reserved_at_40[0x9]; 10914 u8 fullness_threshold[0x7]; 10915 u8 port_buffer_size[0x10]; 10916 10917 struct mlx5_ifc_bufferx_reg_bits buffer[10]; 10918 10919 u8 reserved_at_2e0[0x80]; 10920 }; 10921 10922 struct mlx5_ifc_qtct_reg_bits { 10923 u8 reserved_at_0[0x8]; 10924 u8 port_number[0x8]; 10925 u8 reserved_at_10[0xd]; 10926 u8 prio[0x3]; 10927 10928 u8 reserved_at_20[0x1d]; 10929 u8 tclass[0x3]; 10930 }; 10931 10932 struct mlx5_ifc_mcia_reg_bits { 10933 u8 l[0x1]; 10934 u8 reserved_at_1[0x7]; 10935 u8 module[0x8]; 10936 u8 reserved_at_10[0x8]; 10937 u8 status[0x8]; 10938 10939 u8 i2c_device_address[0x8]; 10940 u8 page_number[0x8]; 10941 u8 device_address[0x10]; 10942 10943 u8 reserved_at_40[0x10]; 10944 u8 size[0x10]; 10945 10946 u8 reserved_at_60[0x20]; 10947 10948 u8 dword_0[0x20]; 10949 u8 dword_1[0x20]; 10950 u8 dword_2[0x20]; 10951 u8 dword_3[0x20]; 10952 u8 dword_4[0x20]; 10953 u8 dword_5[0x20]; 10954 u8 dword_6[0x20]; 10955 u8 dword_7[0x20]; 10956 u8 dword_8[0x20]; 10957 u8 dword_9[0x20]; 10958 u8 dword_10[0x20]; 10959 u8 dword_11[0x20]; 10960 }; 10961 10962 struct mlx5_ifc_dcbx_param_bits { 10963 u8 dcbx_cee_cap[0x1]; 10964 u8 dcbx_ieee_cap[0x1]; 10965 u8 dcbx_standby_cap[0x1]; 10966 u8 reserved_at_3[0x5]; 10967 u8 port_number[0x8]; 10968 u8 reserved_at_10[0xa]; 10969 u8 max_application_table_size[6]; 10970 u8 reserved_at_20[0x15]; 10971 u8 version_oper[0x3]; 10972 u8 reserved_at_38[5]; 10973 u8 version_admin[0x3]; 10974 u8 willing_admin[0x1]; 10975 u8 reserved_at_41[0x3]; 10976 u8 pfc_cap_oper[0x4]; 10977 u8 reserved_at_48[0x4]; 10978 u8 pfc_cap_admin[0x4]; 10979 u8 reserved_at_50[0x4]; 10980 u8 num_of_tc_oper[0x4]; 10981 u8 reserved_at_58[0x4]; 10982 u8 num_of_tc_admin[0x4]; 10983 u8 remote_willing[0x1]; 10984 u8 reserved_at_61[3]; 10985 u8 remote_pfc_cap[4]; 10986 u8 reserved_at_68[0x14]; 10987 u8 remote_num_of_tc[0x4]; 10988 u8 reserved_at_80[0x18]; 10989 u8 error[0x8]; 10990 u8 reserved_at_a0[0x160]; 10991 }; 10992 10993 enum { 10994 MLX5_LAG_PORT_SELECT_MODE_QUEUE_AFFINITY = 0, 10995 MLX5_LAG_PORT_SELECT_MODE_PORT_SELECT_FT = 1, 10996 MLX5_LAG_PORT_SELECT_MODE_PORT_SELECT_MPESW = 2, 10997 }; 10998 10999 struct mlx5_ifc_lagc_bits { 11000 u8 fdb_selection_mode[0x1]; 11001 u8 reserved_at_1[0x14]; 11002 u8 port_select_mode[0x3]; 11003 u8 reserved_at_18[0x5]; 11004 u8 lag_state[0x3]; 11005 11006 u8 reserved_at_20[0xc]; 11007 u8 active_port[0x4]; 11008 u8 reserved_at_30[0x4]; 11009 u8 tx_remap_affinity_2[0x4]; 11010 u8 reserved_at_38[0x4]; 11011 u8 tx_remap_affinity_1[0x4]; 11012 }; 11013 11014 struct mlx5_ifc_create_lag_out_bits { 11015 u8 status[0x8]; 11016 u8 reserved_at_8[0x18]; 11017 11018 u8 syndrome[0x20]; 11019 11020 u8 reserved_at_40[0x40]; 11021 }; 11022 11023 struct mlx5_ifc_create_lag_in_bits { 11024 u8 opcode[0x10]; 11025 u8 reserved_at_10[0x10]; 11026 11027 u8 reserved_at_20[0x10]; 11028 u8 op_mod[0x10]; 11029 11030 struct mlx5_ifc_lagc_bits ctx; 11031 }; 11032 11033 struct mlx5_ifc_modify_lag_out_bits { 11034 u8 status[0x8]; 11035 u8 reserved_at_8[0x18]; 11036 11037 u8 syndrome[0x20]; 11038 11039 u8 reserved_at_40[0x40]; 11040 }; 11041 11042 struct mlx5_ifc_modify_lag_in_bits { 11043 u8 opcode[0x10]; 11044 u8 reserved_at_10[0x10]; 11045 11046 u8 reserved_at_20[0x10]; 11047 u8 op_mod[0x10]; 11048 11049 u8 reserved_at_40[0x20]; 11050 u8 field_select[0x20]; 11051 11052 struct mlx5_ifc_lagc_bits ctx; 11053 }; 11054 11055 struct mlx5_ifc_query_lag_out_bits { 11056 u8 status[0x8]; 11057 u8 reserved_at_8[0x18]; 11058 11059 u8 syndrome[0x20]; 11060 11061 struct mlx5_ifc_lagc_bits ctx; 11062 }; 11063 11064 struct mlx5_ifc_query_lag_in_bits { 11065 u8 opcode[0x10]; 11066 u8 reserved_at_10[0x10]; 11067 11068 u8 reserved_at_20[0x10]; 11069 u8 op_mod[0x10]; 11070 11071 u8 reserved_at_40[0x40]; 11072 }; 11073 11074 struct mlx5_ifc_destroy_lag_out_bits { 11075 u8 status[0x8]; 11076 u8 reserved_at_8[0x18]; 11077 11078 u8 syndrome[0x20]; 11079 11080 u8 reserved_at_40[0x40]; 11081 }; 11082 11083 struct mlx5_ifc_destroy_lag_in_bits { 11084 u8 opcode[0x10]; 11085 u8 reserved_at_10[0x10]; 11086 11087 u8 reserved_at_20[0x10]; 11088 u8 op_mod[0x10]; 11089 11090 u8 reserved_at_40[0x40]; 11091 }; 11092 11093 struct mlx5_ifc_create_vport_lag_out_bits { 11094 u8 status[0x8]; 11095 u8 reserved_at_8[0x18]; 11096 11097 u8 syndrome[0x20]; 11098 11099 u8 reserved_at_40[0x40]; 11100 }; 11101 11102 struct mlx5_ifc_create_vport_lag_in_bits { 11103 u8 opcode[0x10]; 11104 u8 reserved_at_10[0x10]; 11105 11106 u8 reserved_at_20[0x10]; 11107 u8 op_mod[0x10]; 11108 11109 u8 reserved_at_40[0x40]; 11110 }; 11111 11112 struct mlx5_ifc_destroy_vport_lag_out_bits { 11113 u8 status[0x8]; 11114 u8 reserved_at_8[0x18]; 11115 11116 u8 syndrome[0x20]; 11117 11118 u8 reserved_at_40[0x40]; 11119 }; 11120 11121 struct mlx5_ifc_destroy_vport_lag_in_bits { 11122 u8 opcode[0x10]; 11123 u8 reserved_at_10[0x10]; 11124 11125 u8 reserved_at_20[0x10]; 11126 u8 op_mod[0x10]; 11127 11128 u8 reserved_at_40[0x40]; 11129 }; 11130 11131 enum { 11132 MLX5_MODIFY_MEMIC_OP_MOD_ALLOC, 11133 MLX5_MODIFY_MEMIC_OP_MOD_DEALLOC, 11134 }; 11135 11136 struct mlx5_ifc_modify_memic_in_bits { 11137 u8 opcode[0x10]; 11138 u8 uid[0x10]; 11139 11140 u8 reserved_at_20[0x10]; 11141 u8 op_mod[0x10]; 11142 11143 u8 reserved_at_40[0x20]; 11144 11145 u8 reserved_at_60[0x18]; 11146 u8 memic_operation_type[0x8]; 11147 11148 u8 memic_start_addr[0x40]; 11149 11150 u8 reserved_at_c0[0x140]; 11151 }; 11152 11153 struct mlx5_ifc_modify_memic_out_bits { 11154 u8 status[0x8]; 11155 u8 reserved_at_8[0x18]; 11156 11157 u8 syndrome[0x20]; 11158 11159 u8 reserved_at_40[0x40]; 11160 11161 u8 memic_operation_addr[0x40]; 11162 11163 u8 reserved_at_c0[0x140]; 11164 }; 11165 11166 struct mlx5_ifc_alloc_memic_in_bits { 11167 u8 opcode[0x10]; 11168 u8 reserved_at_10[0x10]; 11169 11170 u8 reserved_at_20[0x10]; 11171 u8 op_mod[0x10]; 11172 11173 u8 reserved_at_30[0x20]; 11174 11175 u8 reserved_at_40[0x18]; 11176 u8 log_memic_addr_alignment[0x8]; 11177 11178 u8 range_start_addr[0x40]; 11179 11180 u8 range_size[0x20]; 11181 11182 u8 memic_size[0x20]; 11183 }; 11184 11185 struct mlx5_ifc_alloc_memic_out_bits { 11186 u8 status[0x8]; 11187 u8 reserved_at_8[0x18]; 11188 11189 u8 syndrome[0x20]; 11190 11191 u8 memic_start_addr[0x40]; 11192 }; 11193 11194 struct mlx5_ifc_dealloc_memic_in_bits { 11195 u8 opcode[0x10]; 11196 u8 reserved_at_10[0x10]; 11197 11198 u8 reserved_at_20[0x10]; 11199 u8 op_mod[0x10]; 11200 11201 u8 reserved_at_40[0x40]; 11202 11203 u8 memic_start_addr[0x40]; 11204 11205 u8 memic_size[0x20]; 11206 11207 u8 reserved_at_e0[0x20]; 11208 }; 11209 11210 struct mlx5_ifc_dealloc_memic_out_bits { 11211 u8 status[0x8]; 11212 u8 reserved_at_8[0x18]; 11213 11214 u8 syndrome[0x20]; 11215 11216 u8 reserved_at_40[0x40]; 11217 }; 11218 11219 struct mlx5_ifc_umem_bits { 11220 u8 reserved_at_0[0x80]; 11221 11222 u8 ats[0x1]; 11223 u8 reserved_at_81[0x1a]; 11224 u8 log_page_size[0x5]; 11225 11226 u8 page_offset[0x20]; 11227 11228 u8 num_of_mtt[0x40]; 11229 11230 struct mlx5_ifc_mtt_bits mtt[]; 11231 }; 11232 11233 struct mlx5_ifc_uctx_bits { 11234 u8 cap[0x20]; 11235 11236 u8 reserved_at_20[0x160]; 11237 }; 11238 11239 struct mlx5_ifc_sw_icm_bits { 11240 u8 modify_field_select[0x40]; 11241 11242 u8 reserved_at_40[0x18]; 11243 u8 log_sw_icm_size[0x8]; 11244 11245 u8 reserved_at_60[0x20]; 11246 11247 u8 sw_icm_start_addr[0x40]; 11248 11249 u8 reserved_at_c0[0x140]; 11250 }; 11251 11252 struct mlx5_ifc_geneve_tlv_option_bits { 11253 u8 modify_field_select[0x40]; 11254 11255 u8 reserved_at_40[0x18]; 11256 u8 geneve_option_fte_index[0x8]; 11257 11258 u8 option_class[0x10]; 11259 u8 option_type[0x8]; 11260 u8 reserved_at_78[0x3]; 11261 u8 option_data_length[0x5]; 11262 11263 u8 reserved_at_80[0x180]; 11264 }; 11265 11266 struct mlx5_ifc_create_umem_in_bits { 11267 u8 opcode[0x10]; 11268 u8 uid[0x10]; 11269 11270 u8 reserved_at_20[0x10]; 11271 u8 op_mod[0x10]; 11272 11273 u8 reserved_at_40[0x40]; 11274 11275 struct mlx5_ifc_umem_bits umem; 11276 }; 11277 11278 struct mlx5_ifc_create_umem_out_bits { 11279 u8 status[0x8]; 11280 u8 reserved_at_8[0x18]; 11281 11282 u8 syndrome[0x20]; 11283 11284 u8 reserved_at_40[0x8]; 11285 u8 umem_id[0x18]; 11286 11287 u8 reserved_at_60[0x20]; 11288 }; 11289 11290 struct mlx5_ifc_destroy_umem_in_bits { 11291 u8 opcode[0x10]; 11292 u8 uid[0x10]; 11293 11294 u8 reserved_at_20[0x10]; 11295 u8 op_mod[0x10]; 11296 11297 u8 reserved_at_40[0x8]; 11298 u8 umem_id[0x18]; 11299 11300 u8 reserved_at_60[0x20]; 11301 }; 11302 11303 struct mlx5_ifc_destroy_umem_out_bits { 11304 u8 status[0x8]; 11305 u8 reserved_at_8[0x18]; 11306 11307 u8 syndrome[0x20]; 11308 11309 u8 reserved_at_40[0x40]; 11310 }; 11311 11312 struct mlx5_ifc_create_uctx_in_bits { 11313 u8 opcode[0x10]; 11314 u8 reserved_at_10[0x10]; 11315 11316 u8 reserved_at_20[0x10]; 11317 u8 op_mod[0x10]; 11318 11319 u8 reserved_at_40[0x40]; 11320 11321 struct mlx5_ifc_uctx_bits uctx; 11322 }; 11323 11324 struct mlx5_ifc_create_uctx_out_bits { 11325 u8 status[0x8]; 11326 u8 reserved_at_8[0x18]; 11327 11328 u8 syndrome[0x20]; 11329 11330 u8 reserved_at_40[0x10]; 11331 u8 uid[0x10]; 11332 11333 u8 reserved_at_60[0x20]; 11334 }; 11335 11336 struct mlx5_ifc_destroy_uctx_in_bits { 11337 u8 opcode[0x10]; 11338 u8 reserved_at_10[0x10]; 11339 11340 u8 reserved_at_20[0x10]; 11341 u8 op_mod[0x10]; 11342 11343 u8 reserved_at_40[0x10]; 11344 u8 uid[0x10]; 11345 11346 u8 reserved_at_60[0x20]; 11347 }; 11348 11349 struct mlx5_ifc_destroy_uctx_out_bits { 11350 u8 status[0x8]; 11351 u8 reserved_at_8[0x18]; 11352 11353 u8 syndrome[0x20]; 11354 11355 u8 reserved_at_40[0x40]; 11356 }; 11357 11358 struct mlx5_ifc_create_sw_icm_in_bits { 11359 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 11360 struct mlx5_ifc_sw_icm_bits sw_icm; 11361 }; 11362 11363 struct mlx5_ifc_create_geneve_tlv_option_in_bits { 11364 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 11365 struct mlx5_ifc_geneve_tlv_option_bits geneve_tlv_opt; 11366 }; 11367 11368 struct mlx5_ifc_mtrc_string_db_param_bits { 11369 u8 string_db_base_address[0x20]; 11370 11371 u8 reserved_at_20[0x8]; 11372 u8 string_db_size[0x18]; 11373 }; 11374 11375 struct mlx5_ifc_mtrc_cap_bits { 11376 u8 trace_owner[0x1]; 11377 u8 trace_to_memory[0x1]; 11378 u8 reserved_at_2[0x4]; 11379 u8 trc_ver[0x2]; 11380 u8 reserved_at_8[0x14]; 11381 u8 num_string_db[0x4]; 11382 11383 u8 first_string_trace[0x8]; 11384 u8 num_string_trace[0x8]; 11385 u8 reserved_at_30[0x28]; 11386 11387 u8 log_max_trace_buffer_size[0x8]; 11388 11389 u8 reserved_at_60[0x20]; 11390 11391 struct mlx5_ifc_mtrc_string_db_param_bits string_db_param[8]; 11392 11393 u8 reserved_at_280[0x180]; 11394 }; 11395 11396 struct mlx5_ifc_mtrc_conf_bits { 11397 u8 reserved_at_0[0x1c]; 11398 u8 trace_mode[0x4]; 11399 u8 reserved_at_20[0x18]; 11400 u8 log_trace_buffer_size[0x8]; 11401 u8 trace_mkey[0x20]; 11402 u8 reserved_at_60[0x3a0]; 11403 }; 11404 11405 struct mlx5_ifc_mtrc_stdb_bits { 11406 u8 string_db_index[0x4]; 11407 u8 reserved_at_4[0x4]; 11408 u8 read_size[0x18]; 11409 u8 start_offset[0x20]; 11410 u8 string_db_data[]; 11411 }; 11412 11413 struct mlx5_ifc_mtrc_ctrl_bits { 11414 u8 trace_status[0x2]; 11415 u8 reserved_at_2[0x2]; 11416 u8 arm_event[0x1]; 11417 u8 reserved_at_5[0xb]; 11418 u8 modify_field_select[0x10]; 11419 u8 reserved_at_20[0x2b]; 11420 u8 current_timestamp52_32[0x15]; 11421 u8 current_timestamp31_0[0x20]; 11422 u8 reserved_at_80[0x180]; 11423 }; 11424 11425 struct mlx5_ifc_host_params_context_bits { 11426 u8 host_number[0x8]; 11427 u8 reserved_at_8[0x7]; 11428 u8 host_pf_disabled[0x1]; 11429 u8 host_num_of_vfs[0x10]; 11430 11431 u8 host_total_vfs[0x10]; 11432 u8 host_pci_bus[0x10]; 11433 11434 u8 reserved_at_40[0x10]; 11435 u8 host_pci_device[0x10]; 11436 11437 u8 reserved_at_60[0x10]; 11438 u8 host_pci_function[0x10]; 11439 11440 u8 reserved_at_80[0x180]; 11441 }; 11442 11443 struct mlx5_ifc_query_esw_functions_in_bits { 11444 u8 opcode[0x10]; 11445 u8 reserved_at_10[0x10]; 11446 11447 u8 reserved_at_20[0x10]; 11448 u8 op_mod[0x10]; 11449 11450 u8 reserved_at_40[0x40]; 11451 }; 11452 11453 struct mlx5_ifc_query_esw_functions_out_bits { 11454 u8 status[0x8]; 11455 u8 reserved_at_8[0x18]; 11456 11457 u8 syndrome[0x20]; 11458 11459 u8 reserved_at_40[0x40]; 11460 11461 struct mlx5_ifc_host_params_context_bits host_params_context; 11462 11463 u8 reserved_at_280[0x180]; 11464 u8 host_sf_enable[][0x40]; 11465 }; 11466 11467 struct mlx5_ifc_sf_partition_bits { 11468 u8 reserved_at_0[0x10]; 11469 u8 log_num_sf[0x8]; 11470 u8 log_sf_bar_size[0x8]; 11471 }; 11472 11473 struct mlx5_ifc_query_sf_partitions_out_bits { 11474 u8 status[0x8]; 11475 u8 reserved_at_8[0x18]; 11476 11477 u8 syndrome[0x20]; 11478 11479 u8 reserved_at_40[0x18]; 11480 u8 num_sf_partitions[0x8]; 11481 11482 u8 reserved_at_60[0x20]; 11483 11484 struct mlx5_ifc_sf_partition_bits sf_partition[]; 11485 }; 11486 11487 struct mlx5_ifc_query_sf_partitions_in_bits { 11488 u8 opcode[0x10]; 11489 u8 reserved_at_10[0x10]; 11490 11491 u8 reserved_at_20[0x10]; 11492 u8 op_mod[0x10]; 11493 11494 u8 reserved_at_40[0x40]; 11495 }; 11496 11497 struct mlx5_ifc_dealloc_sf_out_bits { 11498 u8 status[0x8]; 11499 u8 reserved_at_8[0x18]; 11500 11501 u8 syndrome[0x20]; 11502 11503 u8 reserved_at_40[0x40]; 11504 }; 11505 11506 struct mlx5_ifc_dealloc_sf_in_bits { 11507 u8 opcode[0x10]; 11508 u8 reserved_at_10[0x10]; 11509 11510 u8 reserved_at_20[0x10]; 11511 u8 op_mod[0x10]; 11512 11513 u8 reserved_at_40[0x10]; 11514 u8 function_id[0x10]; 11515 11516 u8 reserved_at_60[0x20]; 11517 }; 11518 11519 struct mlx5_ifc_alloc_sf_out_bits { 11520 u8 status[0x8]; 11521 u8 reserved_at_8[0x18]; 11522 11523 u8 syndrome[0x20]; 11524 11525 u8 reserved_at_40[0x40]; 11526 }; 11527 11528 struct mlx5_ifc_alloc_sf_in_bits { 11529 u8 opcode[0x10]; 11530 u8 reserved_at_10[0x10]; 11531 11532 u8 reserved_at_20[0x10]; 11533 u8 op_mod[0x10]; 11534 11535 u8 reserved_at_40[0x10]; 11536 u8 function_id[0x10]; 11537 11538 u8 reserved_at_60[0x20]; 11539 }; 11540 11541 struct mlx5_ifc_affiliated_event_header_bits { 11542 u8 reserved_at_0[0x10]; 11543 u8 obj_type[0x10]; 11544 11545 u8 obj_id[0x20]; 11546 }; 11547 11548 enum { 11549 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = BIT_ULL(0xc), 11550 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_IPSEC = BIT_ULL(0x13), 11551 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_SAMPLER = BIT_ULL(0x20), 11552 MLX5_HCA_CAP_GENERAL_OBJECT_TYPES_FLOW_METER_ASO = BIT_ULL(0x24), 11553 }; 11554 11555 enum { 11556 MLX5_GENERAL_OBJECT_TYPES_ENCRYPTION_KEY = 0xc, 11557 MLX5_GENERAL_OBJECT_TYPES_IPSEC = 0x13, 11558 MLX5_GENERAL_OBJECT_TYPES_SAMPLER = 0x20, 11559 MLX5_GENERAL_OBJECT_TYPES_FLOW_METER_ASO = 0x24, 11560 MLX5_GENERAL_OBJECT_TYPES_MACSEC = 0x27, 11561 }; 11562 11563 enum { 11564 MLX5_IPSEC_OBJECT_ICV_LEN_16B, 11565 }; 11566 11567 struct mlx5_ifc_ipsec_obj_bits { 11568 u8 modify_field_select[0x40]; 11569 u8 full_offload[0x1]; 11570 u8 reserved_at_41[0x1]; 11571 u8 esn_en[0x1]; 11572 u8 esn_overlap[0x1]; 11573 u8 reserved_at_44[0x2]; 11574 u8 icv_length[0x2]; 11575 u8 reserved_at_48[0x4]; 11576 u8 aso_return_reg[0x4]; 11577 u8 reserved_at_50[0x10]; 11578 11579 u8 esn_msb[0x20]; 11580 11581 u8 reserved_at_80[0x8]; 11582 u8 dekn[0x18]; 11583 11584 u8 salt[0x20]; 11585 11586 u8 implicit_iv[0x40]; 11587 11588 u8 reserved_at_100[0x700]; 11589 }; 11590 11591 struct mlx5_ifc_create_ipsec_obj_in_bits { 11592 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 11593 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 11594 }; 11595 11596 enum { 11597 MLX5_MODIFY_IPSEC_BITMASK_ESN_OVERLAP = BIT(0), 11598 MLX5_MODIFY_IPSEC_BITMASK_ESN_MSB = BIT(1), 11599 }; 11600 11601 struct mlx5_ifc_query_ipsec_obj_out_bits { 11602 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 11603 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 11604 }; 11605 11606 struct mlx5_ifc_modify_ipsec_obj_in_bits { 11607 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 11608 struct mlx5_ifc_ipsec_obj_bits ipsec_object; 11609 }; 11610 11611 enum { 11612 MLX5_MACSEC_ASO_REPLAY_PROTECTION = 0x1, 11613 }; 11614 11615 enum { 11616 MLX5_MACSEC_ASO_REPLAY_WIN_32BIT = 0x0, 11617 MLX5_MACSEC_ASO_REPLAY_WIN_64BIT = 0x1, 11618 MLX5_MACSEC_ASO_REPLAY_WIN_128BIT = 0x2, 11619 MLX5_MACSEC_ASO_REPLAY_WIN_256BIT = 0x3, 11620 }; 11621 11622 #define MLX5_MACSEC_ASO_INC_SN 0x2 11623 #define MLX5_MACSEC_ASO_REG_C_4_5 0x2 11624 11625 struct mlx5_ifc_macsec_aso_bits { 11626 u8 valid[0x1]; 11627 u8 reserved_at_1[0x1]; 11628 u8 mode[0x2]; 11629 u8 window_size[0x2]; 11630 u8 soft_lifetime_arm[0x1]; 11631 u8 hard_lifetime_arm[0x1]; 11632 u8 remove_flow_enable[0x1]; 11633 u8 epn_event_arm[0x1]; 11634 u8 reserved_at_a[0x16]; 11635 11636 u8 remove_flow_packet_count[0x20]; 11637 11638 u8 remove_flow_soft_lifetime[0x20]; 11639 11640 u8 reserved_at_60[0x80]; 11641 11642 u8 mode_parameter[0x20]; 11643 11644 u8 replay_protection_window[8][0x20]; 11645 }; 11646 11647 struct mlx5_ifc_macsec_offload_obj_bits { 11648 u8 modify_field_select[0x40]; 11649 11650 u8 confidentiality_en[0x1]; 11651 u8 reserved_at_41[0x1]; 11652 u8 epn_en[0x1]; 11653 u8 epn_overlap[0x1]; 11654 u8 reserved_at_44[0x2]; 11655 u8 confidentiality_offset[0x2]; 11656 u8 reserved_at_48[0x4]; 11657 u8 aso_return_reg[0x4]; 11658 u8 reserved_at_50[0x10]; 11659 11660 u8 epn_msb[0x20]; 11661 11662 u8 reserved_at_80[0x8]; 11663 u8 dekn[0x18]; 11664 11665 u8 reserved_at_a0[0x20]; 11666 11667 u8 sci[0x40]; 11668 11669 u8 reserved_at_100[0x8]; 11670 u8 macsec_aso_access_pd[0x18]; 11671 11672 u8 reserved_at_120[0x60]; 11673 11674 u8 salt[3][0x20]; 11675 11676 u8 reserved_at_1e0[0x20]; 11677 11678 struct mlx5_ifc_macsec_aso_bits macsec_aso; 11679 }; 11680 11681 struct mlx5_ifc_create_macsec_obj_in_bits { 11682 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 11683 struct mlx5_ifc_macsec_offload_obj_bits macsec_object; 11684 }; 11685 11686 struct mlx5_ifc_modify_macsec_obj_in_bits { 11687 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 11688 struct mlx5_ifc_macsec_offload_obj_bits macsec_object; 11689 }; 11690 11691 enum { 11692 MLX5_MODIFY_MACSEC_BITMASK_EPN_OVERLAP = BIT(0), 11693 MLX5_MODIFY_MACSEC_BITMASK_EPN_MSB = BIT(1), 11694 }; 11695 11696 struct mlx5_ifc_query_macsec_obj_out_bits { 11697 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 11698 struct mlx5_ifc_macsec_offload_obj_bits macsec_object; 11699 }; 11700 11701 struct mlx5_ifc_encryption_key_obj_bits { 11702 u8 modify_field_select[0x40]; 11703 11704 u8 reserved_at_40[0x14]; 11705 u8 key_size[0x4]; 11706 u8 reserved_at_58[0x4]; 11707 u8 key_type[0x4]; 11708 11709 u8 reserved_at_60[0x8]; 11710 u8 pd[0x18]; 11711 11712 u8 reserved_at_80[0x180]; 11713 u8 key[8][0x20]; 11714 11715 u8 reserved_at_300[0x500]; 11716 }; 11717 11718 struct mlx5_ifc_create_encryption_key_in_bits { 11719 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 11720 struct mlx5_ifc_encryption_key_obj_bits encryption_key_object; 11721 }; 11722 11723 enum { 11724 MLX5_FLOW_METER_MODE_BYTES_IP_LENGTH = 0x0, 11725 MLX5_FLOW_METER_MODE_BYTES_CALC_WITH_L2 = 0x1, 11726 MLX5_FLOW_METER_MODE_BYTES_CALC_WITH_L2_IPG = 0x2, 11727 MLX5_FLOW_METER_MODE_NUM_PACKETS = 0x3, 11728 }; 11729 11730 struct mlx5_ifc_flow_meter_parameters_bits { 11731 u8 valid[0x1]; 11732 u8 bucket_overflow[0x1]; 11733 u8 start_color[0x2]; 11734 u8 both_buckets_on_green[0x1]; 11735 u8 reserved_at_5[0x1]; 11736 u8 meter_mode[0x2]; 11737 u8 reserved_at_8[0x18]; 11738 11739 u8 reserved_at_20[0x20]; 11740 11741 u8 reserved_at_40[0x3]; 11742 u8 cbs_exponent[0x5]; 11743 u8 cbs_mantissa[0x8]; 11744 u8 reserved_at_50[0x3]; 11745 u8 cir_exponent[0x5]; 11746 u8 cir_mantissa[0x8]; 11747 11748 u8 reserved_at_60[0x20]; 11749 11750 u8 reserved_at_80[0x3]; 11751 u8 ebs_exponent[0x5]; 11752 u8 ebs_mantissa[0x8]; 11753 u8 reserved_at_90[0x3]; 11754 u8 eir_exponent[0x5]; 11755 u8 eir_mantissa[0x8]; 11756 11757 u8 reserved_at_a0[0x60]; 11758 }; 11759 11760 struct mlx5_ifc_flow_meter_aso_obj_bits { 11761 u8 modify_field_select[0x40]; 11762 11763 u8 reserved_at_40[0x40]; 11764 11765 u8 reserved_at_80[0x8]; 11766 u8 meter_aso_access_pd[0x18]; 11767 11768 u8 reserved_at_a0[0x160]; 11769 11770 struct mlx5_ifc_flow_meter_parameters_bits flow_meter_parameters[2]; 11771 }; 11772 11773 struct mlx5_ifc_create_flow_meter_aso_obj_in_bits { 11774 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr; 11775 struct mlx5_ifc_flow_meter_aso_obj_bits flow_meter_aso_obj; 11776 }; 11777 11778 struct mlx5_ifc_sampler_obj_bits { 11779 u8 modify_field_select[0x40]; 11780 11781 u8 table_type[0x8]; 11782 u8 level[0x8]; 11783 u8 reserved_at_50[0xf]; 11784 u8 ignore_flow_level[0x1]; 11785 11786 u8 sample_ratio[0x20]; 11787 11788 u8 reserved_at_80[0x8]; 11789 u8 sample_table_id[0x18]; 11790 11791 u8 reserved_at_a0[0x8]; 11792 u8 default_table_id[0x18]; 11793 11794 u8 sw_steering_icm_address_rx[0x40]; 11795 u8 sw_steering_icm_address_tx[0x40]; 11796 11797 u8 reserved_at_140[0xa0]; 11798 }; 11799 11800 struct mlx5_ifc_create_sampler_obj_in_bits { 11801 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 11802 struct mlx5_ifc_sampler_obj_bits sampler_object; 11803 }; 11804 11805 struct mlx5_ifc_query_sampler_obj_out_bits { 11806 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr; 11807 struct mlx5_ifc_sampler_obj_bits sampler_object; 11808 }; 11809 11810 enum { 11811 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_128 = 0x0, 11812 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_KEY_SIZE_256 = 0x1, 11813 }; 11814 11815 enum { 11816 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_TLS = 0x1, 11817 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_IPSEC = 0x2, 11818 MLX5_GENERAL_OBJECT_TYPE_ENCRYPTION_KEY_TYPE_MACSEC = 0x4, 11819 }; 11820 11821 struct mlx5_ifc_tls_static_params_bits { 11822 u8 const_2[0x2]; 11823 u8 tls_version[0x4]; 11824 u8 const_1[0x2]; 11825 u8 reserved_at_8[0x14]; 11826 u8 encryption_standard[0x4]; 11827 11828 u8 reserved_at_20[0x20]; 11829 11830 u8 initial_record_number[0x40]; 11831 11832 u8 resync_tcp_sn[0x20]; 11833 11834 u8 gcm_iv[0x20]; 11835 11836 u8 implicit_iv[0x40]; 11837 11838 u8 reserved_at_100[0x8]; 11839 u8 dek_index[0x18]; 11840 11841 u8 reserved_at_120[0xe0]; 11842 }; 11843 11844 struct mlx5_ifc_tls_progress_params_bits { 11845 u8 next_record_tcp_sn[0x20]; 11846 11847 u8 hw_resync_tcp_sn[0x20]; 11848 11849 u8 record_tracker_state[0x2]; 11850 u8 auth_state[0x2]; 11851 u8 reserved_at_44[0x4]; 11852 u8 hw_offset_record_number[0x18]; 11853 }; 11854 11855 enum { 11856 MLX5_MTT_PERM_READ = 1 << 0, 11857 MLX5_MTT_PERM_WRITE = 1 << 1, 11858 MLX5_MTT_PERM_RW = MLX5_MTT_PERM_READ | MLX5_MTT_PERM_WRITE, 11859 }; 11860 11861 enum { 11862 MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_INITIATOR = 0x0, 11863 MLX5_SUSPEND_VHCA_IN_OP_MOD_SUSPEND_RESPONDER = 0x1, 11864 }; 11865 11866 struct mlx5_ifc_suspend_vhca_in_bits { 11867 u8 opcode[0x10]; 11868 u8 uid[0x10]; 11869 11870 u8 reserved_at_20[0x10]; 11871 u8 op_mod[0x10]; 11872 11873 u8 reserved_at_40[0x10]; 11874 u8 vhca_id[0x10]; 11875 11876 u8 reserved_at_60[0x20]; 11877 }; 11878 11879 struct mlx5_ifc_suspend_vhca_out_bits { 11880 u8 status[0x8]; 11881 u8 reserved_at_8[0x18]; 11882 11883 u8 syndrome[0x20]; 11884 11885 u8 reserved_at_40[0x40]; 11886 }; 11887 11888 enum { 11889 MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_RESPONDER = 0x0, 11890 MLX5_RESUME_VHCA_IN_OP_MOD_RESUME_INITIATOR = 0x1, 11891 }; 11892 11893 struct mlx5_ifc_resume_vhca_in_bits { 11894 u8 opcode[0x10]; 11895 u8 uid[0x10]; 11896 11897 u8 reserved_at_20[0x10]; 11898 u8 op_mod[0x10]; 11899 11900 u8 reserved_at_40[0x10]; 11901 u8 vhca_id[0x10]; 11902 11903 u8 reserved_at_60[0x20]; 11904 }; 11905 11906 struct mlx5_ifc_resume_vhca_out_bits { 11907 u8 status[0x8]; 11908 u8 reserved_at_8[0x18]; 11909 11910 u8 syndrome[0x20]; 11911 11912 u8 reserved_at_40[0x40]; 11913 }; 11914 11915 struct mlx5_ifc_query_vhca_migration_state_in_bits { 11916 u8 opcode[0x10]; 11917 u8 uid[0x10]; 11918 11919 u8 reserved_at_20[0x10]; 11920 u8 op_mod[0x10]; 11921 11922 u8 reserved_at_40[0x10]; 11923 u8 vhca_id[0x10]; 11924 11925 u8 reserved_at_60[0x20]; 11926 }; 11927 11928 struct mlx5_ifc_query_vhca_migration_state_out_bits { 11929 u8 status[0x8]; 11930 u8 reserved_at_8[0x18]; 11931 11932 u8 syndrome[0x20]; 11933 11934 u8 reserved_at_40[0x40]; 11935 11936 u8 required_umem_size[0x20]; 11937 11938 u8 reserved_at_a0[0x160]; 11939 }; 11940 11941 struct mlx5_ifc_save_vhca_state_in_bits { 11942 u8 opcode[0x10]; 11943 u8 uid[0x10]; 11944 11945 u8 reserved_at_20[0x10]; 11946 u8 op_mod[0x10]; 11947 11948 u8 reserved_at_40[0x10]; 11949 u8 vhca_id[0x10]; 11950 11951 u8 reserved_at_60[0x20]; 11952 11953 u8 va[0x40]; 11954 11955 u8 mkey[0x20]; 11956 11957 u8 size[0x20]; 11958 }; 11959 11960 struct mlx5_ifc_save_vhca_state_out_bits { 11961 u8 status[0x8]; 11962 u8 reserved_at_8[0x18]; 11963 11964 u8 syndrome[0x20]; 11965 11966 u8 actual_image_size[0x20]; 11967 11968 u8 reserved_at_60[0x20]; 11969 }; 11970 11971 struct mlx5_ifc_load_vhca_state_in_bits { 11972 u8 opcode[0x10]; 11973 u8 uid[0x10]; 11974 11975 u8 reserved_at_20[0x10]; 11976 u8 op_mod[0x10]; 11977 11978 u8 reserved_at_40[0x10]; 11979 u8 vhca_id[0x10]; 11980 11981 u8 reserved_at_60[0x20]; 11982 11983 u8 va[0x40]; 11984 11985 u8 mkey[0x20]; 11986 11987 u8 size[0x20]; 11988 }; 11989 11990 struct mlx5_ifc_load_vhca_state_out_bits { 11991 u8 status[0x8]; 11992 u8 reserved_at_8[0x18]; 11993 11994 u8 syndrome[0x20]; 11995 11996 u8 reserved_at_40[0x40]; 11997 }; 11998 11999 struct mlx5_ifc_adv_virtualization_cap_bits { 12000 u8 reserved_at_0[0x3]; 12001 u8 pg_track_log_max_num[0x5]; 12002 u8 pg_track_max_num_range[0x8]; 12003 u8 pg_track_log_min_addr_space[0x8]; 12004 u8 pg_track_log_max_addr_space[0x8]; 12005 12006 u8 reserved_at_20[0x3]; 12007 u8 pg_track_log_min_msg_size[0x5]; 12008 u8 reserved_at_28[0x3]; 12009 u8 pg_track_log_max_msg_size[0x5]; 12010 u8 reserved_at_30[0x3]; 12011 u8 pg_track_log_min_page_size[0x5]; 12012 u8 reserved_at_38[0x3]; 12013 u8 pg_track_log_max_page_size[0x5]; 12014 12015 u8 reserved_at_40[0x7c0]; 12016 }; 12017 12018 struct mlx5_ifc_page_track_report_entry_bits { 12019 u8 dirty_address_high[0x20]; 12020 12021 u8 dirty_address_low[0x20]; 12022 }; 12023 12024 enum { 12025 MLX5_PAGE_TRACK_STATE_TRACKING, 12026 MLX5_PAGE_TRACK_STATE_REPORTING, 12027 MLX5_PAGE_TRACK_STATE_ERROR, 12028 }; 12029 12030 struct mlx5_ifc_page_track_range_bits { 12031 u8 start_address[0x40]; 12032 12033 u8 length[0x40]; 12034 }; 12035 12036 struct mlx5_ifc_page_track_bits { 12037 u8 modify_field_select[0x40]; 12038 12039 u8 reserved_at_40[0x10]; 12040 u8 vhca_id[0x10]; 12041 12042 u8 reserved_at_60[0x20]; 12043 12044 u8 state[0x4]; 12045 u8 track_type[0x4]; 12046 u8 log_addr_space_size[0x8]; 12047 u8 reserved_at_90[0x3]; 12048 u8 log_page_size[0x5]; 12049 u8 reserved_at_98[0x3]; 12050 u8 log_msg_size[0x5]; 12051 12052 u8 reserved_at_a0[0x8]; 12053 u8 reporting_qpn[0x18]; 12054 12055 u8 reserved_at_c0[0x18]; 12056 u8 num_ranges[0x8]; 12057 12058 u8 reserved_at_e0[0x20]; 12059 12060 u8 range_start_address[0x40]; 12061 12062 u8 length[0x40]; 12063 12064 struct mlx5_ifc_page_track_range_bits track_range[0]; 12065 }; 12066 12067 struct mlx5_ifc_create_page_track_obj_in_bits { 12068 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12069 struct mlx5_ifc_page_track_bits obj_context; 12070 }; 12071 12072 struct mlx5_ifc_modify_page_track_obj_in_bits { 12073 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr; 12074 struct mlx5_ifc_page_track_bits obj_context; 12075 }; 12076 12077 #endif /* MLX5_IFC_H */ 12078