1 /*******************************************************************
2  * This file is part of the Emulex Linux Device Driver for         *
3  * Fibre Channel Host Bus Adapters.                                *
4  * Copyright (C) 2017-2022 Broadcom. All Rights Reserved. The term *
5  * “Broadcom” refers to Broadcom Inc. and/or its subsidiaries.     *
6  * Copyright (C) 2004-2016 Emulex.  All rights reserved.           *
7  * EMULEX and SLI are trademarks of Emulex.                        *
8  * www.broadcom.com                                                *
9  *                                                                 *
10  * This program is free software; you can redistribute it and/or   *
11  * modify it under the terms of version 2 of the GNU General       *
12  * Public License as published by the Free Software Foundation.    *
13  * This program is distributed in the hope that it will be useful. *
14  * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND          *
15  * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY,  *
16  * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE      *
17  * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD *
18  * TO BE LEGALLY INVALID.  See the GNU General Public License for  *
19  * more details, a copy of which can be found in the file COPYING  *
20  * included with this package.                                     *
21  *******************************************************************/
22 
23 #define FDMI_DID        0xfffffaU
24 #define NameServer_DID  0xfffffcU
25 #define Fabric_Cntl_DID 0xfffffdU
26 #define Fabric_DID      0xfffffeU
27 #define Bcast_DID       0xffffffU
28 #define Mask_DID        0xffffffU
29 #define CT_DID_MASK     0xffff00U
30 #define Fabric_DID_MASK 0xfff000U
31 #define WELL_KNOWN_DID_MASK 0xfffff0U
32 
33 #define PT2PT_LocalID	1
34 #define PT2PT_RemoteID	2
35 
36 #define FF_DEF_EDTOV          2000	/* Default E_D_TOV (2000ms) */
37 #define FF_DEF_ALTOV            15	/* Default AL_TIME (15ms) */
38 #define FF_DEF_RATOV            10	/* Default RA_TOV (10s) */
39 #define FF_DEF_ARBTOV         1900	/* Default ARB_TOV (1900ms) */
40 
41 #define LPFC_BUF_RING0        64	/* Number of buffers to post to RING
42 					   0 */
43 
44 #define FCELSSIZE             1024	/* maximum ELS transfer size */
45 
46 #define LPFC_FCP_RING            0	/* ring 0 for FCP initiator commands */
47 #define LPFC_EXTRA_RING          1	/* ring 1 for other protocols */
48 #define LPFC_ELS_RING            2	/* ring 2 for ELS commands */
49 
50 #define SLI2_IOCB_CMD_R0_ENTRIES    172	/* SLI-2 FCP command ring entries */
51 #define SLI2_IOCB_RSP_R0_ENTRIES    134	/* SLI-2 FCP response ring entries */
52 #define SLI2_IOCB_CMD_R1_ENTRIES      4	/* SLI-2 extra command ring entries */
53 #define SLI2_IOCB_RSP_R1_ENTRIES      4	/* SLI-2 extra response ring entries */
54 #define SLI2_IOCB_CMD_R1XTRA_ENTRIES 36	/* SLI-2 extra FCP cmd ring entries */
55 #define SLI2_IOCB_RSP_R1XTRA_ENTRIES 52	/* SLI-2 extra FCP rsp ring entries */
56 #define SLI2_IOCB_CMD_R2_ENTRIES     20	/* SLI-2 ELS command ring entries */
57 #define SLI2_IOCB_RSP_R2_ENTRIES     20	/* SLI-2 ELS response ring entries */
58 #define SLI2_IOCB_CMD_R3_ENTRIES      0
59 #define SLI2_IOCB_RSP_R3_ENTRIES      0
60 #define SLI2_IOCB_CMD_R3XTRA_ENTRIES 24
61 #define SLI2_IOCB_RSP_R3XTRA_ENTRIES 32
62 
63 #define SLI2_IOCB_CMD_SIZE	32
64 #define SLI2_IOCB_RSP_SIZE	32
65 #define SLI3_IOCB_CMD_SIZE	128
66 #define SLI3_IOCB_RSP_SIZE	64
67 
68 #define LPFC_UNREG_ALL_RPIS_VPORT	0xffff
69 #define LPFC_UNREG_ALL_DFLT_RPIS	0xffffffff
70 
71 /* vendor ID used in SCSI netlink calls */
72 #define LPFC_NL_VENDOR_ID (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_EMULEX)
73 
74 #define FW_REV_STR_SIZE	32
75 /* Common Transport structures and definitions */
76 
77 union CtRevisionId {
78 	/* Structure is in Big Endian format */
79 	struct {
80 		uint32_t Revision:8;
81 		uint32_t InId:24;
82 	} bits;
83 	uint32_t word;
84 };
85 
86 union CtCommandResponse {
87 	/* Structure is in Big Endian format */
88 	struct {
89 		uint32_t CmdRsp:16;
90 		uint32_t Size:16;
91 	} bits;
92 	uint32_t word;
93 };
94 
95 /* FC4 Feature bits for RFF_ID */
96 #define FC4_FEATURE_TARGET	0x1
97 #define FC4_FEATURE_INIT	0x2
98 #define FC4_FEATURE_NVME_DISC	0x4
99 
100 enum rft_word0 {
101 	RFT_FCP_REG	= (0x1 << 8),
102 };
103 
104 enum rft_word1 {
105 	RFT_NVME_REG	= (0x1 << 8),
106 };
107 
108 enum rft_word3 {
109 	RFT_APP_SERV_REG	= (0x1 << 0),
110 };
111 
112 struct lpfc_sli_ct_request {
113 	/* Structure is in Big Endian format */
114 	union CtRevisionId RevisionId;
115 	uint8_t FsType;
116 	uint8_t FsSubType;
117 	uint8_t Options;
118 	uint8_t Rsrvd1;
119 	union CtCommandResponse CommandResponse;
120 	uint8_t Rsrvd2;
121 	uint8_t ReasonCode;
122 	uint8_t Explanation;
123 	uint8_t VendorUnique;
124 #define LPFC_CT_PREAMBLE	20	/* Size of CTReq + 4 up to here */
125 
126 	union {
127 		uint32_t PortID;
128 		struct gid {
129 			uint8_t PortType;	/* for GID_PT requests */
130 #define GID_PT_N_PORT	1
131 			uint8_t DomainScope;
132 			uint8_t AreaScope;
133 			uint8_t Fc4Type;	/* for GID_FT requests */
134 		} gid;
135 		struct gid_ff {
136 			uint8_t Flags;
137 			uint8_t DomainScope;
138 			uint8_t AreaScope;
139 			uint8_t rsvd1;
140 			uint8_t rsvd2;
141 			uint8_t rsvd3;
142 			uint8_t Fc4FBits;
143 			uint8_t Fc4Type;
144 		} gid_ff;
145 		struct rft {
146 			__be32 port_id; /* For RFT_ID requests */
147 
148 			__be32 fcp_reg;	/* rsvd 31:9, fcp_reg 8, rsvd 7:0 */
149 			__be32 nvme_reg; /* rsvd 31:9, nvme_reg 8, rsvd 7:0 */
150 			__be32 word2;
151 			__be32 app_serv_reg; /* rsvd 31:1, app_serv_reg 0 */
152 			__be32 word[4];
153 		} rft;
154 		struct rnn {
155 			uint32_t PortId;	/* For RNN_ID requests */
156 			uint8_t wwnn[8];
157 		} rnn;
158 		struct rsnn {	/* For RSNN_ID requests */
159 			uint8_t wwnn[8];
160 			uint8_t len;
161 			uint8_t symbname[255];
162 		} rsnn;
163 		struct da_id { /* For DA_ID requests */
164 			uint32_t port_id;
165 		} da_id;
166 		struct rspn {	/* For RSPN_ID requests */
167 			uint32_t PortId;
168 			uint8_t len;
169 			uint8_t symbname[255];
170 		} rspn;
171 		struct gff {
172 			uint32_t PortId;
173 		} gff;
174 		struct gff_acc {
175 			uint8_t fbits[128];
176 		} gff_acc;
177 		struct gft {
178 			uint32_t PortId;
179 		} gft;
180 		struct gft_acc {
181 			uint32_t fc4_types[8];
182 		} gft_acc;
183 #define FCP_TYPE_FEATURE_OFFSET 7
184 		struct rff {
185 			uint32_t PortId;
186 			uint8_t reserved[2];
187 			uint8_t fbits;
188 			uint8_t type_code;     /* type=8 for FCP */
189 		} rff;
190 	} un;
191 };
192 
193 #define LPFC_MAX_CT_SIZE	(60 * 4096)
194 
195 #define  SLI_CT_REVISION        1
196 #define  GID_REQUEST_SZ   (offsetof(struct lpfc_sli_ct_request, un) + \
197 			   sizeof(struct gid))
198 #define  GIDFF_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
199 			   sizeof(struct gid_ff))
200 #define  GFF_REQUEST_SZ   (offsetof(struct lpfc_sli_ct_request, un) + \
201 			   sizeof(struct gff))
202 #define  GFT_REQUEST_SZ   (offsetof(struct lpfc_sli_ct_request, un) + \
203 			   sizeof(struct gft))
204 #define  RFT_REQUEST_SZ   (offsetof(struct lpfc_sli_ct_request, un) + \
205 			   sizeof(struct rft))
206 #define  RFF_REQUEST_SZ   (offsetof(struct lpfc_sli_ct_request, un) + \
207 			   sizeof(struct rff))
208 #define  RNN_REQUEST_SZ   (offsetof(struct lpfc_sli_ct_request, un) + \
209 			   sizeof(struct rnn))
210 #define  RSNN_REQUEST_SZ  (offsetof(struct lpfc_sli_ct_request, un) + \
211 			   sizeof(struct rsnn))
212 #define DA_ID_REQUEST_SZ (offsetof(struct lpfc_sli_ct_request, un) + \
213 			  sizeof(struct da_id))
214 #define  RSPN_REQUEST_SZ  (offsetof(struct lpfc_sli_ct_request, un) + \
215 			   sizeof(struct rspn))
216 
217 /*
218  * FsType Definitions
219  */
220 
221 #define  SLI_CT_MANAGEMENT_SERVICE        0xFA
222 #define  SLI_CT_TIME_SERVICE              0xFB
223 #define  SLI_CT_DIRECTORY_SERVICE         0xFC
224 #define  SLI_CT_FABRIC_CONTROLLER_SERVICE 0xFD
225 
226 /*
227  * Directory Service Subtypes
228  */
229 
230 #define  SLI_CT_DIRECTORY_NAME_SERVER     0x02
231 
232 /*
233  * Response Codes
234  */
235 
236 #define  SLI_CT_RESPONSE_FS_RJT           0x8001
237 #define  SLI_CT_RESPONSE_FS_ACC           0x8002
238 
239 /*
240  * Reason Codes
241  */
242 
243 #define  SLI_CT_NO_ADDITIONAL_EXPL	  0x0
244 #define  SLI_CT_INVALID_COMMAND           0x01
245 #define  SLI_CT_INVALID_VERSION           0x02
246 #define  SLI_CT_LOGICAL_ERROR             0x03
247 #define  SLI_CT_INVALID_IU_SIZE           0x04
248 #define  SLI_CT_LOGICAL_BUSY              0x05
249 #define  SLI_CT_PROTOCOL_ERROR            0x07
250 #define  SLI_CT_UNABLE_TO_PERFORM_REQ     0x09
251 #define  SLI_CT_REQ_NOT_SUPPORTED         0x0b
252 #define  SLI_CT_HBA_INFO_NOT_REGISTERED	  0x10
253 #define  SLI_CT_MULTIPLE_HBA_ATTR_OF_SAME_TYPE  0x11
254 #define  SLI_CT_INVALID_HBA_ATTR_BLOCK_LEN      0x12
255 #define  SLI_CT_HBA_ATTR_NOT_PRESENT	  0x13
256 #define  SLI_CT_PORT_INFO_NOT_REGISTERED  0x20
257 #define  SLI_CT_MULTIPLE_PORT_ATTR_OF_SAME_TYPE 0x21
258 #define  SLI_CT_INVALID_PORT_ATTR_BLOCK_LEN     0x22
259 #define  SLI_CT_VENDOR_UNIQUE             0xff
260 
261 /*
262  * Name Server SLI_CT_UNABLE_TO_PERFORM_REQ Explanations
263  */
264 
265 #define  SLI_CT_NO_PORT_ID                0x01
266 #define  SLI_CT_NO_PORT_NAME              0x02
267 #define  SLI_CT_NO_NODE_NAME              0x03
268 #define  SLI_CT_NO_CLASS_OF_SERVICE       0x04
269 #define  SLI_CT_NO_IP_ADDRESS             0x05
270 #define  SLI_CT_NO_IPA                    0x06
271 #define  SLI_CT_NO_FC4_TYPES              0x07
272 #define  SLI_CT_NO_SYMBOLIC_PORT_NAME     0x08
273 #define  SLI_CT_NO_SYMBOLIC_NODE_NAME     0x09
274 #define  SLI_CT_NO_PORT_TYPE              0x0A
275 #define  SLI_CT_ACCESS_DENIED             0x10
276 #define  SLI_CT_INVALID_PORT_ID           0x11
277 #define  SLI_CT_DATABASE_EMPTY            0x12
278 #define  SLI_CT_APP_ID_NOT_AVAILABLE      0x40
279 
280 /*
281  * Name Server Command Codes
282  */
283 
284 #define  SLI_CTNS_GA_NXT      0x0100
285 #define  SLI_CTNS_GPN_ID      0x0112
286 #define  SLI_CTNS_GNN_ID      0x0113
287 #define  SLI_CTNS_GCS_ID      0x0114
288 #define  SLI_CTNS_GFT_ID      0x0117
289 #define  SLI_CTNS_GSPN_ID     0x0118
290 #define  SLI_CTNS_GPT_ID      0x011A
291 #define  SLI_CTNS_GFF_ID      0x011F
292 #define  SLI_CTNS_GID_PN      0x0121
293 #define  SLI_CTNS_GID_NN      0x0131
294 #define  SLI_CTNS_GIP_NN      0x0135
295 #define  SLI_CTNS_GIPA_NN     0x0136
296 #define  SLI_CTNS_GSNN_NN     0x0139
297 #define  SLI_CTNS_GNN_IP      0x0153
298 #define  SLI_CTNS_GIPA_IP     0x0156
299 #define  SLI_CTNS_GID_FT      0x0171
300 #define  SLI_CTNS_GID_FF      0x01F1
301 #define  SLI_CTNS_GID_PT      0x01A1
302 #define  SLI_CTNS_RPN_ID      0x0212
303 #define  SLI_CTNS_RNN_ID      0x0213
304 #define  SLI_CTNS_RCS_ID      0x0214
305 #define  SLI_CTNS_RFT_ID      0x0217
306 #define  SLI_CTNS_RSPN_ID     0x0218
307 #define  SLI_CTNS_RPT_ID      0x021A
308 #define  SLI_CTNS_RFF_ID      0x021F
309 #define  SLI_CTNS_RIP_NN      0x0235
310 #define  SLI_CTNS_RIPA_NN     0x0236
311 #define  SLI_CTNS_RSNN_NN     0x0239
312 #define  SLI_CTNS_DA_ID       0x0300
313 
314 /*
315  * Port Types
316  */
317 
318 #define SLI_CTPT_N_PORT		0x01
319 #define SLI_CTPT_NL_PORT	0x02
320 #define SLI_CTPT_FNL_PORT	0x03
321 #define SLI_CTPT_IP		0x04
322 #define SLI_CTPT_FCP		0x08
323 #define SLI_CTPT_NVME		0x28
324 #define SLI_CTPT_NX_PORT	0x7F
325 #define SLI_CTPT_F_PORT		0x81
326 #define SLI_CTPT_FL_PORT	0x82
327 #define SLI_CTPT_E_PORT		0x84
328 
329 #define SLI_CT_LAST_ENTRY     0x80000000
330 
331 /* Fibre Channel Service Parameter definitions */
332 
333 #define FC_PH_4_0   6		/* FC-PH version 4.0 */
334 #define FC_PH_4_1   7		/* FC-PH version 4.1 */
335 #define FC_PH_4_2   8		/* FC-PH version 4.2 */
336 #define FC_PH_4_3   9		/* FC-PH version 4.3 */
337 
338 #define FC_PH_LOW   8		/* Lowest supported FC-PH version */
339 #define FC_PH_HIGH  9		/* Highest supported FC-PH version */
340 #define FC_PH3   0x20		/* FC-PH-3 version */
341 
342 #define FF_FRAME_SIZE     2048
343 
344 struct lpfc_name {
345 	union {
346 		struct {
347 #ifdef __BIG_ENDIAN_BITFIELD
348 			uint8_t nameType:4;	/* FC Word 0, bit 28:31 */
349 			uint8_t IEEEextMsn:4;	/* FC Word 0, bit 24:27, bit
350 						   8:11 of IEEE ext */
351 #else	/*  __LITTLE_ENDIAN_BITFIELD */
352 			uint8_t IEEEextMsn:4;	/* FC Word 0, bit 24:27, bit
353 						   8:11 of IEEE ext */
354 			uint8_t nameType:4;	/* FC Word 0, bit 28:31 */
355 #endif
356 
357 #define NAME_IEEE           0x1	/* IEEE name - nameType */
358 #define NAME_IEEE_EXT       0x2	/* IEEE extended name */
359 #define NAME_FC_TYPE        0x3	/* FC native name type */
360 #define NAME_IP_TYPE        0x4	/* IP address */
361 #define NAME_CCITT_TYPE     0xC
362 #define NAME_CCITT_GR_TYPE  0xE
363 			uint8_t IEEEextLsb;	/* FC Word 0, bit 16:23, IEEE
364 						   extended Lsb */
365 			uint8_t IEEE[6];	/* FC IEEE address */
366 		} s;
367 		uint8_t wwn[8];
368 		uint64_t name;
369 	} u;
370 };
371 
372 struct csp {
373 	uint8_t fcphHigh;	/* FC Word 0, byte 0 */
374 	uint8_t fcphLow;
375 	uint8_t bbCreditMsb;
376 	uint8_t bbCreditLsb;	/* FC Word 0, byte 3 */
377 
378 /*
379  * Word 1 Bit 31 in common service parameter is overloaded.
380  * Word 1 Bit 31 in FLOGI request is multiple NPort request
381  * Word 1 Bit 31 in FLOGI response is clean address bit
382  */
383 #define clean_address_bit request_multiple_Nport /* Word 1, bit 31 */
384 /*
385  * Word 1 Bit 30 in common service parameter is overloaded.
386  * Word 1 Bit 30 in FLOGI request is Virtual Fabrics
387  * Word 1 Bit 30 in PLOGI request is random offset
388  */
389 #define virtual_fabric_support randomOffset /* Word 1, bit 30 */
390 /*
391  * Word 1 Bit 29 in common service parameter is overloaded.
392  * Word 1 Bit 29 in FLOGI response is multiple NPort assignment
393  * Word 1 Bit 29 in FLOGI/PLOGI request is Valid Vendor Version Level
394  */
395 #define valid_vendor_ver_level response_multiple_NPort /* Word 1, bit 29 */
396 #ifdef __BIG_ENDIAN_BITFIELD
397 	uint16_t request_multiple_Nport:1;	/* FC Word 1, bit 31 */
398 	uint16_t randomOffset:1;	/* FC Word 1, bit 30 */
399 	uint16_t response_multiple_NPort:1;	/* FC Word 1, bit 29 */
400 	uint16_t fPort:1;	/* FC Word 1, bit 28 */
401 	uint16_t altBbCredit:1;	/* FC Word 1, bit 27 */
402 	uint16_t edtovResolution:1;	/* FC Word 1, bit 26 */
403 	uint16_t multicast:1;	/* FC Word 1, bit 25 */
404 	uint16_t app_hdr_support:1;	/* FC Word 1, bit 24 */
405 
406 	uint16_t priority_tagging:1;	/* FC Word 1, bit 23 */
407 	uint16_t simplex:1;	/* FC Word 1, bit 22 */
408 	uint16_t word1Reserved1:3;	/* FC Word 1, bit 21:19 */
409 	uint16_t dhd:1;		/* FC Word 1, bit 18 */
410 	uint16_t contIncSeqCnt:1;	/* FC Word 1, bit 17 */
411 	uint16_t payloadlength:1;	/* FC Word 1, bit 16 */
412 #else	/*  __LITTLE_ENDIAN_BITFIELD */
413 	uint16_t app_hdr_support:1;	/* FC Word 1, bit 24 */
414 	uint16_t multicast:1;	/* FC Word 1, bit 25 */
415 	uint16_t edtovResolution:1;	/* FC Word 1, bit 26 */
416 	uint16_t altBbCredit:1;	/* FC Word 1, bit 27 */
417 	uint16_t fPort:1;	/* FC Word 1, bit 28 */
418 	uint16_t response_multiple_NPort:1;	/* FC Word 1, bit 29 */
419 	uint16_t randomOffset:1;	/* FC Word 1, bit 30 */
420 	uint16_t request_multiple_Nport:1;	/* FC Word 1, bit 31 */
421 
422 	uint16_t payloadlength:1;	/* FC Word 1, bit 16 */
423 	uint16_t contIncSeqCnt:1;	/* FC Word 1, bit 17 */
424 	uint16_t dhd:1;		/* FC Word 1, bit 18 */
425 	uint16_t word1Reserved1:3;	/* FC Word 1, bit 21:19 */
426 	uint16_t simplex:1;	/* FC Word 1, bit 22 */
427 	uint16_t priority_tagging:1;	/* FC Word 1, bit 23 */
428 #endif
429 
430 	uint8_t bbRcvSizeMsb;	/* Upper nibble is reserved */
431 	uint8_t bbRcvSizeLsb;	/* FC Word 1, byte 3 */
432 	union {
433 		struct {
434 			uint8_t word2Reserved1;	/* FC Word 2 byte 0 */
435 
436 			uint8_t totalConcurrSeq;	/* FC Word 2 byte 1 */
437 			uint8_t roByCategoryMsb;	/* FC Word 2 byte 2 */
438 
439 			uint8_t roByCategoryLsb;	/* FC Word 2 byte 3 */
440 		} nPort;
441 		uint32_t r_a_tov;	/* R_A_TOV must be in B.E. format */
442 	} w2;
443 
444 	uint32_t e_d_tov;	/* E_D_TOV must be in B.E. format */
445 };
446 
447 struct class_parms {
448 #ifdef __BIG_ENDIAN_BITFIELD
449 	uint8_t classValid:1;	/* FC Word 0, bit 31 */
450 	uint8_t intermix:1;	/* FC Word 0, bit 30 */
451 	uint8_t stackedXparent:1;	/* FC Word 0, bit 29 */
452 	uint8_t stackedLockDown:1;	/* FC Word 0, bit 28 */
453 	uint8_t seqDelivery:1;	/* FC Word 0, bit 27 */
454 	uint8_t word0Reserved1:3;	/* FC Word 0, bit 24:26 */
455 #else	/*  __LITTLE_ENDIAN_BITFIELD */
456 	uint8_t word0Reserved1:3;	/* FC Word 0, bit 24:26 */
457 	uint8_t seqDelivery:1;	/* FC Word 0, bit 27 */
458 	uint8_t stackedLockDown:1;	/* FC Word 0, bit 28 */
459 	uint8_t stackedXparent:1;	/* FC Word 0, bit 29 */
460 	uint8_t intermix:1;	/* FC Word 0, bit 30 */
461 	uint8_t classValid:1;	/* FC Word 0, bit 31 */
462 
463 #endif
464 
465 	uint8_t word0Reserved2;	/* FC Word 0, bit 16:23 */
466 
467 #ifdef __BIG_ENDIAN_BITFIELD
468 	uint8_t iCtlXidReAssgn:2;	/* FC Word 0, Bit 14:15 */
469 	uint8_t iCtlInitialPa:2;	/* FC Word 0, bit 12:13 */
470 	uint8_t iCtlAck0capable:1;	/* FC Word 0, bit 11 */
471 	uint8_t iCtlAckNcapable:1;	/* FC Word 0, bit 10 */
472 	uint8_t word0Reserved3:2;	/* FC Word 0, bit  8: 9 */
473 #else	/*  __LITTLE_ENDIAN_BITFIELD */
474 	uint8_t word0Reserved3:2;	/* FC Word 0, bit  8: 9 */
475 	uint8_t iCtlAckNcapable:1;	/* FC Word 0, bit 10 */
476 	uint8_t iCtlAck0capable:1;	/* FC Word 0, bit 11 */
477 	uint8_t iCtlInitialPa:2;	/* FC Word 0, bit 12:13 */
478 	uint8_t iCtlXidReAssgn:2;	/* FC Word 0, Bit 14:15 */
479 #endif
480 
481 	uint8_t word0Reserved4;	/* FC Word 0, bit  0: 7 */
482 
483 #ifdef __BIG_ENDIAN_BITFIELD
484 	uint8_t rCtlAck0capable:1;	/* FC Word 1, bit 31 */
485 	uint8_t rCtlAckNcapable:1;	/* FC Word 1, bit 30 */
486 	uint8_t rCtlXidInterlck:1;	/* FC Word 1, bit 29 */
487 	uint8_t rCtlErrorPolicy:2;	/* FC Word 1, bit 27:28 */
488 	uint8_t word1Reserved1:1;	/* FC Word 1, bit 26 */
489 	uint8_t rCtlCatPerSeq:2;	/* FC Word 1, bit 24:25 */
490 #else	/*  __LITTLE_ENDIAN_BITFIELD */
491 	uint8_t rCtlCatPerSeq:2;	/* FC Word 1, bit 24:25 */
492 	uint8_t word1Reserved1:1;	/* FC Word 1, bit 26 */
493 	uint8_t rCtlErrorPolicy:2;	/* FC Word 1, bit 27:28 */
494 	uint8_t rCtlXidInterlck:1;	/* FC Word 1, bit 29 */
495 	uint8_t rCtlAckNcapable:1;	/* FC Word 1, bit 30 */
496 	uint8_t rCtlAck0capable:1;	/* FC Word 1, bit 31 */
497 #endif
498 
499 	uint8_t word1Reserved2;	/* FC Word 1, bit 16:23 */
500 	uint8_t rcvDataSizeMsb;	/* FC Word 1, bit  8:15 */
501 	uint8_t rcvDataSizeLsb;	/* FC Word 1, bit  0: 7 */
502 
503 	uint8_t concurrentSeqMsb;	/* FC Word 2, bit 24:31 */
504 	uint8_t concurrentSeqLsb;	/* FC Word 2, bit 16:23 */
505 	uint8_t EeCreditSeqMsb;	/* FC Word 2, bit  8:15 */
506 	uint8_t EeCreditSeqLsb;	/* FC Word 2, bit  0: 7 */
507 
508 	uint8_t openSeqPerXchgMsb;	/* FC Word 3, bit 24:31 */
509 	uint8_t openSeqPerXchgLsb;	/* FC Word 3, bit 16:23 */
510 	uint8_t word3Reserved1;	/* Fc Word 3, bit  8:15 */
511 	uint8_t word3Reserved2;	/* Fc Word 3, bit  0: 7 */
512 };
513 
514 struct serv_parm {	/* Structure is in Big Endian format */
515 	struct csp cmn;
516 	struct lpfc_name portName;
517 	struct lpfc_name nodeName;
518 	struct class_parms cls1;
519 	struct class_parms cls2;
520 	struct class_parms cls3;
521 	struct class_parms cls4;
522 	union {
523 		uint8_t vendorVersion[16];
524 		struct {
525 			uint32_t vid;
526 #define LPFC_VV_EMLX_ID	0x454d4c58	/* EMLX */
527 			uint32_t flags;
528 #define LPFC_VV_SUPPRESS_RSP	1
529 		} vv;
530 	} un;
531 };
532 
533 /*
534  * Virtual Fabric Tagging Header
535  */
536 struct fc_vft_header {
537 	 uint32_t word0;
538 #define fc_vft_hdr_r_ctl_SHIFT		24
539 #define fc_vft_hdr_r_ctl_MASK		0xFF
540 #define fc_vft_hdr_r_ctl_WORD		word0
541 #define fc_vft_hdr_ver_SHIFT		22
542 #define fc_vft_hdr_ver_MASK		0x3
543 #define fc_vft_hdr_ver_WORD		word0
544 #define fc_vft_hdr_type_SHIFT		18
545 #define fc_vft_hdr_type_MASK		0xF
546 #define fc_vft_hdr_type_WORD		word0
547 #define fc_vft_hdr_e_SHIFT		16
548 #define fc_vft_hdr_e_MASK		0x1
549 #define fc_vft_hdr_e_WORD		word0
550 #define fc_vft_hdr_priority_SHIFT	13
551 #define fc_vft_hdr_priority_MASK	0x7
552 #define fc_vft_hdr_priority_WORD	word0
553 #define fc_vft_hdr_vf_id_SHIFT		1
554 #define fc_vft_hdr_vf_id_MASK		0xFFF
555 #define fc_vft_hdr_vf_id_WORD		word0
556 	uint32_t word1;
557 #define fc_vft_hdr_hopct_SHIFT		24
558 #define fc_vft_hdr_hopct_MASK		0xFF
559 #define fc_vft_hdr_hopct_WORD		word1
560 };
561 
562 #include <uapi/scsi/fc/fc_els.h>
563 
564 /*
565  *  Extended Link Service LS_COMMAND codes (Payload Word 0)
566  */
567 #ifdef __BIG_ENDIAN_BITFIELD
568 #define ELS_CMD_MASK      0xffff0000
569 #define ELS_RSP_MASK      0xff000000
570 #define ELS_CMD_LS_RJT    0x01000000
571 #define ELS_CMD_ACC       0x02000000
572 #define ELS_CMD_PLOGI     0x03000000
573 #define ELS_CMD_FLOGI     0x04000000
574 #define ELS_CMD_LOGO      0x05000000
575 #define ELS_CMD_ABTX      0x06000000
576 #define ELS_CMD_RCS       0x07000000
577 #define ELS_CMD_RES       0x08000000
578 #define ELS_CMD_RSS       0x09000000
579 #define ELS_CMD_RSI       0x0A000000
580 #define ELS_CMD_ESTS      0x0B000000
581 #define ELS_CMD_ESTC      0x0C000000
582 #define ELS_CMD_ADVC      0x0D000000
583 #define ELS_CMD_RTV       0x0E000000
584 #define ELS_CMD_RLS       0x0F000000
585 #define ELS_CMD_ECHO      0x10000000
586 #define ELS_CMD_TEST      0x11000000
587 #define ELS_CMD_RRQ       0x12000000
588 #define ELS_CMD_REC       0x13000000
589 #define ELS_CMD_RDP       0x18000000
590 #define ELS_CMD_RDF       0x19000000
591 #define ELS_CMD_PRLI      0x20100014
592 #define ELS_CMD_NVMEPRLI  0x20140018
593 #define ELS_CMD_PRLO      0x21100014
594 #define ELS_CMD_PRLO_ACC  0x02100014
595 #define ELS_CMD_PDISC     0x50000000
596 #define ELS_CMD_FDISC     0x51000000
597 #define ELS_CMD_ADISC     0x52000000
598 #define ELS_CMD_FARP      0x54000000
599 #define ELS_CMD_FARPR     0x55000000
600 #define ELS_CMD_RPL       0x57000000
601 #define ELS_CMD_FAN       0x60000000
602 #define ELS_CMD_RSCN      0x61040000
603 #define ELS_CMD_RSCN_XMT  0x61040008
604 #define ELS_CMD_SCR       0x62000000
605 #define ELS_CMD_RNID      0x78000000
606 #define ELS_CMD_LIRR      0x7A000000
607 #define ELS_CMD_LCB	  0x81000000
608 #define ELS_CMD_FPIN	  0x16000000
609 #define ELS_CMD_EDC	  0x17000000
610 #define ELS_CMD_QFPA      0xB0000000
611 #define ELS_CMD_UVEM      0xB1000000
612 #else	/*  __LITTLE_ENDIAN_BITFIELD */
613 #define ELS_CMD_MASK      0xffff
614 #define ELS_RSP_MASK      0xff
615 #define ELS_CMD_LS_RJT    0x01
616 #define ELS_CMD_ACC       0x02
617 #define ELS_CMD_PLOGI     0x03
618 #define ELS_CMD_FLOGI     0x04
619 #define ELS_CMD_LOGO      0x05
620 #define ELS_CMD_ABTX      0x06
621 #define ELS_CMD_RCS       0x07
622 #define ELS_CMD_RES       0x08
623 #define ELS_CMD_RSS       0x09
624 #define ELS_CMD_RSI       0x0A
625 #define ELS_CMD_ESTS      0x0B
626 #define ELS_CMD_ESTC      0x0C
627 #define ELS_CMD_ADVC      0x0D
628 #define ELS_CMD_RTV       0x0E
629 #define ELS_CMD_RLS       0x0F
630 #define ELS_CMD_ECHO      0x10
631 #define ELS_CMD_TEST      0x11
632 #define ELS_CMD_RRQ       0x12
633 #define ELS_CMD_REC       0x13
634 #define ELS_CMD_RDP	  0x18
635 #define ELS_CMD_RDF	  0x19
636 #define ELS_CMD_PRLI      0x14001020
637 #define ELS_CMD_NVMEPRLI  0x18001420
638 #define ELS_CMD_PRLO      0x14001021
639 #define ELS_CMD_PRLO_ACC  0x14001002
640 #define ELS_CMD_PDISC     0x50
641 #define ELS_CMD_FDISC     0x51
642 #define ELS_CMD_ADISC     0x52
643 #define ELS_CMD_FARP      0x54
644 #define ELS_CMD_FARPR     0x55
645 #define ELS_CMD_RPL       0x57
646 #define ELS_CMD_FAN       0x60
647 #define ELS_CMD_RSCN      0x0461
648 #define ELS_CMD_RSCN_XMT  0x08000461
649 #define ELS_CMD_SCR       0x62
650 #define ELS_CMD_RNID      0x78
651 #define ELS_CMD_LIRR      0x7A
652 #define ELS_CMD_LCB	  0x81
653 #define ELS_CMD_FPIN	  ELS_FPIN
654 #define ELS_CMD_EDC	  ELS_EDC
655 #define ELS_CMD_QFPA      0xB0
656 #define ELS_CMD_UVEM      0xB1
657 #endif
658 
659 /*
660  *  LS_RJT Payload Definition
661  */
662 
663 struct ls_rjt {	/* Structure is in Big Endian format */
664 	union {
665 		__be32 ls_rjt_error_be;
666 		uint32_t lsRjtError;
667 		struct {
668 			uint8_t lsRjtRsvd0;	/* FC Word 0, bit 24:31 */
669 
670 			uint8_t lsRjtRsnCode;	/* FC Word 0, bit 16:23 */
671 			/* LS_RJT reason codes */
672 #define LSRJT_INVALID_CMD     0x01
673 #define LSRJT_LOGICAL_ERR     0x03
674 #define LSRJT_LOGICAL_BSY     0x05
675 #define LSRJT_PROTOCOL_ERR    0x07
676 #define LSRJT_UNABLE_TPC      0x09	/* Unable to perform command */
677 #define LSRJT_CMD_UNSUPPORTED 0x0B
678 #define LSRJT_VENDOR_UNIQUE   0xFF	/* See Byte 3 */
679 
680 			uint8_t lsRjtRsnCodeExp; /* FC Word 0, bit 8:15 */
681 			/* LS_RJT reason explanation */
682 #define LSEXP_NOTHING_MORE      0x00
683 #define LSEXP_SPARM_OPTIONS     0x01
684 #define LSEXP_SPARM_ICTL        0x03
685 #define LSEXP_SPARM_RCTL        0x05
686 #define LSEXP_SPARM_RCV_SIZE    0x07
687 #define LSEXP_SPARM_CONCUR_SEQ  0x09
688 #define LSEXP_SPARM_CREDIT      0x0B
689 #define LSEXP_INVALID_PNAME     0x0D
690 #define LSEXP_INVALID_NNAME     0x0E
691 #define LSEXP_INVALID_CSP       0x0F
692 #define LSEXP_INVALID_ASSOC_HDR 0x11
693 #define LSEXP_ASSOC_HDR_REQ     0x13
694 #define LSEXP_INVALID_O_SID     0x15
695 #define LSEXP_INVALID_OX_RX     0x17
696 #define LSEXP_CMD_IN_PROGRESS   0x19
697 #define LSEXP_PORT_LOGIN_REQ    0x1E
698 #define LSEXP_INVALID_NPORT_ID  0x1F
699 #define LSEXP_INVALID_SEQ_ID    0x21
700 #define LSEXP_INVALID_XCHG      0x23
701 #define LSEXP_INACTIVE_XCHG     0x25
702 #define LSEXP_RQ_REQUIRED       0x27
703 #define LSEXP_OUT_OF_RESOURCE   0x29
704 #define LSEXP_CANT_GIVE_DATA    0x2A
705 #define LSEXP_REQ_UNSUPPORTED   0x2C
706 #define LSEXP_NO_RSRC_ASSIGN    0x52
707 			uint8_t vendorUnique;	/* FC Word 0, bit  0: 7 */
708 		} b;
709 	} un;
710 };
711 
712 /*
713  *  N_Port Login (FLOGO/PLOGO Request) Payload Definition
714  */
715 
716 typedef struct _LOGO {		/* Structure is in Big Endian format */
717 	union {
718 		uint32_t nPortId32;	/* Access nPortId as a word */
719 		struct {
720 			uint8_t word1Reserved1;	/* FC Word 1, bit 31:24 */
721 			uint8_t nPortIdByte0;	/* N_port  ID bit 16:23 */
722 			uint8_t nPortIdByte1;	/* N_port  ID bit  8:15 */
723 			uint8_t nPortIdByte2;	/* N_port  ID bit  0: 7 */
724 		} b;
725 	} un;
726 	struct lpfc_name portName;	/* N_port name field */
727 } LOGO;
728 
729 /*
730  *  FCP Login (PRLI Request / ACC) Payload Definition
731  */
732 
733 #define PRLX_PAGE_LEN   0x10
734 #define TPRLO_PAGE_LEN  0x14
735 
736 typedef struct _PRLI {		/* Structure is in Big Endian format */
737 	uint8_t prliType;	/* FC Parm Word 0, bit 24:31 */
738 
739 #define PRLI_FCP_TYPE 0x08
740 #define PRLI_NVME_TYPE 0x28
741 	uint8_t word0Reserved1;	/* FC Parm Word 0, bit 16:23 */
742 
743 #ifdef __BIG_ENDIAN_BITFIELD
744 	uint8_t origProcAssocV:1;	/* FC Parm Word 0, bit 15 */
745 	uint8_t respProcAssocV:1;	/* FC Parm Word 0, bit 14 */
746 	uint8_t estabImagePair:1;	/* FC Parm Word 0, bit 13 */
747 
748 	/*    ACC = imagePairEstablished */
749 	uint8_t word0Reserved2:1;	/* FC Parm Word 0, bit 12 */
750 	uint8_t acceptRspCode:4;	/* FC Parm Word 0, bit 8:11, ACC ONLY */
751 #else	/*  __LITTLE_ENDIAN_BITFIELD */
752 	uint8_t acceptRspCode:4;	/* FC Parm Word 0, bit 8:11, ACC ONLY */
753 	uint8_t word0Reserved2:1;	/* FC Parm Word 0, bit 12 */
754 	uint8_t estabImagePair:1;	/* FC Parm Word 0, bit 13 */
755 	uint8_t respProcAssocV:1;	/* FC Parm Word 0, bit 14 */
756 	uint8_t origProcAssocV:1;	/* FC Parm Word 0, bit 15 */
757 	/*    ACC = imagePairEstablished */
758 #endif
759 
760 #define PRLI_REQ_EXECUTED     0x1	/* acceptRspCode */
761 #define PRLI_NO_RESOURCES     0x2
762 #define PRLI_INIT_INCOMPLETE  0x3
763 #define PRLI_NO_SUCH_PA       0x4
764 #define PRLI_PREDEF_CONFIG    0x5
765 #define PRLI_PARTIAL_SUCCESS  0x6
766 #define PRLI_INVALID_PAGE_CNT 0x7
767 	uint8_t word0Reserved3;	/* FC Parm Word 0, bit 0:7 */
768 
769 	uint32_t origProcAssoc;	/* FC Parm Word 1, bit 0:31 */
770 
771 	uint32_t respProcAssoc;	/* FC Parm Word 2, bit 0:31 */
772 
773 	uint8_t word3Reserved1;	/* FC Parm Word 3, bit 24:31 */
774 	uint8_t word3Reserved2;	/* FC Parm Word 3, bit 16:23 */
775 
776 #ifdef __BIG_ENDIAN_BITFIELD
777 	uint16_t Word3bit15Resved:1;	/* FC Parm Word 3, bit 15 */
778 	uint16_t Word3bit14Resved:1;	/* FC Parm Word 3, bit 14 */
779 	uint16_t Word3bit13Resved:1;	/* FC Parm Word 3, bit 13 */
780 	uint16_t Word3bit12Resved:1;	/* FC Parm Word 3, bit 12 */
781 	uint16_t Word3bit11Resved:1;	/* FC Parm Word 3, bit 11 */
782 	uint16_t Word3bit10Resved:1;	/* FC Parm Word 3, bit 10 */
783 	uint16_t TaskRetryIdReq:1;	/* FC Parm Word 3, bit  9 */
784 	uint16_t Retry:1;	/* FC Parm Word 3, bit  8 */
785 	uint16_t ConfmComplAllowed:1;	/* FC Parm Word 3, bit  7 */
786 	uint16_t dataOverLay:1;	/* FC Parm Word 3, bit  6 */
787 	uint16_t initiatorFunc:1;	/* FC Parm Word 3, bit  5 */
788 	uint16_t targetFunc:1;	/* FC Parm Word 3, bit  4 */
789 	uint16_t cmdDataMixEna:1;	/* FC Parm Word 3, bit  3 */
790 	uint16_t dataRspMixEna:1;	/* FC Parm Word 3, bit  2 */
791 	uint16_t readXferRdyDis:1;	/* FC Parm Word 3, bit  1 */
792 	uint16_t writeXferRdyDis:1;	/* FC Parm Word 3, bit  0 */
793 #else	/*  __LITTLE_ENDIAN_BITFIELD */
794 	uint16_t Retry:1;	/* FC Parm Word 3, bit  8 */
795 	uint16_t TaskRetryIdReq:1;	/* FC Parm Word 3, bit  9 */
796 	uint16_t Word3bit10Resved:1;	/* FC Parm Word 3, bit 10 */
797 	uint16_t Word3bit11Resved:1;	/* FC Parm Word 3, bit 11 */
798 	uint16_t Word3bit12Resved:1;	/* FC Parm Word 3, bit 12 */
799 	uint16_t Word3bit13Resved:1;	/* FC Parm Word 3, bit 13 */
800 	uint16_t Word3bit14Resved:1;	/* FC Parm Word 3, bit 14 */
801 	uint16_t Word3bit15Resved:1;	/* FC Parm Word 3, bit 15 */
802 	uint16_t writeXferRdyDis:1;	/* FC Parm Word 3, bit  0 */
803 	uint16_t readXferRdyDis:1;	/* FC Parm Word 3, bit  1 */
804 	uint16_t dataRspMixEna:1;	/* FC Parm Word 3, bit  2 */
805 	uint16_t cmdDataMixEna:1;	/* FC Parm Word 3, bit  3 */
806 	uint16_t targetFunc:1;	/* FC Parm Word 3, bit  4 */
807 	uint16_t initiatorFunc:1;	/* FC Parm Word 3, bit  5 */
808 	uint16_t dataOverLay:1;	/* FC Parm Word 3, bit  6 */
809 	uint16_t ConfmComplAllowed:1;	/* FC Parm Word 3, bit  7 */
810 #endif
811 } PRLI;
812 
813 /*
814  *  FCP Logout (PRLO Request / ACC) Payload Definition
815  */
816 
817 typedef struct _PRLO {		/* Structure is in Big Endian format */
818 	uint8_t prloType;	/* FC Parm Word 0, bit 24:31 */
819 
820 #define PRLO_FCP_TYPE  0x08
821 	uint8_t word0Reserved1;	/* FC Parm Word 0, bit 16:23 */
822 
823 #ifdef __BIG_ENDIAN_BITFIELD
824 	uint8_t origProcAssocV:1;	/* FC Parm Word 0, bit 15 */
825 	uint8_t respProcAssocV:1;	/* FC Parm Word 0, bit 14 */
826 	uint8_t word0Reserved2:2;	/* FC Parm Word 0, bit 12:13 */
827 	uint8_t acceptRspCode:4;	/* FC Parm Word 0, bit 8:11, ACC ONLY */
828 #else	/*  __LITTLE_ENDIAN_BITFIELD */
829 	uint8_t acceptRspCode:4;	/* FC Parm Word 0, bit 8:11, ACC ONLY */
830 	uint8_t word0Reserved2:2;	/* FC Parm Word 0, bit 12:13 */
831 	uint8_t respProcAssocV:1;	/* FC Parm Word 0, bit 14 */
832 	uint8_t origProcAssocV:1;	/* FC Parm Word 0, bit 15 */
833 #endif
834 
835 #define PRLO_REQ_EXECUTED     0x1	/* acceptRspCode */
836 #define PRLO_NO_SUCH_IMAGE    0x4
837 #define PRLO_INVALID_PAGE_CNT 0x7
838 
839 	uint8_t word0Reserved3;	/* FC Parm Word 0, bit 0:7 */
840 
841 	uint32_t origProcAssoc;	/* FC Parm Word 1, bit 0:31 */
842 
843 	uint32_t respProcAssoc;	/* FC Parm Word 2, bit 0:31 */
844 
845 	uint32_t word3Reserved1;	/* FC Parm Word 3, bit 0:31 */
846 } PRLO;
847 
848 typedef struct _ADISC {		/* Structure is in Big Endian format */
849 	uint32_t hardAL_PA;
850 	struct lpfc_name portName;
851 	struct lpfc_name nodeName;
852 	uint32_t DID;
853 } __packed ADISC;
854 
855 typedef struct _FARP {		/* Structure is in Big Endian format */
856 	uint32_t Mflags:8;
857 	uint32_t Odid:24;
858 #define FARP_NO_ACTION          0	/* FARP information enclosed, no
859 					   action */
860 #define FARP_MATCH_PORT         0x1	/* Match on Responder Port Name */
861 #define FARP_MATCH_NODE         0x2	/* Match on Responder Node Name */
862 #define FARP_MATCH_IP           0x4	/* Match on IP address, not supported */
863 #define FARP_MATCH_IPV4         0x5	/* Match on IPV4 address, not
864 					   supported */
865 #define FARP_MATCH_IPV6         0x6	/* Match on IPV6 address, not
866 					   supported */
867 	uint32_t Rflags:8;
868 	uint32_t Rdid:24;
869 #define FARP_REQUEST_PLOGI      0x1	/* Request for PLOGI */
870 #define FARP_REQUEST_FARPR      0x2	/* Request for FARP Response */
871 	struct lpfc_name OportName;
872 	struct lpfc_name OnodeName;
873 	struct lpfc_name RportName;
874 	struct lpfc_name RnodeName;
875 	uint8_t Oipaddr[16];
876 	uint8_t Ripaddr[16];
877 } FARP;
878 
879 typedef struct _FAN {		/* Structure is in Big Endian format */
880 	uint32_t Fdid;
881 	struct lpfc_name FportName;
882 	struct lpfc_name FnodeName;
883 } __packed FAN;
884 
885 typedef struct _SCR {		/* Structure is in Big Endian format */
886 	uint8_t resvd1;
887 	uint8_t resvd2;
888 	uint8_t resvd3;
889 	uint8_t Function;
890 #define  SCR_FUNC_FABRIC     0x01
891 #define  SCR_FUNC_NPORT      0x02
892 #define  SCR_FUNC_FULL       0x03
893 #define  SCR_CLEAR           0xff
894 } SCR;
895 
896 typedef struct _RNID_TOP_DISC {
897 	struct lpfc_name portName;
898 	uint8_t resvd[8];
899 	uint32_t unitType;
900 #define RNID_HBA            0x7
901 #define RNID_HOST           0xa
902 #define RNID_DRIVER         0xd
903 	uint32_t physPort;
904 	uint32_t attachedNodes;
905 	uint16_t ipVersion;
906 #define RNID_IPV4           0x1
907 #define RNID_IPV6           0x2
908 	uint16_t UDPport;
909 	uint8_t ipAddr[16];
910 	uint16_t resvd1;
911 	uint16_t flags;
912 #define RNID_TD_SUPPORT     0x1
913 #define RNID_LP_VALID       0x2
914 } RNID_TOP_DISC;
915 
916 typedef struct _RNID {		/* Structure is in Big Endian format */
917 	uint8_t Format;
918 #define RNID_TOPOLOGY_DISC  0xdf
919 	uint8_t CommonLen;
920 	uint8_t resvd1;
921 	uint8_t SpecificLen;
922 	struct lpfc_name portName;
923 	struct lpfc_name nodeName;
924 	union {
925 		RNID_TOP_DISC topologyDisc;	/* topology disc (0xdf) */
926 	} un;
927 } __packed RNID;
928 
929 struct RLS {			/* Structure is in Big Endian format */
930 	uint32_t rls;
931 #define rls_rsvd_SHIFT		24
932 #define rls_rsvd_MASK		0x000000ff
933 #define rls_rsvd_WORD		rls
934 #define rls_did_SHIFT		0
935 #define rls_did_MASK		0x00ffffff
936 #define rls_did_WORD		rls
937 };
938 
939 struct  RLS_RSP {		/* Structure is in Big Endian format */
940 	uint32_t linkFailureCnt;
941 	uint32_t lossSyncCnt;
942 	uint32_t lossSignalCnt;
943 	uint32_t primSeqErrCnt;
944 	uint32_t invalidXmitWord;
945 	uint32_t crcCnt;
946 };
947 
948 struct RRQ {			/* Structure is in Big Endian format */
949 	uint32_t rrq;
950 #define rrq_rsvd_SHIFT		24
951 #define rrq_rsvd_MASK		0x000000ff
952 #define rrq_rsvd_WORD		rrq
953 #define rrq_did_SHIFT		0
954 #define rrq_did_MASK		0x00ffffff
955 #define rrq_did_WORD		rrq
956 	uint32_t rrq_exchg;
957 #define rrq_oxid_SHIFT		16
958 #define rrq_oxid_MASK		0xffff
959 #define rrq_oxid_WORD		rrq_exchg
960 #define rrq_rxid_SHIFT		0
961 #define rrq_rxid_MASK		0xffff
962 #define rrq_rxid_WORD		rrq_exchg
963 };
964 
965 #define LPFC_MAX_VFN_PER_PFN	255 /* Maximum VFs allowed per ARI */
966 #define LPFC_DEF_VFN_PER_PFN	0   /* Default VFs due to platform limitation*/
967 
968 struct RTV_RSP {		/* Structure is in Big Endian format */
969 	uint32_t ratov;
970 	uint32_t edtov;
971 	uint32_t qtov;
972 #define qtov_rsvd0_SHIFT	28
973 #define qtov_rsvd0_MASK		0x0000000f
974 #define qtov_rsvd0_WORD		qtov		/* reserved */
975 #define qtov_edtovres_SHIFT	27
976 #define qtov_edtovres_MASK	0x00000001
977 #define qtov_edtovres_WORD	qtov		/* E_D_TOV Resolution */
978 #define qtov__rsvd1_SHIFT	19
979 #define qtov_rsvd1_MASK		0x0000003f
980 #define qtov_rsvd1_WORD		qtov		/* reserved */
981 #define qtov_rttov_SHIFT	18
982 #define qtov_rttov_MASK		0x00000001
983 #define qtov_rttov_WORD		qtov		/* R_T_TOV value */
984 #define qtov_rsvd2_SHIFT	0
985 #define qtov_rsvd2_MASK		0x0003ffff
986 #define qtov_rsvd2_WORD		qtov		/* reserved */
987 };
988 
989 
990 typedef struct  _RPL {		/* Structure is in Big Endian format */
991 	uint32_t maxsize;
992 	uint32_t index;
993 } RPL;
994 
995 typedef struct  _PORT_NUM_BLK {
996 	uint32_t portNum;
997 	uint32_t portID;
998 	struct lpfc_name portName;
999 } PORT_NUM_BLK;
1000 
1001 typedef struct  _RPL_RSP {	/* Structure is in Big Endian format */
1002 	uint32_t listLen;
1003 	uint32_t index;
1004 	PORT_NUM_BLK port_num_blk;
1005 } RPL_RSP;
1006 
1007 /* This is used for RSCN command */
1008 typedef struct _D_ID {		/* Structure is in Big Endian format */
1009 	union {
1010 		uint32_t word;
1011 		struct {
1012 #ifdef __BIG_ENDIAN_BITFIELD
1013 			uint8_t resv;
1014 			uint8_t domain;
1015 			uint8_t area;
1016 			uint8_t id;
1017 #else	/*  __LITTLE_ENDIAN_BITFIELD */
1018 			uint8_t id;
1019 			uint8_t area;
1020 			uint8_t domain;
1021 			uint8_t resv;
1022 #endif
1023 		} b;
1024 	} un;
1025 } D_ID;
1026 
1027 #define RSCN_ADDRESS_FORMAT_PORT	0x0
1028 #define RSCN_ADDRESS_FORMAT_AREA	0x1
1029 #define RSCN_ADDRESS_FORMAT_DOMAIN	0x2
1030 #define RSCN_ADDRESS_FORMAT_FABRIC	0x3
1031 #define RSCN_ADDRESS_FORMAT_MASK	0x3
1032 
1033 /*
1034  *  Structure to define all ELS Payload types
1035  */
1036 
1037 typedef struct _ELS_PKT {	/* Structure is in Big Endian format */
1038 	uint8_t elsCode;	/* FC Word 0, bit 24:31 */
1039 	uint8_t elsByte1;
1040 	uint8_t elsByte2;
1041 	uint8_t elsByte3;
1042 	union {
1043 		struct ls_rjt lsRjt;	/* Payload for LS_RJT ELS response */
1044 		struct serv_parm logi;	/* Payload for PLOGI/FLOGI/PDISC/ACC */
1045 		LOGO logo;	/* Payload for PLOGO/FLOGO/ACC */
1046 		PRLI prli;	/* Payload for PRLI/ACC */
1047 		PRLO prlo;	/* Payload for PRLO/ACC */
1048 		ADISC adisc;	/* Payload for ADISC/ACC */
1049 		FARP farp;	/* Payload for FARP/ACC */
1050 		FAN fan;	/* Payload for FAN */
1051 		SCR scr;	/* Payload for SCR/ACC */
1052 		RNID rnid;	/* Payload for RNID */
1053 		uint8_t pad[128 - 4];	/* Pad out to payload of 128 bytes */
1054 	} un;
1055 } ELS_PKT;
1056 
1057 /*
1058  * Link Cable Beacon (LCB) ELS Frame
1059  */
1060 
1061 struct fc_lcb_request_frame {
1062 	uint32_t      lcb_command;      /* ELS command opcode (0x81)     */
1063 	uint8_t       lcb_sub_command;/* LCB Payload Word 1, bit 24:31 */
1064 #define LPFC_LCB_ON		0x1
1065 #define LPFC_LCB_OFF		0x2
1066 	uint8_t       reserved[2];
1067 	uint8_t	      capability;	/* LCB Payload Word 1, bit 0:7 */
1068 	uint8_t       lcb_type; /* LCB Payload Word 2, bit 24:31 */
1069 #define LPFC_LCB_GREEN		0x1
1070 #define LPFC_LCB_AMBER		0x2
1071 	uint8_t       lcb_frequency;    /* LCB Payload Word 2, bit 16:23 */
1072 #define LCB_CAPABILITY_DURATION	1
1073 #define BEACON_VERSION_V1	1
1074 #define BEACON_VERSION_V0	0
1075 	uint16_t      lcb_duration;     /* LCB Payload Word 2, bit 15:0  */
1076 };
1077 
1078 /*
1079  * Link Cable Beacon (LCB) ELS Response Frame
1080  */
1081 struct fc_lcb_res_frame {
1082 	uint32_t      lcb_ls_acc;       /* Acceptance of LCB request (0x02) */
1083 	uint8_t       lcb_sub_command;/* LCB Payload Word 1, bit 24:31 */
1084 	uint8_t       reserved[2];
1085 	uint8_t	      capability;	/* LCB Payload Word 1, bit 0:7 */
1086 	uint8_t       lcb_type; /* LCB Payload Word 2, bit 24:31 */
1087 	uint8_t       lcb_frequency;    /* LCB Payload Word 2, bit 16:23 */
1088 	uint16_t      lcb_duration;     /* LCB Payload Word 2, bit 15:0  */
1089 };
1090 
1091 /*
1092  * Read Diagnostic Parameters (RDP) ELS frame.
1093  */
1094 #define SFF_PG0_IDENT_SFP              0x3
1095 
1096 #define SFP_FLAG_PT_OPTICAL            0x0
1097 #define SFP_FLAG_PT_SWLASER            0x01
1098 #define SFP_FLAG_PT_LWLASER_LC1310     0x02
1099 #define SFP_FLAG_PT_LWLASER_LL1550     0x03
1100 #define SFP_FLAG_PT_MASK               0x0F
1101 #define SFP_FLAG_PT_SHIFT              0
1102 
1103 #define SFP_FLAG_IS_OPTICAL_PORT       0x01
1104 #define SFP_FLAG_IS_OPTICAL_MASK       0x010
1105 #define SFP_FLAG_IS_OPTICAL_SHIFT      4
1106 
1107 #define SFP_FLAG_IS_DESC_VALID         0x01
1108 #define SFP_FLAG_IS_DESC_VALID_MASK    0x020
1109 #define SFP_FLAG_IS_DESC_VALID_SHIFT   5
1110 
1111 #define SFP_FLAG_CT_UNKNOWN            0x0
1112 #define SFP_FLAG_CT_SFP_PLUS           0x01
1113 #define SFP_FLAG_CT_MASK               0x3C
1114 #define SFP_FLAG_CT_SHIFT              6
1115 
1116 struct fc_rdp_port_name_info {
1117 	uint8_t wwnn[8];
1118 	uint8_t wwpn[8];
1119 };
1120 
1121 
1122 /*
1123  * Link Error Status Block Structure (FC-FS-3) for RDP
1124  * This similar to RPS ELS
1125  */
1126 struct fc_link_status {
1127 	uint32_t      link_failure_cnt;
1128 	uint32_t      loss_of_synch_cnt;
1129 	uint32_t      loss_of_signal_cnt;
1130 	uint32_t      primitive_seq_proto_err;
1131 	uint32_t      invalid_trans_word;
1132 	uint32_t      invalid_crc_cnt;
1133 
1134 };
1135 
1136 #define RDP_PORT_NAMES_DESC_TAG  0x00010003
1137 struct fc_rdp_port_name_desc {
1138 	uint32_t	tag;     /* 0001 0003h */
1139 	uint32_t	length;  /* set to size of payload struct */
1140 	struct fc_rdp_port_name_info  port_names;
1141 };
1142 
1143 
1144 struct fc_rdp_fec_info {
1145 	uint32_t CorrectedBlocks;
1146 	uint32_t UncorrectableBlocks;
1147 };
1148 
1149 #define RDP_FEC_DESC_TAG  0x00010005
1150 struct fc_fec_rdp_desc {
1151 	uint32_t tag;
1152 	uint32_t length;
1153 	struct fc_rdp_fec_info info;
1154 };
1155 
1156 struct fc_rdp_link_error_status_payload_info {
1157 	struct fc_link_status link_status; /* 24 bytes */
1158 	uint32_t  port_type;             /* bits 31-30 only */
1159 };
1160 
1161 #define RDP_LINK_ERROR_STATUS_DESC_TAG  0x00010002
1162 struct fc_rdp_link_error_status_desc {
1163 	uint32_t         tag;     /* 0001 0002h */
1164 	uint32_t         length;  /* set to size of payload struct */
1165 	struct fc_rdp_link_error_status_payload_info info;
1166 };
1167 
1168 #define VN_PT_PHY_UNKNOWN      0x00
1169 #define VN_PT_PHY_PF_PORT      0x01
1170 #define VN_PT_PHY_ETH_MAC      0x10
1171 #define VN_PT_PHY_SHIFT                30
1172 
1173 #define RDP_PS_1GB             0x8000
1174 #define RDP_PS_2GB             0x4000
1175 #define RDP_PS_4GB             0x2000
1176 #define RDP_PS_10GB            0x1000
1177 #define RDP_PS_8GB             0x0800
1178 #define RDP_PS_16GB            0x0400
1179 #define RDP_PS_32GB            0x0200
1180 #define RDP_PS_64GB            0x0100
1181 #define RDP_PS_128GB           0x0080
1182 #define RDP_PS_256GB           0x0040
1183 
1184 #define RDP_CAP_USER_CONFIGURED 0x0002
1185 #define RDP_CAP_UNKNOWN         0x0001
1186 #define RDP_PS_UNKNOWN          0x0002
1187 #define RDP_PS_NOT_ESTABLISHED  0x0001
1188 
1189 struct fc_rdp_port_speed {
1190 	uint16_t   capabilities;
1191 	uint16_t   speed;
1192 };
1193 
1194 struct fc_rdp_port_speed_info {
1195 	struct fc_rdp_port_speed   port_speed;
1196 };
1197 
1198 #define RDP_PORT_SPEED_DESC_TAG  0x00010001
1199 struct fc_rdp_port_speed_desc {
1200 	uint32_t         tag;            /* 00010001h */
1201 	uint32_t         length;         /* set to size of payload struct */
1202 	struct fc_rdp_port_speed_info info;
1203 };
1204 
1205 #define RDP_NPORT_ID_SIZE      4
1206 #define RDP_N_PORT_DESC_TAG    0x00000003
1207 struct fc_rdp_nport_desc {
1208 	uint32_t         tag;          /* 0000 0003h, big endian */
1209 	uint32_t         length;       /* size of RDP_N_PORT_ID struct */
1210 	uint32_t         nport_id : 12;
1211 	uint32_t         reserved : 8;
1212 };
1213 
1214 
1215 struct fc_rdp_link_service_info {
1216 	uint32_t         els_req;    /* Request payload word 0 value.*/
1217 };
1218 
1219 #define RDP_LINK_SERVICE_DESC_TAG  0x00000001
1220 struct fc_rdp_link_service_desc {
1221 	uint32_t         tag;     /* Descriptor tag  1 */
1222 	uint32_t         length;  /* set to size of payload struct. */
1223 	struct fc_rdp_link_service_info  payload;
1224 				  /* must be ELS req Word 0(0x18) */
1225 };
1226 
1227 struct fc_rdp_sfp_info {
1228 	uint16_t	temperature;
1229 	uint16_t	vcc;
1230 	uint16_t	tx_bias;
1231 	uint16_t	tx_power;
1232 	uint16_t	rx_power;
1233 	uint16_t	flags;
1234 };
1235 
1236 #define RDP_SFP_DESC_TAG  0x00010000
1237 struct fc_rdp_sfp_desc {
1238 	uint32_t         tag;
1239 	uint32_t         length;  /* set to size of sfp_info struct */
1240 	struct fc_rdp_sfp_info sfp_info;
1241 };
1242 
1243 /* Buffer Credit Descriptor */
1244 struct fc_rdp_bbc_info {
1245 	uint32_t              port_bbc; /* FC_Port buffer-to-buffer credit */
1246 	uint32_t              attached_port_bbc;
1247 	uint32_t              rtt;      /* Round trip time */
1248 };
1249 #define RDP_BBC_DESC_TAG  0x00010006
1250 struct fc_rdp_bbc_desc {
1251 	uint32_t              tag;
1252 	uint32_t              length;
1253 	struct fc_rdp_bbc_info  bbc_info;
1254 };
1255 
1256 /* Optical Element Type Transgression Flags */
1257 #define RDP_OET_LOW_WARNING  0x1
1258 #define RDP_OET_HIGH_WARNING 0x2
1259 #define RDP_OET_LOW_ALARM    0x4
1260 #define RDP_OET_HIGH_ALARM   0x8
1261 
1262 #define RDP_OED_TEMPERATURE  0x1
1263 #define RDP_OED_VOLTAGE      0x2
1264 #define RDP_OED_TXBIAS       0x3
1265 #define RDP_OED_TXPOWER      0x4
1266 #define RDP_OED_RXPOWER      0x5
1267 
1268 #define RDP_OED_TYPE_SHIFT   28
1269 /* Optical Element Data descriptor */
1270 struct fc_rdp_oed_info {
1271 	uint16_t            hi_alarm;
1272 	uint16_t            lo_alarm;
1273 	uint16_t            hi_warning;
1274 	uint16_t            lo_warning;
1275 	uint32_t            function_flags;
1276 };
1277 #define RDP_OED_DESC_TAG  0x00010007
1278 struct fc_rdp_oed_sfp_desc {
1279 	uint32_t             tag;
1280 	uint32_t             length;
1281 	struct fc_rdp_oed_info oed_info;
1282 };
1283 
1284 /* Optical Product Data descriptor */
1285 struct fc_rdp_opd_sfp_info {
1286 	uint8_t            vendor_name[16];
1287 	uint8_t            model_number[16];
1288 	uint8_t            serial_number[16];
1289 	uint8_t            revision[4];
1290 	uint8_t            date[8];
1291 };
1292 
1293 #define RDP_OPD_DESC_TAG  0x00010008
1294 struct fc_rdp_opd_sfp_desc {
1295 	uint32_t             tag;
1296 	uint32_t             length;
1297 	struct fc_rdp_opd_sfp_info opd_info;
1298 };
1299 
1300 struct fc_rdp_req_frame {
1301 	uint32_t         rdp_command;           /* ELS command opcode (0x18)*/
1302 	uint32_t         rdp_des_length;        /* RDP Payload Word 1 */
1303 	struct fc_rdp_nport_desc nport_id_desc; /* RDP Payload Word 2 - 4 */
1304 };
1305 
1306 
1307 struct fc_rdp_res_frame {
1308 	uint32_t    reply_sequence;		/* FC word0 LS_ACC or LS_RJT */
1309 	uint32_t   length;			/* FC Word 1      */
1310 	struct fc_rdp_link_service_desc link_service_desc;    /* Word 2 -4   */
1311 	struct fc_rdp_sfp_desc sfp_desc;                      /* Word 5 -9   */
1312 	struct fc_rdp_port_speed_desc portspeed_desc;         /* Word 10 -12 */
1313 	struct fc_rdp_link_error_status_desc link_error_desc; /* Word 13 -21 */
1314 	struct fc_rdp_port_name_desc diag_port_names_desc;    /* Word 22 -27 */
1315 	struct fc_rdp_port_name_desc attached_port_names_desc;/* Word 28 -33 */
1316 	struct fc_fec_rdp_desc fec_desc;                      /* FC word 34-37*/
1317 	struct fc_rdp_bbc_desc bbc_desc;                      /* FC Word 38-42*/
1318 	struct fc_rdp_oed_sfp_desc oed_temp_desc;             /* FC Word 43-47*/
1319 	struct fc_rdp_oed_sfp_desc oed_voltage_desc;          /* FC word 48-52*/
1320 	struct fc_rdp_oed_sfp_desc oed_txbias_desc;           /* FC word 53-57*/
1321 	struct fc_rdp_oed_sfp_desc oed_txpower_desc;          /* FC word 58-62*/
1322 	struct fc_rdp_oed_sfp_desc oed_rxpower_desc;          /* FC word 63-67*/
1323 	struct fc_rdp_opd_sfp_desc opd_desc;                  /* FC word 68-84*/
1324 };
1325 
1326 
1327 /* UVEM */
1328 
1329 #define LPFC_UVEM_SIZE 60
1330 #define LPFC_UVEM_VEM_ID_DESC_SIZE 16
1331 #define LPFC_UVEM_VE_MAP_DESC_SIZE 20
1332 
1333 #define VEM_ID_DESC_TAG  0x0001000A
1334 struct lpfc_vem_id_desc {
1335 	uint32_t tag;
1336 	uint32_t length;
1337 	uint8_t vem_id[16];
1338 };
1339 
1340 #define LPFC_QFPA_SIZE	4
1341 
1342 #define INSTANTIATED_VE_DESC_TAG  0x0001000B
1343 struct instantiated_ve_desc {
1344 	uint32_t tag;
1345 	uint32_t length;
1346 	uint8_t global_vem_id[16];
1347 	uint32_t word6;
1348 #define lpfc_instantiated_local_id_SHIFT   0
1349 #define lpfc_instantiated_local_id_MASK    0x000000ff
1350 #define lpfc_instantiated_local_id_WORD    word6
1351 #define lpfc_instantiated_nport_id_SHIFT   8
1352 #define lpfc_instantiated_nport_id_MASK    0x00ffffff
1353 #define lpfc_instantiated_nport_id_WORD    word6
1354 };
1355 
1356 #define DEINSTANTIATED_VE_DESC_TAG  0x0001000C
1357 struct deinstantiated_ve_desc {
1358 	uint32_t tag;
1359 	uint32_t length;
1360 	uint8_t global_vem_id[16];
1361 	uint32_t word6;
1362 #define lpfc_deinstantiated_nport_id_SHIFT   0
1363 #define lpfc_deinstantiated_nport_id_MASK    0x000000ff
1364 #define lpfc_deinstantiated_nport_id_WORD    word6
1365 #define lpfc_deinstantiated_local_id_SHIFT   24
1366 #define lpfc_deinstantiated_local_id_MASK    0x00ffffff
1367 #define lpfc_deinstantiated_local_id_WORD    word6
1368 };
1369 
1370 /* Query Fabric Priority Allocation Response */
1371 #define LPFC_PRIORITY_RANGE_DESC_SIZE 12
1372 
1373 struct priority_range_desc {
1374 	uint32_t tag;
1375 	uint32_t length;
1376 	uint8_t lo_range;
1377 	uint8_t hi_range;
1378 	uint8_t qos_priority;
1379 	uint8_t local_ve_id;
1380 };
1381 
1382 struct fc_qfpa_res {
1383 	uint32_t reply_sequence;	/* LS_ACC or LS_RJT */
1384 	uint32_t length;	/* FC Word 1    */
1385 	struct priority_range_desc desc[1];
1386 };
1387 
1388 /* Application Server command code */
1389 /* VMID               */
1390 
1391 #define SLI_CT_APP_SEV_Subtypes     0x20	/* Application Server subtype */
1392 
1393 #define SLI_CTAS_GAPPIA_ENT    0x0100	/* Get Application Identifier */
1394 #define SLI_CTAS_GALLAPPIA     0x0101	/* Get All Application Identifier */
1395 #define SLI_CTAS_GALLAPPIA_ID  0x0102	/* Get All Application Identifier */
1396 					/* for Nport */
1397 #define SLI_CTAS_GAPPIA_IDAPP  0x0103	/* Get Application Identifier */
1398 					/* for Nport */
1399 #define SLI_CTAS_RAPP_IDENT    0x0200	/* Register Application Identifier */
1400 #define SLI_CTAS_DAPP_IDENT    0x0300	/* Deregister Application */
1401 					/* Identifier */
1402 #define SLI_CTAS_DALLAPP_ID    0x0301	/* Deregister All Application */
1403 					/* Identifier */
1404 
1405 struct entity_id_object {
1406 	uint8_t entity_id_len;
1407 	uint8_t entity_id[255];	/* VM UUID */
1408 };
1409 
1410 struct app_id_object {
1411 	uint32_t port_id;
1412 	uint32_t app_id;
1413 	struct entity_id_object obj;
1414 };
1415 
1416 struct lpfc_vmid_rapp_ident_list {
1417 	uint32_t no_of_objects;
1418 	struct entity_id_object obj[1];
1419 };
1420 
1421 struct lpfc_vmid_dapp_ident_list {
1422 	uint32_t no_of_objects;
1423 	struct entity_id_object obj[1];
1424 };
1425 
1426 #define GALLAPPIA_ID_LAST  0x80
1427 struct lpfc_vmid_gallapp_ident_list {
1428 	uint8_t control;
1429 	uint8_t reserved[3];
1430 	struct app_id_object app_id;
1431 };
1432 
1433 #define RAPP_IDENT_OFFSET  (offsetof(struct lpfc_sli_ct_request, un) + 4)
1434 #define DAPP_IDENT_OFFSET  (offsetof(struct lpfc_sli_ct_request, un) + 4)
1435 #define GALLAPPIA_ID_SIZE  (offsetof(struct lpfc_sli_ct_request, un) + 4)
1436 #define DALLAPP_ID_SIZE    (offsetof(struct lpfc_sli_ct_request, un) + 4)
1437 
1438 /******** FDMI ********/
1439 
1440 /* lpfc_sli_ct_request defines the CT_IU preamble for FDMI commands */
1441 #define  SLI_CT_FDMI_Subtypes     0x10	/* Management Service Subtype */
1442 
1443 /* Definitions for HBA / Port attribute entries */
1444 
1445 /* Attribute Entry Structures */
1446 
1447 struct lpfc_fdmi_attr_u32 {
1448 	__be16 type;
1449 	__be16 len;
1450 	__be32 value_u32;
1451 };
1452 
1453 struct lpfc_fdmi_attr_wwn {
1454 	__be16 type;
1455 	__be16 len;
1456 
1457 	/* Keep as u8[8] instead of __be64 to avoid accidental zero padding
1458 	 * by compiler
1459 	 */
1460 	u8 name[8];
1461 };
1462 
1463 struct lpfc_fdmi_attr_fullwwn {
1464 	__be16 type;
1465 	__be16 len;
1466 
1467 	/* Keep as u8[8] instead of __be64 to avoid accidental zero padding
1468 	 * by compiler
1469 	 */
1470 	u8 nname[8];
1471 	u8 pname[8];
1472 };
1473 
1474 struct lpfc_fdmi_attr_fc4types {
1475 	__be16 type;
1476 	__be16 len;
1477 	u8 value_types[32];
1478 };
1479 
1480 struct lpfc_fdmi_attr_string {
1481 	__be16 type;
1482 	__be16 len;
1483 	char value_string[256];
1484 };
1485 
1486 /* Maximum FDMI attribute length is Type+Len (4 bytes) + 256 byte string */
1487 #define FDMI_MAX_ATTRLEN	sizeof(struct lpfc_fdmi_attr_string)
1488 
1489 /*
1490  * HBA Attribute Block
1491  */
1492 struct lpfc_fdmi_attr_block {
1493 	uint32_t EntryCnt;		/* Number of HBA attribute entries */
1494 	/* Variable Length Attribute Entry TLV's follow */
1495 };
1496 
1497 /*
1498  * Port Entry
1499  */
1500 struct lpfc_fdmi_port_entry {
1501 	struct lpfc_name PortName;
1502 };
1503 
1504 /*
1505  * HBA Identifier
1506  */
1507 struct lpfc_fdmi_hba_ident {
1508 	struct lpfc_name PortName;
1509 };
1510 
1511 /*
1512  * Registered Port List Format
1513  */
1514 struct lpfc_fdmi_reg_port_list {
1515 	uint32_t EntryCnt;
1516 	struct lpfc_fdmi_port_entry pe;
1517 } __packed;
1518 
1519 /*
1520  * Register HBA(RHBA)
1521  */
1522 struct lpfc_fdmi_reg_hba {
1523 	struct lpfc_fdmi_hba_ident hi;
1524 	struct lpfc_fdmi_reg_port_list rpl;
1525 };
1526 
1527 /******** MI MIB ********/
1528 #define SLI_CT_MIB_Subtypes	0x11
1529 
1530 /*
1531  * Register HBA Attributes (RHAT)
1532  */
1533 struct lpfc_fdmi_reg_hbaattr {
1534 	struct lpfc_name HBA_PortName;
1535 	struct lpfc_fdmi_attr_block ab;
1536 };
1537 
1538 /*
1539  * Register Port Attributes (RPA)
1540  */
1541 struct lpfc_fdmi_reg_portattr {
1542 	struct lpfc_name PortName;
1543 	struct lpfc_fdmi_attr_block ab;
1544 };
1545 
1546 /*
1547  * HBA MAnagement Operations Command Codes
1548  */
1549 #define  SLI_MGMT_GRHL     0x100	/* Get registered HBA list */
1550 #define  SLI_MGMT_GHAT     0x101	/* Get HBA attributes */
1551 #define  SLI_MGMT_GRPL     0x102	/* Get registered Port list */
1552 #define  SLI_MGMT_GPAT     0x110	/* Get Port attributes */
1553 #define  SLI_MGMT_GPAS     0x120	/* Get Port Statistics */
1554 #define  SLI_MGMT_RHBA     0x200	/* Register HBA */
1555 #define  SLI_MGMT_RHAT     0x201	/* Register HBA attributes */
1556 #define  SLI_MGMT_RPRT     0x210	/* Register Port */
1557 #define  SLI_MGMT_RPA      0x211	/* Register Port attributes */
1558 #define  SLI_MGMT_DHBA     0x300	/* De-register HBA */
1559 #define  SLI_MGMT_DHAT     0x301	/* De-register HBA attributes */
1560 #define  SLI_MGMT_DPRT     0x310	/* De-register Port */
1561 #define  SLI_MGMT_DPA      0x311	/* De-register Port attributes */
1562 
1563 #define LPFC_FDMI_MAX_RETRY     3  /* Max retries for a FDMI command */
1564 
1565 /*
1566  * HBA Attribute Types
1567  */
1568 #define  RHBA_NODENAME           0x1 /* 8 byte WWNN */
1569 #define  RHBA_MANUFACTURER       0x2 /* 4 to 64 byte ASCII string */
1570 #define  RHBA_SERIAL_NUMBER      0x3 /* 4 to 64 byte ASCII string */
1571 #define  RHBA_MODEL              0x4 /* 4 to 256 byte ASCII string */
1572 #define  RHBA_MODEL_DESCRIPTION  0x5 /* 4 to 256 byte ASCII string */
1573 #define  RHBA_HARDWARE_VERSION   0x6 /* 4 to 256 byte ASCII string */
1574 #define  RHBA_DRIVER_VERSION     0x7 /* 4 to 256 byte ASCII string */
1575 #define  RHBA_OPTION_ROM_VERSION 0x8 /* 4 to 256 byte ASCII string */
1576 #define  RHBA_FIRMWARE_VERSION   0x9 /* 4 to 256 byte ASCII string */
1577 #define  RHBA_OS_NAME_VERSION	 0xa /* 4 to 256 byte ASCII string */
1578 #define  RHBA_MAX_CT_PAYLOAD_LEN 0xb /* 32-bit unsigned int */
1579 #define  RHBA_SYM_NODENAME       0xc /* 4 to 256 byte ASCII string */
1580 #define  RHBA_VENDOR_INFO        0xd  /* 32-bit unsigned int */
1581 #define  RHBA_NUM_PORTS          0xe  /* 32-bit unsigned int */
1582 #define  RHBA_FABRIC_WWNN        0xf  /* 8 byte WWNN */
1583 #define  RHBA_BIOS_VERSION       0x10 /* 4 to 256 byte ASCII string */
1584 #define  RHBA_BIOS_STATE         0x11 /* 32-bit unsigned int */
1585 #define  RHBA_VENDOR_ID          0xe0 /* 8 byte ASCII string */
1586 
1587 /* Bit mask for all individual HBA attributes */
1588 #define LPFC_FDMI_HBA_ATTR_wwnn			0x00000001
1589 #define LPFC_FDMI_HBA_ATTR_manufacturer		0x00000002
1590 #define LPFC_FDMI_HBA_ATTR_sn			0x00000004
1591 #define LPFC_FDMI_HBA_ATTR_model		0x00000008
1592 #define LPFC_FDMI_HBA_ATTR_description		0x00000010
1593 #define LPFC_FDMI_HBA_ATTR_hdw_ver		0x00000020
1594 #define LPFC_FDMI_HBA_ATTR_drvr_ver		0x00000040
1595 #define LPFC_FDMI_HBA_ATTR_rom_ver		0x00000080
1596 #define LPFC_FDMI_HBA_ATTR_fmw_ver		0x00000100
1597 #define LPFC_FDMI_HBA_ATTR_os_ver		0x00000200
1598 #define LPFC_FDMI_HBA_ATTR_ct_len		0x00000400
1599 #define LPFC_FDMI_HBA_ATTR_symbolic_name	0x00000800
1600 #define LPFC_FDMI_HBA_ATTR_vendor_info		0x00001000 /* Not used */
1601 #define LPFC_FDMI_HBA_ATTR_num_ports		0x00002000
1602 #define LPFC_FDMI_HBA_ATTR_fabric_wwnn		0x00004000
1603 #define LPFC_FDMI_HBA_ATTR_bios_ver		0x00008000
1604 #define LPFC_FDMI_HBA_ATTR_bios_state		0x00010000 /* Not used */
1605 #define LPFC_FDMI_HBA_ATTR_vendor_id		0x00020000
1606 
1607 /* Bit mask for FDMI-1 defined HBA attributes */
1608 #define LPFC_FDMI1_HBA_ATTR			0x000007ff
1609 
1610 /* Bit mask for FDMI-2 defined HBA attributes */
1611 /* Skip vendor_info and bios_state */
1612 #define LPFC_FDMI2_HBA_ATTR			0x0002efff
1613 
1614 /*
1615  * Port Attribute Types
1616  */
1617 #define  RPRT_SUPPORTED_FC4_TYPES     0x1 /* 32 byte binary array */
1618 #define  RPRT_SUPPORTED_SPEED         0x2 /* 32-bit unsigned int */
1619 #define  RPRT_PORT_SPEED              0x3 /* 32-bit unsigned int */
1620 #define  RPRT_MAX_FRAME_SIZE          0x4 /* 32-bit unsigned int */
1621 #define  RPRT_OS_DEVICE_NAME          0x5 /* 4 to 256 byte ASCII string */
1622 #define  RPRT_HOST_NAME               0x6 /* 4 to 256 byte ASCII string */
1623 #define  RPRT_NODENAME                0x7 /* 8 byte WWNN */
1624 #define  RPRT_PORTNAME                0x8 /* 8 byte WWPN */
1625 #define  RPRT_SYM_PORTNAME            0x9 /* 4 to 256 byte ASCII string */
1626 #define  RPRT_PORT_TYPE               0xa /* 32-bit unsigned int */
1627 #define  RPRT_SUPPORTED_CLASS         0xb /* 32-bit unsigned int */
1628 #define  RPRT_FABRICNAME              0xc /* 8 byte Fabric WWPN */
1629 #define  RPRT_ACTIVE_FC4_TYPES        0xd /* 32 byte binary array */
1630 #define  RPRT_PORT_STATE              0x101 /* 32-bit unsigned int */
1631 #define  RPRT_DISC_PORT               0x102 /* 32-bit unsigned int */
1632 #define  RPRT_PORT_ID                 0x103 /* 32-bit unsigned int */
1633 #define  RPRT_VENDOR_MI               0xf047 /* vendor ascii string */
1634 #define  RPRT_SMART_SERVICE           0xf100 /* 4 to 256 byte ASCII string */
1635 #define  RPRT_SMART_GUID              0xf101 /* 8 byte WWNN + 8 byte WWPN */
1636 #define  RPRT_SMART_VERSION           0xf102 /* 4 to 256 byte ASCII string */
1637 #define  RPRT_SMART_MODEL             0xf103 /* 4 to 256 byte ASCII string */
1638 #define  RPRT_SMART_PORT_INFO         0xf104 /* 32-bit unsigned int */
1639 #define  RPRT_SMART_QOS               0xf105 /* 32-bit unsigned int */
1640 #define  RPRT_SMART_SECURITY          0xf106 /* 32-bit unsigned int */
1641 
1642 /* Bit mask for all individual PORT attributes */
1643 #define LPFC_FDMI_PORT_ATTR_fc4type		0x00000001
1644 #define LPFC_FDMI_PORT_ATTR_support_speed	0x00000002
1645 #define LPFC_FDMI_PORT_ATTR_speed		0x00000004
1646 #define LPFC_FDMI_PORT_ATTR_max_frame		0x00000008
1647 #define LPFC_FDMI_PORT_ATTR_os_devname		0x00000010
1648 #define LPFC_FDMI_PORT_ATTR_host_name		0x00000020
1649 #define LPFC_FDMI_PORT_ATTR_wwnn		0x00000040
1650 #define LPFC_FDMI_PORT_ATTR_wwpn		0x00000080
1651 #define LPFC_FDMI_PORT_ATTR_symbolic_name	0x00000100
1652 #define LPFC_FDMI_PORT_ATTR_port_type		0x00000200
1653 #define LPFC_FDMI_PORT_ATTR_class		0x00000400
1654 #define LPFC_FDMI_PORT_ATTR_fabric_wwpn		0x00000800
1655 #define LPFC_FDMI_PORT_ATTR_port_state		0x00001000
1656 #define LPFC_FDMI_PORT_ATTR_active_fc4type	0x00002000
1657 #define LPFC_FDMI_PORT_ATTR_num_disc		0x00004000
1658 #define LPFC_FDMI_PORT_ATTR_nportid		0x00008000
1659 #define LPFC_FDMI_SMART_ATTR_service		0x00010000 /* Vendor specific */
1660 #define LPFC_FDMI_SMART_ATTR_guid		0x00020000 /* Vendor specific */
1661 #define LPFC_FDMI_SMART_ATTR_version		0x00040000 /* Vendor specific */
1662 #define LPFC_FDMI_SMART_ATTR_model		0x00080000 /* Vendor specific */
1663 #define LPFC_FDMI_SMART_ATTR_port_info		0x00100000 /* Vendor specific */
1664 #define LPFC_FDMI_SMART_ATTR_qos		0x00200000 /* Vendor specific */
1665 #define LPFC_FDMI_SMART_ATTR_security		0x00400000 /* Vendor specific */
1666 #define LPFC_FDMI_VENDOR_ATTR_mi		0x00800000 /* Vendor specific */
1667 
1668 /* Bit mask for FDMI-1 defined PORT attributes */
1669 #define LPFC_FDMI1_PORT_ATTR			0x0000003f
1670 
1671 /* Bit mask for FDMI-2 defined PORT attributes */
1672 #define LPFC_FDMI2_PORT_ATTR			0x0000ffff
1673 
1674 /* Bit mask for Smart SAN defined PORT attributes */
1675 #define LPFC_FDMI2_SMART_ATTR			0x007fffff
1676 
1677 /* Defines for PORT port state attribute */
1678 #define LPFC_FDMI_PORTSTATE_UNKNOWN	1
1679 #define LPFC_FDMI_PORTSTATE_ONLINE	2
1680 
1681 /* Defines for PORT port type attribute */
1682 #define LPFC_FDMI_PORTTYPE_UNKNOWN	0
1683 #define LPFC_FDMI_PORTTYPE_NPORT	1
1684 #define LPFC_FDMI_PORTTYPE_NLPORT	2
1685 
1686 /*
1687  *  Begin HBA configuration parameters.
1688  *  The PCI configuration register BAR assignments are:
1689  *  BAR0, offset 0x10 - SLIM base memory address
1690  *  BAR1, offset 0x14 - SLIM base memory high address
1691  *  BAR2, offset 0x18 - REGISTER base memory address
1692  *  BAR3, offset 0x1c - REGISTER base memory high address
1693  *  BAR4, offset 0x20 - BIU I/O registers
1694  *  BAR5, offset 0x24 - REGISTER base io high address
1695  */
1696 
1697 /* Number of rings currently used and available. */
1698 #define MAX_SLI3_CONFIGURED_RINGS     3
1699 #define MAX_SLI3_RINGS                4
1700 
1701 /* IOCB / Mailbox is owned by FireFly */
1702 #define OWN_CHIP        1
1703 
1704 /* IOCB / Mailbox is owned by Host */
1705 #define OWN_HOST        0
1706 
1707 /* Number of 4-byte words in an IOCB. */
1708 #define IOCB_WORD_SZ    8
1709 
1710 /* network headers for Dfctl field */
1711 #define FC_NET_HDR      0x20
1712 
1713 /* Start FireFly Register definitions */
1714 #define PCI_VENDOR_ID_EMULEX        0x10df
1715 #define PCI_DEVICE_ID_FIREFLY       0x1ae5
1716 #define PCI_DEVICE_ID_PROTEUS_VF    0xe100
1717 #define PCI_DEVICE_ID_BALIUS        0xe131
1718 #define PCI_DEVICE_ID_PROTEUS_PF    0xe180
1719 #define PCI_DEVICE_ID_LANCER_FC     0xe200
1720 #define PCI_DEVICE_ID_LANCER_FC_VF  0xe208
1721 #define PCI_DEVICE_ID_LANCER_FCOE   0xe260
1722 #define PCI_DEVICE_ID_LANCER_FCOE_VF 0xe268
1723 #define PCI_DEVICE_ID_LANCER_G6_FC  0xe300
1724 #define PCI_DEVICE_ID_LANCER_G7_FC  0xf400
1725 #define PCI_DEVICE_ID_LANCER_G7P_FC 0xf500
1726 #define PCI_DEVICE_ID_SAT_SMB       0xf011
1727 #define PCI_DEVICE_ID_SAT_MID       0xf015
1728 #define PCI_DEVICE_ID_RFLY          0xf095
1729 #define PCI_DEVICE_ID_PFLY          0xf098
1730 #define PCI_DEVICE_ID_LP101         0xf0a1
1731 #define PCI_DEVICE_ID_TFLY          0xf0a5
1732 #define PCI_DEVICE_ID_BSMB          0xf0d1
1733 #define PCI_DEVICE_ID_BMID          0xf0d5
1734 #define PCI_DEVICE_ID_ZSMB          0xf0e1
1735 #define PCI_DEVICE_ID_ZMID          0xf0e5
1736 #define PCI_DEVICE_ID_NEPTUNE       0xf0f5
1737 #define PCI_DEVICE_ID_NEPTUNE_SCSP  0xf0f6
1738 #define PCI_DEVICE_ID_NEPTUNE_DCSP  0xf0f7
1739 #define PCI_DEVICE_ID_SAT           0xf100
1740 #define PCI_DEVICE_ID_SAT_SCSP      0xf111
1741 #define PCI_DEVICE_ID_SAT_DCSP      0xf112
1742 #define PCI_DEVICE_ID_FALCON        0xf180
1743 #define PCI_DEVICE_ID_SUPERFLY      0xf700
1744 #define PCI_DEVICE_ID_DRAGONFLY     0xf800
1745 #define PCI_DEVICE_ID_CENTAUR       0xf900
1746 #define PCI_DEVICE_ID_PEGASUS       0xf980
1747 #define PCI_DEVICE_ID_THOR          0xfa00
1748 #define PCI_DEVICE_ID_VIPER         0xfb00
1749 #define PCI_DEVICE_ID_LP10000S      0xfc00
1750 #define PCI_DEVICE_ID_LP11000S      0xfc10
1751 #define PCI_DEVICE_ID_LPE11000S     0xfc20
1752 #define PCI_DEVICE_ID_SAT_S         0xfc40
1753 #define PCI_DEVICE_ID_PROTEUS_S     0xfc50
1754 #define PCI_DEVICE_ID_HELIOS        0xfd00
1755 #define PCI_DEVICE_ID_HELIOS_SCSP   0xfd11
1756 #define PCI_DEVICE_ID_HELIOS_DCSP   0xfd12
1757 #define PCI_DEVICE_ID_ZEPHYR        0xfe00
1758 #define PCI_DEVICE_ID_ZEPHYR_SCSP   0xfe11
1759 #define PCI_DEVICE_ID_ZEPHYR_DCSP   0xfe12
1760 #define PCI_VENDOR_ID_SERVERENGINE  0x19a2
1761 #define PCI_DEVICE_ID_TIGERSHARK    0x0704
1762 #define PCI_DEVICE_ID_TOMCAT        0x0714
1763 #define PCI_DEVICE_ID_SKYHAWK       0x0724
1764 #define PCI_DEVICE_ID_SKYHAWK_VF    0x072c
1765 #define PCI_VENDOR_ID_ATTO          0x117c
1766 #define PCI_DEVICE_ID_CLRY_16XE     0x0064
1767 #define PCI_DEVICE_ID_CLRY_161E     0x0063
1768 #define PCI_DEVICE_ID_CLRY_162E     0x0064
1769 #define PCI_DEVICE_ID_CLRY_164E     0x0065
1770 #define PCI_DEVICE_ID_CLRY_16XP     0x0094
1771 #define PCI_DEVICE_ID_CLRY_161P     0x00a0
1772 #define PCI_DEVICE_ID_CLRY_162P     0x0094
1773 #define PCI_DEVICE_ID_CLRY_164P     0x00a1
1774 #define PCI_DEVICE_ID_CLRY_32XE     0x0094
1775 #define PCI_DEVICE_ID_CLRY_321E     0x00a2
1776 #define PCI_DEVICE_ID_CLRY_322E     0x00a3
1777 #define PCI_DEVICE_ID_CLRY_324E     0x00ac
1778 #define PCI_DEVICE_ID_CLRY_32XP     0x00bb
1779 #define PCI_DEVICE_ID_CLRY_321P     0x00bc
1780 #define PCI_DEVICE_ID_CLRY_322P     0x00bd
1781 #define PCI_DEVICE_ID_CLRY_324P     0x00be
1782 #define PCI_DEVICE_ID_TLFC_2        0x0064
1783 #define PCI_DEVICE_ID_TLFC_2XX2     0x4064
1784 #define PCI_DEVICE_ID_TLFC_3        0x0094
1785 #define PCI_DEVICE_ID_TLFC_3162     0x40a6
1786 #define PCI_DEVICE_ID_TLFC_3322     0x40a7
1787 
1788 #define JEDEC_ID_ADDRESS            0x0080001c
1789 #define FIREFLY_JEDEC_ID            0x1ACC
1790 #define SUPERFLY_JEDEC_ID           0x0020
1791 #define DRAGONFLY_JEDEC_ID          0x0021
1792 #define DRAGONFLY_V2_JEDEC_ID       0x0025
1793 #define CENTAUR_2G_JEDEC_ID         0x0026
1794 #define CENTAUR_1G_JEDEC_ID         0x0028
1795 #define PEGASUS_ORION_JEDEC_ID      0x0036
1796 #define PEGASUS_JEDEC_ID            0x0038
1797 #define THOR_JEDEC_ID               0x0012
1798 #define HELIOS_JEDEC_ID             0x0364
1799 #define ZEPHYR_JEDEC_ID             0x0577
1800 #define VIPER_JEDEC_ID              0x4838
1801 #define SATURN_JEDEC_ID             0x1004
1802 
1803 #define JEDEC_ID_MASK               0x0FFFF000
1804 #define JEDEC_ID_SHIFT              12
1805 #define FC_JEDEC_ID(id)             ((id & JEDEC_ID_MASK) >> JEDEC_ID_SHIFT)
1806 
1807 typedef struct {		/* FireFly BIU registers */
1808 	uint32_t hostAtt;	/* See definitions for Host Attention
1809 				   register */
1810 	uint32_t chipAtt;	/* See definitions for Chip Attention
1811 				   register */
1812 	uint32_t hostStatus;	/* See definitions for Host Status register */
1813 	uint32_t hostControl;	/* See definitions for Host Control register */
1814 	uint32_t buiConfig;	/* See definitions for BIU configuration
1815 				   register */
1816 } FF_REGS;
1817 
1818 /* IO Register size in bytes */
1819 #define FF_REG_AREA_SIZE       256
1820 
1821 /* Host Attention Register */
1822 
1823 #define HA_REG_OFFSET  0	/* Byte offset from register base address */
1824 
1825 #define HA_R0RE_REQ    0x00000001	/* Bit  0 */
1826 #define HA_R0CE_RSP    0x00000002	/* Bit  1 */
1827 #define HA_R0ATT       0x00000008	/* Bit  3 */
1828 #define HA_R1RE_REQ    0x00000010	/* Bit  4 */
1829 #define HA_R1CE_RSP    0x00000020	/* Bit  5 */
1830 #define HA_R1ATT       0x00000080	/* Bit  7 */
1831 #define HA_R2RE_REQ    0x00000100	/* Bit  8 */
1832 #define HA_R2CE_RSP    0x00000200	/* Bit  9 */
1833 #define HA_R2ATT       0x00000800	/* Bit 11 */
1834 #define HA_R3RE_REQ    0x00001000	/* Bit 12 */
1835 #define HA_R3CE_RSP    0x00002000	/* Bit 13 */
1836 #define HA_R3ATT       0x00008000	/* Bit 15 */
1837 #define HA_LATT        0x20000000	/* Bit 29 */
1838 #define HA_MBATT       0x40000000	/* Bit 30 */
1839 #define HA_ERATT       0x80000000	/* Bit 31 */
1840 
1841 #define HA_RXRE_REQ    0x00000001	/* Bit  0 */
1842 #define HA_RXCE_RSP    0x00000002	/* Bit  1 */
1843 #define HA_RXATT       0x00000008	/* Bit  3 */
1844 #define HA_RXMASK      0x0000000f
1845 
1846 #define HA_R0_CLR_MSK	(HA_R0RE_REQ | HA_R0CE_RSP | HA_R0ATT)
1847 #define HA_R1_CLR_MSK	(HA_R1RE_REQ | HA_R1CE_RSP | HA_R1ATT)
1848 #define HA_R2_CLR_MSK	(HA_R2RE_REQ | HA_R2CE_RSP | HA_R2ATT)
1849 #define HA_R3_CLR_MSK	(HA_R3RE_REQ | HA_R3CE_RSP | HA_R3ATT)
1850 
1851 #define HA_R0_POS	3
1852 #define HA_R1_POS	7
1853 #define HA_R2_POS	11
1854 #define HA_R3_POS	15
1855 #define HA_LE_POS	29
1856 #define HA_MB_POS	30
1857 #define HA_ER_POS	31
1858 /* Chip Attention Register */
1859 
1860 #define CA_REG_OFFSET  4	/* Byte offset from register base address */
1861 
1862 #define CA_R0CE_REQ    0x00000001	/* Bit  0 */
1863 #define CA_R0RE_RSP    0x00000002	/* Bit  1 */
1864 #define CA_R0ATT       0x00000008	/* Bit  3 */
1865 #define CA_R1CE_REQ    0x00000010	/* Bit  4 */
1866 #define CA_R1RE_RSP    0x00000020	/* Bit  5 */
1867 #define CA_R1ATT       0x00000080	/* Bit  7 */
1868 #define CA_R2CE_REQ    0x00000100	/* Bit  8 */
1869 #define CA_R2RE_RSP    0x00000200	/* Bit  9 */
1870 #define CA_R2ATT       0x00000800	/* Bit 11 */
1871 #define CA_R3CE_REQ    0x00001000	/* Bit 12 */
1872 #define CA_R3RE_RSP    0x00002000	/* Bit 13 */
1873 #define CA_R3ATT       0x00008000	/* Bit 15 */
1874 #define CA_MBATT       0x40000000	/* Bit 30 */
1875 
1876 /* Host Status Register */
1877 
1878 #define HS_REG_OFFSET  8	/* Byte offset from register base address */
1879 
1880 #define HS_MBRDY       0x00400000	/* Bit 22 */
1881 #define HS_FFRDY       0x00800000	/* Bit 23 */
1882 #define HS_FFER8       0x01000000	/* Bit 24 */
1883 #define HS_FFER7       0x02000000	/* Bit 25 */
1884 #define HS_FFER6       0x04000000	/* Bit 26 */
1885 #define HS_FFER5       0x08000000	/* Bit 27 */
1886 #define HS_FFER4       0x10000000	/* Bit 28 */
1887 #define HS_FFER3       0x20000000	/* Bit 29 */
1888 #define HS_FFER2       0x40000000	/* Bit 30 */
1889 #define HS_FFER1       0x80000000	/* Bit 31 */
1890 #define HS_CRIT_TEMP   0x00000100	/* Bit 8  */
1891 #define HS_FFERM       0xFF000100	/* Mask for error bits 31:24 and 8 */
1892 #define UNPLUG_ERR     0x00000001	/* Indicate pci hot unplug */
1893 /* Host Control Register */
1894 
1895 #define HC_REG_OFFSET  12	/* Byte offset from register base address */
1896 
1897 #define HC_MBINT_ENA   0x00000001	/* Bit  0 */
1898 #define HC_R0INT_ENA   0x00000002	/* Bit  1 */
1899 #define HC_R1INT_ENA   0x00000004	/* Bit  2 */
1900 #define HC_R2INT_ENA   0x00000008	/* Bit  3 */
1901 #define HC_R3INT_ENA   0x00000010	/* Bit  4 */
1902 #define HC_INITHBI     0x02000000	/* Bit 25 */
1903 #define HC_INITMB      0x04000000	/* Bit 26 */
1904 #define HC_INITFF      0x08000000	/* Bit 27 */
1905 #define HC_LAINT_ENA   0x20000000	/* Bit 29 */
1906 #define HC_ERINT_ENA   0x80000000	/* Bit 31 */
1907 
1908 /* Message Signaled Interrupt eXtension (MSI-X) message identifiers */
1909 #define MSIX_DFLT_ID	0
1910 #define MSIX_RNG0_ID	0
1911 #define MSIX_RNG1_ID	1
1912 #define MSIX_RNG2_ID	2
1913 #define MSIX_RNG3_ID	3
1914 
1915 #define MSIX_LINK_ID	4
1916 #define MSIX_MBOX_ID	5
1917 
1918 #define MSIX_SPARE0_ID	6
1919 #define MSIX_SPARE1_ID	7
1920 
1921 /* Mailbox Commands */
1922 #define MBX_SHUTDOWN        0x00	/* terminate testing */
1923 #define MBX_LOAD_SM         0x01
1924 #define MBX_READ_NV         0x02
1925 #define MBX_WRITE_NV        0x03
1926 #define MBX_RUN_BIU_DIAG    0x04
1927 #define MBX_INIT_LINK       0x05
1928 #define MBX_DOWN_LINK       0x06
1929 #define MBX_CONFIG_LINK     0x07
1930 #define MBX_CONFIG_RING     0x09
1931 #define MBX_RESET_RING      0x0A
1932 #define MBX_READ_CONFIG     0x0B
1933 #define MBX_READ_RCONFIG    0x0C
1934 #define MBX_READ_SPARM      0x0D
1935 #define MBX_READ_STATUS     0x0E
1936 #define MBX_READ_RPI        0x0F
1937 #define MBX_READ_XRI        0x10
1938 #define MBX_READ_REV        0x11
1939 #define MBX_READ_LNK_STAT   0x12
1940 #define MBX_REG_LOGIN       0x13
1941 #define MBX_UNREG_LOGIN     0x14
1942 #define MBX_CLEAR_LA        0x16
1943 #define MBX_DUMP_MEMORY     0x17
1944 #define MBX_DUMP_CONTEXT    0x18
1945 #define MBX_RUN_DIAGS       0x19
1946 #define MBX_RESTART         0x1A
1947 #define MBX_UPDATE_CFG      0x1B
1948 #define MBX_DOWN_LOAD       0x1C
1949 #define MBX_DEL_LD_ENTRY    0x1D
1950 #define MBX_RUN_PROGRAM     0x1E
1951 #define MBX_SET_MASK        0x20
1952 #define MBX_SET_VARIABLE    0x21
1953 #define MBX_UNREG_D_ID      0x23
1954 #define MBX_KILL_BOARD      0x24
1955 #define MBX_CONFIG_FARP     0x25
1956 #define MBX_BEACON          0x2A
1957 #define MBX_CONFIG_MSI      0x30
1958 #define MBX_HEARTBEAT       0x31
1959 #define MBX_WRITE_VPARMS    0x32
1960 #define MBX_ASYNCEVT_ENABLE 0x33
1961 #define MBX_READ_EVENT_LOG_STATUS 0x37
1962 #define MBX_READ_EVENT_LOG  0x38
1963 #define MBX_WRITE_EVENT_LOG 0x39
1964 
1965 #define MBX_PORT_CAPABILITIES 0x3B
1966 #define MBX_PORT_IOV_CONTROL 0x3C
1967 
1968 #define MBX_CONFIG_HBQ	    0x7C
1969 #define MBX_LOAD_AREA       0x81
1970 #define MBX_RUN_BIU_DIAG64  0x84
1971 #define MBX_CONFIG_PORT     0x88
1972 #define MBX_READ_SPARM64    0x8D
1973 #define MBX_READ_RPI64      0x8F
1974 #define MBX_REG_LOGIN64     0x93
1975 #define MBX_READ_TOPOLOGY   0x95
1976 #define MBX_REG_VPI	    0x96
1977 #define MBX_UNREG_VPI	    0x97
1978 
1979 #define MBX_WRITE_WWN       0x98
1980 #define MBX_SET_DEBUG       0x99
1981 #define MBX_LOAD_EXP_ROM    0x9C
1982 #define MBX_SLI4_CONFIG	    0x9B
1983 #define MBX_SLI4_REQ_FTRS   0x9D
1984 #define MBX_MAX_CMDS        0x9E
1985 #define MBX_RESUME_RPI      0x9E
1986 #define MBX_SLI2_CMD_MASK   0x80
1987 #define MBX_REG_VFI         0x9F
1988 #define MBX_REG_FCFI        0xA0
1989 #define MBX_UNREG_VFI       0xA1
1990 #define MBX_UNREG_FCFI	    0xA2
1991 #define MBX_INIT_VFI        0xA3
1992 #define MBX_INIT_VPI        0xA4
1993 #define MBX_ACCESS_VDATA    0xA5
1994 #define MBX_REG_FCFI_MRQ    0xAF
1995 
1996 #define MBX_AUTH_PORT       0xF8
1997 #define MBX_SECURITY_MGMT   0xF9
1998 
1999 /* IOCB Commands */
2000 
2001 #define CMD_RCV_SEQUENCE_CX     0x01
2002 #define CMD_XMIT_SEQUENCE_CR    0x02
2003 #define CMD_XMIT_SEQUENCE_CX    0x03
2004 #define CMD_XMIT_BCAST_CN       0x04
2005 #define CMD_XMIT_BCAST_CX       0x05
2006 #define CMD_QUE_RING_BUF_CN     0x06
2007 #define CMD_QUE_XRI_BUF_CX      0x07
2008 #define CMD_IOCB_CONTINUE_CN    0x08
2009 #define CMD_RET_XRI_BUF_CX      0x09
2010 #define CMD_ELS_REQUEST_CR      0x0A
2011 #define CMD_ELS_REQUEST_CX      0x0B
2012 #define CMD_RCV_ELS_REQ_CX      0x0D
2013 #define CMD_ABORT_XRI_CN        0x0E
2014 #define CMD_ABORT_XRI_CX        0x0F
2015 #define CMD_CLOSE_XRI_CN        0x10
2016 #define CMD_CLOSE_XRI_CX        0x11
2017 #define CMD_CREATE_XRI_CR       0x12
2018 #define CMD_CREATE_XRI_CX       0x13
2019 #define CMD_GET_RPI_CN          0x14
2020 #define CMD_XMIT_ELS_RSP_CX     0x15
2021 #define CMD_GET_RPI_CR          0x16
2022 #define CMD_XRI_ABORTED_CX      0x17
2023 #define CMD_FCP_IWRITE_CR       0x18
2024 #define CMD_FCP_IWRITE_CX       0x19
2025 #define CMD_FCP_IREAD_CR        0x1A
2026 #define CMD_FCP_IREAD_CX        0x1B
2027 #define CMD_FCP_ICMND_CR        0x1C
2028 #define CMD_FCP_ICMND_CX        0x1D
2029 #define CMD_FCP_TSEND_CX        0x1F
2030 #define CMD_FCP_TRECEIVE_CX     0x21
2031 #define CMD_FCP_TRSP_CX	        0x23
2032 #define CMD_FCP_AUTO_TRSP_CX    0x29
2033 
2034 #define CMD_ADAPTER_MSG         0x20
2035 #define CMD_ADAPTER_DUMP        0x22
2036 
2037 /*  SLI_2 IOCB Command Set */
2038 
2039 #define CMD_ASYNC_STATUS        0x7C
2040 #define CMD_RCV_SEQUENCE64_CX   0x81
2041 #define CMD_XMIT_SEQUENCE64_CR  0x82
2042 #define CMD_XMIT_SEQUENCE64_CX  0x83
2043 #define CMD_XMIT_BCAST64_CN     0x84
2044 #define CMD_XMIT_BCAST64_CX     0x85
2045 #define CMD_QUE_RING_BUF64_CN   0x86
2046 #define CMD_QUE_XRI_BUF64_CX    0x87
2047 #define CMD_IOCB_CONTINUE64_CN  0x88
2048 #define CMD_RET_XRI_BUF64_CX    0x89
2049 #define CMD_ELS_REQUEST64_CR    0x8A
2050 #define CMD_ELS_REQUEST64_CX    0x8B
2051 #define CMD_ABORT_MXRI64_CN     0x8C
2052 #define CMD_RCV_ELS_REQ64_CX    0x8D
2053 #define CMD_XMIT_ELS_RSP64_CX   0x95
2054 #define CMD_XMIT_BLS_RSP64_CX   0x97
2055 #define CMD_FCP_IWRITE64_CR     0x98
2056 #define CMD_FCP_IWRITE64_CX     0x99
2057 #define CMD_FCP_IREAD64_CR      0x9A
2058 #define CMD_FCP_IREAD64_CX      0x9B
2059 #define CMD_FCP_ICMND64_CR      0x9C
2060 #define CMD_FCP_ICMND64_CX      0x9D
2061 #define CMD_FCP_TSEND64_CX      0x9F
2062 #define CMD_FCP_TRECEIVE64_CX   0xA1
2063 #define CMD_FCP_TRSP64_CX       0xA3
2064 
2065 #define CMD_QUE_XRI64_CX	0xB3
2066 #define CMD_IOCB_RCV_SEQ64_CX	0xB5
2067 #define CMD_IOCB_RCV_ELS64_CX	0xB7
2068 #define CMD_IOCB_RET_XRI64_CX	0xB9
2069 #define CMD_IOCB_RCV_CONT64_CX	0xBB
2070 
2071 #define CMD_GEN_REQUEST64_CR    0xC2
2072 #define CMD_GEN_REQUEST64_CX    0xC3
2073 
2074 /* Unhandled SLI-3 Commands */
2075 #define CMD_IOCB_XMIT_MSEQ64_CR		0xB0
2076 #define CMD_IOCB_XMIT_MSEQ64_CX		0xB1
2077 #define CMD_IOCB_RCV_SEQ_LIST64_CX	0xC1
2078 #define CMD_IOCB_RCV_ELS_LIST64_CX	0xCD
2079 #define CMD_IOCB_CLOSE_EXTENDED_CN	0xB6
2080 #define CMD_IOCB_ABORT_EXTENDED_CN	0xBA
2081 #define CMD_IOCB_RET_HBQE64_CN		0xCA
2082 #define CMD_IOCB_FCP_IBIDIR64_CR	0xAC
2083 #define CMD_IOCB_FCP_IBIDIR64_CX	0xAD
2084 #define CMD_IOCB_FCP_ITASKMGT64_CX	0xAF
2085 #define CMD_IOCB_LOGENTRY_CN		0x94
2086 #define CMD_IOCB_LOGENTRY_ASYNC_CN	0x96
2087 
2088 /* Data Security SLI Commands */
2089 #define DSSCMD_IWRITE64_CR		0xF8
2090 #define DSSCMD_IWRITE64_CX		0xF9
2091 #define DSSCMD_IREAD64_CR		0xFA
2092 #define DSSCMD_IREAD64_CX		0xFB
2093 
2094 #define CMD_MAX_IOCB_CMD        0xFB
2095 #define CMD_IOCB_MASK           0xff
2096 
2097 #define MAX_MSG_DATA            28	/* max msg data in CMD_ADAPTER_MSG
2098 					   iocb */
2099 #define LPFC_MAX_ADPTMSG         32	/* max msg data */
2100 /*
2101  *  Define Status
2102  */
2103 #define MBX_SUCCESS                 0
2104 #define MBXERR_NUM_RINGS            1
2105 #define MBXERR_NUM_IOCBS            2
2106 #define MBXERR_IOCBS_EXCEEDED       3
2107 #define MBXERR_BAD_RING_NUMBER      4
2108 #define MBXERR_MASK_ENTRIES_RANGE   5
2109 #define MBXERR_MASKS_EXCEEDED       6
2110 #define MBXERR_BAD_PROFILE          7
2111 #define MBXERR_BAD_DEF_CLASS        8
2112 #define MBXERR_BAD_MAX_RESPONDER    9
2113 #define MBXERR_BAD_MAX_ORIGINATOR   10
2114 #define MBXERR_RPI_REGISTERED       11
2115 #define MBXERR_RPI_FULL             12
2116 #define MBXERR_NO_RESOURCES         13
2117 #define MBXERR_BAD_RCV_LENGTH       14
2118 #define MBXERR_DMA_ERROR            15
2119 #define MBXERR_ERROR                16
2120 #define MBXERR_LINK_DOWN            0x33
2121 #define MBXERR_SEC_NO_PERMISSION    0xF02
2122 #define MBX_NOT_FINISHED            255
2123 
2124 #define MBX_BUSY                   0xffffff /* Attempted cmd to busy Mailbox */
2125 #define MBX_TIMEOUT                0xfffffe /* time-out expired waiting for */
2126 
2127 #define TEMPERATURE_OFFSET 0xB0	/* Slim offset for critical temperature event */
2128 
2129 /*
2130  * return code Fail
2131  */
2132 #define FAILURE 1
2133 
2134 /*
2135  *    Begin Structure Definitions for Mailbox Commands
2136  */
2137 
2138 typedef struct {
2139 #ifdef __BIG_ENDIAN_BITFIELD
2140 	uint8_t tval;
2141 	uint8_t tmask;
2142 	uint8_t rval;
2143 	uint8_t rmask;
2144 #else	/*  __LITTLE_ENDIAN_BITFIELD */
2145 	uint8_t rmask;
2146 	uint8_t rval;
2147 	uint8_t tmask;
2148 	uint8_t tval;
2149 #endif
2150 } RR_REG;
2151 
2152 struct ulp_bde {
2153 	uint32_t bdeAddress;
2154 #ifdef __BIG_ENDIAN_BITFIELD
2155 	uint32_t bdeReserved:4;
2156 	uint32_t bdeAddrHigh:4;
2157 	uint32_t bdeSize:24;
2158 #else	/*  __LITTLE_ENDIAN_BITFIELD */
2159 	uint32_t bdeSize:24;
2160 	uint32_t bdeAddrHigh:4;
2161 	uint32_t bdeReserved:4;
2162 #endif
2163 };
2164 
2165 typedef struct ULP_BDL {	/* SLI-2 */
2166 #ifdef __BIG_ENDIAN_BITFIELD
2167 	uint32_t bdeFlags:8;	/* BDL Flags */
2168 	uint32_t bdeSize:24;	/* Size of BDL array in host memory (bytes) */
2169 #else	/*  __LITTLE_ENDIAN_BITFIELD */
2170 	uint32_t bdeSize:24;	/* Size of BDL array in host memory (bytes) */
2171 	uint32_t bdeFlags:8;	/* BDL Flags */
2172 #endif
2173 
2174 	uint32_t addrLow;	/* Address 0:31 */
2175 	uint32_t addrHigh;	/* Address 32:63 */
2176 	uint32_t ulpIoTag32;	/* Can be used for 32 bit I/O Tag */
2177 } ULP_BDL;
2178 
2179 /*
2180  * BlockGuard Definitions
2181  */
2182 
2183 enum lpfc_protgrp_type {
2184 	LPFC_PG_TYPE_INVALID = 0, /* used to indicate errors                  */
2185 	LPFC_PG_TYPE_NO_DIF,	  /* no DIF data pointed to by prot grp       */
2186 	LPFC_PG_TYPE_EMBD_DIF,	  /* DIF is embedded (inline) with data       */
2187 	LPFC_PG_TYPE_DIF_BUF	  /* DIF has its own scatter/gather list      */
2188 };
2189 
2190 /* PDE Descriptors */
2191 #define LPFC_PDE5_DESCRIPTOR		0x85
2192 #define LPFC_PDE6_DESCRIPTOR		0x86
2193 #define LPFC_PDE7_DESCRIPTOR		0x87
2194 
2195 /* BlockGuard Opcodes */
2196 #define BG_OP_IN_NODIF_OUT_CRC		0x0
2197 #define	BG_OP_IN_CRC_OUT_NODIF		0x1
2198 #define	BG_OP_IN_NODIF_OUT_CSUM		0x2
2199 #define	BG_OP_IN_CSUM_OUT_NODIF		0x3
2200 #define	BG_OP_IN_CRC_OUT_CRC		0x4
2201 #define	BG_OP_IN_CSUM_OUT_CSUM		0x5
2202 #define	BG_OP_IN_CRC_OUT_CSUM		0x6
2203 #define	BG_OP_IN_CSUM_OUT_CRC		0x7
2204 #define	BG_OP_RAW_MODE			0x8
2205 
2206 struct lpfc_pde5 {
2207 	uint32_t word0;
2208 #define pde5_type_SHIFT		24
2209 #define pde5_type_MASK		0x000000ff
2210 #define pde5_type_WORD		word0
2211 #define pde5_rsvd0_SHIFT	0
2212 #define pde5_rsvd0_MASK		0x00ffffff
2213 #define pde5_rsvd0_WORD		word0
2214 	uint32_t reftag;	/* Reference Tag Value			*/
2215 	uint32_t reftagtr;	/* Reference Tag Translation Value 	*/
2216 };
2217 
2218 struct lpfc_pde6 {
2219 	uint32_t word0;
2220 #define pde6_type_SHIFT		24
2221 #define pde6_type_MASK		0x000000ff
2222 #define pde6_type_WORD		word0
2223 #define pde6_rsvd0_SHIFT	0
2224 #define pde6_rsvd0_MASK		0x00ffffff
2225 #define pde6_rsvd0_WORD		word0
2226 	uint32_t word1;
2227 #define pde6_rsvd1_SHIFT	26
2228 #define pde6_rsvd1_MASK		0x0000003f
2229 #define pde6_rsvd1_WORD		word1
2230 #define pde6_na_SHIFT		25
2231 #define pde6_na_MASK		0x00000001
2232 #define pde6_na_WORD		word1
2233 #define pde6_rsvd2_SHIFT	16
2234 #define pde6_rsvd2_MASK		0x000001FF
2235 #define pde6_rsvd2_WORD		word1
2236 #define pde6_apptagtr_SHIFT	0
2237 #define pde6_apptagtr_MASK	0x0000ffff
2238 #define pde6_apptagtr_WORD	word1
2239 	uint32_t word2;
2240 #define pde6_optx_SHIFT		28
2241 #define pde6_optx_MASK		0x0000000f
2242 #define pde6_optx_WORD		word2
2243 #define pde6_oprx_SHIFT		24
2244 #define pde6_oprx_MASK		0x0000000f
2245 #define pde6_oprx_WORD		word2
2246 #define pde6_nr_SHIFT		23
2247 #define pde6_nr_MASK		0x00000001
2248 #define pde6_nr_WORD		word2
2249 #define pde6_ce_SHIFT		22
2250 #define pde6_ce_MASK		0x00000001
2251 #define pde6_ce_WORD		word2
2252 #define pde6_re_SHIFT		21
2253 #define pde6_re_MASK		0x00000001
2254 #define pde6_re_WORD		word2
2255 #define pde6_ae_SHIFT		20
2256 #define pde6_ae_MASK		0x00000001
2257 #define pde6_ae_WORD		word2
2258 #define pde6_ai_SHIFT		19
2259 #define pde6_ai_MASK		0x00000001
2260 #define pde6_ai_WORD		word2
2261 #define pde6_bs_SHIFT		16
2262 #define pde6_bs_MASK		0x00000007
2263 #define pde6_bs_WORD		word2
2264 #define pde6_apptagval_SHIFT	0
2265 #define pde6_apptagval_MASK	0x0000ffff
2266 #define pde6_apptagval_WORD	word2
2267 };
2268 
2269 struct lpfc_pde7 {
2270 	uint32_t word0;
2271 #define pde7_type_SHIFT		24
2272 #define pde7_type_MASK		0x000000ff
2273 #define pde7_type_WORD		word0
2274 #define pde7_rsvd0_SHIFT	0
2275 #define pde7_rsvd0_MASK		0x00ffffff
2276 #define pde7_rsvd0_WORD		word0
2277 	uint32_t addrHigh;
2278 	uint32_t addrLow;
2279 };
2280 
2281 /* Structure for MB Command LOAD_SM and DOWN_LOAD */
2282 
2283 typedef struct {
2284 #ifdef __BIG_ENDIAN_BITFIELD
2285 	uint32_t rsvd2:25;
2286 	uint32_t acknowledgment:1;
2287 	uint32_t version:1;
2288 	uint32_t erase_or_prog:1;
2289 	uint32_t update_flash:1;
2290 	uint32_t update_ram:1;
2291 	uint32_t method:1;
2292 	uint32_t load_cmplt:1;
2293 #else	/*  __LITTLE_ENDIAN_BITFIELD */
2294 	uint32_t load_cmplt:1;
2295 	uint32_t method:1;
2296 	uint32_t update_ram:1;
2297 	uint32_t update_flash:1;
2298 	uint32_t erase_or_prog:1;
2299 	uint32_t version:1;
2300 	uint32_t acknowledgment:1;
2301 	uint32_t rsvd2:25;
2302 #endif
2303 
2304 	uint32_t dl_to_adr_low;
2305 	uint32_t dl_to_adr_high;
2306 	uint32_t dl_len;
2307 	union {
2308 		uint32_t dl_from_mbx_offset;
2309 		struct ulp_bde dl_from_bde;
2310 		struct ulp_bde64 dl_from_bde64;
2311 	} un;
2312 
2313 } LOAD_SM_VAR;
2314 
2315 /* Structure for MB Command READ_NVPARM (02) */
2316 
2317 typedef struct {
2318 	uint32_t rsvd1[3];	/* Read as all one's */
2319 	uint32_t rsvd2;		/* Read as all zero's */
2320 	uint32_t portname[2];	/* N_PORT name */
2321 	uint32_t nodename[2];	/* NODE name */
2322 
2323 #ifdef __BIG_ENDIAN_BITFIELD
2324 	uint32_t pref_DID:24;
2325 	uint32_t hardAL_PA:8;
2326 #else	/*  __LITTLE_ENDIAN_BITFIELD */
2327 	uint32_t hardAL_PA:8;
2328 	uint32_t pref_DID:24;
2329 #endif
2330 
2331 	uint32_t rsvd3[21];	/* Read as all one's */
2332 } READ_NV_VAR;
2333 
2334 /* Structure for MB Command WRITE_NVPARMS (03) */
2335 
2336 typedef struct {
2337 	uint32_t rsvd1[3];	/* Must be all one's */
2338 	uint32_t rsvd2;		/* Must be all zero's */
2339 	uint32_t portname[2];	/* N_PORT name */
2340 	uint32_t nodename[2];	/* NODE name */
2341 
2342 #ifdef __BIG_ENDIAN_BITFIELD
2343 	uint32_t pref_DID:24;
2344 	uint32_t hardAL_PA:8;
2345 #else	/*  __LITTLE_ENDIAN_BITFIELD */
2346 	uint32_t hardAL_PA:8;
2347 	uint32_t pref_DID:24;
2348 #endif
2349 
2350 	uint32_t rsvd3[21];	/* Must be all one's */
2351 } WRITE_NV_VAR;
2352 
2353 /* Structure for MB Command RUN_BIU_DIAG (04) */
2354 /* Structure for MB Command RUN_BIU_DIAG64 (0x84) */
2355 
2356 typedef struct {
2357 	uint32_t rsvd1;
2358 	union {
2359 		struct {
2360 			struct ulp_bde xmit_bde;
2361 			struct ulp_bde rcv_bde;
2362 		} s1;
2363 		struct {
2364 			struct ulp_bde64 xmit_bde64;
2365 			struct ulp_bde64 rcv_bde64;
2366 		} s2;
2367 	} un;
2368 } BIU_DIAG_VAR;
2369 
2370 /* Structure for MB command READ_EVENT_LOG (0x38) */
2371 struct READ_EVENT_LOG_VAR {
2372 	uint32_t word1;
2373 #define lpfc_event_log_SHIFT	29
2374 #define lpfc_event_log_MASK	0x00000001
2375 #define lpfc_event_log_WORD	word1
2376 #define USE_MAILBOX_RESPONSE	1
2377 	uint32_t offset;
2378 	struct ulp_bde64 rcv_bde64;
2379 };
2380 
2381 /* Structure for MB Command INIT_LINK (05) */
2382 
2383 typedef struct {
2384 #ifdef __BIG_ENDIAN_BITFIELD
2385 	uint32_t rsvd1:24;
2386 	uint32_t lipsr_AL_PA:8;	/* AL_PA to issue Lip Selective Reset to */
2387 #else	/*  __LITTLE_ENDIAN_BITFIELD */
2388 	uint32_t lipsr_AL_PA:8;	/* AL_PA to issue Lip Selective Reset to */
2389 	uint32_t rsvd1:24;
2390 #endif
2391 
2392 #ifdef __BIG_ENDIAN_BITFIELD
2393 	uint8_t fabric_AL_PA;	/* If using a Fabric Assigned AL_PA */
2394 	uint8_t rsvd2;
2395 	uint16_t link_flags;
2396 #else	/*  __LITTLE_ENDIAN_BITFIELD */
2397 	uint16_t link_flags;
2398 	uint8_t rsvd2;
2399 	uint8_t fabric_AL_PA;	/* If using a Fabric Assigned AL_PA */
2400 #endif
2401 
2402 #define FLAGS_TOPOLOGY_MODE_LOOP_PT  0x00 /* Attempt loop then pt-pt */
2403 #define FLAGS_LOCAL_LB               0x01 /* link_flags (=1) ENDEC loopback */
2404 #define FLAGS_TOPOLOGY_MODE_PT_PT    0x02 /* Attempt pt-pt only */
2405 #define FLAGS_TOPOLOGY_MODE_LOOP     0x04 /* Attempt loop only */
2406 #define FLAGS_TOPOLOGY_MODE_PT_LOOP  0x06 /* Attempt pt-pt then loop */
2407 #define	FLAGS_UNREG_LOGIN_ALL	     0x08 /* UNREG_LOGIN all on link down */
2408 #define FLAGS_LIRP_LILP              0x80 /* LIRP / LILP is disabled */
2409 
2410 #define FLAGS_TOPOLOGY_FAILOVER      0x0400	/* Bit 10 */
2411 #define FLAGS_LINK_SPEED             0x0800	/* Bit 11 */
2412 #define FLAGS_IMED_ABORT             0x04000	/* Bit 14 */
2413 
2414 	uint32_t link_speed;
2415 #define LINK_SPEED_AUTO 0x0     /* Auto selection */
2416 #define LINK_SPEED_1G   0x1     /* 1 Gigabaud */
2417 #define LINK_SPEED_2G   0x2     /* 2 Gigabaud */
2418 #define LINK_SPEED_4G   0x4     /* 4 Gigabaud */
2419 #define LINK_SPEED_8G   0x8     /* 8 Gigabaud */
2420 #define LINK_SPEED_10G  0x10    /* 10 Gigabaud */
2421 #define LINK_SPEED_16G  0x11    /* 16 Gigabaud */
2422 #define LINK_SPEED_32G  0x14    /* 32 Gigabaud */
2423 #define LINK_SPEED_64G  0x17    /* 64 Gigabaud */
2424 #define LINK_SPEED_128G 0x1A    /* 128 Gigabaud */
2425 #define LINK_SPEED_256G 0x1D    /* 256 Gigabaud */
2426 
2427 } INIT_LINK_VAR;
2428 
2429 /* Structure for MB Command DOWN_LINK (06) */
2430 
2431 typedef struct {
2432 	uint32_t rsvd1;
2433 } DOWN_LINK_VAR;
2434 
2435 /* Structure for MB Command CONFIG_LINK (07) */
2436 
2437 typedef struct {
2438 #ifdef __BIG_ENDIAN_BITFIELD
2439 	uint32_t cr:1;
2440 	uint32_t ci:1;
2441 	uint32_t cr_delay:6;
2442 	uint32_t cr_count:8;
2443 	uint32_t rsvd1:8;
2444 	uint32_t MaxBBC:8;
2445 #else	/*  __LITTLE_ENDIAN_BITFIELD */
2446 	uint32_t MaxBBC:8;
2447 	uint32_t rsvd1:8;
2448 	uint32_t cr_count:8;
2449 	uint32_t cr_delay:6;
2450 	uint32_t ci:1;
2451 	uint32_t cr:1;
2452 #endif
2453 
2454 	uint32_t myId;
2455 	uint32_t rsvd2;
2456 	uint32_t edtov;
2457 	uint32_t arbtov;
2458 	uint32_t ratov;
2459 	uint32_t rttov;
2460 	uint32_t altov;
2461 	uint32_t crtov;
2462 
2463 #ifdef __BIG_ENDIAN_BITFIELD
2464 	uint32_t rsvd4:19;
2465 	uint32_t cscn:1;
2466 	uint32_t bbscn:4;
2467 	uint32_t rsvd3:8;
2468 #else	/*  __LITTLE_ENDIAN_BITFIELD */
2469 	uint32_t rsvd3:8;
2470 	uint32_t bbscn:4;
2471 	uint32_t cscn:1;
2472 	uint32_t rsvd4:19;
2473 #endif
2474 
2475 #ifdef __BIG_ENDIAN_BITFIELD
2476 	uint32_t rrq_enable:1;
2477 	uint32_t rrq_immed:1;
2478 	uint32_t rsvd5:29;
2479 	uint32_t ack0_enable:1;
2480 #else	/*  __LITTLE_ENDIAN_BITFIELD */
2481 	uint32_t ack0_enable:1;
2482 	uint32_t rsvd5:29;
2483 	uint32_t rrq_immed:1;
2484 	uint32_t rrq_enable:1;
2485 #endif
2486 } CONFIG_LINK;
2487 
2488 /* Structure for MB Command PART_SLIM (08)
2489  * will be removed since SLI1 is no longer supported!
2490  */
2491 typedef struct {
2492 #ifdef __BIG_ENDIAN_BITFIELD
2493 	uint16_t offCiocb;
2494 	uint16_t numCiocb;
2495 	uint16_t offRiocb;
2496 	uint16_t numRiocb;
2497 #else	/*  __LITTLE_ENDIAN_BITFIELD */
2498 	uint16_t numCiocb;
2499 	uint16_t offCiocb;
2500 	uint16_t numRiocb;
2501 	uint16_t offRiocb;
2502 #endif
2503 } RING_DEF;
2504 
2505 typedef struct {
2506 #ifdef __BIG_ENDIAN_BITFIELD
2507 	uint32_t unused1:24;
2508 	uint32_t numRing:8;
2509 #else	/*  __LITTLE_ENDIAN_BITFIELD */
2510 	uint32_t numRing:8;
2511 	uint32_t unused1:24;
2512 #endif
2513 
2514 	RING_DEF ringdef[4];
2515 	uint32_t hbainit;
2516 } PART_SLIM_VAR;
2517 
2518 /* Structure for MB Command CONFIG_RING (09) */
2519 
2520 typedef struct {
2521 #ifdef __BIG_ENDIAN_BITFIELD
2522 	uint32_t unused2:6;
2523 	uint32_t recvSeq:1;
2524 	uint32_t recvNotify:1;
2525 	uint32_t numMask:8;
2526 	uint32_t profile:8;
2527 	uint32_t unused1:4;
2528 	uint32_t ring:4;
2529 #else	/*  __LITTLE_ENDIAN_BITFIELD */
2530 	uint32_t ring:4;
2531 	uint32_t unused1:4;
2532 	uint32_t profile:8;
2533 	uint32_t numMask:8;
2534 	uint32_t recvNotify:1;
2535 	uint32_t recvSeq:1;
2536 	uint32_t unused2:6;
2537 #endif
2538 
2539 #ifdef __BIG_ENDIAN_BITFIELD
2540 	uint16_t maxRespXchg;
2541 	uint16_t maxOrigXchg;
2542 #else	/*  __LITTLE_ENDIAN_BITFIELD */
2543 	uint16_t maxOrigXchg;
2544 	uint16_t maxRespXchg;
2545 #endif
2546 
2547 	RR_REG rrRegs[6];
2548 } CONFIG_RING_VAR;
2549 
2550 /* Structure for MB Command RESET_RING (10) */
2551 
2552 typedef struct {
2553 	uint32_t ring_no;
2554 } RESET_RING_VAR;
2555 
2556 /* Structure for MB Command READ_CONFIG (11) */
2557 
2558 typedef struct {
2559 #ifdef __BIG_ENDIAN_BITFIELD
2560 	uint32_t cr:1;
2561 	uint32_t ci:1;
2562 	uint32_t cr_delay:6;
2563 	uint32_t cr_count:8;
2564 	uint32_t InitBBC:8;
2565 	uint32_t MaxBBC:8;
2566 #else	/*  __LITTLE_ENDIAN_BITFIELD */
2567 	uint32_t MaxBBC:8;
2568 	uint32_t InitBBC:8;
2569 	uint32_t cr_count:8;
2570 	uint32_t cr_delay:6;
2571 	uint32_t ci:1;
2572 	uint32_t cr:1;
2573 #endif
2574 
2575 #ifdef __BIG_ENDIAN_BITFIELD
2576 	uint32_t topology:8;
2577 	uint32_t myDid:24;
2578 #else	/*  __LITTLE_ENDIAN_BITFIELD */
2579 	uint32_t myDid:24;
2580 	uint32_t topology:8;
2581 #endif
2582 
2583 	/* Defines for topology (defined previously) */
2584 #ifdef __BIG_ENDIAN_BITFIELD
2585 	uint32_t AR:1;
2586 	uint32_t IR:1;
2587 	uint32_t rsvd1:29;
2588 	uint32_t ack0:1;
2589 #else	/*  __LITTLE_ENDIAN_BITFIELD */
2590 	uint32_t ack0:1;
2591 	uint32_t rsvd1:29;
2592 	uint32_t IR:1;
2593 	uint32_t AR:1;
2594 #endif
2595 
2596 	uint32_t edtov;
2597 	uint32_t arbtov;
2598 	uint32_t ratov;
2599 	uint32_t rttov;
2600 	uint32_t altov;
2601 	uint32_t lmt;
2602 #define LMT_RESERVED  0x000    /* Not used */
2603 #define LMT_1Gb       0x004
2604 #define LMT_2Gb       0x008
2605 #define LMT_4Gb       0x040
2606 #define LMT_8Gb       0x080
2607 #define LMT_10Gb      0x100
2608 #define LMT_16Gb      0x200
2609 #define LMT_32Gb      0x400
2610 #define LMT_64Gb      0x800
2611 #define LMT_128Gb     0x1000
2612 #define LMT_256Gb     0x2000
2613 	uint32_t rsvd2;
2614 	uint32_t rsvd3;
2615 	uint32_t max_xri;
2616 	uint32_t max_iocb;
2617 	uint32_t max_rpi;
2618 	uint32_t avail_xri;
2619 	uint32_t avail_iocb;
2620 	uint32_t avail_rpi;
2621 	uint32_t max_vpi;
2622 	uint32_t rsvd4;
2623 	uint32_t rsvd5;
2624 	uint32_t avail_vpi;
2625 } READ_CONFIG_VAR;
2626 
2627 /* Structure for MB Command READ_RCONFIG (12) */
2628 
2629 typedef struct {
2630 #ifdef __BIG_ENDIAN_BITFIELD
2631 	uint32_t rsvd2:7;
2632 	uint32_t recvNotify:1;
2633 	uint32_t numMask:8;
2634 	uint32_t profile:8;
2635 	uint32_t rsvd1:4;
2636 	uint32_t ring:4;
2637 #else	/*  __LITTLE_ENDIAN_BITFIELD */
2638 	uint32_t ring:4;
2639 	uint32_t rsvd1:4;
2640 	uint32_t profile:8;
2641 	uint32_t numMask:8;
2642 	uint32_t recvNotify:1;
2643 	uint32_t rsvd2:7;
2644 #endif
2645 
2646 #ifdef __BIG_ENDIAN_BITFIELD
2647 	uint16_t maxResp;
2648 	uint16_t maxOrig;
2649 #else	/*  __LITTLE_ENDIAN_BITFIELD */
2650 	uint16_t maxOrig;
2651 	uint16_t maxResp;
2652 #endif
2653 
2654 	RR_REG rrRegs[6];
2655 
2656 #ifdef __BIG_ENDIAN_BITFIELD
2657 	uint16_t cmdRingOffset;
2658 	uint16_t cmdEntryCnt;
2659 	uint16_t rspRingOffset;
2660 	uint16_t rspEntryCnt;
2661 	uint16_t nextCmdOffset;
2662 	uint16_t rsvd3;
2663 	uint16_t nextRspOffset;
2664 	uint16_t rsvd4;
2665 #else	/*  __LITTLE_ENDIAN_BITFIELD */
2666 	uint16_t cmdEntryCnt;
2667 	uint16_t cmdRingOffset;
2668 	uint16_t rspEntryCnt;
2669 	uint16_t rspRingOffset;
2670 	uint16_t rsvd3;
2671 	uint16_t nextCmdOffset;
2672 	uint16_t rsvd4;
2673 	uint16_t nextRspOffset;
2674 #endif
2675 } READ_RCONF_VAR;
2676 
2677 /* Structure for MB Command READ_SPARM (13) */
2678 /* Structure for MB Command READ_SPARM64 (0x8D) */
2679 
2680 typedef struct {
2681 	uint32_t rsvd1;
2682 	uint32_t rsvd2;
2683 	union {
2684 		struct ulp_bde sp; /* This BDE points to struct serv_parm
2685 				      structure */
2686 		struct ulp_bde64 sp64;
2687 	} un;
2688 #ifdef __BIG_ENDIAN_BITFIELD
2689 	uint16_t rsvd3;
2690 	uint16_t vpi;
2691 #else	/*  __LITTLE_ENDIAN_BITFIELD */
2692 	uint16_t vpi;
2693 	uint16_t rsvd3;
2694 #endif
2695 } READ_SPARM_VAR;
2696 
2697 /* Structure for MB Command READ_STATUS (14) */
2698 enum read_status_word1 {
2699 	RD_ST_CC	= 0x01,
2700 	RD_ST_XKB	= 0x80,
2701 };
2702 
2703 enum read_status_word17 {
2704 	RD_ST_XMIT_XKB_MASK = 0x3fffff,
2705 };
2706 
2707 enum read_status_word18 {
2708 	RD_ST_RCV_XKB_MASK = 0x3fffff,
2709 };
2710 
2711 typedef struct {
2712 	u8 clear_counters; /* rsvd 7:1, cc 0 */
2713 	u8 rsvd5;
2714 	u8 rsvd6;
2715 	u8 xkb; /* xkb 7, rsvd 6:0 */
2716 
2717 	u32 rsvd8;
2718 
2719 	uint32_t xmitByteCnt;
2720 	uint32_t rcvByteCnt;
2721 	uint32_t xmitFrameCnt;
2722 	uint32_t rcvFrameCnt;
2723 	uint32_t xmitSeqCnt;
2724 	uint32_t rcvSeqCnt;
2725 	uint32_t totalOrigExchanges;
2726 	uint32_t totalRespExchanges;
2727 	uint32_t rcvPbsyCnt;
2728 	uint32_t rcvFbsyCnt;
2729 
2730 	u32 drop_frame_no_rq;
2731 	u32 empty_rq;
2732 	u32 drop_frame_no_xri;
2733 	u32 empty_xri;
2734 
2735 	u32 xmit_xkb; /* rsvd 31:22, xmit_xkb 21:0 */
2736 	u32 rcv_xkb; /* rsvd 31:22, rcv_xkb 21:0 */
2737 } READ_STATUS_VAR;
2738 
2739 /* Structure for MB Command READ_RPI (15) */
2740 /* Structure for MB Command READ_RPI64 (0x8F) */
2741 
2742 typedef struct {
2743 #ifdef __BIG_ENDIAN_BITFIELD
2744 	uint16_t nextRpi;
2745 	uint16_t reqRpi;
2746 	uint32_t rsvd2:8;
2747 	uint32_t DID:24;
2748 #else	/*  __LITTLE_ENDIAN_BITFIELD */
2749 	uint16_t reqRpi;
2750 	uint16_t nextRpi;
2751 	uint32_t DID:24;
2752 	uint32_t rsvd2:8;
2753 #endif
2754 
2755 	union {
2756 		struct ulp_bde sp;
2757 		struct ulp_bde64 sp64;
2758 	} un;
2759 
2760 } READ_RPI_VAR;
2761 
2762 /* Structure for MB Command READ_XRI (16) */
2763 
2764 typedef struct {
2765 #ifdef __BIG_ENDIAN_BITFIELD
2766 	uint16_t nextXri;
2767 	uint16_t reqXri;
2768 	uint16_t rsvd1;
2769 	uint16_t rpi;
2770 	uint32_t rsvd2:8;
2771 	uint32_t DID:24;
2772 	uint32_t rsvd3:8;
2773 	uint32_t SID:24;
2774 	uint32_t rsvd4;
2775 	uint8_t seqId;
2776 	uint8_t rsvd5;
2777 	uint16_t seqCount;
2778 	uint16_t oxId;
2779 	uint16_t rxId;
2780 	uint32_t rsvd6:30;
2781 	uint32_t si:1;
2782 	uint32_t exchOrig:1;
2783 #else	/*  __LITTLE_ENDIAN_BITFIELD */
2784 	uint16_t reqXri;
2785 	uint16_t nextXri;
2786 	uint16_t rpi;
2787 	uint16_t rsvd1;
2788 	uint32_t DID:24;
2789 	uint32_t rsvd2:8;
2790 	uint32_t SID:24;
2791 	uint32_t rsvd3:8;
2792 	uint32_t rsvd4;
2793 	uint16_t seqCount;
2794 	uint8_t rsvd5;
2795 	uint8_t seqId;
2796 	uint16_t rxId;
2797 	uint16_t oxId;
2798 	uint32_t exchOrig:1;
2799 	uint32_t si:1;
2800 	uint32_t rsvd6:30;
2801 #endif
2802 } READ_XRI_VAR;
2803 
2804 /* Structure for MB Command READ_REV (17) */
2805 
2806 typedef struct {
2807 #ifdef __BIG_ENDIAN_BITFIELD
2808 	uint32_t cv:1;
2809 	uint32_t rr:1;
2810 	uint32_t rsvd2:2;
2811 	uint32_t v3req:1;
2812 	uint32_t v3rsp:1;
2813 	uint32_t rsvd1:25;
2814 	uint32_t rv:1;
2815 #else	/*  __LITTLE_ENDIAN_BITFIELD */
2816 	uint32_t rv:1;
2817 	uint32_t rsvd1:25;
2818 	uint32_t v3rsp:1;
2819 	uint32_t v3req:1;
2820 	uint32_t rsvd2:2;
2821 	uint32_t rr:1;
2822 	uint32_t cv:1;
2823 #endif
2824 
2825 	uint32_t biuRev;
2826 	uint32_t smRev;
2827 	union {
2828 		uint32_t smFwRev;
2829 		struct {
2830 #ifdef __BIG_ENDIAN_BITFIELD
2831 			uint8_t ProgType;
2832 			uint8_t ProgId;
2833 			uint16_t ProgVer:4;
2834 			uint16_t ProgRev:4;
2835 			uint16_t ProgFixLvl:2;
2836 			uint16_t ProgDistType:2;
2837 			uint16_t DistCnt:4;
2838 #else	/*  __LITTLE_ENDIAN_BITFIELD */
2839 			uint16_t DistCnt:4;
2840 			uint16_t ProgDistType:2;
2841 			uint16_t ProgFixLvl:2;
2842 			uint16_t ProgRev:4;
2843 			uint16_t ProgVer:4;
2844 			uint8_t ProgId;
2845 			uint8_t ProgType;
2846 #endif
2847 
2848 		} b;
2849 	} un;
2850 	uint32_t endecRev;
2851 #ifdef __BIG_ENDIAN_BITFIELD
2852 	uint8_t feaLevelHigh;
2853 	uint8_t feaLevelLow;
2854 	uint8_t fcphHigh;
2855 	uint8_t fcphLow;
2856 #else	/*  __LITTLE_ENDIAN_BITFIELD */
2857 	uint8_t fcphLow;
2858 	uint8_t fcphHigh;
2859 	uint8_t feaLevelLow;
2860 	uint8_t feaLevelHigh;
2861 #endif
2862 
2863 	uint32_t postKernRev;
2864 	uint32_t opFwRev;
2865 	uint8_t opFwName[16];
2866 	uint32_t sli1FwRev;
2867 	uint8_t sli1FwName[16];
2868 	uint32_t sli2FwRev;
2869 	uint8_t sli2FwName[16];
2870 	uint32_t sli3Feat;
2871 	uint32_t RandomData[6];
2872 } READ_REV_VAR;
2873 
2874 /* Structure for MB Command READ_LINK_STAT (18) */
2875 
2876 typedef struct {
2877 	uint32_t word0;
2878 
2879 #define lpfc_read_link_stat_rec_SHIFT   0
2880 #define lpfc_read_link_stat_rec_MASK   0x1
2881 #define lpfc_read_link_stat_rec_WORD   word0
2882 
2883 #define lpfc_read_link_stat_gec_SHIFT	1
2884 #define lpfc_read_link_stat_gec_MASK   0x1
2885 #define lpfc_read_link_stat_gec_WORD   word0
2886 
2887 #define lpfc_read_link_stat_w02oftow23of_SHIFT	2
2888 #define lpfc_read_link_stat_w02oftow23of_MASK   0x3FFFFF
2889 #define lpfc_read_link_stat_w02oftow23of_WORD   word0
2890 
2891 #define lpfc_read_link_stat_rsvd_SHIFT	24
2892 #define lpfc_read_link_stat_rsvd_MASK   0x1F
2893 #define lpfc_read_link_stat_rsvd_WORD   word0
2894 
2895 #define lpfc_read_link_stat_gec2_SHIFT  29
2896 #define lpfc_read_link_stat_gec2_MASK   0x1
2897 #define lpfc_read_link_stat_gec2_WORD   word0
2898 
2899 #define lpfc_read_link_stat_clrc_SHIFT  30
2900 #define lpfc_read_link_stat_clrc_MASK   0x1
2901 #define lpfc_read_link_stat_clrc_WORD   word0
2902 
2903 #define lpfc_read_link_stat_clof_SHIFT  31
2904 #define lpfc_read_link_stat_clof_MASK   0x1
2905 #define lpfc_read_link_stat_clof_WORD   word0
2906 
2907 	uint32_t linkFailureCnt;
2908 	uint32_t lossSyncCnt;
2909 	uint32_t lossSignalCnt;
2910 	uint32_t primSeqErrCnt;
2911 	uint32_t invalidXmitWord;
2912 	uint32_t crcCnt;
2913 	uint32_t primSeqTimeout;
2914 	uint32_t elasticOverrun;
2915 	uint32_t arbTimeout;
2916 	uint32_t advRecBufCredit;
2917 	uint32_t curRecBufCredit;
2918 	uint32_t advTransBufCredit;
2919 	uint32_t curTransBufCredit;
2920 	uint32_t recEofCount;
2921 	uint32_t recEofdtiCount;
2922 	uint32_t recEofniCount;
2923 	uint32_t recSofcount;
2924 	uint32_t rsvd1;
2925 	uint32_t rsvd2;
2926 	uint32_t recDrpXriCount;
2927 	uint32_t fecCorrBlkCount;
2928 	uint32_t fecUncorrBlkCount;
2929 } READ_LNK_VAR;
2930 
2931 /* Structure for MB Command REG_LOGIN (19) */
2932 /* Structure for MB Command REG_LOGIN64 (0x93) */
2933 
2934 typedef struct {
2935 #ifdef __BIG_ENDIAN_BITFIELD
2936 	uint16_t rsvd1;
2937 	uint16_t rpi;
2938 	uint32_t rsvd2:8;
2939 	uint32_t did:24;
2940 #else	/*  __LITTLE_ENDIAN_BITFIELD */
2941 	uint16_t rpi;
2942 	uint16_t rsvd1;
2943 	uint32_t did:24;
2944 	uint32_t rsvd2:8;
2945 #endif
2946 
2947 	union {
2948 		struct ulp_bde sp;
2949 		struct ulp_bde64 sp64;
2950 	} un;
2951 
2952 #ifdef __BIG_ENDIAN_BITFIELD
2953 	uint16_t rsvd6;
2954 	uint16_t vpi;
2955 #else /* __LITTLE_ENDIAN_BITFIELD */
2956 	uint16_t vpi;
2957 	uint16_t rsvd6;
2958 #endif
2959 
2960 } REG_LOGIN_VAR;
2961 
2962 /* Word 30 contents for REG_LOGIN */
2963 typedef union {
2964 	struct {
2965 #ifdef __BIG_ENDIAN_BITFIELD
2966 		uint16_t rsvd1:12;
2967 		uint16_t wd30_class:4;
2968 		uint16_t xri;
2969 #else	/*  __LITTLE_ENDIAN_BITFIELD */
2970 		uint16_t xri;
2971 		uint16_t wd30_class:4;
2972 		uint16_t rsvd1:12;
2973 #endif
2974 	} f;
2975 	uint32_t word;
2976 } REG_WD30;
2977 
2978 /* Structure for MB Command UNREG_LOGIN (20) */
2979 
2980 typedef struct {
2981 #ifdef __BIG_ENDIAN_BITFIELD
2982 	uint16_t rsvd1;
2983 	uint16_t rpi;
2984 	uint32_t rsvd2;
2985 	uint32_t rsvd3;
2986 	uint32_t rsvd4;
2987 	uint32_t rsvd5;
2988 	uint16_t rsvd6;
2989 	uint16_t vpi;
2990 #else	/*  __LITTLE_ENDIAN_BITFIELD */
2991 	uint16_t rpi;
2992 	uint16_t rsvd1;
2993 	uint32_t rsvd2;
2994 	uint32_t rsvd3;
2995 	uint32_t rsvd4;
2996 	uint32_t rsvd5;
2997 	uint16_t vpi;
2998 	uint16_t rsvd6;
2999 #endif
3000 } UNREG_LOGIN_VAR;
3001 
3002 /* Structure for MB Command REG_VPI (0x96) */
3003 typedef struct {
3004 #ifdef __BIG_ENDIAN_BITFIELD
3005 	uint32_t rsvd1;
3006 	uint32_t rsvd2:7;
3007 	uint32_t upd:1;
3008 	uint32_t sid:24;
3009 	uint32_t wwn[2];
3010 	uint32_t rsvd5;
3011 	uint16_t vfi;
3012 	uint16_t vpi;
3013 #else	/*  __LITTLE_ENDIAN */
3014 	uint32_t rsvd1;
3015 	uint32_t sid:24;
3016 	uint32_t upd:1;
3017 	uint32_t rsvd2:7;
3018 	uint32_t wwn[2];
3019 	uint32_t rsvd5;
3020 	uint16_t vpi;
3021 	uint16_t vfi;
3022 #endif
3023 } REG_VPI_VAR;
3024 
3025 /* Structure for MB Command UNREG_VPI (0x97) */
3026 typedef struct {
3027 	uint32_t rsvd1;
3028 #ifdef __BIG_ENDIAN_BITFIELD
3029 	uint16_t rsvd2;
3030 	uint16_t sli4_vpi;
3031 #else	/*  __LITTLE_ENDIAN */
3032 	uint16_t sli4_vpi;
3033 	uint16_t rsvd2;
3034 #endif
3035 	uint32_t rsvd3;
3036 	uint32_t rsvd4;
3037 	uint32_t rsvd5;
3038 #ifdef __BIG_ENDIAN_BITFIELD
3039 	uint16_t rsvd6;
3040 	uint16_t vpi;
3041 #else	/*  __LITTLE_ENDIAN */
3042 	uint16_t vpi;
3043 	uint16_t rsvd6;
3044 #endif
3045 } UNREG_VPI_VAR;
3046 
3047 /* Structure for MB Command UNREG_D_ID (0x23) */
3048 
3049 typedef struct {
3050 	uint32_t did;
3051 	uint32_t rsvd2;
3052 	uint32_t rsvd3;
3053 	uint32_t rsvd4;
3054 	uint32_t rsvd5;
3055 #ifdef __BIG_ENDIAN_BITFIELD
3056 	uint16_t rsvd6;
3057 	uint16_t vpi;
3058 #else
3059 	uint16_t vpi;
3060 	uint16_t rsvd6;
3061 #endif
3062 } UNREG_D_ID_VAR;
3063 
3064 /* Structure for MB Command READ_TOPOLOGY (0x95) */
3065 struct lpfc_mbx_read_top {
3066 	uint32_t eventTag;	/* Event tag */
3067 	uint32_t word2;
3068 #define lpfc_mbx_read_top_fa_SHIFT		12
3069 #define lpfc_mbx_read_top_fa_MASK		0x00000001
3070 #define lpfc_mbx_read_top_fa_WORD		word2
3071 #define lpfc_mbx_read_top_mm_SHIFT		11
3072 #define lpfc_mbx_read_top_mm_MASK		0x00000001
3073 #define lpfc_mbx_read_top_mm_WORD		word2
3074 #define lpfc_mbx_read_top_pb_SHIFT		9
3075 #define lpfc_mbx_read_top_pb_MASK		0X00000001
3076 #define lpfc_mbx_read_top_pb_WORD		word2
3077 #define lpfc_mbx_read_top_il_SHIFT		8
3078 #define lpfc_mbx_read_top_il_MASK		0x00000001
3079 #define lpfc_mbx_read_top_il_WORD		word2
3080 #define lpfc_mbx_read_top_att_type_SHIFT	0
3081 #define lpfc_mbx_read_top_att_type_MASK		0x000000FF
3082 #define lpfc_mbx_read_top_att_type_WORD		word2
3083 #define LPFC_ATT_RESERVED    0x00	/* Reserved - attType */
3084 #define LPFC_ATT_LINK_UP     0x01	/* Link is up */
3085 #define LPFC_ATT_LINK_DOWN   0x02	/* Link is down */
3086 #define LPFC_ATT_UNEXP_WWPN  0x06	/* Link is down Unexpected WWWPN */
3087 	uint32_t word3;
3088 #define lpfc_mbx_read_top_alpa_granted_SHIFT	24
3089 #define lpfc_mbx_read_top_alpa_granted_MASK	0x000000FF
3090 #define lpfc_mbx_read_top_alpa_granted_WORD	word3
3091 #define lpfc_mbx_read_top_lip_alps_SHIFT	16
3092 #define lpfc_mbx_read_top_lip_alps_MASK		0x000000FF
3093 #define lpfc_mbx_read_top_lip_alps_WORD		word3
3094 #define lpfc_mbx_read_top_lip_type_SHIFT	8
3095 #define lpfc_mbx_read_top_lip_type_MASK		0x000000FF
3096 #define lpfc_mbx_read_top_lip_type_WORD		word3
3097 #define lpfc_mbx_read_top_topology_SHIFT	0
3098 #define lpfc_mbx_read_top_topology_MASK		0x000000FF
3099 #define lpfc_mbx_read_top_topology_WORD		word3
3100 #define LPFC_TOPOLOGY_PT_PT 0x01	/* Topology is pt-pt / pt-fabric */
3101 #define LPFC_TOPOLOGY_LOOP  0x02	/* Topology is FC-AL */
3102 	/* store the LILP AL_PA position map into */
3103 	struct ulp_bde64 lilpBde64;
3104 #define LPFC_ALPA_MAP_SIZE	128
3105 	uint32_t word7;
3106 #define lpfc_mbx_read_top_ld_lu_SHIFT		31
3107 #define lpfc_mbx_read_top_ld_lu_MASK		0x00000001
3108 #define lpfc_mbx_read_top_ld_lu_WORD		word7
3109 #define lpfc_mbx_read_top_ld_tf_SHIFT		30
3110 #define lpfc_mbx_read_top_ld_tf_MASK		0x00000001
3111 #define lpfc_mbx_read_top_ld_tf_WORD		word7
3112 #define lpfc_mbx_read_top_ld_link_spd_SHIFT	8
3113 #define lpfc_mbx_read_top_ld_link_spd_MASK	0x000000FF
3114 #define lpfc_mbx_read_top_ld_link_spd_WORD	word7
3115 #define lpfc_mbx_read_top_ld_nl_port_SHIFT	4
3116 #define lpfc_mbx_read_top_ld_nl_port_MASK	0x0000000F
3117 #define lpfc_mbx_read_top_ld_nl_port_WORD	word7
3118 #define lpfc_mbx_read_top_ld_tx_SHIFT		2
3119 #define lpfc_mbx_read_top_ld_tx_MASK		0x00000003
3120 #define lpfc_mbx_read_top_ld_tx_WORD		word7
3121 #define lpfc_mbx_read_top_ld_rx_SHIFT		0
3122 #define lpfc_mbx_read_top_ld_rx_MASK		0x00000003
3123 #define lpfc_mbx_read_top_ld_rx_WORD		word7
3124 	uint32_t word8;
3125 #define lpfc_mbx_read_top_lu_SHIFT		31
3126 #define lpfc_mbx_read_top_lu_MASK		0x00000001
3127 #define lpfc_mbx_read_top_lu_WORD		word8
3128 #define lpfc_mbx_read_top_tf_SHIFT		30
3129 #define lpfc_mbx_read_top_tf_MASK		0x00000001
3130 #define lpfc_mbx_read_top_tf_WORD		word8
3131 #define lpfc_mbx_read_top_link_spd_SHIFT	8
3132 #define lpfc_mbx_read_top_link_spd_MASK		0x000000FF
3133 #define lpfc_mbx_read_top_link_spd_WORD		word8
3134 #define lpfc_mbx_read_top_nl_port_SHIFT		4
3135 #define lpfc_mbx_read_top_nl_port_MASK		0x0000000F
3136 #define lpfc_mbx_read_top_nl_port_WORD		word8
3137 #define lpfc_mbx_read_top_tx_SHIFT		2
3138 #define lpfc_mbx_read_top_tx_MASK		0x00000003
3139 #define lpfc_mbx_read_top_tx_WORD		word8
3140 #define lpfc_mbx_read_top_rx_SHIFT		0
3141 #define lpfc_mbx_read_top_rx_MASK		0x00000003
3142 #define lpfc_mbx_read_top_rx_WORD		word8
3143 #define LPFC_LINK_SPEED_UNKNOWN	0x0
3144 #define LPFC_LINK_SPEED_1GHZ	0x04
3145 #define LPFC_LINK_SPEED_2GHZ	0x08
3146 #define LPFC_LINK_SPEED_4GHZ	0x10
3147 #define LPFC_LINK_SPEED_8GHZ	0x20
3148 #define LPFC_LINK_SPEED_10GHZ	0x40
3149 #define LPFC_LINK_SPEED_16GHZ	0x80
3150 #define LPFC_LINK_SPEED_32GHZ	0x90
3151 #define LPFC_LINK_SPEED_64GHZ	0xA0
3152 #define LPFC_LINK_SPEED_128GHZ	0xB0
3153 #define LPFC_LINK_SPEED_256GHZ	0xC0
3154 };
3155 
3156 /* Structure for MB Command CLEAR_LA (22) */
3157 
3158 typedef struct {
3159 	uint32_t eventTag;	/* Event tag */
3160 	uint32_t rsvd1;
3161 } CLEAR_LA_VAR;
3162 
3163 /* Structure for MB Command DUMP */
3164 
3165 typedef struct {
3166 #ifdef __BIG_ENDIAN_BITFIELD
3167 	uint32_t rsvd:25;
3168 	uint32_t ra:1;
3169 	uint32_t co:1;
3170 	uint32_t cv:1;
3171 	uint32_t type:4;
3172 	uint32_t entry_index:16;
3173 	uint32_t region_id:16;
3174 #else	/*  __LITTLE_ENDIAN_BITFIELD */
3175 	uint32_t type:4;
3176 	uint32_t cv:1;
3177 	uint32_t co:1;
3178 	uint32_t ra:1;
3179 	uint32_t rsvd:25;
3180 	uint32_t region_id:16;
3181 	uint32_t entry_index:16;
3182 #endif
3183 
3184 	uint32_t sli4_length;
3185 	uint32_t word_cnt;
3186 	uint32_t resp_offset;
3187 } DUMP_VAR;
3188 
3189 #define  DMP_MEM_REG             0x1
3190 #define  DMP_NV_PARAMS           0x2
3191 #define  DMP_LMSD                0x3 /* Link Module Serial Data */
3192 #define  DMP_WELL_KNOWN          0x4
3193 
3194 #define  DMP_REGION_VPD          0xe
3195 #define  DMP_VPD_SIZE            0x400  /* maximum amount of VPD */
3196 #define  DMP_RSP_OFFSET          0x14   /* word 5 contains first word of rsp */
3197 #define  DMP_RSP_SIZE            0x6C   /* maximum of 27 words of rsp data */
3198 
3199 #define  DMP_REGION_VPORT	 0x16   /* VPort info region */
3200 #define  DMP_VPORT_REGION_SIZE	 0x200
3201 #define  DMP_MBOX_OFFSET_WORD	 0x5
3202 
3203 #define  DMP_REGION_23		 0x17   /* fcoe param  and port state region */
3204 #define  DMP_RGN23_SIZE		 0x400
3205 
3206 #define  WAKE_UP_PARMS_REGION_ID    4
3207 #define  WAKE_UP_PARMS_WORD_SIZE   15
3208 
3209 struct vport_rec {
3210 	uint8_t wwpn[8];
3211 	uint8_t wwnn[8];
3212 };
3213 
3214 #define VPORT_INFO_SIG 0x32324752
3215 #define VPORT_INFO_REV_MASK 0xff
3216 #define VPORT_INFO_REV 0x1
3217 #define MAX_STATIC_VPORT_COUNT 16
3218 struct static_vport_info {
3219 	uint32_t		signature;
3220 	uint32_t		rev;
3221 	struct vport_rec	vport_list[MAX_STATIC_VPORT_COUNT];
3222 	uint32_t		resvd[66];
3223 };
3224 
3225 /* Option rom version structure */
3226 struct prog_id {
3227 #ifdef __BIG_ENDIAN_BITFIELD
3228 	uint8_t  type;
3229 	uint8_t  id;
3230 	uint32_t ver:4;  /* Major Version */
3231 	uint32_t rev:4;  /* Revision */
3232 	uint32_t lev:2;  /* Level */
3233 	uint32_t dist:2; /* Dist Type */
3234 	uint32_t num:4;  /* number after dist type */
3235 #else /*  __LITTLE_ENDIAN_BITFIELD */
3236 	uint32_t num:4;  /* number after dist type */
3237 	uint32_t dist:2; /* Dist Type */
3238 	uint32_t lev:2;  /* Level */
3239 	uint32_t rev:4;  /* Revision */
3240 	uint32_t ver:4;  /* Major Version */
3241 	uint8_t  id;
3242 	uint8_t  type;
3243 #endif
3244 };
3245 
3246 /* Structure for MB Command UPDATE_CFG (0x1B) */
3247 
3248 struct update_cfg_var {
3249 #ifdef __BIG_ENDIAN_BITFIELD
3250 	uint32_t rsvd2:16;
3251 	uint32_t type:8;
3252 	uint32_t rsvd:1;
3253 	uint32_t ra:1;
3254 	uint32_t co:1;
3255 	uint32_t cv:1;
3256 	uint32_t req:4;
3257 	uint32_t entry_length:16;
3258 	uint32_t region_id:16;
3259 #else  /*  __LITTLE_ENDIAN_BITFIELD */
3260 	uint32_t req:4;
3261 	uint32_t cv:1;
3262 	uint32_t co:1;
3263 	uint32_t ra:1;
3264 	uint32_t rsvd:1;
3265 	uint32_t type:8;
3266 	uint32_t rsvd2:16;
3267 	uint32_t region_id:16;
3268 	uint32_t entry_length:16;
3269 #endif
3270 
3271 	uint32_t resp_info;
3272 	uint32_t byte_cnt;
3273 	uint32_t data_offset;
3274 };
3275 
3276 struct hbq_mask {
3277 #ifdef __BIG_ENDIAN_BITFIELD
3278 	uint8_t tmatch;
3279 	uint8_t tmask;
3280 	uint8_t rctlmatch;
3281 	uint8_t rctlmask;
3282 #else	/*  __LITTLE_ENDIAN */
3283 	uint8_t rctlmask;
3284 	uint8_t rctlmatch;
3285 	uint8_t tmask;
3286 	uint8_t tmatch;
3287 #endif
3288 };
3289 
3290 
3291 /* Structure for MB Command CONFIG_HBQ (7c) */
3292 
3293 struct config_hbq_var {
3294 #ifdef __BIG_ENDIAN_BITFIELD
3295 	uint32_t rsvd1      :7;
3296 	uint32_t recvNotify :1;     /* Receive Notification */
3297 	uint32_t numMask    :8;     /* # Mask Entries       */
3298 	uint32_t profile    :8;     /* Selection Profile    */
3299 	uint32_t rsvd2      :8;
3300 #else	/*  __LITTLE_ENDIAN */
3301 	uint32_t rsvd2      :8;
3302 	uint32_t profile    :8;     /* Selection Profile    */
3303 	uint32_t numMask    :8;     /* # Mask Entries       */
3304 	uint32_t recvNotify :1;     /* Receive Notification */
3305 	uint32_t rsvd1      :7;
3306 #endif
3307 
3308 #ifdef __BIG_ENDIAN_BITFIELD
3309 	uint32_t hbqId      :16;
3310 	uint32_t rsvd3      :12;
3311 	uint32_t ringMask   :4;
3312 #else	/*  __LITTLE_ENDIAN */
3313 	uint32_t ringMask   :4;
3314 	uint32_t rsvd3      :12;
3315 	uint32_t hbqId      :16;
3316 #endif
3317 
3318 #ifdef __BIG_ENDIAN_BITFIELD
3319 	uint32_t entry_count :16;
3320 	uint32_t rsvd4        :8;
3321 	uint32_t headerLen    :8;
3322 #else	/*  __LITTLE_ENDIAN */
3323 	uint32_t headerLen    :8;
3324 	uint32_t rsvd4        :8;
3325 	uint32_t entry_count :16;
3326 #endif
3327 
3328 	uint32_t hbqaddrLow;
3329 	uint32_t hbqaddrHigh;
3330 
3331 #ifdef __BIG_ENDIAN_BITFIELD
3332 	uint32_t rsvd5      :31;
3333 	uint32_t logEntry   :1;
3334 #else	/*  __LITTLE_ENDIAN */
3335 	uint32_t logEntry   :1;
3336 	uint32_t rsvd5      :31;
3337 #endif
3338 
3339 	uint32_t rsvd6;    /* w7 */
3340 	uint32_t rsvd7;    /* w8 */
3341 	uint32_t rsvd8;    /* w9 */
3342 
3343 	struct hbq_mask hbqMasks[6];
3344 
3345 
3346 	union {
3347 		uint32_t allprofiles[12];
3348 
3349 		struct {
3350 			#ifdef __BIG_ENDIAN_BITFIELD
3351 				uint32_t	seqlenoff	:16;
3352 				uint32_t	maxlen		:16;
3353 			#else	/*  __LITTLE_ENDIAN */
3354 				uint32_t	maxlen		:16;
3355 				uint32_t	seqlenoff	:16;
3356 			#endif
3357 			#ifdef __BIG_ENDIAN_BITFIELD
3358 				uint32_t	rsvd1		:28;
3359 				uint32_t	seqlenbcnt	:4;
3360 			#else	/*  __LITTLE_ENDIAN */
3361 				uint32_t	seqlenbcnt	:4;
3362 				uint32_t	rsvd1		:28;
3363 			#endif
3364 			uint32_t rsvd[10];
3365 		} profile2;
3366 
3367 		struct {
3368 			#ifdef __BIG_ENDIAN_BITFIELD
3369 				uint32_t	seqlenoff	:16;
3370 				uint32_t	maxlen		:16;
3371 			#else	/*  __LITTLE_ENDIAN */
3372 				uint32_t	maxlen		:16;
3373 				uint32_t	seqlenoff	:16;
3374 			#endif
3375 			#ifdef __BIG_ENDIAN_BITFIELD
3376 				uint32_t	cmdcodeoff	:28;
3377 				uint32_t	rsvd1		:12;
3378 				uint32_t	seqlenbcnt	:4;
3379 			#else	/*  __LITTLE_ENDIAN */
3380 				uint32_t	seqlenbcnt	:4;
3381 				uint32_t	rsvd1		:12;
3382 				uint32_t	cmdcodeoff	:28;
3383 			#endif
3384 			uint32_t cmdmatch[8];
3385 
3386 			uint32_t rsvd[2];
3387 		} profile3;
3388 
3389 		struct {
3390 			#ifdef __BIG_ENDIAN_BITFIELD
3391 				uint32_t	seqlenoff	:16;
3392 				uint32_t	maxlen		:16;
3393 			#else	/*  __LITTLE_ENDIAN */
3394 				uint32_t	maxlen		:16;
3395 				uint32_t	seqlenoff	:16;
3396 			#endif
3397 			#ifdef __BIG_ENDIAN_BITFIELD
3398 				uint32_t	cmdcodeoff	:28;
3399 				uint32_t	rsvd1		:12;
3400 				uint32_t	seqlenbcnt	:4;
3401 			#else	/*  __LITTLE_ENDIAN */
3402 				uint32_t	seqlenbcnt	:4;
3403 				uint32_t	rsvd1		:12;
3404 				uint32_t	cmdcodeoff	:28;
3405 			#endif
3406 			uint32_t cmdmatch[8];
3407 
3408 			uint32_t rsvd[2];
3409 		} profile5;
3410 
3411 	} profiles;
3412 
3413 };
3414 
3415 
3416 
3417 /* Structure for MB Command CONFIG_PORT (0x88) */
3418 typedef struct {
3419 #ifdef __BIG_ENDIAN_BITFIELD
3420 	uint32_t cBE       :  1;
3421 	uint32_t cET       :  1;
3422 	uint32_t cHpcb     :  1;
3423 	uint32_t cMA       :  1;
3424 	uint32_t sli_mode  :  4;
3425 	uint32_t pcbLen    : 24;       /* bit 23:0  of memory based port
3426 					* config block */
3427 #else	/*  __LITTLE_ENDIAN */
3428 	uint32_t pcbLen    : 24;       /* bit 23:0  of memory based port
3429 					* config block */
3430 	uint32_t sli_mode  :  4;
3431 	uint32_t cMA       :  1;
3432 	uint32_t cHpcb     :  1;
3433 	uint32_t cET       :  1;
3434 	uint32_t cBE       :  1;
3435 #endif
3436 
3437 	uint32_t pcbLow;       /* bit 31:0  of memory based port config block */
3438 	uint32_t pcbHigh;      /* bit 63:32 of memory based port config block */
3439 	uint32_t hbainit[5];
3440 #ifdef __BIG_ENDIAN_BITFIELD
3441 	uint32_t hps	   :  1; /* bit 31 word9 Host Pointer in slim */
3442 	uint32_t rsvd	   : 31; /* least significant 31 bits of word 9 */
3443 #else   /*  __LITTLE_ENDIAN */
3444 	uint32_t rsvd      : 31; /* least significant 31 bits of word 9 */
3445 	uint32_t hps	   :  1; /* bit 31 word9 Host Pointer in slim */
3446 #endif
3447 
3448 #ifdef __BIG_ENDIAN_BITFIELD
3449 	uint32_t rsvd1     : 20;  /* Reserved                             */
3450 	uint32_t casabt    :  1;  /* Configure async abts status notice   */
3451 	uint32_t rsvd2     :  2;  /* Reserved                             */
3452 	uint32_t cbg       :  1;  /* Configure BlockGuard                 */
3453 	uint32_t cmv       :  1;  /* Configure Max VPIs                   */
3454 	uint32_t ccrp      :  1;  /* Config Command Ring Polling          */
3455 	uint32_t csah      :  1;  /* Configure Synchronous Abort Handling */
3456 	uint32_t chbs      :  1;  /* Cofigure Host Backing store          */
3457 	uint32_t cinb      :  1;  /* Enable Interrupt Notification Block  */
3458 	uint32_t cerbm	   :  1;  /* Configure Enhanced Receive Buf Mgmt  */
3459 	uint32_t cmx	   :  1;  /* Configure Max XRIs                   */
3460 	uint32_t cmr	   :  1;  /* Configure Max RPIs                   */
3461 #else	/*  __LITTLE_ENDIAN */
3462 	uint32_t cmr	   :  1;  /* Configure Max RPIs                   */
3463 	uint32_t cmx	   :  1;  /* Configure Max XRIs                   */
3464 	uint32_t cerbm	   :  1;  /* Configure Enhanced Receive Buf Mgmt  */
3465 	uint32_t cinb      :  1;  /* Enable Interrupt Notification Block  */
3466 	uint32_t chbs      :  1;  /* Cofigure Host Backing store          */
3467 	uint32_t csah      :  1;  /* Configure Synchronous Abort Handling */
3468 	uint32_t ccrp      :  1;  /* Config Command Ring Polling          */
3469 	uint32_t cmv	   :  1;  /* Configure Max VPIs                   */
3470 	uint32_t cbg       :  1;  /* Configure BlockGuard                 */
3471 	uint32_t rsvd2     :  2;  /* Reserved                             */
3472 	uint32_t casabt    :  1;  /* Configure async abts status notice   */
3473 	uint32_t rsvd1     : 20;  /* Reserved                             */
3474 #endif
3475 #ifdef __BIG_ENDIAN_BITFIELD
3476 	uint32_t rsvd3     : 20;  /* Reserved                             */
3477 	uint32_t gasabt    :  1;  /* Grant async abts status notice       */
3478 	uint32_t rsvd4     :  2;  /* Reserved                             */
3479 	uint32_t gbg       :  1;  /* Grant BlockGuard                     */
3480 	uint32_t gmv	   :  1;  /* Grant Max VPIs                       */
3481 	uint32_t gcrp	   :  1;  /* Grant Command Ring Polling           */
3482 	uint32_t gsah	   :  1;  /* Grant Synchronous Abort Handling     */
3483 	uint32_t ghbs	   :  1;  /* Grant Host Backing Store             */
3484 	uint32_t ginb	   :  1;  /* Grant Interrupt Notification Block   */
3485 	uint32_t gerbm	   :  1;  /* Grant ERBM Request                   */
3486 	uint32_t gmx	   :  1;  /* Grant Max XRIs                       */
3487 	uint32_t gmr	   :  1;  /* Grant Max RPIs                       */
3488 #else	/*  __LITTLE_ENDIAN */
3489 	uint32_t gmr	   :  1;  /* Grant Max RPIs                       */
3490 	uint32_t gmx	   :  1;  /* Grant Max XRIs                       */
3491 	uint32_t gerbm	   :  1;  /* Grant ERBM Request                   */
3492 	uint32_t ginb	   :  1;  /* Grant Interrupt Notification Block   */
3493 	uint32_t ghbs	   :  1;  /* Grant Host Backing Store             */
3494 	uint32_t gsah	   :  1;  /* Grant Synchronous Abort Handling     */
3495 	uint32_t gcrp	   :  1;  /* Grant Command Ring Polling           */
3496 	uint32_t gmv	   :  1;  /* Grant Max VPIs                       */
3497 	uint32_t gbg       :  1;  /* Grant BlockGuard                     */
3498 	uint32_t rsvd4     :  2;  /* Reserved                             */
3499 	uint32_t gasabt    :  1;  /* Grant async abts status notice       */
3500 	uint32_t rsvd3     : 20;  /* Reserved                             */
3501 #endif
3502 
3503 #ifdef __BIG_ENDIAN_BITFIELD
3504 	uint32_t max_rpi   : 16;  /* Max RPIs Port should configure       */
3505 	uint32_t max_xri   : 16;  /* Max XRIs Port should configure       */
3506 #else	/*  __LITTLE_ENDIAN */
3507 	uint32_t max_xri   : 16;  /* Max XRIs Port should configure       */
3508 	uint32_t max_rpi   : 16;  /* Max RPIs Port should configure       */
3509 #endif
3510 
3511 #ifdef __BIG_ENDIAN_BITFIELD
3512 	uint32_t max_hbq   : 16;  /* Max HBQs Host expect to configure    */
3513 	uint32_t rsvd5     : 16;  /* Max HBQs Host expect to configure    */
3514 #else	/*  __LITTLE_ENDIAN */
3515 	uint32_t rsvd5     : 16;  /* Max HBQs Host expect to configure    */
3516 	uint32_t max_hbq   : 16;  /* Max HBQs Host expect to configure    */
3517 #endif
3518 
3519 	uint32_t rsvd6;           /* Reserved                             */
3520 
3521 #ifdef __BIG_ENDIAN_BITFIELD
3522 	uint32_t rsvd7      : 16;
3523 	uint32_t max_vpi    : 16;  /* Max number of virt N-Ports           */
3524 #else	/*  __LITTLE_ENDIAN */
3525 	uint32_t max_vpi    : 16;  /* Max number of virt N-Ports           */
3526 	uint32_t rsvd7      : 16;
3527 #endif
3528 
3529 } CONFIG_PORT_VAR;
3530 
3531 /* Structure for MB Command CONFIG_MSI (0x30) */
3532 struct config_msi_var {
3533 #ifdef __BIG_ENDIAN_BITFIELD
3534 	uint32_t dfltMsgNum:8;	/* Default message number            */
3535 	uint32_t rsvd1:11;	/* Reserved                          */
3536 	uint32_t NID:5;		/* Number of secondary attention IDs */
3537 	uint32_t rsvd2:5;	/* Reserved                          */
3538 	uint32_t dfltPresent:1;	/* Default message number present    */
3539 	uint32_t addFlag:1;	/* Add association flag              */
3540 	uint32_t reportFlag:1;	/* Report association flag           */
3541 #else	/*  __LITTLE_ENDIAN_BITFIELD */
3542 	uint32_t reportFlag:1;	/* Report association flag           */
3543 	uint32_t addFlag:1;	/* Add association flag              */
3544 	uint32_t dfltPresent:1;	/* Default message number present    */
3545 	uint32_t rsvd2:5;	/* Reserved                          */
3546 	uint32_t NID:5;		/* Number of secondary attention IDs */
3547 	uint32_t rsvd1:11;	/* Reserved                          */
3548 	uint32_t dfltMsgNum:8;	/* Default message number            */
3549 #endif
3550 	uint32_t attentionConditions[2];
3551 	uint8_t  attentionId[16];
3552 	uint8_t  messageNumberByHA[64];
3553 	uint8_t  messageNumberByID[16];
3554 	uint32_t autoClearHA[2];
3555 #ifdef __BIG_ENDIAN_BITFIELD
3556 	uint32_t rsvd3:16;
3557 	uint32_t autoClearID:16;
3558 #else	/*  __LITTLE_ENDIAN_BITFIELD */
3559 	uint32_t autoClearID:16;
3560 	uint32_t rsvd3:16;
3561 #endif
3562 	uint32_t rsvd4;
3563 };
3564 
3565 /* SLI-2 Port Control Block */
3566 
3567 /* SLIM POINTER */
3568 #define SLIMOFF 0x30		/* WORD */
3569 
3570 typedef struct _SLI2_RDSC {
3571 	uint32_t cmdEntries;
3572 	uint32_t cmdAddrLow;
3573 	uint32_t cmdAddrHigh;
3574 
3575 	uint32_t rspEntries;
3576 	uint32_t rspAddrLow;
3577 	uint32_t rspAddrHigh;
3578 } SLI2_RDSC;
3579 
3580 typedef struct _PCB {
3581 #ifdef __BIG_ENDIAN_BITFIELD
3582 	uint32_t type:8;
3583 #define TYPE_NATIVE_SLI2       0x01
3584 	uint32_t feature:8;
3585 #define FEATURE_INITIAL_SLI2   0x01
3586 	uint32_t rsvd:12;
3587 	uint32_t maxRing:4;
3588 #else	/*  __LITTLE_ENDIAN_BITFIELD */
3589 	uint32_t maxRing:4;
3590 	uint32_t rsvd:12;
3591 	uint32_t feature:8;
3592 #define FEATURE_INITIAL_SLI2   0x01
3593 	uint32_t type:8;
3594 #define TYPE_NATIVE_SLI2       0x01
3595 #endif
3596 
3597 	uint32_t mailBoxSize;
3598 	uint32_t mbAddrLow;
3599 	uint32_t mbAddrHigh;
3600 
3601 	uint32_t hgpAddrLow;
3602 	uint32_t hgpAddrHigh;
3603 
3604 	uint32_t pgpAddrLow;
3605 	uint32_t pgpAddrHigh;
3606 	SLI2_RDSC rdsc[MAX_SLI3_RINGS];
3607 } PCB_t;
3608 
3609 /* NEW_FEATURE */
3610 typedef struct {
3611 #ifdef __BIG_ENDIAN_BITFIELD
3612 	uint32_t rsvd0:27;
3613 	uint32_t discardFarp:1;
3614 	uint32_t IPEnable:1;
3615 	uint32_t nodeName:1;
3616 	uint32_t portName:1;
3617 	uint32_t filterEnable:1;
3618 #else	/*  __LITTLE_ENDIAN_BITFIELD */
3619 	uint32_t filterEnable:1;
3620 	uint32_t portName:1;
3621 	uint32_t nodeName:1;
3622 	uint32_t IPEnable:1;
3623 	uint32_t discardFarp:1;
3624 	uint32_t rsvd:27;
3625 #endif
3626 
3627 	uint8_t portname[8];	/* Used to be struct lpfc_name */
3628 	uint8_t nodename[8];
3629 	uint32_t rsvd1;
3630 	uint32_t rsvd2;
3631 	uint32_t rsvd3;
3632 	uint32_t IPAddress;
3633 } CONFIG_FARP_VAR;
3634 
3635 /* Structure for MB Command MBX_ASYNCEVT_ENABLE (0x33) */
3636 
3637 typedef struct {
3638 #ifdef __BIG_ENDIAN_BITFIELD
3639 	uint32_t rsvd:30;
3640 	uint32_t ring:2;	/* Ring for ASYNC_EVENT iocb Bits 0-1*/
3641 #else /*  __LITTLE_ENDIAN */
3642 	uint32_t ring:2;	/* Ring for ASYNC_EVENT iocb Bits 0-1*/
3643 	uint32_t rsvd:30;
3644 #endif
3645 } ASYNCEVT_ENABLE_VAR;
3646 
3647 /* Union of all Mailbox Command types */
3648 #define MAILBOX_CMD_WSIZE	32
3649 #define MAILBOX_CMD_SIZE	(MAILBOX_CMD_WSIZE * sizeof(uint32_t))
3650 /* ext_wsize times 4 bytes should not be greater than max xmit size */
3651 #define MAILBOX_EXT_WSIZE	512
3652 #define MAILBOX_EXT_SIZE	(MAILBOX_EXT_WSIZE * sizeof(uint32_t))
3653 #define MAILBOX_HBA_EXT_OFFSET  0x100
3654 /* max mbox xmit size is a page size for sysfs IO operations */
3655 #define MAILBOX_SYSFS_MAX	4096
3656 
3657 typedef union {
3658 	uint32_t varWords[MAILBOX_CMD_WSIZE - 1]; /* first word is type/
3659 						    * feature/max ring number
3660 						    */
3661 	LOAD_SM_VAR varLdSM;		/* cmd =  1 (LOAD_SM)        */
3662 	READ_NV_VAR varRDnvp;		/* cmd =  2 (READ_NVPARMS)   */
3663 	WRITE_NV_VAR varWTnvp;		/* cmd =  3 (WRITE_NVPARMS)  */
3664 	BIU_DIAG_VAR varBIUdiag;	/* cmd =  4 (RUN_BIU_DIAG)   */
3665 	INIT_LINK_VAR varInitLnk;	/* cmd =  5 (INIT_LINK)      */
3666 	DOWN_LINK_VAR varDwnLnk;	/* cmd =  6 (DOWN_LINK)      */
3667 	CONFIG_LINK varCfgLnk;		/* cmd =  7 (CONFIG_LINK)    */
3668 	PART_SLIM_VAR varSlim;		/* cmd =  8 (PART_SLIM)      */
3669 	CONFIG_RING_VAR varCfgRing;	/* cmd =  9 (CONFIG_RING)    */
3670 	RESET_RING_VAR varRstRing;	/* cmd = 10 (RESET_RING)     */
3671 	READ_CONFIG_VAR varRdConfig;	/* cmd = 11 (READ_CONFIG)    */
3672 	READ_RCONF_VAR varRdRConfig;	/* cmd = 12 (READ_RCONFIG)   */
3673 	READ_SPARM_VAR varRdSparm;	/* cmd = 13 (READ_SPARM(64)) */
3674 	READ_STATUS_VAR varRdStatus;	/* cmd = 14 (READ_STATUS)    */
3675 	READ_RPI_VAR varRdRPI;		/* cmd = 15 (READ_RPI(64))   */
3676 	READ_XRI_VAR varRdXRI;		/* cmd = 16 (READ_XRI)       */
3677 	READ_REV_VAR varRdRev;		/* cmd = 17 (READ_REV)       */
3678 	READ_LNK_VAR varRdLnk;		/* cmd = 18 (READ_LNK_STAT)  */
3679 	REG_LOGIN_VAR varRegLogin;	/* cmd = 19 (REG_LOGIN(64))  */
3680 	UNREG_LOGIN_VAR varUnregLogin;	/* cmd = 20 (UNREG_LOGIN)    */
3681 	CLEAR_LA_VAR varClearLA;	/* cmd = 22 (CLEAR_LA)       */
3682 	DUMP_VAR varDmp;		/* Warm Start DUMP mbx cmd   */
3683 	UNREG_D_ID_VAR varUnregDID;	/* cmd = 0x23 (UNREG_D_ID)   */
3684 	CONFIG_FARP_VAR varCfgFarp;	/* cmd = 0x25 (CONFIG_FARP)
3685 					 * NEW_FEATURE
3686 					 */
3687 	struct config_hbq_var varCfgHbq;/* cmd = 0x7c (CONFIG_HBQ)  */
3688 	struct update_cfg_var varUpdateCfg; /* cmd = 0x1B (UPDATE_CFG)*/
3689 	CONFIG_PORT_VAR varCfgPort;	/* cmd = 0x88 (CONFIG_PORT)  */
3690 	struct lpfc_mbx_read_top varReadTop; /* cmd = 0x95 (READ_TOPOLOGY) */
3691 	REG_VPI_VAR varRegVpi;		/* cmd = 0x96 (REG_VPI) */
3692 	UNREG_VPI_VAR varUnregVpi;	/* cmd = 0x97 (UNREG_VPI) */
3693 	ASYNCEVT_ENABLE_VAR varCfgAsyncEvent; /*cmd = x33 (CONFIG_ASYNC) */
3694 	struct READ_EVENT_LOG_VAR varRdEventLog;	/* cmd = 0x38
3695 							 * (READ_EVENT_LOG)
3696 							 */
3697 	struct config_msi_var varCfgMSI;/* cmd = x30 (CONFIG_MSI)     */
3698 } MAILVARIANTS;
3699 
3700 /*
3701  * SLI-2 specific structures
3702  */
3703 
3704 struct lpfc_hgp {
3705 	__le32 cmdPutInx;
3706 	__le32 rspGetInx;
3707 };
3708 
3709 struct lpfc_pgp {
3710 	__le32 cmdGetInx;
3711 	__le32 rspPutInx;
3712 };
3713 
3714 struct sli2_desc {
3715 	uint32_t unused1[16];
3716 	struct lpfc_hgp host[MAX_SLI3_RINGS];
3717 	struct lpfc_pgp port[MAX_SLI3_RINGS];
3718 };
3719 
3720 struct sli3_desc {
3721 	struct lpfc_hgp host[MAX_SLI3_RINGS];
3722 	uint32_t reserved[8];
3723 	uint32_t hbq_put[16];
3724 };
3725 
3726 struct sli3_pgp {
3727 	struct lpfc_pgp port[MAX_SLI3_RINGS];
3728 	uint32_t hbq_get[16];
3729 };
3730 
3731 union sli_var {
3732 	struct sli2_desc	s2;
3733 	struct sli3_desc	s3;
3734 	struct sli3_pgp		s3_pgp;
3735 };
3736 
3737 typedef struct {
3738 	struct_group_tagged(MAILBOX_word0, bits,
3739 		union {
3740 			struct {
3741 #ifdef __BIG_ENDIAN_BITFIELD
3742 				uint16_t mbxStatus;
3743 				uint8_t mbxCommand;
3744 				uint8_t mbxReserved:6;
3745 				uint8_t mbxHc:1;
3746 				uint8_t mbxOwner:1;	/* Low order bit first word */
3747 #else	/*  __LITTLE_ENDIAN_BITFIELD */
3748 				uint8_t mbxOwner:1;	/* Low order bit first word */
3749 				uint8_t mbxHc:1;
3750 				uint8_t mbxReserved:6;
3751 				uint8_t mbxCommand;
3752 				uint16_t mbxStatus;
3753 #endif
3754 			};
3755 			u32 word0;
3756 		};
3757 	);
3758 
3759 	MAILVARIANTS un;
3760 	union sli_var us;
3761 } MAILBOX_t;
3762 
3763 /*
3764  *    Begin Structure Definitions for IOCB Commands
3765  */
3766 
3767 typedef struct {
3768 #ifdef __BIG_ENDIAN_BITFIELD
3769 	uint8_t statAction;
3770 	uint8_t statRsn;
3771 	uint8_t statBaExp;
3772 	uint8_t statLocalError;
3773 #else	/*  __LITTLE_ENDIAN_BITFIELD */
3774 	uint8_t statLocalError;
3775 	uint8_t statBaExp;
3776 	uint8_t statRsn;
3777 	uint8_t statAction;
3778 #endif
3779 	/* statRsn  P/F_RJT reason codes */
3780 #define RJT_BAD_D_ID       0x01	/* Invalid D_ID field */
3781 #define RJT_BAD_S_ID       0x02	/* Invalid S_ID field */
3782 #define RJT_UNAVAIL_TEMP   0x03	/* N_Port unavailable temp. */
3783 #define RJT_UNAVAIL_PERM   0x04	/* N_Port unavailable perm. */
3784 #define RJT_UNSUP_CLASS    0x05	/* Class not supported */
3785 #define RJT_DELIM_ERR      0x06	/* Delimiter usage error */
3786 #define RJT_UNSUP_TYPE     0x07	/* Type not supported */
3787 #define RJT_BAD_CONTROL    0x08	/* Invalid link conrtol */
3788 #define RJT_BAD_RCTL       0x09	/* R_CTL invalid */
3789 #define RJT_BAD_FCTL       0x0A	/* F_CTL invalid */
3790 #define RJT_BAD_OXID       0x0B	/* OX_ID invalid */
3791 #define RJT_BAD_RXID       0x0C	/* RX_ID invalid */
3792 #define RJT_BAD_SEQID      0x0D	/* SEQ_ID invalid */
3793 #define RJT_BAD_DFCTL      0x0E	/* DF_CTL invalid */
3794 #define RJT_BAD_SEQCNT     0x0F	/* SEQ_CNT invalid */
3795 #define RJT_BAD_PARM       0x10	/* Param. field invalid */
3796 #define RJT_XCHG_ERR       0x11	/* Exchange error */
3797 #define RJT_PROT_ERR       0x12	/* Protocol error */
3798 #define RJT_BAD_LENGTH     0x13	/* Invalid Length */
3799 #define RJT_UNEXPECTED_ACK 0x14	/* Unexpected ACK */
3800 #define RJT_LOGIN_REQUIRED 0x16	/* Login required */
3801 #define RJT_TOO_MANY_SEQ   0x17	/* Excessive sequences */
3802 #define RJT_XCHG_NOT_STRT  0x18	/* Exchange not started */
3803 #define RJT_UNSUP_SEC_HDR  0x19	/* Security hdr not supported */
3804 #define RJT_UNAVAIL_PATH   0x1A	/* Fabric Path not available */
3805 #define RJT_VENDOR_UNIQUE  0xFF	/* Vendor unique error */
3806 
3807 #define IOERR_SUCCESS                 0x00	/* statLocalError */
3808 #define IOERR_MISSING_CONTINUE        0x01
3809 #define IOERR_SEQUENCE_TIMEOUT        0x02
3810 #define IOERR_INTERNAL_ERROR          0x03
3811 #define IOERR_INVALID_RPI             0x04
3812 #define IOERR_NO_XRI                  0x05
3813 #define IOERR_ILLEGAL_COMMAND         0x06
3814 #define IOERR_XCHG_DROPPED            0x07
3815 #define IOERR_ILLEGAL_FIELD           0x08
3816 #define IOERR_RPI_SUSPENDED           0x09
3817 #define IOERR_TOO_MANY_BUFFERS        0x0A
3818 #define IOERR_RCV_BUFFER_WAITING      0x0B
3819 #define IOERR_NO_CONNECTION           0x0C
3820 #define IOERR_TX_DMA_FAILED           0x0D
3821 #define IOERR_RX_DMA_FAILED           0x0E
3822 #define IOERR_ILLEGAL_FRAME           0x0F
3823 #define IOERR_EXTRA_DATA              0x10
3824 #define IOERR_NO_RESOURCES            0x11
3825 #define IOERR_RESERVED                0x12
3826 #define IOERR_ILLEGAL_LENGTH          0x13
3827 #define IOERR_UNSUPPORTED_FEATURE     0x14
3828 #define IOERR_ABORT_IN_PROGRESS       0x15
3829 #define IOERR_ABORT_REQUESTED         0x16
3830 #define IOERR_RECEIVE_BUFFER_TIMEOUT  0x17
3831 #define IOERR_LOOP_OPEN_FAILURE       0x18
3832 #define IOERR_RING_RESET              0x19
3833 #define IOERR_LINK_DOWN               0x1A
3834 #define IOERR_CORRUPTED_DATA          0x1B
3835 #define IOERR_CORRUPTED_RPI           0x1C
3836 #define IOERR_OUT_OF_ORDER_DATA       0x1D
3837 #define IOERR_OUT_OF_ORDER_ACK        0x1E
3838 #define IOERR_DUP_FRAME               0x1F
3839 #define IOERR_LINK_CONTROL_FRAME      0x20	/* ACK_N received */
3840 #define IOERR_BAD_HOST_ADDRESS        0x21
3841 #define IOERR_RCV_HDRBUF_WAITING      0x22
3842 #define IOERR_MISSING_HDR_BUFFER      0x23
3843 #define IOERR_MSEQ_CHAIN_CORRUPTED    0x24
3844 #define IOERR_ABORTMULT_REQUESTED     0x25
3845 #define IOERR_BUFFER_SHORTAGE         0x28
3846 #define IOERR_DEFAULT                 0x29
3847 #define IOERR_CNT                     0x2A
3848 #define IOERR_SLER_FAILURE            0x46
3849 #define IOERR_SLER_CMD_RCV_FAILURE    0x47
3850 #define IOERR_SLER_REC_RJT_ERR        0x48
3851 #define IOERR_SLER_REC_SRR_RETRY_ERR  0x49
3852 #define IOERR_SLER_SRR_RJT_ERR        0x4A
3853 #define IOERR_SLER_RRQ_RJT_ERR        0x4C
3854 #define IOERR_SLER_RRQ_RETRY_ERR      0x4D
3855 #define IOERR_SLER_ABTS_ERR           0x4E
3856 #define IOERR_ELXSEC_KEY_UNWRAP_ERROR		0xF0
3857 #define IOERR_ELXSEC_KEY_UNWRAP_COMPARE_ERROR	0xF1
3858 #define IOERR_ELXSEC_CRYPTO_ERROR		0xF2
3859 #define IOERR_ELXSEC_CRYPTO_COMPARE_ERROR	0xF3
3860 #define IOERR_DRVR_MASK               0x100
3861 #define IOERR_SLI_DOWN                0x101  /* ulpStatus  - Driver defined */
3862 #define IOERR_SLI_BRESET              0x102
3863 #define IOERR_SLI_ABORTED             0x103
3864 #define IOERR_PARAM_MASK              0x1ff
3865 } PARM_ERR;
3866 
3867 typedef union {
3868 	struct {
3869 #ifdef __BIG_ENDIAN_BITFIELD
3870 		uint8_t Rctl;	/* R_CTL field */
3871 		uint8_t Type;	/* TYPE field */
3872 		uint8_t Dfctl;	/* DF_CTL field */
3873 		uint8_t Fctl;	/* Bits 0-7 of IOCB word 5 */
3874 #else	/*  __LITTLE_ENDIAN_BITFIELD */
3875 		uint8_t Fctl;	/* Bits 0-7 of IOCB word 5 */
3876 		uint8_t Dfctl;	/* DF_CTL field */
3877 		uint8_t Type;	/* TYPE field */
3878 		uint8_t Rctl;	/* R_CTL field */
3879 #endif
3880 
3881 #define BC      0x02		/* Broadcast Received  - Fctl */
3882 #define SI      0x04		/* Sequence Initiative */
3883 #define LA      0x08		/* Ignore Link Attention state */
3884 #define LS      0x80		/* Last Sequence */
3885 	} hcsw;
3886 	uint32_t reserved;
3887 } WORD5;
3888 
3889 /* IOCB Command template for a generic response */
3890 typedef struct {
3891 	uint32_t reserved[4];
3892 	PARM_ERR perr;
3893 } GENERIC_RSP;
3894 
3895 /* IOCB Command template for XMIT / XMIT_BCAST / RCV_SEQUENCE / XMIT_ELS */
3896 typedef struct {
3897 	struct ulp_bde xrsqbde[2];
3898 	uint32_t xrsqRo;	/* Starting Relative Offset */
3899 	WORD5 w5;		/* Header control/status word */
3900 } XR_SEQ_FIELDS;
3901 
3902 /* IOCB Command template for ELS_REQUEST */
3903 typedef struct {
3904 	struct ulp_bde elsReq;
3905 	struct ulp_bde elsRsp;
3906 
3907 #ifdef __BIG_ENDIAN_BITFIELD
3908 	uint32_t word4Rsvd:7;
3909 	uint32_t fl:1;
3910 	uint32_t myID:24;
3911 	uint32_t word5Rsvd:8;
3912 	uint32_t remoteID:24;
3913 #else	/*  __LITTLE_ENDIAN_BITFIELD */
3914 	uint32_t myID:24;
3915 	uint32_t fl:1;
3916 	uint32_t word4Rsvd:7;
3917 	uint32_t remoteID:24;
3918 	uint32_t word5Rsvd:8;
3919 #endif
3920 } ELS_REQUEST;
3921 
3922 /* IOCB Command template for RCV_ELS_REQ */
3923 typedef struct {
3924 	struct ulp_bde elsReq[2];
3925 	uint32_t parmRo;
3926 
3927 #ifdef __BIG_ENDIAN_BITFIELD
3928 	uint32_t word5Rsvd:8;
3929 	uint32_t remoteID:24;
3930 #else	/*  __LITTLE_ENDIAN_BITFIELD */
3931 	uint32_t remoteID:24;
3932 	uint32_t word5Rsvd:8;
3933 #endif
3934 } RCV_ELS_REQ;
3935 
3936 /* IOCB Command template for ABORT / CLOSE_XRI */
3937 typedef struct {
3938 	uint32_t rsvd[3];
3939 	uint32_t abortType;
3940 #define ABORT_TYPE_ABTX  0x00000000
3941 #define ABORT_TYPE_ABTS  0x00000001
3942 	uint32_t parm;
3943 #ifdef __BIG_ENDIAN_BITFIELD
3944 	uint16_t abortContextTag; /* ulpContext from command to abort/close */
3945 	uint16_t abortIoTag;	/* ulpIoTag from command to abort/close */
3946 #else	/*  __LITTLE_ENDIAN_BITFIELD */
3947 	uint16_t abortIoTag;	/* ulpIoTag from command to abort/close */
3948 	uint16_t abortContextTag; /* ulpContext from command to abort/close */
3949 #endif
3950 } AC_XRI;
3951 
3952 /* IOCB Command template for ABORT_MXRI64 */
3953 typedef struct {
3954 	uint32_t rsvd[3];
3955 	uint32_t abortType;
3956 	uint32_t parm;
3957 	uint32_t iotag32;
3958 } A_MXRI64;
3959 
3960 /* IOCB Command template for GET_RPI */
3961 typedef struct {
3962 	uint32_t rsvd[4];
3963 	uint32_t parmRo;
3964 #ifdef __BIG_ENDIAN_BITFIELD
3965 	uint32_t word5Rsvd:8;
3966 	uint32_t remoteID:24;
3967 #else	/*  __LITTLE_ENDIAN_BITFIELD */
3968 	uint32_t remoteID:24;
3969 	uint32_t word5Rsvd:8;
3970 #endif
3971 } GET_RPI;
3972 
3973 /* IOCB Command template for all FCP Initiator commands */
3974 typedef struct {
3975 	struct ulp_bde fcpi_cmnd;	/* FCP_CMND payload descriptor */
3976 	struct ulp_bde fcpi_rsp;	/* Rcv buffer */
3977 	uint32_t fcpi_parm;
3978 	uint32_t fcpi_XRdy;	/* transfer ready for IWRITE */
3979 } FCPI_FIELDS;
3980 
3981 /* IOCB Command template for all FCP Target commands */
3982 typedef struct {
3983 	struct ulp_bde fcpt_Buffer[2];	/* FCP_CMND payload descriptor */
3984 	uint32_t fcpt_Offset;
3985 	uint32_t fcpt_Length;	/* transfer ready for IWRITE */
3986 } FCPT_FIELDS;
3987 
3988 /* SLI-2 IOCB structure definitions */
3989 
3990 /* IOCB Command template for 64 bit XMIT / XMIT_BCAST / XMIT_ELS */
3991 typedef struct {
3992 	ULP_BDL bdl;
3993 	uint32_t xrsqRo;	/* Starting Relative Offset */
3994 	WORD5 w5;		/* Header control/status word */
3995 } XMT_SEQ_FIELDS64;
3996 
3997 /* This word is remote ports D_ID for XMIT_ELS_RSP64 */
3998 #define xmit_els_remoteID xrsqRo
3999 
4000 /* IOCB Command template for 64 bit RCV_SEQUENCE64 */
4001 typedef struct {
4002 	struct ulp_bde64 rcvBde;
4003 	uint32_t rsvd1;
4004 	uint32_t xrsqRo;	/* Starting Relative Offset */
4005 	WORD5 w5;		/* Header control/status word */
4006 } RCV_SEQ_FIELDS64;
4007 
4008 /* IOCB Command template for ELS_REQUEST64 */
4009 typedef struct {
4010 	ULP_BDL bdl;
4011 #ifdef __BIG_ENDIAN_BITFIELD
4012 	uint32_t word4Rsvd:7;
4013 	uint32_t fl:1;
4014 	uint32_t myID:24;
4015 	uint32_t word5Rsvd:8;
4016 	uint32_t remoteID:24;
4017 #else	/*  __LITTLE_ENDIAN_BITFIELD */
4018 	uint32_t myID:24;
4019 	uint32_t fl:1;
4020 	uint32_t word4Rsvd:7;
4021 	uint32_t remoteID:24;
4022 	uint32_t word5Rsvd:8;
4023 #endif
4024 } ELS_REQUEST64;
4025 
4026 /* IOCB Command template for GEN_REQUEST64 */
4027 typedef struct {
4028 	ULP_BDL bdl;
4029 	uint32_t xrsqRo;	/* Starting Relative Offset */
4030 	WORD5 w5;		/* Header control/status word */
4031 } GEN_REQUEST64;
4032 
4033 /* IOCB Command template for RCV_ELS_REQ64 */
4034 typedef struct {
4035 	struct ulp_bde64 elsReq;
4036 	uint32_t rcvd1;
4037 	uint32_t parmRo;
4038 
4039 #ifdef __BIG_ENDIAN_BITFIELD
4040 	uint32_t word5Rsvd:8;
4041 	uint32_t remoteID:24;
4042 #else	/*  __LITTLE_ENDIAN_BITFIELD */
4043 	uint32_t remoteID:24;
4044 	uint32_t word5Rsvd:8;
4045 #endif
4046 } RCV_ELS_REQ64;
4047 
4048 /* IOCB Command template for RCV_SEQ64 */
4049 struct rcv_seq64 {
4050 	struct ulp_bde64 elsReq;
4051 	uint32_t hbq_1;
4052 	uint32_t parmRo;
4053 #ifdef __BIG_ENDIAN_BITFIELD
4054 	uint32_t rctl:8;
4055 	uint32_t type:8;
4056 	uint32_t dfctl:8;
4057 	uint32_t ls:1;
4058 	uint32_t fs:1;
4059 	uint32_t rsvd2:3;
4060 	uint32_t si:1;
4061 	uint32_t bc:1;
4062 	uint32_t rsvd3:1;
4063 #else	/*  __LITTLE_ENDIAN_BITFIELD */
4064 	uint32_t rsvd3:1;
4065 	uint32_t bc:1;
4066 	uint32_t si:1;
4067 	uint32_t rsvd2:3;
4068 	uint32_t fs:1;
4069 	uint32_t ls:1;
4070 	uint32_t dfctl:8;
4071 	uint32_t type:8;
4072 	uint32_t rctl:8;
4073 #endif
4074 };
4075 
4076 /* IOCB Command template for all 64 bit FCP Initiator commands */
4077 typedef struct {
4078 	ULP_BDL bdl;
4079 	uint32_t fcpi_parm;
4080 	uint32_t fcpi_XRdy;	/* transfer ready for IWRITE */
4081 } FCPI_FIELDS64;
4082 
4083 /* IOCB Command template for all 64 bit FCP Target commands */
4084 typedef struct {
4085 	ULP_BDL bdl;
4086 	uint32_t fcpt_Offset;
4087 	uint32_t fcpt_Length;	/* transfer ready for IWRITE */
4088 } FCPT_FIELDS64;
4089 
4090 /* IOCB Command template for Async Status iocb commands */
4091 typedef struct {
4092 	uint32_t rsvd[4];
4093 	uint32_t param;
4094 #ifdef __BIG_ENDIAN_BITFIELD
4095 	uint16_t evt_code;		/* High order bits word 5 */
4096 	uint16_t sub_ctxt_tag;		/* Low  order bits word 5 */
4097 #else   /*  __LITTLE_ENDIAN_BITFIELD */
4098 	uint16_t sub_ctxt_tag;		/* High order bits word 5 */
4099 	uint16_t evt_code;		/* Low  order bits word 5 */
4100 #endif
4101 } ASYNCSTAT_FIELDS;
4102 #define ASYNC_TEMP_WARN		0x100
4103 #define ASYNC_TEMP_SAFE		0x101
4104 #define ASYNC_STATUS_CN		0x102
4105 
4106 /* IOCB Command template for CMD_IOCB_RCV_ELS64_CX (0xB7)
4107    or CMD_IOCB_RCV_SEQ64_CX (0xB5) */
4108 
4109 struct rcv_sli3 {
4110 #ifdef __BIG_ENDIAN_BITFIELD
4111 	uint16_t ox_id;
4112 	uint16_t seq_cnt;
4113 
4114 	uint16_t vpi;
4115 	uint16_t word9Rsvd;
4116 #else  /*  __LITTLE_ENDIAN */
4117 	uint16_t seq_cnt;
4118 	uint16_t ox_id;
4119 
4120 	uint16_t word9Rsvd;
4121 	uint16_t vpi;
4122 #endif
4123 	uint32_t word10Rsvd;
4124 	uint32_t acc_len;      /* accumulated length */
4125 	struct ulp_bde64 bde2;
4126 };
4127 
4128 /* Structure used for a single HBQ entry */
4129 struct lpfc_hbq_entry {
4130 	struct ulp_bde64 bde;
4131 	uint32_t buffer_tag;
4132 };
4133 
4134 /* IOCB Command template for QUE_XRI64_CX (0xB3) command */
4135 typedef struct {
4136 	struct lpfc_hbq_entry   buff;
4137 	uint32_t                rsvd;
4138 	uint32_t		rsvd1;
4139 } QUE_XRI64_CX_FIELDS;
4140 
4141 struct que_xri64cx_ext_fields {
4142 	uint32_t	iotag64_low;
4143 	uint32_t	iotag64_high;
4144 	uint32_t	ebde_count;
4145 	uint32_t	rsvd;
4146 	struct lpfc_hbq_entry	buff[5];
4147 };
4148 
4149 struct sli3_bg_fields {
4150 	uint32_t filler[6];	/* word 8-13 in IOCB */
4151 	uint32_t bghm;		/* word 14 - BlockGuard High Water Mark */
4152 /* Bitfields for bgstat (BlockGuard Status - word 15 of IOCB) */
4153 #define BGS_BIDIR_BG_PROF_MASK		0xff000000
4154 #define BGS_BIDIR_BG_PROF_SHIFT		24
4155 #define BGS_BIDIR_ERR_COND_FLAGS_MASK	0x003f0000
4156 #define BGS_BIDIR_ERR_COND_SHIFT	16
4157 #define BGS_BG_PROFILE_MASK		0x0000ff00
4158 #define BGS_BG_PROFILE_SHIFT		8
4159 #define BGS_INVALID_PROF_MASK		0x00000020
4160 #define BGS_INVALID_PROF_SHIFT		5
4161 #define BGS_UNINIT_DIF_BLOCK_MASK	0x00000010
4162 #define BGS_UNINIT_DIF_BLOCK_SHIFT	4
4163 #define BGS_HI_WATER_MARK_PRESENT_MASK	0x00000008
4164 #define BGS_HI_WATER_MARK_PRESENT_SHIFT	3
4165 #define BGS_REFTAG_ERR_MASK		0x00000004
4166 #define BGS_REFTAG_ERR_SHIFT		2
4167 #define BGS_APPTAG_ERR_MASK		0x00000002
4168 #define BGS_APPTAG_ERR_SHIFT		1
4169 #define BGS_GUARD_ERR_MASK		0x00000001
4170 #define BGS_GUARD_ERR_SHIFT		0
4171 	uint32_t bgstat;	/* word 15 - BlockGuard Status */
4172 };
4173 
4174 static inline uint32_t
lpfc_bgs_get_bidir_bg_prof(uint32_t bgstat)4175 lpfc_bgs_get_bidir_bg_prof(uint32_t bgstat)
4176 {
4177 	return (bgstat & BGS_BIDIR_BG_PROF_MASK) >>
4178 				BGS_BIDIR_BG_PROF_SHIFT;
4179 }
4180 
4181 static inline uint32_t
lpfc_bgs_get_bidir_err_cond(uint32_t bgstat)4182 lpfc_bgs_get_bidir_err_cond(uint32_t bgstat)
4183 {
4184 	return (bgstat & BGS_BIDIR_ERR_COND_FLAGS_MASK) >>
4185 				BGS_BIDIR_ERR_COND_SHIFT;
4186 }
4187 
4188 static inline uint32_t
lpfc_bgs_get_bg_prof(uint32_t bgstat)4189 lpfc_bgs_get_bg_prof(uint32_t bgstat)
4190 {
4191 	return (bgstat & BGS_BG_PROFILE_MASK) >>
4192 				BGS_BG_PROFILE_SHIFT;
4193 }
4194 
4195 static inline uint32_t
lpfc_bgs_get_invalid_prof(uint32_t bgstat)4196 lpfc_bgs_get_invalid_prof(uint32_t bgstat)
4197 {
4198 	return (bgstat & BGS_INVALID_PROF_MASK) >>
4199 				BGS_INVALID_PROF_SHIFT;
4200 }
4201 
4202 static inline uint32_t
lpfc_bgs_get_uninit_dif_block(uint32_t bgstat)4203 lpfc_bgs_get_uninit_dif_block(uint32_t bgstat)
4204 {
4205 	return (bgstat & BGS_UNINIT_DIF_BLOCK_MASK) >>
4206 				BGS_UNINIT_DIF_BLOCK_SHIFT;
4207 }
4208 
4209 static inline uint32_t
lpfc_bgs_get_hi_water_mark_present(uint32_t bgstat)4210 lpfc_bgs_get_hi_water_mark_present(uint32_t bgstat)
4211 {
4212 	return (bgstat & BGS_HI_WATER_MARK_PRESENT_MASK) >>
4213 				BGS_HI_WATER_MARK_PRESENT_SHIFT;
4214 }
4215 
4216 static inline uint32_t
lpfc_bgs_get_reftag_err(uint32_t bgstat)4217 lpfc_bgs_get_reftag_err(uint32_t bgstat)
4218 {
4219 	return (bgstat & BGS_REFTAG_ERR_MASK) >>
4220 				BGS_REFTAG_ERR_SHIFT;
4221 }
4222 
4223 static inline uint32_t
lpfc_bgs_get_apptag_err(uint32_t bgstat)4224 lpfc_bgs_get_apptag_err(uint32_t bgstat)
4225 {
4226 	return (bgstat & BGS_APPTAG_ERR_MASK) >>
4227 				BGS_APPTAG_ERR_SHIFT;
4228 }
4229 
4230 static inline uint32_t
lpfc_bgs_get_guard_err(uint32_t bgstat)4231 lpfc_bgs_get_guard_err(uint32_t bgstat)
4232 {
4233 	return (bgstat & BGS_GUARD_ERR_MASK) >>
4234 				BGS_GUARD_ERR_SHIFT;
4235 }
4236 
4237 #define LPFC_EXT_DATA_BDE_COUNT 3
4238 struct fcp_irw_ext {
4239 	uint32_t	io_tag64_low;
4240 	uint32_t	io_tag64_high;
4241 #ifdef __BIG_ENDIAN_BITFIELD
4242 	uint8_t		reserved1;
4243 	uint8_t		reserved2;
4244 	uint8_t		reserved3;
4245 	uint8_t		ebde_count;
4246 #else  /* __LITTLE_ENDIAN */
4247 	uint8_t		ebde_count;
4248 	uint8_t		reserved3;
4249 	uint8_t		reserved2;
4250 	uint8_t		reserved1;
4251 #endif
4252 	uint32_t	reserved4;
4253 	struct ulp_bde64 rbde;		/* response bde */
4254 	struct ulp_bde64 dbde[LPFC_EXT_DATA_BDE_COUNT];	/* data BDE or BPL */
4255 	uint8_t icd[32];		/* immediate command data (32 bytes) */
4256 };
4257 
4258 typedef struct _IOCB {	/* IOCB structure */
4259 	union {
4260 		GENERIC_RSP grsp;	/* Generic response */
4261 		XR_SEQ_FIELDS xrseq;	/* XMIT / BCAST / RCV_SEQUENCE cmd */
4262 		struct ulp_bde cont[3];	/* up to 3 continuation bdes */
4263 		RCV_ELS_REQ rcvels;	/* RCV_ELS_REQ template */
4264 		AC_XRI acxri;	/* ABORT / CLOSE_XRI template */
4265 		A_MXRI64 amxri;	/* abort multiple xri command overlay */
4266 		GET_RPI getrpi;	/* GET_RPI template */
4267 		FCPI_FIELDS fcpi;	/* FCP Initiator template */
4268 		FCPT_FIELDS fcpt;	/* FCP target template */
4269 
4270 		/* SLI-2 structures */
4271 
4272 		struct ulp_bde64 cont64[2];  /* up to 2 64 bit continuation
4273 					      * bde_64s */
4274 		ELS_REQUEST64 elsreq64;	/* ELS_REQUEST template */
4275 		GEN_REQUEST64 genreq64;	/* GEN_REQUEST template */
4276 		RCV_ELS_REQ64 rcvels64;	/* RCV_ELS_REQ template */
4277 		XMT_SEQ_FIELDS64 xseq64;	/* XMIT / BCAST cmd */
4278 		FCPI_FIELDS64 fcpi64;	/* FCP 64 bit Initiator template */
4279 		FCPT_FIELDS64 fcpt64;	/* FCP 64 bit target template */
4280 		ASYNCSTAT_FIELDS asyncstat; /* async_status iocb */
4281 		QUE_XRI64_CX_FIELDS quexri64cx; /* que_xri64_cx fields */
4282 		struct rcv_seq64 rcvseq64;	/* RCV_SEQ64 and RCV_CONT64 */
4283 		struct sli4_bls_rsp bls_rsp; /* UNSOL ABTS BLS_RSP params */
4284 		uint32_t ulpWord[IOCB_WORD_SZ - 2];	/* generic 6 'words' */
4285 	} un;
4286 	union {
4287 		struct {
4288 #ifdef __BIG_ENDIAN_BITFIELD
4289 			uint16_t ulpContext;	/* High order bits word 6 */
4290 			uint16_t ulpIoTag;	/* Low  order bits word 6 */
4291 #else	/*  __LITTLE_ENDIAN_BITFIELD */
4292 			uint16_t ulpIoTag;	/* Low  order bits word 6 */
4293 			uint16_t ulpContext;	/* High order bits word 6 */
4294 #endif
4295 		} t1;
4296 		struct {
4297 #ifdef __BIG_ENDIAN_BITFIELD
4298 			uint16_t ulpContext;	/* High order bits word 6 */
4299 			uint16_t ulpIoTag1:2;	/* Low  order bits word 6 */
4300 			uint16_t ulpIoTag0:14;	/* Low  order bits word 6 */
4301 #else	/*  __LITTLE_ENDIAN_BITFIELD */
4302 			uint16_t ulpIoTag0:14;	/* Low  order bits word 6 */
4303 			uint16_t ulpIoTag1:2;	/* Low  order bits word 6 */
4304 			uint16_t ulpContext;	/* High order bits word 6 */
4305 #endif
4306 		} t2;
4307 	} un1;
4308 #define ulpContext un1.t1.ulpContext
4309 #define ulpIoTag   un1.t1.ulpIoTag
4310 #define ulpIoTag0  un1.t2.ulpIoTag0
4311 
4312 #ifdef __BIG_ENDIAN_BITFIELD
4313 	uint32_t ulpTimeout:8;
4314 	uint32_t ulpXS:1;
4315 	uint32_t ulpFCP2Rcvy:1;
4316 	uint32_t ulpPU:2;
4317 	uint32_t ulpIr:1;
4318 	uint32_t ulpClass:3;
4319 	uint32_t ulpCommand:8;
4320 	uint32_t ulpStatus:4;
4321 	uint32_t ulpBdeCount:2;
4322 	uint32_t ulpLe:1;
4323 	uint32_t ulpOwner:1;	/* Low order bit word 7 */
4324 #else	/*  __LITTLE_ENDIAN_BITFIELD */
4325 	uint32_t ulpOwner:1;	/* Low order bit word 7 */
4326 	uint32_t ulpLe:1;
4327 	uint32_t ulpBdeCount:2;
4328 	uint32_t ulpStatus:4;
4329 	uint32_t ulpCommand:8;
4330 	uint32_t ulpClass:3;
4331 	uint32_t ulpIr:1;
4332 	uint32_t ulpPU:2;
4333 	uint32_t ulpFCP2Rcvy:1;
4334 	uint32_t ulpXS:1;
4335 	uint32_t ulpTimeout:8;
4336 #endif
4337 
4338 	union {
4339 		struct rcv_sli3 rcvsli3; /* words 8 - 15 */
4340 
4341 		/* words 8-31 used for que_xri_cx iocb */
4342 		struct que_xri64cx_ext_fields que_xri64cx_ext_words;
4343 		struct fcp_irw_ext fcp_ext;
4344 		uint32_t sli3Words[24]; /* 96 extra bytes for SLI-3 */
4345 
4346 		/* words 8-15 for BlockGuard */
4347 		struct sli3_bg_fields sli3_bg;
4348 	} unsli3;
4349 
4350 #define ulpCt_h ulpXS
4351 #define ulpCt_l ulpFCP2Rcvy
4352 
4353 #define IOCB_FCP	   1	/* IOCB is used for FCP ELS cmds-ulpRsvByte */
4354 #define IOCB_IP		   2	/* IOCB is used for IP ELS cmds */
4355 #define PARM_UNUSED        0	/* PU field (Word 4) not used */
4356 #define PARM_REL_OFF       1	/* PU field (Word 4) = R. O. */
4357 #define PARM_READ_CHECK    2	/* PU field (Word 4) = Data Transfer Length */
4358 #define PARM_NPIV_DID	   3
4359 #define CLASS1             0	/* Class 1 */
4360 #define CLASS2             1	/* Class 2 */
4361 #define CLASS3             2	/* Class 3 */
4362 #define CLASS_FCP_INTERMIX 7	/* FCP Data->Cls 1, all else->Cls 2 */
4363 
4364 #define IOSTAT_SUCCESS         0x0	/* ulpStatus  - HBA defined */
4365 #define IOSTAT_FCP_RSP_ERROR   0x1
4366 #define IOSTAT_REMOTE_STOP     0x2
4367 #define IOSTAT_LOCAL_REJECT    0x3
4368 #define IOSTAT_NPORT_RJT       0x4
4369 #define IOSTAT_FABRIC_RJT      0x5
4370 #define IOSTAT_NPORT_BSY       0x6
4371 #define IOSTAT_FABRIC_BSY      0x7
4372 #define IOSTAT_INTERMED_RSP    0x8
4373 #define IOSTAT_LS_RJT          0x9
4374 #define IOSTAT_BA_RJT          0xA
4375 #define IOSTAT_RSVD1           0xB
4376 #define IOSTAT_RSVD2           0xC
4377 #define IOSTAT_RSVD3           0xD
4378 #define IOSTAT_RSVD4           0xE
4379 #define IOSTAT_NEED_BUFFER     0xF
4380 #define IOSTAT_DRIVER_REJECT   0x10   /* ulpStatus  - Driver defined */
4381 #define IOSTAT_DEFAULT         0xF    /* Same as rsvd5 for now */
4382 #define IOSTAT_CNT             0x11
4383 
4384 } IOCB_t;
4385 
4386 
4387 #define SLI1_SLIM_SIZE   (4 * 1024)
4388 
4389 /* Up to 498 IOCBs will fit into 16k
4390  * 256 (MAILBOX_t) + 140 (PCB_t) + ( 32 (IOCB_t) * 498 ) = < 16384
4391  */
4392 #define SLI2_SLIM_SIZE   (64 * 1024)
4393 
4394 /* Maximum IOCBs that will fit in SLI2 slim */
4395 #define MAX_SLI2_IOCB    498
4396 #define MAX_SLIM_IOCB_SIZE (SLI2_SLIM_SIZE - \
4397 			    (sizeof(MAILBOX_t) + sizeof(PCB_t) + \
4398 			    sizeof(uint32_t) * MAILBOX_EXT_WSIZE))
4399 
4400 /* HBQ entries are 4 words each = 4k */
4401 #define LPFC_TOTAL_HBQ_SIZE (sizeof(struct lpfc_hbq_entry) *  \
4402 			     lpfc_sli_hbq_count())
4403 
4404 struct lpfc_sli2_slim {
4405 	MAILBOX_t mbx;
4406 	uint32_t  mbx_ext_words[MAILBOX_EXT_WSIZE];
4407 	PCB_t pcb;
4408 	IOCB_t IOCBs[MAX_SLIM_IOCB_SIZE];
4409 };
4410 
4411 /*
4412  * This function checks PCI device to allow special handling for LC HBAs.
4413  *
4414  * Parameters:
4415  * device : struct pci_dev 's device field
4416  *
4417  * return 1 => TRUE
4418  *        0 => FALSE
4419  */
4420 static inline int
lpfc_is_LC_HBA(unsigned short device)4421 lpfc_is_LC_HBA(unsigned short device)
4422 {
4423 	if ((device == PCI_DEVICE_ID_TFLY) ||
4424 	    (device == PCI_DEVICE_ID_PFLY) ||
4425 	    (device == PCI_DEVICE_ID_LP101) ||
4426 	    (device == PCI_DEVICE_ID_BMID) ||
4427 	    (device == PCI_DEVICE_ID_BSMB) ||
4428 	    (device == PCI_DEVICE_ID_ZMID) ||
4429 	    (device == PCI_DEVICE_ID_ZSMB) ||
4430 	    (device == PCI_DEVICE_ID_SAT_MID) ||
4431 	    (device == PCI_DEVICE_ID_SAT_SMB) ||
4432 	    (device == PCI_DEVICE_ID_RFLY))
4433 		return 1;
4434 	else
4435 		return 0;
4436 }
4437 
4438 /*
4439  * Determine if failed because of a link event or firmware reset.
4440  */
4441 static inline int
lpfc_error_lost_link(u32 ulp_status,u32 ulp_word4)4442 lpfc_error_lost_link(u32 ulp_status, u32 ulp_word4)
4443 {
4444 	return (ulp_status == IOSTAT_LOCAL_REJECT &&
4445 		(ulp_word4 == IOERR_SLI_ABORTED ||
4446 		 ulp_word4 == IOERR_LINK_DOWN ||
4447 		 ulp_word4 == IOERR_SLI_DOWN));
4448 }
4449 
4450 #define BPL_ALIGN_SZ 8 /* 8 byte alignment for bpl and mbufs */
4451