1 /*
2  * This file is provided under a dual BSD/GPLv2 license.  When using or
3  * redistributing this file, you may do so under either license.
4  *
5  * GPL LICENSE SUMMARY
6  *
7  * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
8  *
9  * This program is free software; you can redistribute it and/or modify
10  * it under the terms of version 2 of the GNU General Public License as
11  * published by the Free Software Foundation.
12  *
13  * This program is distributed in the hope that it will be useful, but
14  * WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
16  * General Public License for more details.
17  *
18  * You should have received a copy of the GNU General Public License
19  * along with this program; if not, write to the Free Software
20  * Foundation, Inc., 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
21  * The full GNU General Public License is included in this distribution
22  * in the file called LICENSE.GPL.
23  *
24  * BSD LICENSE
25  *
26  * Copyright(c) 2008 - 2011 Intel Corporation. All rights reserved.
27  * All rights reserved.
28  *
29  * Redistribution and use in source and binary forms, with or without
30  * modification, are permitted provided that the following conditions
31  * are met:
32  *
33  *   * Redistributions of source code must retain the above copyright
34  *     notice, this list of conditions and the following disclaimer.
35  *   * Redistributions in binary form must reproduce the above copyright
36  *     notice, this list of conditions and the following disclaimer in
37  *     the documentation and/or other materials provided with the
38  *     distribution.
39  *   * Neither the name of Intel Corporation nor the names of its
40  *     contributors may be used to endorse or promote products derived
41  *     from this software without specific prior written permission.
42  *
43  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
44  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
45  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
46  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
47  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
48  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
49  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
50  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
51  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
52  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
53  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
54  */
55 #ifndef _ISCI_PROBE_ROMS_H_
56 #define _ISCI_PROBE_ROMS_H_
57 
58 #ifdef __KERNEL__
59 #include <linux/firmware.h>
60 #include <linux/pci.h>
61 #include <linux/efi.h>
62 #include "isci.h"
63 
64 #define SCIC_SDS_PARM_NO_SPEED   0
65 
66 /* generation 1 (i.e. 1.5 Gb/s) */
67 #define SCIC_SDS_PARM_GEN1_SPEED 1
68 
69 /* generation 2 (i.e. 3.0 Gb/s) */
70 #define SCIC_SDS_PARM_GEN2_SPEED 2
71 
72 /* generation 3 (i.e. 6.0 Gb/s) */
73 #define SCIC_SDS_PARM_GEN3_SPEED 3
74 #define SCIC_SDS_PARM_MAX_SPEED SCIC_SDS_PARM_GEN3_SPEED
75 
76 /* parameters that can be set by module parameters */
77 struct sci_user_parameters {
78 	struct sci_phy_user_params {
79 		/**
80 		 * This field specifies the NOTIFY (ENABLE SPIN UP) primitive
81 		 * insertion frequency for this phy index.
82 		 */
83 		u32 notify_enable_spin_up_insertion_frequency;
84 
85 		/**
86 		 * This method specifies the number of transmitted DWORDs within which
87 		 * to transmit a single ALIGN primitive.  This value applies regardless
88 		 * of what type of device is attached or connection state.  A value of
89 		 * 0 indicates that no ALIGN primitives will be inserted.
90 		 */
91 		u16 align_insertion_frequency;
92 
93 		/**
94 		 * This method specifies the number of transmitted DWORDs within which
95 		 * to transmit 2 ALIGN primitives.  This applies for SAS connections
96 		 * only.  A minimum value of 3 is required for this field.
97 		 */
98 		u16 in_connection_align_insertion_frequency;
99 
100 		/**
101 		 * This field indicates the maximum speed generation to be utilized
102 		 * by phys in the supplied port.
103 		 * - A value of 1 indicates generation 1 (i.e. 1.5 Gb/s).
104 		 * - A value of 2 indicates generation 2 (i.e. 3.0 Gb/s).
105 		 * - A value of 3 indicates generation 3 (i.e. 6.0 Gb/s).
106 		 */
107 		u8 max_speed_generation;
108 
109 	} phys[SCI_MAX_PHYS];
110 
111 	/**
112 	 * This field specifies the maximum number of direct attached devices
113 	 * that can have power supplied to them simultaneously.
114 	 */
115 	u8 max_concurr_spinup;
116 
117 	/**
118 	 * This field specifies the number of seconds to allow a phy to consume
119 	 * power before yielding to another phy.
120 	 *
121 	 */
122 	u8 phy_spin_up_delay_interval;
123 
124 	/**
125 	 * These timer values specifies how long a link will remain open with no
126 	 * activity in increments of a microsecond, it can be in increments of
127 	 * 100 microseconds if the upper most bit is set.
128 	 *
129 	 */
130 	u16 stp_inactivity_timeout;
131 	u16 ssp_inactivity_timeout;
132 
133 	/**
134 	 * These timer values specifies how long a link will remain open in increments
135 	 * of 100 microseconds.
136 	 *
137 	 */
138 	u16 stp_max_occupancy_timeout;
139 	u16 ssp_max_occupancy_timeout;
140 
141 	/**
142 	 * This timer value specifies how long a link will remain open with no
143 	 * outbound traffic in increments of a microsecond.
144 	 *
145 	 */
146 	u8 no_outbound_task_timeout;
147 
148 };
149 
150 #define SCIC_SDS_PARM_PHY_MASK_MIN 0x0
151 #define SCIC_SDS_PARM_PHY_MASK_MAX 0xF
152 #define MAX_CONCURRENT_DEVICE_SPIN_UP_COUNT 4
153 
154 struct sci_oem_params;
155 int sci_oem_parameters_validate(struct sci_oem_params *oem, u8 version);
156 
157 struct isci_orom;
158 struct isci_orom *isci_request_oprom(struct pci_dev *pdev);
159 struct isci_orom *isci_request_firmware(struct pci_dev *pdev, const struct firmware *fw);
160 struct isci_orom *isci_get_efi_var(struct pci_dev *pdev);
161 
162 struct isci_oem_hdr {
163 	u8 sig[4];
164 	u8 rev_major;
165 	u8 rev_minor;
166 	u16 len;
167 	u8 checksum;
168 	u8 reserved1;
169 	u16 reserved2;
170 } __attribute__ ((packed));
171 
172 #else
173 #define SCI_MAX_PORTS 4
174 #define SCI_MAX_PHYS 4
175 #define SCI_MAX_CONTROLLERS 2
176 #endif
177 
178 #define ISCI_FW_NAME		"isci/isci_firmware.bin"
179 
180 #define ROMSIGNATURE		0xaa55
181 
182 #define ISCI_OEM_SIG		"$OEM"
183 #define ISCI_OEM_SIG_SIZE	4
184 #define ISCI_ROM_SIG		"ISCUOEMB"
185 #define ISCI_ROM_SIG_SIZE	8
186 
187 #define ISCI_EFI_VENDOR_GUID	\
188 	EFI_GUID(0x193dfefa, 0xa445, 0x4302, 0x99, 0xd8, 0xef, 0x3a, 0xad, \
189 			0x1a, 0x04, 0xc6)
190 #define ISCI_EFI_VAR_NAME	"RstScuO"
191 
192 #define ISCI_ROM_VER_1_0	0x10
193 #define ISCI_ROM_VER_1_1	0x11
194 #define ISCI_ROM_VER_1_3	0x13
195 #define ISCI_ROM_VER_LATEST	ISCI_ROM_VER_1_3
196 
197 /* Allowed PORT configuration modes APC Automatic PORT configuration mode is
198  * defined by the OEM configuration parameters providing no PHY_MASK parameters
199  * for any PORT. i.e. There are no phys assigned to any of the ports at start.
200  * MPC Manual PORT configuration mode is defined by the OEM configuration
201  * parameters providing a PHY_MASK value for any PORT.  It is assumed that any
202  * PORT with no PHY_MASK is an invalid port and not all PHYs must be assigned.
203  * A PORT_PHY mask that assigns just a single PHY to a port and no other PHYs
204  * being assigned is sufficient to declare manual PORT configuration.
205  */
206 enum sci_port_configuration_mode {
207 	SCIC_PORT_MANUAL_CONFIGURATION_MODE = 0,
208 	SCIC_PORT_AUTOMATIC_CONFIGURATION_MODE = 1
209 };
210 
211 struct sci_bios_oem_param_block_hdr {
212 	uint8_t signature[ISCI_ROM_SIG_SIZE];
213 	uint16_t total_block_length;
214 	uint8_t hdr_length;
215 	uint8_t version;
216 	uint8_t preboot_source;
217 	uint8_t num_elements;
218 	uint16_t element_length;
219 	uint8_t reserved[8];
220 } __attribute__ ((packed));
221 
222 struct sci_oem_params {
223 	struct {
224 		uint8_t mode_type;
225 		uint8_t max_concurr_spin_up;
226 		/*
227 		 * This bitfield indicates the OEM's desired default Tx
228 		 * Spread Spectrum Clocking (SSC) settings for SATA and SAS.
229 		 * NOTE: Default SSC Modulation Frequency is 31.5KHz.
230 		 */
231 		union {
232 			struct {
233 			/*
234 			 * NOTE: Max spread for SATA is +0 / -5000 PPM.
235 			 * Down-spreading SSC (only method allowed for SATA):
236 			 *  SATA SSC Tx Disabled                    = 0x0
237 			 *  SATA SSC Tx at +0 / -1419 PPM Spread    = 0x2
238 			 *  SATA SSC Tx at +0 / -2129 PPM Spread    = 0x3
239 			 *  SATA SSC Tx at +0 / -4257 PPM Spread    = 0x6
240 			 *  SATA SSC Tx at +0 / -4967 PPM Spread    = 0x7
241 			 */
242 				uint8_t ssc_sata_tx_spread_level:4;
243 			/*
244 			 * SAS SSC Tx Disabled                     = 0x0
245 			 *
246 			 * NOTE: Max spread for SAS down-spreading +0 /
247 			 *	 -2300 PPM
248 			 * Down-spreading SSC:
249 			 *  SAS SSC Tx at +0 / -1419 PPM Spread     = 0x2
250 			 *  SAS SSC Tx at +0 / -2129 PPM Spread     = 0x3
251 			 *
252 			 * NOTE: Max spread for SAS center-spreading +2300 /
253 			 *	 -2300 PPM
254 			 * Center-spreading SSC:
255 			 *  SAS SSC Tx at +1064 / -1064 PPM Spread  = 0x3
256 			 *  SAS SSC Tx at +2129 / -2129 PPM Spread  = 0x6
257 			 */
258 				uint8_t ssc_sas_tx_spread_level:3;
259 			/*
260 			 * NOTE: Refer to the SSC section of the SAS 2.x
261 			 * Specification for proper setting of this field.
262 			 * For standard SAS Initiator SAS PHY operation it
263 			 * should be 0 for Down-spreading.
264 			 * SAS SSC Tx spread type:
265 			 *  Down-spreading SSC      = 0
266 			 *  Center-spreading SSC    = 1
267 			 */
268 				uint8_t ssc_sas_tx_type:1;
269 			};
270 			uint8_t do_enable_ssc;
271 		};
272 		/*
273 		 * This field indicates length of the SAS/SATA cable between
274 		 * host and device.
275 		 * This field is used make relationship between analog
276 		 * parameters of the phy in the silicon and length of the cable.
277 		 * Supported cable attenuation levels:
278 		 * "short"- up to 3m, "medium"-3m to 6m, and "long"- more than
279 		 * 6m.
280 		 *
281 		 * This is bit mask field:
282 		 *
283 		 * BIT:      (MSB) 7     6     5     4
284 		 * ASSIGNMENT:   <phy3><phy2><phy1><phy0>  - Medium cable
285 		 *                                           length assignment
286 		 * BIT:            3     2     1     0  (LSB)
287 		 * ASSIGNMENT:   <phy3><phy2><phy1><phy0>  - Long cable length
288 		 *                                           assignment
289 		 *
290 		 * BITS 7-4 are set when the cable length is assigned to medium
291 		 * BITS 3-0 are set when the cable length is assigned to long
292 		 *
293 		 * The BIT positions are clear when the cable length is
294 		 * assigned to short.
295 		 *
296 		 * Setting the bits for both long and medium cable length is
297 		 * undefined.
298 		 *
299 		 * A value of 0x84 would assign
300 		 *    phy3 - medium
301 		 *    phy2 - long
302 		 *    phy1 - short
303 		 *    phy0 - short
304 		 */
305 		uint8_t cable_selection_mask;
306 	} controller;
307 
308 	struct {
309 		uint8_t phy_mask;
310 	} ports[SCI_MAX_PORTS];
311 
312 	struct sci_phy_oem_params {
313 		struct {
314 			uint32_t high;
315 			uint32_t low;
316 		} sas_address;
317 
318 		uint32_t afe_tx_amp_control0;
319 		uint32_t afe_tx_amp_control1;
320 		uint32_t afe_tx_amp_control2;
321 		uint32_t afe_tx_amp_control3;
322 	} phys[SCI_MAX_PHYS];
323 } __attribute__ ((packed));
324 
325 struct isci_orom {
326 	struct sci_bios_oem_param_block_hdr hdr;
327 	struct sci_oem_params ctrl[SCI_MAX_CONTROLLERS];
328 } __attribute__ ((packed));
329 
330 #endif
331