1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * STMicroelectronics STM32 USB PHY Controller driver
4 *
5 * Copyright (C) 2018 STMicroelectronics
6 * Author(s): Amelie Delaunay <amelie.delaunay@st.com>.
7 */
8 #include <linux/bitfield.h>
9 #include <linux/clk.h>
10 #include <linux/clk-provider.h>
11 #include <linux/delay.h>
12 #include <linux/iopoll.h>
13 #include <linux/kernel.h>
14 #include <linux/module.h>
15 #include <linux/of_platform.h>
16 #include <linux/phy/phy.h>
17 #include <linux/reset.h>
18 #include <linux/units.h>
19
20 #define STM32_USBPHYC_PLL 0x0
21 #define STM32_USBPHYC_MISC 0x8
22 #define STM32_USBPHYC_MONITOR(X) (0x108 + ((X) * 0x100))
23 #define STM32_USBPHYC_TUNE(X) (0x10C + ((X) * 0x100))
24 #define STM32_USBPHYC_VERSION 0x3F4
25
26 /* STM32_USBPHYC_PLL bit fields */
27 #define PLLNDIV GENMASK(6, 0)
28 #define PLLFRACIN GENMASK(25, 10)
29 #define PLLEN BIT(26)
30 #define PLLSTRB BIT(27)
31 #define PLLSTRBYP BIT(28)
32 #define PLLFRACCTL BIT(29)
33 #define PLLDITHEN0 BIT(30)
34 #define PLLDITHEN1 BIT(31)
35
36 /* STM32_USBPHYC_MISC bit fields */
37 #define SWITHOST BIT(0)
38
39 /* STM32_USBPHYC_MONITOR bit fields */
40 #define STM32_USBPHYC_MON_OUT GENMASK(3, 0)
41 #define STM32_USBPHYC_MON_SEL GENMASK(8, 4)
42 #define STM32_USBPHYC_MON_SEL_LOCKP 0x1F
43 #define STM32_USBPHYC_MON_OUT_LOCKP BIT(3)
44
45 /* STM32_USBPHYC_TUNE bit fields */
46 #define INCURREN BIT(0)
47 #define INCURRINT BIT(1)
48 #define LFSCAPEN BIT(2)
49 #define HSDRVSLEW BIT(3)
50 #define HSDRVDCCUR BIT(4)
51 #define HSDRVDCLEV BIT(5)
52 #define HSDRVCURINCR BIT(6)
53 #define FSDRVRFADJ BIT(7)
54 #define HSDRVRFRED BIT(8)
55 #define HSDRVCHKITRM GENMASK(12, 9)
56 #define HSDRVCHKZTRM GENMASK(14, 13)
57 #define OTPCOMP GENMASK(19, 15)
58 #define SQLCHCTL GENMASK(21, 20)
59 #define HDRXGNEQEN BIT(22)
60 #define HSRXOFF GENMASK(24, 23)
61 #define HSFALLPREEM BIT(25)
62 #define SHTCCTCTLPROT BIT(26)
63 #define STAGSEL BIT(27)
64
65 enum boosting_vals {
66 BOOST_1000_UA = 1000,
67 BOOST_2000_UA = 2000,
68 };
69
70 enum dc_level_vals {
71 DC_NOMINAL,
72 DC_PLUS_5_TO_7_MV,
73 DC_PLUS_10_TO_14_MV,
74 DC_MINUS_5_TO_7_MV,
75 DC_MAX,
76 };
77
78 enum current_trim {
79 CUR_NOMINAL,
80 CUR_PLUS_1_56_PCT,
81 CUR_PLUS_3_12_PCT,
82 CUR_PLUS_4_68_PCT,
83 CUR_PLUS_6_24_PCT,
84 CUR_PLUS_7_8_PCT,
85 CUR_PLUS_9_36_PCT,
86 CUR_PLUS_10_92_PCT,
87 CUR_PLUS_12_48_PCT,
88 CUR_PLUS_14_04_PCT,
89 CUR_PLUS_15_6_PCT,
90 CUR_PLUS_17_16_PCT,
91 CUR_PLUS_19_01_PCT,
92 CUR_PLUS_20_58_PCT,
93 CUR_PLUS_22_16_PCT,
94 CUR_PLUS_23_73_PCT,
95 CUR_MAX,
96 };
97
98 enum impedance_trim {
99 IMP_NOMINAL,
100 IMP_MINUS_2_OHMS,
101 IMP_MINUS_4_OMHS,
102 IMP_MINUS_6_OHMS,
103 IMP_MAX,
104 };
105
106 enum squelch_level {
107 SQLCH_NOMINAL,
108 SQLCH_PLUS_7_MV,
109 SQLCH_MINUS_5_MV,
110 SQLCH_PLUS_14_MV,
111 SQLCH_MAX,
112 };
113
114 enum rx_offset {
115 NO_RX_OFFSET,
116 RX_OFFSET_PLUS_5_MV,
117 RX_OFFSET_PLUS_10_MV,
118 RX_OFFSET_MINUS_5_MV,
119 RX_OFFSET_MAX,
120 };
121
122 /* STM32_USBPHYC_VERSION bit fields */
123 #define MINREV GENMASK(3, 0)
124 #define MAJREV GENMASK(7, 4)
125
126 #define PLL_FVCO_MHZ 2880
127 #define PLL_INFF_MIN_RATE_HZ 19200000
128 #define PLL_INFF_MAX_RATE_HZ 38400000
129
130 struct pll_params {
131 u8 ndiv;
132 u16 frac;
133 };
134
135 struct stm32_usbphyc_phy {
136 struct phy *phy;
137 struct stm32_usbphyc *usbphyc;
138 struct regulator *vbus;
139 u32 index;
140 bool active;
141 u32 tune;
142 };
143
144 struct stm32_usbphyc {
145 struct device *dev;
146 void __iomem *base;
147 struct clk *clk;
148 struct reset_control *rst;
149 struct stm32_usbphyc_phy **phys;
150 int nphys;
151 struct regulator *vdda1v1;
152 struct regulator *vdda1v8;
153 atomic_t n_pll_cons;
154 struct clk_hw clk48_hw;
155 int switch_setup;
156 };
157
stm32_usbphyc_set_bits(void __iomem * reg,u32 bits)158 static inline void stm32_usbphyc_set_bits(void __iomem *reg, u32 bits)
159 {
160 writel_relaxed(readl_relaxed(reg) | bits, reg);
161 }
162
stm32_usbphyc_clr_bits(void __iomem * reg,u32 bits)163 static inline void stm32_usbphyc_clr_bits(void __iomem *reg, u32 bits)
164 {
165 writel_relaxed(readl_relaxed(reg) & ~bits, reg);
166 }
167
stm32_usbphyc_regulators_enable(struct stm32_usbphyc * usbphyc)168 static int stm32_usbphyc_regulators_enable(struct stm32_usbphyc *usbphyc)
169 {
170 int ret;
171
172 ret = regulator_enable(usbphyc->vdda1v1);
173 if (ret)
174 return ret;
175
176 ret = regulator_enable(usbphyc->vdda1v8);
177 if (ret)
178 goto vdda1v1_disable;
179
180 return 0;
181
182 vdda1v1_disable:
183 regulator_disable(usbphyc->vdda1v1);
184
185 return ret;
186 }
187
stm32_usbphyc_regulators_disable(struct stm32_usbphyc * usbphyc)188 static int stm32_usbphyc_regulators_disable(struct stm32_usbphyc *usbphyc)
189 {
190 int ret;
191
192 ret = regulator_disable(usbphyc->vdda1v8);
193 if (ret)
194 return ret;
195
196 ret = regulator_disable(usbphyc->vdda1v1);
197 if (ret)
198 return ret;
199
200 return 0;
201 }
202
stm32_usbphyc_get_pll_params(u32 clk_rate,struct pll_params * pll_params)203 static void stm32_usbphyc_get_pll_params(u32 clk_rate,
204 struct pll_params *pll_params)
205 {
206 unsigned long long fvco, ndiv, frac;
207
208 /* _
209 * | FVCO = INFF*2*(NDIV + FRACT/2^16) when DITHER_DISABLE[1] = 1
210 * | FVCO = 2880MHz
211 * <
212 * | NDIV = integer part of input bits to set the LDF
213 * |_FRACT = fractional part of input bits to set the LDF
214 * => PLLNDIV = integer part of (FVCO / (INFF*2))
215 * => PLLFRACIN = fractional part of(FVCO / INFF*2) * 2^16
216 * <=> PLLFRACIN = ((FVCO / (INFF*2)) - PLLNDIV) * 2^16
217 */
218 fvco = (unsigned long long)PLL_FVCO_MHZ * HZ_PER_MHZ;
219
220 ndiv = fvco;
221 do_div(ndiv, (clk_rate * 2));
222 pll_params->ndiv = (u8)ndiv;
223
224 frac = fvco * (1 << 16);
225 do_div(frac, (clk_rate * 2));
226 frac = frac - (ndiv * (1 << 16));
227 pll_params->frac = (u16)frac;
228 }
229
stm32_usbphyc_pll_init(struct stm32_usbphyc * usbphyc)230 static int stm32_usbphyc_pll_init(struct stm32_usbphyc *usbphyc)
231 {
232 struct pll_params pll_params;
233 u32 clk_rate = clk_get_rate(usbphyc->clk);
234 u32 ndiv, frac;
235 u32 usbphyc_pll;
236
237 if ((clk_rate < PLL_INFF_MIN_RATE_HZ) ||
238 (clk_rate > PLL_INFF_MAX_RATE_HZ)) {
239 dev_err(usbphyc->dev, "input clk freq (%dHz) out of range\n",
240 clk_rate);
241 return -EINVAL;
242 }
243
244 stm32_usbphyc_get_pll_params(clk_rate, &pll_params);
245 ndiv = FIELD_PREP(PLLNDIV, pll_params.ndiv);
246 frac = FIELD_PREP(PLLFRACIN, pll_params.frac);
247
248 usbphyc_pll = PLLDITHEN1 | PLLDITHEN0 | PLLSTRBYP | ndiv;
249
250 if (pll_params.frac)
251 usbphyc_pll |= PLLFRACCTL | frac;
252
253 writel_relaxed(usbphyc_pll, usbphyc->base + STM32_USBPHYC_PLL);
254
255 dev_dbg(usbphyc->dev, "input clk freq=%dHz, ndiv=%lu, frac=%lu\n",
256 clk_rate, FIELD_GET(PLLNDIV, usbphyc_pll),
257 FIELD_GET(PLLFRACIN, usbphyc_pll));
258
259 return 0;
260 }
261
__stm32_usbphyc_pll_disable(struct stm32_usbphyc * usbphyc)262 static int __stm32_usbphyc_pll_disable(struct stm32_usbphyc *usbphyc)
263 {
264 void __iomem *pll_reg = usbphyc->base + STM32_USBPHYC_PLL;
265 u32 pllen;
266
267 stm32_usbphyc_clr_bits(pll_reg, PLLEN);
268
269 /* Wait for minimum width of powerdown pulse (ENABLE = Low) */
270 if (readl_relaxed_poll_timeout(pll_reg, pllen, !(pllen & PLLEN), 5, 50))
271 dev_err(usbphyc->dev, "PLL not reset\n");
272
273 return stm32_usbphyc_regulators_disable(usbphyc);
274 }
275
stm32_usbphyc_pll_disable(struct stm32_usbphyc * usbphyc)276 static int stm32_usbphyc_pll_disable(struct stm32_usbphyc *usbphyc)
277 {
278 /* Check if a phy port is still active or clk48 in use */
279 if (atomic_dec_return(&usbphyc->n_pll_cons) > 0)
280 return 0;
281
282 return __stm32_usbphyc_pll_disable(usbphyc);
283 }
284
stm32_usbphyc_pll_enable(struct stm32_usbphyc * usbphyc)285 static int stm32_usbphyc_pll_enable(struct stm32_usbphyc *usbphyc)
286 {
287 void __iomem *pll_reg = usbphyc->base + STM32_USBPHYC_PLL;
288 bool pllen = readl_relaxed(pll_reg) & PLLEN;
289 int ret;
290
291 /*
292 * Check if a phy port or clk48 prepare has configured the pll
293 * and ensure the PLL is enabled
294 */
295 if (atomic_inc_return(&usbphyc->n_pll_cons) > 1 && pllen)
296 return 0;
297
298 if (pllen) {
299 /*
300 * PLL shouldn't be enabled without known consumer,
301 * disable it and reinit n_pll_cons
302 */
303 dev_warn(usbphyc->dev, "PLL enabled without known consumers\n");
304
305 ret = __stm32_usbphyc_pll_disable(usbphyc);
306 if (ret)
307 goto dec_n_pll_cons;
308 }
309
310 ret = stm32_usbphyc_regulators_enable(usbphyc);
311 if (ret)
312 goto dec_n_pll_cons;
313
314 ret = stm32_usbphyc_pll_init(usbphyc);
315 if (ret)
316 goto reg_disable;
317
318 stm32_usbphyc_set_bits(pll_reg, PLLEN);
319
320 return 0;
321
322 reg_disable:
323 stm32_usbphyc_regulators_disable(usbphyc);
324
325 dec_n_pll_cons:
326 atomic_dec(&usbphyc->n_pll_cons);
327
328 return ret;
329 }
330
stm32_usbphyc_phy_init(struct phy * phy)331 static int stm32_usbphyc_phy_init(struct phy *phy)
332 {
333 struct stm32_usbphyc_phy *usbphyc_phy = phy_get_drvdata(phy);
334 struct stm32_usbphyc *usbphyc = usbphyc_phy->usbphyc;
335 u32 reg_mon = STM32_USBPHYC_MONITOR(usbphyc_phy->index);
336 u32 monsel = FIELD_PREP(STM32_USBPHYC_MON_SEL,
337 STM32_USBPHYC_MON_SEL_LOCKP);
338 u32 monout;
339 int ret;
340
341 ret = stm32_usbphyc_pll_enable(usbphyc);
342 if (ret)
343 return ret;
344
345 /* Check that PLL Lock input to PHY is High */
346 writel_relaxed(monsel, usbphyc->base + reg_mon);
347 ret = readl_relaxed_poll_timeout(usbphyc->base + reg_mon, monout,
348 (monout & STM32_USBPHYC_MON_OUT_LOCKP),
349 100, 1000);
350 if (ret) {
351 dev_err(usbphyc->dev, "PLL Lock input to PHY is Low (val=%x)\n",
352 (u32)(monout & STM32_USBPHYC_MON_OUT));
353 goto pll_disable;
354 }
355
356 usbphyc_phy->active = true;
357
358 return 0;
359
360 pll_disable:
361 stm32_usbphyc_pll_disable(usbphyc);
362
363 return ret;
364 }
365
stm32_usbphyc_phy_exit(struct phy * phy)366 static int stm32_usbphyc_phy_exit(struct phy *phy)
367 {
368 struct stm32_usbphyc_phy *usbphyc_phy = phy_get_drvdata(phy);
369 struct stm32_usbphyc *usbphyc = usbphyc_phy->usbphyc;
370
371 usbphyc_phy->active = false;
372
373 return stm32_usbphyc_pll_disable(usbphyc);
374 }
375
stm32_usbphyc_phy_power_on(struct phy * phy)376 static int stm32_usbphyc_phy_power_on(struct phy *phy)
377 {
378 struct stm32_usbphyc_phy *usbphyc_phy = phy_get_drvdata(phy);
379
380 if (usbphyc_phy->vbus)
381 return regulator_enable(usbphyc_phy->vbus);
382
383 return 0;
384 }
385
stm32_usbphyc_phy_power_off(struct phy * phy)386 static int stm32_usbphyc_phy_power_off(struct phy *phy)
387 {
388 struct stm32_usbphyc_phy *usbphyc_phy = phy_get_drvdata(phy);
389
390 if (usbphyc_phy->vbus)
391 return regulator_disable(usbphyc_phy->vbus);
392
393 return 0;
394 }
395
396 static const struct phy_ops stm32_usbphyc_phy_ops = {
397 .init = stm32_usbphyc_phy_init,
398 .exit = stm32_usbphyc_phy_exit,
399 .power_on = stm32_usbphyc_phy_power_on,
400 .power_off = stm32_usbphyc_phy_power_off,
401 .owner = THIS_MODULE,
402 };
403
stm32_usbphyc_clk48_prepare(struct clk_hw * hw)404 static int stm32_usbphyc_clk48_prepare(struct clk_hw *hw)
405 {
406 struct stm32_usbphyc *usbphyc = container_of(hw, struct stm32_usbphyc, clk48_hw);
407
408 return stm32_usbphyc_pll_enable(usbphyc);
409 }
410
stm32_usbphyc_clk48_unprepare(struct clk_hw * hw)411 static void stm32_usbphyc_clk48_unprepare(struct clk_hw *hw)
412 {
413 struct stm32_usbphyc *usbphyc = container_of(hw, struct stm32_usbphyc, clk48_hw);
414
415 stm32_usbphyc_pll_disable(usbphyc);
416 }
417
stm32_usbphyc_clk48_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)418 static unsigned long stm32_usbphyc_clk48_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
419 {
420 return 48000000;
421 }
422
423 static const struct clk_ops usbphyc_clk48_ops = {
424 .prepare = stm32_usbphyc_clk48_prepare,
425 .unprepare = stm32_usbphyc_clk48_unprepare,
426 .recalc_rate = stm32_usbphyc_clk48_recalc_rate,
427 };
428
stm32_usbphyc_clk48_unregister(void * data)429 static void stm32_usbphyc_clk48_unregister(void *data)
430 {
431 struct stm32_usbphyc *usbphyc = data;
432
433 of_clk_del_provider(usbphyc->dev->of_node);
434 clk_hw_unregister(&usbphyc->clk48_hw);
435 }
436
stm32_usbphyc_clk48_register(struct stm32_usbphyc * usbphyc)437 static int stm32_usbphyc_clk48_register(struct stm32_usbphyc *usbphyc)
438 {
439 struct device_node *node = usbphyc->dev->of_node;
440 struct clk_init_data init = { };
441 int ret = 0;
442
443 init.name = "ck_usbo_48m";
444 init.ops = &usbphyc_clk48_ops;
445
446 usbphyc->clk48_hw.init = &init;
447
448 ret = clk_hw_register(usbphyc->dev, &usbphyc->clk48_hw);
449 if (ret)
450 return ret;
451
452 ret = of_clk_add_hw_provider(node, of_clk_hw_simple_get, &usbphyc->clk48_hw);
453 if (ret)
454 clk_hw_unregister(&usbphyc->clk48_hw);
455
456 return ret;
457 }
458
stm32_usbphyc_phy_tuning(struct stm32_usbphyc * usbphyc,struct device_node * np,u32 index)459 static void stm32_usbphyc_phy_tuning(struct stm32_usbphyc *usbphyc,
460 struct device_node *np, u32 index)
461 {
462 struct stm32_usbphyc_phy *usbphyc_phy = usbphyc->phys[index];
463 u32 reg = STM32_USBPHYC_TUNE(index);
464 u32 otpcomp, val;
465 int ret;
466
467 /* Backup OTP compensation code */
468 otpcomp = FIELD_GET(OTPCOMP, readl_relaxed(usbphyc->base + reg));
469
470 ret = of_property_read_u32(np, "st,current-boost-microamp", &val);
471 if (ret != -EINVAL) {
472 if (!ret && (val == BOOST_1000_UA || val == BOOST_2000_UA)) {
473 val = (val == BOOST_2000_UA) ? 1 : 0;
474 usbphyc_phy->tune |= INCURREN | FIELD_PREP(INCURRINT, val);
475 } else {
476 dev_warn(usbphyc->dev, "phy%d: invalid st,current-boost-microamp\n", index);
477 }
478 }
479
480 if (!of_property_read_bool(np, "st,no-lsfs-fb-cap"))
481 usbphyc_phy->tune |= LFSCAPEN;
482
483 if (of_property_read_bool(np, "st,decrease-hs-slew-rate"))
484 usbphyc_phy->tune |= HSDRVSLEW;
485
486 ret = of_property_read_u32(np, "st,tune-hs-dc-level", &val);
487 if (ret != -EINVAL) {
488 if (!ret && val < DC_MAX) {
489 if (val == DC_MINUS_5_TO_7_MV) {/* Decreases HS driver DC level */
490 usbphyc_phy->tune |= HSDRVDCCUR;
491 } else if (val > 0) { /* Increases HS driver DC level */
492 val = (val == DC_PLUS_10_TO_14_MV) ? 1 : 0;
493 usbphyc_phy->tune |= HSDRVCURINCR | FIELD_PREP(HSDRVDCLEV, val);
494 }
495 } else {
496 dev_warn(usbphyc->dev, "phy%d: invalid st,tune-hs-dc-level\n", index);
497 }
498 }
499
500 if (of_property_read_bool(np, "st,enable-fs-rftime-tuning"))
501 usbphyc_phy->tune |= FSDRVRFADJ;
502
503 if (of_property_read_bool(np, "st,enable-hs-rftime-reduction"))
504 usbphyc_phy->tune |= HSDRVRFRED;
505
506 ret = of_property_read_u32(np, "st,trim-hs-current", &val);
507 if (ret != -EINVAL) {
508 if (!ret && val < CUR_MAX)
509 usbphyc_phy->tune |= FIELD_PREP(HSDRVCHKITRM, val);
510 else
511 dev_warn(usbphyc->dev, "phy%d: invalid st,trim-hs-current\n", index);
512 }
513
514 ret = of_property_read_u32(np, "st,trim-hs-impedance", &val);
515 if (ret != -EINVAL) {
516 if (!ret && val < IMP_MAX)
517 usbphyc_phy->tune |= FIELD_PREP(HSDRVCHKZTRM, val);
518 else
519 dev_warn(usbphyc->dev, "phy%d: invalid st,trim-hs-impedance\n", index);
520 }
521
522 ret = of_property_read_u32(np, "st,tune-squelch-level", &val);
523 if (ret != -EINVAL) {
524 if (!ret && val < SQLCH_MAX)
525 usbphyc_phy->tune |= FIELD_PREP(SQLCHCTL, val);
526 else
527 dev_warn(usbphyc->dev, "phy%d: invalid st,tune-squelch\n", index);
528 }
529
530 if (of_property_read_bool(np, "st,enable-hs-rx-gain-eq"))
531 usbphyc_phy->tune |= HDRXGNEQEN;
532
533 ret = of_property_read_u32(np, "st,tune-hs-rx-offset", &val);
534 if (ret != -EINVAL) {
535 if (!ret && val < RX_OFFSET_MAX)
536 usbphyc_phy->tune |= FIELD_PREP(HSRXOFF, val);
537 else
538 dev_warn(usbphyc->dev, "phy%d: invalid st,tune-hs-rx-offset\n", index);
539 }
540
541 if (of_property_read_bool(np, "st,no-hs-ftime-ctrl"))
542 usbphyc_phy->tune |= HSFALLPREEM;
543
544 if (!of_property_read_bool(np, "st,no-lsfs-sc"))
545 usbphyc_phy->tune |= SHTCCTCTLPROT;
546
547 if (of_property_read_bool(np, "st,enable-hs-tx-staggering"))
548 usbphyc_phy->tune |= STAGSEL;
549
550 /* Restore OTP compensation code */
551 usbphyc_phy->tune |= FIELD_PREP(OTPCOMP, otpcomp);
552
553 /*
554 * By default, if no st,xxx tuning property is used, usbphyc_phy->tune is equal to
555 * STM32_USBPHYC_TUNE reset value (LFSCAPEN | SHTCCTCTLPROT | OTPCOMP).
556 */
557 writel_relaxed(usbphyc_phy->tune, usbphyc->base + reg);
558 }
559
stm32_usbphyc_switch_setup(struct stm32_usbphyc * usbphyc,u32 utmi_switch)560 static void stm32_usbphyc_switch_setup(struct stm32_usbphyc *usbphyc,
561 u32 utmi_switch)
562 {
563 if (!utmi_switch)
564 stm32_usbphyc_clr_bits(usbphyc->base + STM32_USBPHYC_MISC,
565 SWITHOST);
566 else
567 stm32_usbphyc_set_bits(usbphyc->base + STM32_USBPHYC_MISC,
568 SWITHOST);
569 usbphyc->switch_setup = utmi_switch;
570 }
571
stm32_usbphyc_of_xlate(struct device * dev,struct of_phandle_args * args)572 static struct phy *stm32_usbphyc_of_xlate(struct device *dev,
573 struct of_phandle_args *args)
574 {
575 struct stm32_usbphyc *usbphyc = dev_get_drvdata(dev);
576 struct stm32_usbphyc_phy *usbphyc_phy = NULL;
577 struct device_node *phynode = args->np;
578 int port = 0;
579
580 for (port = 0; port < usbphyc->nphys; port++) {
581 if (phynode == usbphyc->phys[port]->phy->dev.of_node) {
582 usbphyc_phy = usbphyc->phys[port];
583 break;
584 }
585 }
586 if (!usbphyc_phy) {
587 dev_err(dev, "failed to find phy\n");
588 return ERR_PTR(-EINVAL);
589 }
590
591 if (((usbphyc_phy->index == 0) && (args->args_count != 0)) ||
592 ((usbphyc_phy->index == 1) && (args->args_count != 1))) {
593 dev_err(dev, "invalid number of cells for phy port%d\n",
594 usbphyc_phy->index);
595 return ERR_PTR(-EINVAL);
596 }
597
598 /* Configure the UTMI switch for PHY port#2 */
599 if (usbphyc_phy->index == 1) {
600 if (usbphyc->switch_setup < 0) {
601 stm32_usbphyc_switch_setup(usbphyc, args->args[0]);
602 } else {
603 if (args->args[0] != usbphyc->switch_setup) {
604 dev_err(dev, "phy port1 already used\n");
605 return ERR_PTR(-EBUSY);
606 }
607 }
608 }
609
610 return usbphyc_phy->phy;
611 }
612
stm32_usbphyc_probe(struct platform_device * pdev)613 static int stm32_usbphyc_probe(struct platform_device *pdev)
614 {
615 struct stm32_usbphyc *usbphyc;
616 struct device *dev = &pdev->dev;
617 struct device_node *child, *np = dev->of_node;
618 struct phy_provider *phy_provider;
619 u32 pllen, version;
620 int ret, port = 0;
621
622 usbphyc = devm_kzalloc(dev, sizeof(*usbphyc), GFP_KERNEL);
623 if (!usbphyc)
624 return -ENOMEM;
625 usbphyc->dev = dev;
626 dev_set_drvdata(dev, usbphyc);
627
628 usbphyc->base = devm_platform_ioremap_resource(pdev, 0);
629 if (IS_ERR(usbphyc->base))
630 return PTR_ERR(usbphyc->base);
631
632 usbphyc->clk = devm_clk_get(dev, NULL);
633 if (IS_ERR(usbphyc->clk))
634 return dev_err_probe(dev, PTR_ERR(usbphyc->clk), "clk get_failed\n");
635
636 ret = clk_prepare_enable(usbphyc->clk);
637 if (ret) {
638 dev_err(dev, "clk enable failed: %d\n", ret);
639 return ret;
640 }
641
642 usbphyc->rst = devm_reset_control_get(dev, NULL);
643 if (!IS_ERR(usbphyc->rst)) {
644 reset_control_assert(usbphyc->rst);
645 udelay(2);
646 reset_control_deassert(usbphyc->rst);
647 } else {
648 ret = PTR_ERR(usbphyc->rst);
649 if (ret == -EPROBE_DEFER)
650 goto clk_disable;
651
652 stm32_usbphyc_clr_bits(usbphyc->base + STM32_USBPHYC_PLL, PLLEN);
653 }
654
655 /*
656 * Wait for minimum width of powerdown pulse (ENABLE = Low):
657 * we have to ensure the PLL is disabled before phys initialization.
658 */
659 if (readl_relaxed_poll_timeout(usbphyc->base + STM32_USBPHYC_PLL,
660 pllen, !(pllen & PLLEN), 5, 50)) {
661 dev_warn(usbphyc->dev, "PLL not reset\n");
662 ret = -EPROBE_DEFER;
663 goto clk_disable;
664 }
665
666 usbphyc->switch_setup = -EINVAL;
667 usbphyc->nphys = of_get_child_count(np);
668 usbphyc->phys = devm_kcalloc(dev, usbphyc->nphys,
669 sizeof(*usbphyc->phys), GFP_KERNEL);
670 if (!usbphyc->phys) {
671 ret = -ENOMEM;
672 goto clk_disable;
673 }
674
675 usbphyc->vdda1v1 = devm_regulator_get(dev, "vdda1v1");
676 if (IS_ERR(usbphyc->vdda1v1)) {
677 ret = dev_err_probe(dev, PTR_ERR(usbphyc->vdda1v1),
678 "failed to get vdda1v1 supply\n");
679 goto clk_disable;
680 }
681
682 usbphyc->vdda1v8 = devm_regulator_get(dev, "vdda1v8");
683 if (IS_ERR(usbphyc->vdda1v8)) {
684 ret = dev_err_probe(dev, PTR_ERR(usbphyc->vdda1v8),
685 "failed to get vdda1v8 supply\n");
686 goto clk_disable;
687 }
688
689 for_each_child_of_node(np, child) {
690 struct stm32_usbphyc_phy *usbphyc_phy;
691 struct phy *phy;
692 u32 index;
693
694 phy = devm_phy_create(dev, child, &stm32_usbphyc_phy_ops);
695 if (IS_ERR(phy)) {
696 ret = PTR_ERR(phy);
697 if (ret != -EPROBE_DEFER)
698 dev_err(dev, "failed to create phy%d: %d\n",
699 port, ret);
700 goto put_child;
701 }
702
703 usbphyc_phy = devm_kzalloc(dev, sizeof(*usbphyc_phy),
704 GFP_KERNEL);
705 if (!usbphyc_phy) {
706 ret = -ENOMEM;
707 goto put_child;
708 }
709
710 ret = of_property_read_u32(child, "reg", &index);
711 if (ret || index > usbphyc->nphys) {
712 dev_err(&phy->dev, "invalid reg property: %d\n", ret);
713 if (!ret)
714 ret = -EINVAL;
715 goto put_child;
716 }
717
718 usbphyc->phys[port] = usbphyc_phy;
719 phy_set_bus_width(phy, 8);
720 phy_set_drvdata(phy, usbphyc_phy);
721
722 usbphyc->phys[port]->phy = phy;
723 usbphyc->phys[port]->usbphyc = usbphyc;
724 usbphyc->phys[port]->index = index;
725 usbphyc->phys[port]->active = false;
726
727 usbphyc->phys[port]->vbus = devm_regulator_get_optional(&phy->dev, "vbus");
728 if (IS_ERR(usbphyc->phys[port]->vbus)) {
729 ret = PTR_ERR(usbphyc->phys[port]->vbus);
730 if (ret == -EPROBE_DEFER)
731 goto put_child;
732 usbphyc->phys[port]->vbus = NULL;
733 }
734
735 /* Configure phy tuning */
736 stm32_usbphyc_phy_tuning(usbphyc, child, index);
737
738 port++;
739 }
740
741 phy_provider = devm_of_phy_provider_register(dev,
742 stm32_usbphyc_of_xlate);
743 if (IS_ERR(phy_provider)) {
744 ret = PTR_ERR(phy_provider);
745 dev_err(dev, "failed to register phy provider: %d\n", ret);
746 goto clk_disable;
747 }
748
749 ret = stm32_usbphyc_clk48_register(usbphyc);
750 if (ret) {
751 dev_err(dev, "failed to register ck_usbo_48m clock: %d\n", ret);
752 goto clk_disable;
753 }
754
755 version = readl_relaxed(usbphyc->base + STM32_USBPHYC_VERSION);
756 dev_info(dev, "registered rev:%lu.%lu\n",
757 FIELD_GET(MAJREV, version), FIELD_GET(MINREV, version));
758
759 return 0;
760
761 put_child:
762 of_node_put(child);
763 clk_disable:
764 clk_disable_unprepare(usbphyc->clk);
765
766 return ret;
767 }
768
stm32_usbphyc_remove(struct platform_device * pdev)769 static int stm32_usbphyc_remove(struct platform_device *pdev)
770 {
771 struct stm32_usbphyc *usbphyc = dev_get_drvdata(&pdev->dev);
772 int port;
773
774 /* Ensure PHYs are not active, to allow PLL disabling */
775 for (port = 0; port < usbphyc->nphys; port++)
776 if (usbphyc->phys[port]->active)
777 stm32_usbphyc_phy_exit(usbphyc->phys[port]->phy);
778
779 stm32_usbphyc_clk48_unregister(usbphyc);
780
781 clk_disable_unprepare(usbphyc->clk);
782
783 return 0;
784 }
785
stm32_usbphyc_resume(struct device * dev)786 static int __maybe_unused stm32_usbphyc_resume(struct device *dev)
787 {
788 struct stm32_usbphyc *usbphyc = dev_get_drvdata(dev);
789 struct stm32_usbphyc_phy *usbphyc_phy;
790 int port;
791
792 if (usbphyc->switch_setup >= 0)
793 stm32_usbphyc_switch_setup(usbphyc, usbphyc->switch_setup);
794
795 for (port = 0; port < usbphyc->nphys; port++) {
796 usbphyc_phy = usbphyc->phys[port];
797 writel_relaxed(usbphyc_phy->tune, usbphyc->base + STM32_USBPHYC_TUNE(port));
798 }
799
800 return 0;
801 }
802
803 static SIMPLE_DEV_PM_OPS(stm32_usbphyc_pm_ops, NULL, stm32_usbphyc_resume);
804
805 static const struct of_device_id stm32_usbphyc_of_match[] = {
806 { .compatible = "st,stm32mp1-usbphyc", },
807 { },
808 };
809 MODULE_DEVICE_TABLE(of, stm32_usbphyc_of_match);
810
811 static struct platform_driver stm32_usbphyc_driver = {
812 .probe = stm32_usbphyc_probe,
813 .remove = stm32_usbphyc_remove,
814 .driver = {
815 .of_match_table = stm32_usbphyc_of_match,
816 .name = "stm32-usbphyc",
817 .pm = &stm32_usbphyc_pm_ops,
818 }
819 };
820 module_platform_driver(stm32_usbphyc_driver);
821
822 MODULE_DESCRIPTION("STMicroelectronics STM32 USBPHYC driver");
823 MODULE_AUTHOR("Amelie Delaunay <amelie.delaunay@st.com>");
824 MODULE_LICENSE("GPL v2");
825