1 // SPDX-License-Identifier: GPL-2.0 2 3 /* Copyright (C) 2021 Linaro Ltd. */ 4 5 #include <linux/log2.h> 6 7 #include "../gsi.h" 8 #include "../ipa_data.h" 9 #include "../ipa_endpoint.h" 10 #include "../ipa_mem.h" 11 12 /** enum ipa_resource_type - IPA resource types for an SoC having IPA v4.11 */ 13 enum ipa_resource_type { 14 /* Source resource types; first must have value 0 */ 15 IPA_RESOURCE_TYPE_SRC_PKT_CONTEXTS = 0, 16 IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_LISTS, 17 IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_BUFF, 18 IPA_RESOURCE_TYPE_SRC_HPS_DMARS, 19 IPA_RESOURCE_TYPE_SRC_ACK_ENTRIES, 20 21 /* Destination resource types; first must have value 0 */ 22 IPA_RESOURCE_TYPE_DST_DATA_SECTORS = 0, 23 IPA_RESOURCE_TYPE_DST_DPS_DMARS, 24 }; 25 26 /* Resource groups used for an SoC having IPA v4.11 */ 27 enum ipa_rsrc_group_id { 28 /* Source resource group identifiers */ 29 IPA_RSRC_GROUP_SRC_UL_DL = 0, 30 IPA_RSRC_GROUP_SRC_UC_RX_Q, 31 IPA_RSRC_GROUP_SRC_UNUSED_2, 32 IPA_RSRC_GROUP_SRC_COUNT, /* Last in set; not a source group */ 33 34 /* Destination resource group identifiers */ 35 IPA_RSRC_GROUP_DST_UL_DL_DPL = 0, 36 IPA_RSRC_GROUP_DST_UNUSED_1, 37 IPA_RSRC_GROUP_DST_DRB_IP, 38 IPA_RSRC_GROUP_DST_COUNT, /* Last; not a destination group */ 39 }; 40 41 /* QSB configuration data for an SoC having IPA v4.11 */ 42 static const struct ipa_qsb_data ipa_qsb_data[] = { 43 [IPA_QSB_MASTER_DDR] = { 44 .max_writes = 12, 45 .max_reads = 13, 46 .max_reads_beats = 120, 47 }, 48 }; 49 50 /* Endpoint configuration data for an SoC having IPA v4.11 */ 51 static const struct ipa_gsi_endpoint_data ipa_gsi_endpoint_data[] = { 52 [IPA_ENDPOINT_AP_COMMAND_TX] = { 53 .ee_id = GSI_EE_AP, 54 .channel_id = 5, 55 .endpoint_id = 7, 56 .toward_ipa = true, 57 .channel = { 58 .tre_count = 256, 59 .event_count = 256, 60 .tlv_count = 20, 61 }, 62 .endpoint = { 63 .config = { 64 .resource_group = IPA_RSRC_GROUP_SRC_UL_DL, 65 .dma_mode = true, 66 .dma_endpoint = IPA_ENDPOINT_AP_LAN_RX, 67 .tx = { 68 .seq_type = IPA_SEQ_DMA, 69 }, 70 }, 71 }, 72 }, 73 [IPA_ENDPOINT_AP_LAN_RX] = { 74 .ee_id = GSI_EE_AP, 75 .channel_id = 14, 76 .endpoint_id = 9, 77 .toward_ipa = false, 78 .channel = { 79 .tre_count = 256, 80 .event_count = 256, 81 .tlv_count = 9, 82 }, 83 .endpoint = { 84 .config = { 85 .resource_group = IPA_RSRC_GROUP_DST_UL_DL_DPL, 86 .aggregation = true, 87 .status_enable = true, 88 .rx = { 89 .buffer_size = 8192, 90 .pad_align = ilog2(sizeof(u32)), 91 .aggr_time_limit = 500, 92 }, 93 }, 94 }, 95 }, 96 [IPA_ENDPOINT_AP_MODEM_TX] = { 97 .ee_id = GSI_EE_AP, 98 .channel_id = 2, 99 .endpoint_id = 2, 100 .toward_ipa = true, 101 .channel = { 102 .tre_count = 512, 103 .event_count = 512, 104 .tlv_count = 16, 105 }, 106 .endpoint = { 107 .filter_support = true, 108 .config = { 109 .resource_group = IPA_RSRC_GROUP_SRC_UL_DL, 110 .checksum = true, 111 .qmap = true, 112 .status_enable = true, 113 .tx = { 114 .seq_type = IPA_SEQ_2_PASS_SKIP_LAST_UC, 115 .status_endpoint = 116 IPA_ENDPOINT_MODEM_AP_RX, 117 }, 118 }, 119 }, 120 }, 121 [IPA_ENDPOINT_AP_MODEM_RX] = { 122 .ee_id = GSI_EE_AP, 123 .channel_id = 7, 124 .endpoint_id = 16, 125 .toward_ipa = false, 126 .channel = { 127 .tre_count = 256, 128 .event_count = 256, 129 .tlv_count = 9, 130 }, 131 .endpoint = { 132 .config = { 133 .resource_group = IPA_RSRC_GROUP_DST_UL_DL_DPL, 134 .checksum = true, 135 .qmap = true, 136 .aggregation = true, 137 .rx = { 138 .buffer_size = 32768, 139 .aggr_time_limit = 500, 140 .aggr_close_eof = true, 141 }, 142 }, 143 }, 144 }, 145 [IPA_ENDPOINT_MODEM_AP_TX] = { 146 .ee_id = GSI_EE_MODEM, 147 .channel_id = 0, 148 .endpoint_id = 5, 149 .toward_ipa = true, 150 .endpoint = { 151 .filter_support = true, 152 }, 153 }, 154 [IPA_ENDPOINT_MODEM_AP_RX] = { 155 .ee_id = GSI_EE_MODEM, 156 .channel_id = 7, 157 .endpoint_id = 14, 158 .toward_ipa = false, 159 }, 160 [IPA_ENDPOINT_MODEM_DL_NLO_TX] = { 161 .ee_id = GSI_EE_MODEM, 162 .channel_id = 2, 163 .endpoint_id = 8, 164 .toward_ipa = true, 165 .endpoint = { 166 .filter_support = true, 167 }, 168 }, 169 }; 170 171 /* Source resource configuration data for an SoC having IPA v4.11 */ 172 static const struct ipa_resource ipa_resource_src[] = { 173 [IPA_RESOURCE_TYPE_SRC_PKT_CONTEXTS] = { 174 .limits[IPA_RSRC_GROUP_SRC_UL_DL] = { 175 .min = 6, .max = 6, 176 }, 177 }, 178 [IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_LISTS] = { 179 .limits[IPA_RSRC_GROUP_SRC_UL_DL] = { 180 .min = 8, .max = 8, 181 }, 182 }, 183 [IPA_RESOURCE_TYPE_SRC_DESCRIPTOR_BUFF] = { 184 .limits[IPA_RSRC_GROUP_SRC_UL_DL] = { 185 .min = 18, .max = 18, 186 }, 187 }, 188 [IPA_RESOURCE_TYPE_SRC_HPS_DMARS] = { 189 .limits[IPA_RSRC_GROUP_SRC_UL_DL] = { 190 .min = 2, .max = 2, 191 }, 192 }, 193 [IPA_RESOURCE_TYPE_SRC_ACK_ENTRIES] = { 194 .limits[IPA_RSRC_GROUP_SRC_UL_DL] = { 195 .min = 15, .max = 15, 196 }, 197 }, 198 }; 199 200 /* Destination resource configuration data for an SoC having IPA v4.11 */ 201 static const struct ipa_resource ipa_resource_dst[] = { 202 [IPA_RESOURCE_TYPE_DST_DATA_SECTORS] = { 203 .limits[IPA_RSRC_GROUP_DST_UL_DL_DPL] = { 204 .min = 3, .max = 3, 205 }, 206 .limits[IPA_RSRC_GROUP_DST_DRB_IP] = { 207 .min = 25, .max = 25, 208 }, 209 }, 210 [IPA_RESOURCE_TYPE_DST_DPS_DMARS] = { 211 .limits[IPA_RSRC_GROUP_DST_UL_DL_DPL] = { 212 .min = 2, .max = 2, 213 }, 214 }, 215 }; 216 217 /* Resource configuration data for an SoC having IPA v4.11 */ 218 static const struct ipa_resource_data ipa_resource_data = { 219 .rsrc_group_src_count = IPA_RSRC_GROUP_SRC_COUNT, 220 .rsrc_group_dst_count = IPA_RSRC_GROUP_DST_COUNT, 221 .resource_src_count = ARRAY_SIZE(ipa_resource_src), 222 .resource_src = ipa_resource_src, 223 .resource_dst_count = ARRAY_SIZE(ipa_resource_dst), 224 .resource_dst = ipa_resource_dst, 225 }; 226 227 /* IPA-resident memory region data for an SoC having IPA v4.11 */ 228 static const struct ipa_mem ipa_mem_local_data[] = { 229 { 230 .id = IPA_MEM_UC_SHARED, 231 .offset = 0x0000, 232 .size = 0x0080, 233 .canary_count = 0, 234 }, 235 { 236 .id = IPA_MEM_UC_INFO, 237 .offset = 0x0080, 238 .size = 0x0200, 239 .canary_count = 0, 240 }, 241 { 242 .id = IPA_MEM_V4_FILTER_HASHED, 243 .offset = 0x0288, 244 .size = 0x0078, 245 .canary_count = 2, 246 }, 247 { 248 .id = IPA_MEM_V4_FILTER, 249 .offset = 0x0308, 250 .size = 0x0078, 251 .canary_count = 2, 252 }, 253 { 254 .id = IPA_MEM_V6_FILTER_HASHED, 255 .offset = 0x0388, 256 .size = 0x0078, 257 .canary_count = 2, 258 }, 259 { 260 .id = IPA_MEM_V6_FILTER, 261 .offset = 0x0408, 262 .size = 0x0078, 263 .canary_count = 2, 264 }, 265 { 266 .id = IPA_MEM_V4_ROUTE_HASHED, 267 .offset = 0x0488, 268 .size = 0x0078, 269 .canary_count = 2, 270 }, 271 { 272 .id = IPA_MEM_V4_ROUTE, 273 .offset = 0x0508, 274 .size = 0x0078, 275 .canary_count = 2, 276 }, 277 { 278 .id = IPA_MEM_V6_ROUTE_HASHED, 279 .offset = 0x0588, 280 .size = 0x0078, 281 .canary_count = 2, 282 }, 283 { 284 .id = IPA_MEM_V6_ROUTE, 285 .offset = 0x0608, 286 .size = 0x0078, 287 .canary_count = 2, 288 }, 289 { 290 .id = IPA_MEM_MODEM_HEADER, 291 .offset = 0x0688, 292 .size = 0x0240, 293 .canary_count = 2, 294 }, 295 { 296 .id = IPA_MEM_AP_HEADER, 297 .offset = 0x08c8, 298 .size = 0x0200, 299 .canary_count = 0, 300 }, 301 { 302 .id = IPA_MEM_MODEM_PROC_CTX, 303 .offset = 0x0ad0, 304 .size = 0x0200, 305 .canary_count = 2, 306 }, 307 { 308 .id = IPA_MEM_AP_PROC_CTX, 309 .offset = 0x0cd0, 310 .size = 0x0200, 311 .canary_count = 0, 312 }, 313 { 314 .id = IPA_MEM_NAT_TABLE, 315 .offset = 0x0ee0, 316 .size = 0x0d00, 317 .canary_count = 4, 318 }, 319 { 320 .id = IPA_MEM_PDN_CONFIG, 321 .offset = 0x1be8, 322 .size = 0x0050, 323 .canary_count = 0, 324 }, 325 { 326 .id = IPA_MEM_STATS_QUOTA_MODEM, 327 .offset = 0x1c40, 328 .size = 0x0030, 329 .canary_count = 4, 330 }, 331 { 332 .id = IPA_MEM_STATS_QUOTA_AP, 333 .offset = 0x1c70, 334 .size = 0x0048, 335 .canary_count = 0, 336 }, 337 { 338 .id = IPA_MEM_STATS_TETHERING, 339 .offset = 0x1cb8, 340 .size = 0x0238, 341 .canary_count = 0, 342 }, 343 { 344 .id = IPA_MEM_STATS_DROP, 345 .offset = 0x1ef0, 346 .size = 0x0020, 347 .canary_count = 0, 348 }, 349 { 350 .id = IPA_MEM_MODEM, 351 .offset = 0x1f18, 352 .size = 0x100c, 353 .canary_count = 2, 354 }, 355 { 356 .id = IPA_MEM_END_MARKER, 357 .offset = 0x3000, 358 .size = 0x0000, 359 .canary_count = 1, 360 }, 361 }; 362 363 /* Memory configuration data for an SoC having IPA v4.11 */ 364 static const struct ipa_mem_data ipa_mem_data = { 365 .local_count = ARRAY_SIZE(ipa_mem_local_data), 366 .local = ipa_mem_local_data, 367 .imem_addr = 0x146a8000, 368 .imem_size = 0x00002000, 369 .smem_id = 497, 370 .smem_size = 0x00009000, 371 }; 372 373 /* Interconnect rates are in 1000 byte/second units */ 374 static const struct ipa_interconnect_data ipa_interconnect_data[] = { 375 { 376 .name = "memory", 377 .peak_bandwidth = 600000, /* 600 MBps */ 378 .average_bandwidth = 150000, /* 150 MBps */ 379 }, 380 /* Average rate is unused for the next interconnect */ 381 { 382 .name = "config", 383 .peak_bandwidth = 74000, /* 74 MBps */ 384 .average_bandwidth = 0, /* unused */ 385 }, 386 }; 387 388 /* Clock and interconnect configuration data for an SoC having IPA v4.11 */ 389 static const struct ipa_power_data ipa_power_data = { 390 .core_clock_rate = 60 * 1000 * 1000, /* Hz */ 391 .interconnect_count = ARRAY_SIZE(ipa_interconnect_data), 392 .interconnect_data = ipa_interconnect_data, 393 }; 394 395 /* Configuration data for an SoC having IPA v4.11 */ 396 const struct ipa_data ipa_data_v4_11 = { 397 .version = IPA_VERSION_4_11, 398 .qsb_count = ARRAY_SIZE(ipa_qsb_data), 399 .qsb_data = ipa_qsb_data, 400 .endpoint_count = ARRAY_SIZE(ipa_gsi_endpoint_data), 401 .endpoint_data = ipa_gsi_endpoint_data, 402 .resource_data = &ipa_resource_data, 403 .mem_data = &ipa_mem_data, 404 .power_data = &ipa_power_data, 405 }; 406