1 /* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 */
2 /* Copyright (c) 2016-2018 Mellanox Technologies. All rights reserved */
3 
4 #ifndef _MLXSW_RESOURCES_H
5 #define _MLXSW_RESOURCES_H
6 
7 #include <linux/kernel.h>
8 #include <linux/types.h>
9 
10 enum mlxsw_res_id {
11 	MLXSW_RES_ID_KVD_SIZE,
12 	MLXSW_RES_ID_KVD_SINGLE_MIN_SIZE,
13 	MLXSW_RES_ID_KVD_DOUBLE_MIN_SIZE,
14 	MLXSW_RES_ID_PGT_SIZE,
15 	MLXSW_RES_ID_MAX_KVD_LINEAR_RANGE,
16 	MLXSW_RES_ID_MAX_KVD_ACTION_SETS,
17 	MLXSW_RES_ID_MAX_TRAP_GROUPS,
18 	MLXSW_RES_ID_CQE_V0,
19 	MLXSW_RES_ID_CQE_V1,
20 	MLXSW_RES_ID_CQE_V2,
21 	MLXSW_RES_ID_COUNTER_POOL_SIZE,
22 	MLXSW_RES_ID_COUNTER_BANK_SIZE,
23 	MLXSW_RES_ID_MAX_SPAN,
24 	MLXSW_RES_ID_COUNTER_SIZE_PACKETS_BYTES,
25 	MLXSW_RES_ID_COUNTER_SIZE_ROUTER_BASIC,
26 	MLXSW_RES_ID_MAX_SYSTEM_PORT,
27 	MLXSW_RES_ID_FID,
28 	MLXSW_RES_ID_MAX_LAG,
29 	MLXSW_RES_ID_MAX_LAG_MEMBERS,
30 	MLXSW_RES_ID_GUARANTEED_SHARED_BUFFER,
31 	MLXSW_RES_ID_CELL_SIZE,
32 	MLXSW_RES_ID_MAX_HEADROOM_SIZE,
33 	MLXSW_RES_ID_ACL_MAX_TCAM_REGIONS,
34 	MLXSW_RES_ID_ACL_MAX_TCAM_RULES,
35 	MLXSW_RES_ID_ACL_MAX_REGIONS,
36 	MLXSW_RES_ID_ACL_MAX_GROUPS,
37 	MLXSW_RES_ID_ACL_MAX_GROUP_SIZE,
38 	MLXSW_RES_ID_ACL_MAX_DEFAULT_ACTIONS,
39 	MLXSW_RES_ID_ACL_FLEX_KEYS,
40 	MLXSW_RES_ID_ACL_MAX_ACTION_PER_RULE,
41 	MLXSW_RES_ID_ACL_ACTIONS_PER_SET,
42 	MLXSW_RES_ID_ACL_MAX_ERPT_BANKS,
43 	MLXSW_RES_ID_ACL_MAX_ERPT_BANK_SIZE,
44 	MLXSW_RES_ID_ACL_MAX_LARGE_KEY_ID,
45 	MLXSW_RES_ID_ACL_ERPT_ENTRIES_2KB,
46 	MLXSW_RES_ID_ACL_ERPT_ENTRIES_4KB,
47 	MLXSW_RES_ID_ACL_ERPT_ENTRIES_8KB,
48 	MLXSW_RES_ID_ACL_ERPT_ENTRIES_12KB,
49 	MLXSW_RES_ID_ACL_MAX_BF_LOG,
50 	MLXSW_RES_ID_MAX_GLOBAL_POLICERS,
51 	MLXSW_RES_ID_MAX_CPU_POLICERS,
52 	MLXSW_RES_ID_MAX_VRS,
53 	MLXSW_RES_ID_MAX_RIFS,
54 	MLXSW_RES_ID_MC_ERIF_LIST_ENTRIES,
55 	MLXSW_RES_ID_MAX_RIF_MAC_PROFILES,
56 	MLXSW_RES_ID_MAX_LPM_TREES,
57 	MLXSW_RES_ID_MAX_NVE_MC_ENTRIES_IPV4,
58 	MLXSW_RES_ID_MAX_NVE_MC_ENTRIES_IPV6,
59 
60 	/* Internal resources.
61 	 * Determined by the SW, not queried from the HW.
62 	 */
63 	MLXSW_RES_ID_KVD_SINGLE_SIZE,
64 	MLXSW_RES_ID_KVD_DOUBLE_SIZE,
65 	MLXSW_RES_ID_KVD_LINEAR_SIZE,
66 
67 	__MLXSW_RES_ID_MAX,
68 };
69 
70 static u16 mlxsw_res_ids[] = {
71 	[MLXSW_RES_ID_KVD_SIZE] = 0x1001,
72 	[MLXSW_RES_ID_KVD_SINGLE_MIN_SIZE] = 0x1002,
73 	[MLXSW_RES_ID_KVD_DOUBLE_MIN_SIZE] = 0x1003,
74 	[MLXSW_RES_ID_PGT_SIZE] = 0x1004,
75 	[MLXSW_RES_ID_MAX_KVD_LINEAR_RANGE] = 0x1005,
76 	[MLXSW_RES_ID_MAX_KVD_ACTION_SETS] = 0x1007,
77 	[MLXSW_RES_ID_MAX_TRAP_GROUPS] = 0x2201,
78 	[MLXSW_RES_ID_CQE_V0] = 0x2210,
79 	[MLXSW_RES_ID_CQE_V1] = 0x2211,
80 	[MLXSW_RES_ID_CQE_V2] = 0x2212,
81 	[MLXSW_RES_ID_COUNTER_POOL_SIZE] = 0x2410,
82 	[MLXSW_RES_ID_COUNTER_BANK_SIZE] = 0x2411,
83 	[MLXSW_RES_ID_MAX_SPAN] = 0x2420,
84 	[MLXSW_RES_ID_COUNTER_SIZE_PACKETS_BYTES] = 0x2443,
85 	[MLXSW_RES_ID_COUNTER_SIZE_ROUTER_BASIC] = 0x2449,
86 	[MLXSW_RES_ID_MAX_SYSTEM_PORT] = 0x2502,
87 	[MLXSW_RES_ID_FID] = 0x2512,
88 	[MLXSW_RES_ID_MAX_LAG] = 0x2520,
89 	[MLXSW_RES_ID_MAX_LAG_MEMBERS] = 0x2521,
90 	[MLXSW_RES_ID_GUARANTEED_SHARED_BUFFER] = 0x2805,	/* Bytes */
91 	[MLXSW_RES_ID_CELL_SIZE] = 0x2803,	/* Bytes */
92 	[MLXSW_RES_ID_MAX_HEADROOM_SIZE] = 0x2811,	/* Bytes */
93 	[MLXSW_RES_ID_ACL_MAX_TCAM_REGIONS] = 0x2901,
94 	[MLXSW_RES_ID_ACL_MAX_TCAM_RULES] = 0x2902,
95 	[MLXSW_RES_ID_ACL_MAX_REGIONS] = 0x2903,
96 	[MLXSW_RES_ID_ACL_MAX_GROUPS] = 0x2904,
97 	[MLXSW_RES_ID_ACL_MAX_GROUP_SIZE] = 0x2905,
98 	[MLXSW_RES_ID_ACL_MAX_DEFAULT_ACTIONS] = 0x2908,
99 	[MLXSW_RES_ID_ACL_FLEX_KEYS] = 0x2910,
100 	[MLXSW_RES_ID_ACL_MAX_ACTION_PER_RULE] = 0x2911,
101 	[MLXSW_RES_ID_ACL_ACTIONS_PER_SET] = 0x2912,
102 	[MLXSW_RES_ID_ACL_MAX_ERPT_BANKS] = 0x2940,
103 	[MLXSW_RES_ID_ACL_MAX_ERPT_BANK_SIZE] = 0x2941,
104 	[MLXSW_RES_ID_ACL_MAX_LARGE_KEY_ID] = 0x2942,
105 	[MLXSW_RES_ID_ACL_ERPT_ENTRIES_2KB] = 0x2950,
106 	[MLXSW_RES_ID_ACL_ERPT_ENTRIES_4KB] = 0x2951,
107 	[MLXSW_RES_ID_ACL_ERPT_ENTRIES_8KB] = 0x2952,
108 	[MLXSW_RES_ID_ACL_ERPT_ENTRIES_12KB] = 0x2953,
109 	[MLXSW_RES_ID_ACL_MAX_BF_LOG] = 0x2960,
110 	[MLXSW_RES_ID_MAX_GLOBAL_POLICERS] = 0x2A10,
111 	[MLXSW_RES_ID_MAX_CPU_POLICERS] = 0x2A13,
112 	[MLXSW_RES_ID_MAX_VRS] = 0x2C01,
113 	[MLXSW_RES_ID_MAX_RIFS] = 0x2C02,
114 	[MLXSW_RES_ID_MC_ERIF_LIST_ENTRIES] = 0x2C10,
115 	[MLXSW_RES_ID_MAX_RIF_MAC_PROFILES] = 0x2C14,
116 	[MLXSW_RES_ID_MAX_LPM_TREES] = 0x2C30,
117 	[MLXSW_RES_ID_MAX_NVE_MC_ENTRIES_IPV4] = 0x2E02,
118 	[MLXSW_RES_ID_MAX_NVE_MC_ENTRIES_IPV6] = 0x2E03,
119 };
120 
121 struct mlxsw_res {
122 	bool valid[__MLXSW_RES_ID_MAX];
123 	u64 values[__MLXSW_RES_ID_MAX];
124 };
125 
mlxsw_res_valid(struct mlxsw_res * res,enum mlxsw_res_id res_id)126 static inline bool mlxsw_res_valid(struct mlxsw_res *res,
127 				   enum mlxsw_res_id res_id)
128 {
129 	return res->valid[res_id];
130 }
131 
132 #define MLXSW_RES_VALID(res, short_res_id)			\
133 	mlxsw_res_valid(res, MLXSW_RES_ID_##short_res_id)
134 
mlxsw_res_get(struct mlxsw_res * res,enum mlxsw_res_id res_id)135 static inline u64 mlxsw_res_get(struct mlxsw_res *res,
136 				enum mlxsw_res_id res_id)
137 {
138 	if (WARN_ON(!res->valid[res_id]))
139 		return 0;
140 	return res->values[res_id];
141 }
142 
143 #define MLXSW_RES_GET(res, short_res_id)			\
144 	mlxsw_res_get(res, MLXSW_RES_ID_##short_res_id)
145 
mlxsw_res_set(struct mlxsw_res * res,enum mlxsw_res_id res_id,u64 value)146 static inline void mlxsw_res_set(struct mlxsw_res *res,
147 				 enum mlxsw_res_id res_id, u64 value)
148 {
149 	res->valid[res_id] = true;
150 	res->values[res_id] = value;
151 }
152 
153 #define MLXSW_RES_SET(res, short_res_id, value)			\
154 	mlxsw_res_set(res, MLXSW_RES_ID_##short_res_id, value)
155 
mlxsw_res_parse(struct mlxsw_res * res,u16 id,u64 value)156 static inline void mlxsw_res_parse(struct mlxsw_res *res, u16 id, u64 value)
157 {
158 	int i;
159 
160 	for (i = 0; i < ARRAY_SIZE(mlxsw_res_ids); i++) {
161 		if (mlxsw_res_ids[i] == id) {
162 			mlxsw_res_set(res, i, value);
163 			return;
164 		}
165 	}
166 }
167 
168 #endif
169