1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
4  * Author: Joerg Roedel <jroedel@suse.de>
5  *         Leo Duran <leo.duran@amd.com>
6  */
7 
8 #define pr_fmt(fmt)     "AMD-Vi: " fmt
9 #define dev_fmt(fmt)    pr_fmt(fmt)
10 
11 #include <linux/ratelimit.h>
12 #include <linux/pci.h>
13 #include <linux/acpi.h>
14 #include <linux/pci-ats.h>
15 #include <linux/bitmap.h>
16 #include <linux/slab.h>
17 #include <linux/debugfs.h>
18 #include <linux/scatterlist.h>
19 #include <linux/dma-map-ops.h>
20 #include <linux/dma-direct.h>
21 #include <linux/iommu-helper.h>
22 #include <linux/delay.h>
23 #include <linux/amd-iommu.h>
24 #include <linux/notifier.h>
25 #include <linux/export.h>
26 #include <linux/irq.h>
27 #include <linux/msi.h>
28 #include <linux/irqdomain.h>
29 #include <linux/percpu.h>
30 #include <linux/io-pgtable.h>
31 #include <linux/cc_platform.h>
32 #include <asm/irq_remapping.h>
33 #include <asm/io_apic.h>
34 #include <asm/apic.h>
35 #include <asm/hw_irq.h>
36 #include <asm/proto.h>
37 #include <asm/iommu.h>
38 #include <asm/gart.h>
39 #include <asm/dma.h>
40 
41 #include "amd_iommu.h"
42 #include "../dma-iommu.h"
43 #include "../irq_remapping.h"
44 
45 #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28))
46 
47 #define LOOP_TIMEOUT	100000
48 
49 /* IO virtual address start page frame number */
50 #define IOVA_START_PFN		(1)
51 #define IOVA_PFN(addr)		((addr) >> PAGE_SHIFT)
52 
53 /* Reserved IOVA ranges */
54 #define MSI_RANGE_START		(0xfee00000)
55 #define MSI_RANGE_END		(0xfeefffff)
56 #define HT_RANGE_START		(0xfd00000000ULL)
57 #define HT_RANGE_END		(0xffffffffffULL)
58 
59 #define DEFAULT_PGTABLE_LEVEL	PAGE_MODE_3_LEVEL
60 
61 static DEFINE_SPINLOCK(pd_bitmap_lock);
62 
63 LIST_HEAD(ioapic_map);
64 LIST_HEAD(hpet_map);
65 LIST_HEAD(acpihid_map);
66 
67 const struct iommu_ops amd_iommu_ops;
68 
69 static ATOMIC_NOTIFIER_HEAD(ppr_notifier);
70 int amd_iommu_max_glx_val = -1;
71 
72 /*
73  * general struct to manage commands send to an IOMMU
74  */
75 struct iommu_cmd {
76 	u32 data[4];
77 };
78 
79 struct kmem_cache *amd_iommu_irq_cache;
80 
81 static void detach_device(struct device *dev);
82 static int domain_enable_v2(struct protection_domain *domain, int pasids);
83 
84 /****************************************************************************
85  *
86  * Helper functions
87  *
88  ****************************************************************************/
89 
get_acpihid_device_id(struct device * dev,struct acpihid_map_entry ** entry)90 static inline int get_acpihid_device_id(struct device *dev,
91 					struct acpihid_map_entry **entry)
92 {
93 	struct acpi_device *adev = ACPI_COMPANION(dev);
94 	struct acpihid_map_entry *p;
95 
96 	if (!adev)
97 		return -ENODEV;
98 
99 	list_for_each_entry(p, &acpihid_map, list) {
100 		if (acpi_dev_hid_uid_match(adev, p->hid,
101 					   p->uid[0] ? p->uid : NULL)) {
102 			if (entry)
103 				*entry = p;
104 			return p->devid;
105 		}
106 	}
107 	return -EINVAL;
108 }
109 
get_device_sbdf_id(struct device * dev)110 static inline int get_device_sbdf_id(struct device *dev)
111 {
112 	int sbdf;
113 
114 	if (dev_is_pci(dev))
115 		sbdf = get_pci_sbdf_id(to_pci_dev(dev));
116 	else
117 		sbdf = get_acpihid_device_id(dev, NULL);
118 
119 	return sbdf;
120 }
121 
get_dev_table(struct amd_iommu * iommu)122 struct dev_table_entry *get_dev_table(struct amd_iommu *iommu)
123 {
124 	struct dev_table_entry *dev_table;
125 	struct amd_iommu_pci_seg *pci_seg = iommu->pci_seg;
126 
127 	BUG_ON(pci_seg == NULL);
128 	dev_table = pci_seg->dev_table;
129 	BUG_ON(dev_table == NULL);
130 
131 	return dev_table;
132 }
133 
get_device_segment(struct device * dev)134 static inline u16 get_device_segment(struct device *dev)
135 {
136 	u16 seg;
137 
138 	if (dev_is_pci(dev)) {
139 		struct pci_dev *pdev = to_pci_dev(dev);
140 
141 		seg = pci_domain_nr(pdev->bus);
142 	} else {
143 		u32 devid = get_acpihid_device_id(dev, NULL);
144 
145 		seg = PCI_SBDF_TO_SEGID(devid);
146 	}
147 
148 	return seg;
149 }
150 
151 /* Writes the specific IOMMU for a device into the PCI segment rlookup table */
amd_iommu_set_rlookup_table(struct amd_iommu * iommu,u16 devid)152 void amd_iommu_set_rlookup_table(struct amd_iommu *iommu, u16 devid)
153 {
154 	struct amd_iommu_pci_seg *pci_seg = iommu->pci_seg;
155 
156 	pci_seg->rlookup_table[devid] = iommu;
157 }
158 
__rlookup_amd_iommu(u16 seg,u16 devid)159 static struct amd_iommu *__rlookup_amd_iommu(u16 seg, u16 devid)
160 {
161 	struct amd_iommu_pci_seg *pci_seg;
162 
163 	for_each_pci_segment(pci_seg) {
164 		if (pci_seg->id == seg)
165 			return pci_seg->rlookup_table[devid];
166 	}
167 	return NULL;
168 }
169 
rlookup_amd_iommu(struct device * dev)170 static struct amd_iommu *rlookup_amd_iommu(struct device *dev)
171 {
172 	u16 seg = get_device_segment(dev);
173 	int devid = get_device_sbdf_id(dev);
174 
175 	if (devid < 0)
176 		return NULL;
177 	return __rlookup_amd_iommu(seg, PCI_SBDF_TO_DEVID(devid));
178 }
179 
to_pdomain(struct iommu_domain * dom)180 static struct protection_domain *to_pdomain(struct iommu_domain *dom)
181 {
182 	return container_of(dom, struct protection_domain, domain);
183 }
184 
alloc_dev_data(struct amd_iommu * iommu,u16 devid)185 static struct iommu_dev_data *alloc_dev_data(struct amd_iommu *iommu, u16 devid)
186 {
187 	struct iommu_dev_data *dev_data;
188 	struct amd_iommu_pci_seg *pci_seg = iommu->pci_seg;
189 
190 	dev_data = kzalloc(sizeof(*dev_data), GFP_KERNEL);
191 	if (!dev_data)
192 		return NULL;
193 
194 	spin_lock_init(&dev_data->lock);
195 	dev_data->devid = devid;
196 	ratelimit_default_init(&dev_data->rs);
197 
198 	llist_add(&dev_data->dev_data_list, &pci_seg->dev_data_list);
199 	return dev_data;
200 }
201 
search_dev_data(struct amd_iommu * iommu,u16 devid)202 static struct iommu_dev_data *search_dev_data(struct amd_iommu *iommu, u16 devid)
203 {
204 	struct iommu_dev_data *dev_data;
205 	struct llist_node *node;
206 	struct amd_iommu_pci_seg *pci_seg = iommu->pci_seg;
207 
208 	if (llist_empty(&pci_seg->dev_data_list))
209 		return NULL;
210 
211 	node = pci_seg->dev_data_list.first;
212 	llist_for_each_entry(dev_data, node, dev_data_list) {
213 		if (dev_data->devid == devid)
214 			return dev_data;
215 	}
216 
217 	return NULL;
218 }
219 
clone_alias(struct pci_dev * pdev,u16 alias,void * data)220 static int clone_alias(struct pci_dev *pdev, u16 alias, void *data)
221 {
222 	struct amd_iommu *iommu;
223 	struct dev_table_entry *dev_table;
224 	u16 devid = pci_dev_id(pdev);
225 
226 	if (devid == alias)
227 		return 0;
228 
229 	iommu = rlookup_amd_iommu(&pdev->dev);
230 	if (!iommu)
231 		return 0;
232 
233 	amd_iommu_set_rlookup_table(iommu, alias);
234 	dev_table = get_dev_table(iommu);
235 	memcpy(dev_table[alias].data,
236 	       dev_table[devid].data,
237 	       sizeof(dev_table[alias].data));
238 
239 	return 0;
240 }
241 
clone_aliases(struct amd_iommu * iommu,struct device * dev)242 static void clone_aliases(struct amd_iommu *iommu, struct device *dev)
243 {
244 	struct pci_dev *pdev;
245 
246 	if (!dev_is_pci(dev))
247 		return;
248 	pdev = to_pci_dev(dev);
249 
250 	/*
251 	 * The IVRS alias stored in the alias table may not be
252 	 * part of the PCI DMA aliases if it's bus differs
253 	 * from the original device.
254 	 */
255 	clone_alias(pdev, iommu->pci_seg->alias_table[pci_dev_id(pdev)], NULL);
256 
257 	pci_for_each_dma_alias(pdev, clone_alias, NULL);
258 }
259 
setup_aliases(struct amd_iommu * iommu,struct device * dev)260 static void setup_aliases(struct amd_iommu *iommu, struct device *dev)
261 {
262 	struct pci_dev *pdev = to_pci_dev(dev);
263 	struct amd_iommu_pci_seg *pci_seg = iommu->pci_seg;
264 	u16 ivrs_alias;
265 
266 	/* For ACPI HID devices, there are no aliases */
267 	if (!dev_is_pci(dev))
268 		return;
269 
270 	/*
271 	 * Add the IVRS alias to the pci aliases if it is on the same
272 	 * bus. The IVRS table may know about a quirk that we don't.
273 	 */
274 	ivrs_alias = pci_seg->alias_table[pci_dev_id(pdev)];
275 	if (ivrs_alias != pci_dev_id(pdev) &&
276 	    PCI_BUS_NUM(ivrs_alias) == pdev->bus->number)
277 		pci_add_dma_alias(pdev, ivrs_alias & 0xff, 1);
278 
279 	clone_aliases(iommu, dev);
280 }
281 
find_dev_data(struct amd_iommu * iommu,u16 devid)282 static struct iommu_dev_data *find_dev_data(struct amd_iommu *iommu, u16 devid)
283 {
284 	struct iommu_dev_data *dev_data;
285 
286 	dev_data = search_dev_data(iommu, devid);
287 
288 	if (dev_data == NULL) {
289 		dev_data = alloc_dev_data(iommu, devid);
290 		if (!dev_data)
291 			return NULL;
292 
293 		if (translation_pre_enabled(iommu))
294 			dev_data->defer_attach = true;
295 	}
296 
297 	return dev_data;
298 }
299 
300 /*
301 * Find or create an IOMMU group for a acpihid device.
302 */
acpihid_device_group(struct device * dev)303 static struct iommu_group *acpihid_device_group(struct device *dev)
304 {
305 	struct acpihid_map_entry *p, *entry = NULL;
306 	int devid;
307 
308 	devid = get_acpihid_device_id(dev, &entry);
309 	if (devid < 0)
310 		return ERR_PTR(devid);
311 
312 	list_for_each_entry(p, &acpihid_map, list) {
313 		if ((devid == p->devid) && p->group)
314 			entry->group = p->group;
315 	}
316 
317 	if (!entry->group)
318 		entry->group = generic_device_group(dev);
319 	else
320 		iommu_group_ref_get(entry->group);
321 
322 	return entry->group;
323 }
324 
pci_iommuv2_capable(struct pci_dev * pdev)325 static bool pci_iommuv2_capable(struct pci_dev *pdev)
326 {
327 	static const int caps[] = {
328 		PCI_EXT_CAP_ID_PRI,
329 		PCI_EXT_CAP_ID_PASID,
330 	};
331 	int i, pos;
332 
333 	if (!pci_ats_supported(pdev))
334 		return false;
335 
336 	for (i = 0; i < 2; ++i) {
337 		pos = pci_find_ext_capability(pdev, caps[i]);
338 		if (pos == 0)
339 			return false;
340 	}
341 
342 	return true;
343 }
344 
345 /*
346  * This function checks if the driver got a valid device from the caller to
347  * avoid dereferencing invalid pointers.
348  */
check_device(struct device * dev)349 static bool check_device(struct device *dev)
350 {
351 	struct amd_iommu_pci_seg *pci_seg;
352 	struct amd_iommu *iommu;
353 	int devid, sbdf;
354 
355 	if (!dev)
356 		return false;
357 
358 	sbdf = get_device_sbdf_id(dev);
359 	if (sbdf < 0)
360 		return false;
361 	devid = PCI_SBDF_TO_DEVID(sbdf);
362 
363 	iommu = rlookup_amd_iommu(dev);
364 	if (!iommu)
365 		return false;
366 
367 	/* Out of our scope? */
368 	pci_seg = iommu->pci_seg;
369 	if (devid > pci_seg->last_bdf)
370 		return false;
371 
372 	return true;
373 }
374 
iommu_init_device(struct amd_iommu * iommu,struct device * dev)375 static int iommu_init_device(struct amd_iommu *iommu, struct device *dev)
376 {
377 	struct iommu_dev_data *dev_data;
378 	int devid, sbdf;
379 
380 	if (dev_iommu_priv_get(dev))
381 		return 0;
382 
383 	sbdf = get_device_sbdf_id(dev);
384 	if (sbdf < 0)
385 		return sbdf;
386 
387 	devid = PCI_SBDF_TO_DEVID(sbdf);
388 	dev_data = find_dev_data(iommu, devid);
389 	if (!dev_data)
390 		return -ENOMEM;
391 
392 	dev_data->dev = dev;
393 	setup_aliases(iommu, dev);
394 
395 	/*
396 	 * By default we use passthrough mode for IOMMUv2 capable device.
397 	 * But if amd_iommu=force_isolation is set (e.g. to debug DMA to
398 	 * invalid address), we ignore the capability for the device so
399 	 * it'll be forced to go into translation mode.
400 	 */
401 	if ((iommu_default_passthrough() || !amd_iommu_force_isolation) &&
402 	    dev_is_pci(dev) && pci_iommuv2_capable(to_pci_dev(dev))) {
403 		dev_data->iommu_v2 = iommu->is_iommu_v2;
404 	}
405 
406 	dev_iommu_priv_set(dev, dev_data);
407 
408 	return 0;
409 }
410 
iommu_ignore_device(struct amd_iommu * iommu,struct device * dev)411 static void iommu_ignore_device(struct amd_iommu *iommu, struct device *dev)
412 {
413 	struct amd_iommu_pci_seg *pci_seg = iommu->pci_seg;
414 	struct dev_table_entry *dev_table = get_dev_table(iommu);
415 	int devid, sbdf;
416 
417 	sbdf = get_device_sbdf_id(dev);
418 	if (sbdf < 0)
419 		return;
420 
421 	devid = PCI_SBDF_TO_DEVID(sbdf);
422 	pci_seg->rlookup_table[devid] = NULL;
423 	memset(&dev_table[devid], 0, sizeof(struct dev_table_entry));
424 
425 	setup_aliases(iommu, dev);
426 }
427 
amd_iommu_uninit_device(struct device * dev)428 static void amd_iommu_uninit_device(struct device *dev)
429 {
430 	struct iommu_dev_data *dev_data;
431 
432 	dev_data = dev_iommu_priv_get(dev);
433 	if (!dev_data)
434 		return;
435 
436 	if (dev_data->domain)
437 		detach_device(dev);
438 
439 	dev_iommu_priv_set(dev, NULL);
440 
441 	/*
442 	 * We keep dev_data around for unplugged devices and reuse it when the
443 	 * device is re-plugged - not doing so would introduce a ton of races.
444 	 */
445 }
446 
447 /****************************************************************************
448  *
449  * Interrupt handling functions
450  *
451  ****************************************************************************/
452 
dump_dte_entry(struct amd_iommu * iommu,u16 devid)453 static void dump_dte_entry(struct amd_iommu *iommu, u16 devid)
454 {
455 	int i;
456 	struct dev_table_entry *dev_table = get_dev_table(iommu);
457 
458 	for (i = 0; i < 4; ++i)
459 		pr_err("DTE[%d]: %016llx\n", i, dev_table[devid].data[i]);
460 }
461 
dump_command(unsigned long phys_addr)462 static void dump_command(unsigned long phys_addr)
463 {
464 	struct iommu_cmd *cmd = iommu_phys_to_virt(phys_addr);
465 	int i;
466 
467 	for (i = 0; i < 4; ++i)
468 		pr_err("CMD[%d]: %08x\n", i, cmd->data[i]);
469 }
470 
amd_iommu_report_rmp_hw_error(struct amd_iommu * iommu,volatile u32 * event)471 static void amd_iommu_report_rmp_hw_error(struct amd_iommu *iommu, volatile u32 *event)
472 {
473 	struct iommu_dev_data *dev_data = NULL;
474 	int devid, vmg_tag, flags;
475 	struct pci_dev *pdev;
476 	u64 spa;
477 
478 	devid   = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK;
479 	vmg_tag = (event[1]) & 0xFFFF;
480 	flags   = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK;
481 	spa     = ((u64)event[3] << 32) | (event[2] & 0xFFFFFFF8);
482 
483 	pdev = pci_get_domain_bus_and_slot(iommu->pci_seg->id, PCI_BUS_NUM(devid),
484 					   devid & 0xff);
485 	if (pdev)
486 		dev_data = dev_iommu_priv_get(&pdev->dev);
487 
488 	if (dev_data) {
489 		if (__ratelimit(&dev_data->rs)) {
490 			pci_err(pdev, "Event logged [RMP_HW_ERROR vmg_tag=0x%04x, spa=0x%llx, flags=0x%04x]\n",
491 				vmg_tag, spa, flags);
492 		}
493 	} else {
494 		pr_err_ratelimited("Event logged [RMP_HW_ERROR device=%04x:%02x:%02x.%x, vmg_tag=0x%04x, spa=0x%llx, flags=0x%04x]\n",
495 			iommu->pci_seg->id, PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
496 			vmg_tag, spa, flags);
497 	}
498 
499 	if (pdev)
500 		pci_dev_put(pdev);
501 }
502 
amd_iommu_report_rmp_fault(struct amd_iommu * iommu,volatile u32 * event)503 static void amd_iommu_report_rmp_fault(struct amd_iommu *iommu, volatile u32 *event)
504 {
505 	struct iommu_dev_data *dev_data = NULL;
506 	int devid, flags_rmp, vmg_tag, flags;
507 	struct pci_dev *pdev;
508 	u64 gpa;
509 
510 	devid     = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK;
511 	flags_rmp = (event[0] >> EVENT_FLAGS_SHIFT) & 0xFF;
512 	vmg_tag   = (event[1]) & 0xFFFF;
513 	flags     = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK;
514 	gpa       = ((u64)event[3] << 32) | event[2];
515 
516 	pdev = pci_get_domain_bus_and_slot(iommu->pci_seg->id, PCI_BUS_NUM(devid),
517 					   devid & 0xff);
518 	if (pdev)
519 		dev_data = dev_iommu_priv_get(&pdev->dev);
520 
521 	if (dev_data) {
522 		if (__ratelimit(&dev_data->rs)) {
523 			pci_err(pdev, "Event logged [RMP_PAGE_FAULT vmg_tag=0x%04x, gpa=0x%llx, flags_rmp=0x%04x, flags=0x%04x]\n",
524 				vmg_tag, gpa, flags_rmp, flags);
525 		}
526 	} else {
527 		pr_err_ratelimited("Event logged [RMP_PAGE_FAULT device=%04x:%02x:%02x.%x, vmg_tag=0x%04x, gpa=0x%llx, flags_rmp=0x%04x, flags=0x%04x]\n",
528 			iommu->pci_seg->id, PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
529 			vmg_tag, gpa, flags_rmp, flags);
530 	}
531 
532 	if (pdev)
533 		pci_dev_put(pdev);
534 }
535 
536 #define IS_IOMMU_MEM_TRANSACTION(flags)		\
537 	(((flags) & EVENT_FLAG_I) == 0)
538 
539 #define IS_WRITE_REQUEST(flags)			\
540 	((flags) & EVENT_FLAG_RW)
541 
amd_iommu_report_page_fault(struct amd_iommu * iommu,u16 devid,u16 domain_id,u64 address,int flags)542 static void amd_iommu_report_page_fault(struct amd_iommu *iommu,
543 					u16 devid, u16 domain_id,
544 					u64 address, int flags)
545 {
546 	struct iommu_dev_data *dev_data = NULL;
547 	struct pci_dev *pdev;
548 
549 	pdev = pci_get_domain_bus_and_slot(iommu->pci_seg->id, PCI_BUS_NUM(devid),
550 					   devid & 0xff);
551 	if (pdev)
552 		dev_data = dev_iommu_priv_get(&pdev->dev);
553 
554 	if (dev_data) {
555 		/*
556 		 * If this is a DMA fault (for which the I(nterrupt)
557 		 * bit will be unset), allow report_iommu_fault() to
558 		 * prevent logging it.
559 		 */
560 		if (IS_IOMMU_MEM_TRANSACTION(flags)) {
561 			if (!report_iommu_fault(&dev_data->domain->domain,
562 						&pdev->dev, address,
563 						IS_WRITE_REQUEST(flags) ?
564 							IOMMU_FAULT_WRITE :
565 							IOMMU_FAULT_READ))
566 				goto out;
567 		}
568 
569 		if (__ratelimit(&dev_data->rs)) {
570 			pci_err(pdev, "Event logged [IO_PAGE_FAULT domain=0x%04x address=0x%llx flags=0x%04x]\n",
571 				domain_id, address, flags);
572 		}
573 	} else {
574 		pr_err_ratelimited("Event logged [IO_PAGE_FAULT device=%04x:%02x:%02x.%x domain=0x%04x address=0x%llx flags=0x%04x]\n",
575 			iommu->pci_seg->id, PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
576 			domain_id, address, flags);
577 	}
578 
579 out:
580 	if (pdev)
581 		pci_dev_put(pdev);
582 }
583 
iommu_print_event(struct amd_iommu * iommu,void * __evt)584 static void iommu_print_event(struct amd_iommu *iommu, void *__evt)
585 {
586 	struct device *dev = iommu->iommu.dev;
587 	int type, devid, flags, tag;
588 	volatile u32 *event = __evt;
589 	int count = 0;
590 	u64 address;
591 	u32 pasid;
592 
593 retry:
594 	type    = (event[1] >> EVENT_TYPE_SHIFT)  & EVENT_TYPE_MASK;
595 	devid   = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK;
596 	pasid   = (event[0] & EVENT_DOMID_MASK_HI) |
597 		  (event[1] & EVENT_DOMID_MASK_LO);
598 	flags   = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK;
599 	address = (u64)(((u64)event[3]) << 32) | event[2];
600 
601 	if (type == 0) {
602 		/* Did we hit the erratum? */
603 		if (++count == LOOP_TIMEOUT) {
604 			pr_err("No event written to event log\n");
605 			return;
606 		}
607 		udelay(1);
608 		goto retry;
609 	}
610 
611 	if (type == EVENT_TYPE_IO_FAULT) {
612 		amd_iommu_report_page_fault(iommu, devid, pasid, address, flags);
613 		return;
614 	}
615 
616 	switch (type) {
617 	case EVENT_TYPE_ILL_DEV:
618 		dev_err(dev, "Event logged [ILLEGAL_DEV_TABLE_ENTRY device=%04x:%02x:%02x.%x pasid=0x%05x address=0x%llx flags=0x%04x]\n",
619 			iommu->pci_seg->id, PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
620 			pasid, address, flags);
621 		dump_dte_entry(iommu, devid);
622 		break;
623 	case EVENT_TYPE_DEV_TAB_ERR:
624 		dev_err(dev, "Event logged [DEV_TAB_HARDWARE_ERROR device=%04x:%02x:%02x.%x "
625 			"address=0x%llx flags=0x%04x]\n",
626 			iommu->pci_seg->id, PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
627 			address, flags);
628 		break;
629 	case EVENT_TYPE_PAGE_TAB_ERR:
630 		dev_err(dev, "Event logged [PAGE_TAB_HARDWARE_ERROR device=%04x:%02x:%02x.%x pasid=0x%04x address=0x%llx flags=0x%04x]\n",
631 			iommu->pci_seg->id, PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
632 			pasid, address, flags);
633 		break;
634 	case EVENT_TYPE_ILL_CMD:
635 		dev_err(dev, "Event logged [ILLEGAL_COMMAND_ERROR address=0x%llx]\n", address);
636 		dump_command(address);
637 		break;
638 	case EVENT_TYPE_CMD_HARD_ERR:
639 		dev_err(dev, "Event logged [COMMAND_HARDWARE_ERROR address=0x%llx flags=0x%04x]\n",
640 			address, flags);
641 		break;
642 	case EVENT_TYPE_IOTLB_INV_TO:
643 		dev_err(dev, "Event logged [IOTLB_INV_TIMEOUT device=%04x:%02x:%02x.%x address=0x%llx]\n",
644 			iommu->pci_seg->id, PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
645 			address);
646 		break;
647 	case EVENT_TYPE_INV_DEV_REQ:
648 		dev_err(dev, "Event logged [INVALID_DEVICE_REQUEST device=%04x:%02x:%02x.%x pasid=0x%05x address=0x%llx flags=0x%04x]\n",
649 			iommu->pci_seg->id, PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
650 			pasid, address, flags);
651 		break;
652 	case EVENT_TYPE_RMP_FAULT:
653 		amd_iommu_report_rmp_fault(iommu, event);
654 		break;
655 	case EVENT_TYPE_RMP_HW_ERR:
656 		amd_iommu_report_rmp_hw_error(iommu, event);
657 		break;
658 	case EVENT_TYPE_INV_PPR_REQ:
659 		pasid = PPR_PASID(*((u64 *)__evt));
660 		tag = event[1] & 0x03FF;
661 		dev_err(dev, "Event logged [INVALID_PPR_REQUEST device=%04x:%02x:%02x.%x pasid=0x%05x address=0x%llx flags=0x%04x tag=0x%03x]\n",
662 			iommu->pci_seg->id, PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
663 			pasid, address, flags, tag);
664 		break;
665 	default:
666 		dev_err(dev, "Event logged [UNKNOWN event[0]=0x%08x event[1]=0x%08x event[2]=0x%08x event[3]=0x%08x\n",
667 			event[0], event[1], event[2], event[3]);
668 	}
669 
670 	memset(__evt, 0, 4 * sizeof(u32));
671 }
672 
iommu_poll_events(struct amd_iommu * iommu)673 static void iommu_poll_events(struct amd_iommu *iommu)
674 {
675 	u32 head, tail;
676 
677 	head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
678 	tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
679 
680 	while (head != tail) {
681 		iommu_print_event(iommu, iommu->evt_buf + head);
682 		head = (head + EVENT_ENTRY_SIZE) % EVT_BUFFER_SIZE;
683 	}
684 
685 	writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
686 }
687 
iommu_handle_ppr_entry(struct amd_iommu * iommu,u64 * raw)688 static void iommu_handle_ppr_entry(struct amd_iommu *iommu, u64 *raw)
689 {
690 	struct amd_iommu_fault fault;
691 
692 	if (PPR_REQ_TYPE(raw[0]) != PPR_REQ_FAULT) {
693 		pr_err_ratelimited("Unknown PPR request received\n");
694 		return;
695 	}
696 
697 	fault.address   = raw[1];
698 	fault.pasid     = PPR_PASID(raw[0]);
699 	fault.sbdf      = PCI_SEG_DEVID_TO_SBDF(iommu->pci_seg->id, PPR_DEVID(raw[0]));
700 	fault.tag       = PPR_TAG(raw[0]);
701 	fault.flags     = PPR_FLAGS(raw[0]);
702 
703 	atomic_notifier_call_chain(&ppr_notifier, 0, &fault);
704 }
705 
iommu_poll_ppr_log(struct amd_iommu * iommu)706 static void iommu_poll_ppr_log(struct amd_iommu *iommu)
707 {
708 	u32 head, tail;
709 
710 	if (iommu->ppr_log == NULL)
711 		return;
712 
713 	head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
714 	tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
715 
716 	while (head != tail) {
717 		volatile u64 *raw;
718 		u64 entry[2];
719 		int i;
720 
721 		raw = (u64 *)(iommu->ppr_log + head);
722 
723 		/*
724 		 * Hardware bug: Interrupt may arrive before the entry is
725 		 * written to memory. If this happens we need to wait for the
726 		 * entry to arrive.
727 		 */
728 		for (i = 0; i < LOOP_TIMEOUT; ++i) {
729 			if (PPR_REQ_TYPE(raw[0]) != 0)
730 				break;
731 			udelay(1);
732 		}
733 
734 		/* Avoid memcpy function-call overhead */
735 		entry[0] = raw[0];
736 		entry[1] = raw[1];
737 
738 		/*
739 		 * To detect the hardware bug we need to clear the entry
740 		 * back to zero.
741 		 */
742 		raw[0] = raw[1] = 0UL;
743 
744 		/* Update head pointer of hardware ring-buffer */
745 		head = (head + PPR_ENTRY_SIZE) % PPR_LOG_SIZE;
746 		writel(head, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
747 
748 		/* Handle PPR entry */
749 		iommu_handle_ppr_entry(iommu, entry);
750 
751 		/* Refresh ring-buffer information */
752 		head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
753 		tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
754 	}
755 }
756 
757 #ifdef CONFIG_IRQ_REMAP
758 static int (*iommu_ga_log_notifier)(u32);
759 
amd_iommu_register_ga_log_notifier(int (* notifier)(u32))760 int amd_iommu_register_ga_log_notifier(int (*notifier)(u32))
761 {
762 	iommu_ga_log_notifier = notifier;
763 
764 	return 0;
765 }
766 EXPORT_SYMBOL(amd_iommu_register_ga_log_notifier);
767 
iommu_poll_ga_log(struct amd_iommu * iommu)768 static void iommu_poll_ga_log(struct amd_iommu *iommu)
769 {
770 	u32 head, tail, cnt = 0;
771 
772 	if (iommu->ga_log == NULL)
773 		return;
774 
775 	head = readl(iommu->mmio_base + MMIO_GA_HEAD_OFFSET);
776 	tail = readl(iommu->mmio_base + MMIO_GA_TAIL_OFFSET);
777 
778 	while (head != tail) {
779 		volatile u64 *raw;
780 		u64 log_entry;
781 
782 		raw = (u64 *)(iommu->ga_log + head);
783 		cnt++;
784 
785 		/* Avoid memcpy function-call overhead */
786 		log_entry = *raw;
787 
788 		/* Update head pointer of hardware ring-buffer */
789 		head = (head + GA_ENTRY_SIZE) % GA_LOG_SIZE;
790 		writel(head, iommu->mmio_base + MMIO_GA_HEAD_OFFSET);
791 
792 		/* Handle GA entry */
793 		switch (GA_REQ_TYPE(log_entry)) {
794 		case GA_GUEST_NR:
795 			if (!iommu_ga_log_notifier)
796 				break;
797 
798 			pr_debug("%s: devid=%#x, ga_tag=%#x\n",
799 				 __func__, GA_DEVID(log_entry),
800 				 GA_TAG(log_entry));
801 
802 			if (iommu_ga_log_notifier(GA_TAG(log_entry)) != 0)
803 				pr_err("GA log notifier failed.\n");
804 			break;
805 		default:
806 			break;
807 		}
808 	}
809 }
810 
811 static void
amd_iommu_set_pci_msi_domain(struct device * dev,struct amd_iommu * iommu)812 amd_iommu_set_pci_msi_domain(struct device *dev, struct amd_iommu *iommu)
813 {
814 	if (!irq_remapping_enabled || !dev_is_pci(dev) ||
815 	    pci_dev_has_special_msi_domain(to_pci_dev(dev)))
816 		return;
817 
818 	dev_set_msi_domain(dev, iommu->msi_domain);
819 }
820 
821 #else /* CONFIG_IRQ_REMAP */
822 static inline void
amd_iommu_set_pci_msi_domain(struct device * dev,struct amd_iommu * iommu)823 amd_iommu_set_pci_msi_domain(struct device *dev, struct amd_iommu *iommu) { }
824 #endif /* !CONFIG_IRQ_REMAP */
825 
826 #define AMD_IOMMU_INT_MASK	\
827 	(MMIO_STATUS_EVT_OVERFLOW_INT_MASK | \
828 	 MMIO_STATUS_EVT_INT_MASK | \
829 	 MMIO_STATUS_PPR_INT_MASK | \
830 	 MMIO_STATUS_GALOG_INT_MASK)
831 
amd_iommu_int_thread(int irq,void * data)832 irqreturn_t amd_iommu_int_thread(int irq, void *data)
833 {
834 	struct amd_iommu *iommu = (struct amd_iommu *) data;
835 	u32 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
836 
837 	while (status & AMD_IOMMU_INT_MASK) {
838 		/* Enable interrupt sources again */
839 		writel(AMD_IOMMU_INT_MASK,
840 			iommu->mmio_base + MMIO_STATUS_OFFSET);
841 
842 		if (status & MMIO_STATUS_EVT_INT_MASK) {
843 			pr_devel("Processing IOMMU Event Log\n");
844 			iommu_poll_events(iommu);
845 		}
846 
847 		if (status & MMIO_STATUS_PPR_INT_MASK) {
848 			pr_devel("Processing IOMMU PPR Log\n");
849 			iommu_poll_ppr_log(iommu);
850 		}
851 
852 #ifdef CONFIG_IRQ_REMAP
853 		if (status & MMIO_STATUS_GALOG_INT_MASK) {
854 			pr_devel("Processing IOMMU GA Log\n");
855 			iommu_poll_ga_log(iommu);
856 		}
857 #endif
858 
859 		if (status & MMIO_STATUS_EVT_OVERFLOW_INT_MASK) {
860 			pr_info_ratelimited("IOMMU event log overflow\n");
861 			amd_iommu_restart_event_logging(iommu);
862 		}
863 
864 		/*
865 		 * Hardware bug: ERBT1312
866 		 * When re-enabling interrupt (by writing 1
867 		 * to clear the bit), the hardware might also try to set
868 		 * the interrupt bit in the event status register.
869 		 * In this scenario, the bit will be set, and disable
870 		 * subsequent interrupts.
871 		 *
872 		 * Workaround: The IOMMU driver should read back the
873 		 * status register and check if the interrupt bits are cleared.
874 		 * If not, driver will need to go through the interrupt handler
875 		 * again and re-clear the bits
876 		 */
877 		status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
878 	}
879 	return IRQ_HANDLED;
880 }
881 
amd_iommu_int_handler(int irq,void * data)882 irqreturn_t amd_iommu_int_handler(int irq, void *data)
883 {
884 	return IRQ_WAKE_THREAD;
885 }
886 
887 /****************************************************************************
888  *
889  * IOMMU command queuing functions
890  *
891  ****************************************************************************/
892 
wait_on_sem(struct amd_iommu * iommu,u64 data)893 static int wait_on_sem(struct amd_iommu *iommu, u64 data)
894 {
895 	int i = 0;
896 
897 	while (*iommu->cmd_sem != data && i < LOOP_TIMEOUT) {
898 		udelay(1);
899 		i += 1;
900 	}
901 
902 	if (i == LOOP_TIMEOUT) {
903 		pr_alert("Completion-Wait loop timed out\n");
904 		return -EIO;
905 	}
906 
907 	return 0;
908 }
909 
copy_cmd_to_buffer(struct amd_iommu * iommu,struct iommu_cmd * cmd)910 static void copy_cmd_to_buffer(struct amd_iommu *iommu,
911 			       struct iommu_cmd *cmd)
912 {
913 	u8 *target;
914 	u32 tail;
915 
916 	/* Copy command to buffer */
917 	tail = iommu->cmd_buf_tail;
918 	target = iommu->cmd_buf + tail;
919 	memcpy(target, cmd, sizeof(*cmd));
920 
921 	tail = (tail + sizeof(*cmd)) % CMD_BUFFER_SIZE;
922 	iommu->cmd_buf_tail = tail;
923 
924 	/* Tell the IOMMU about it */
925 	writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
926 }
927 
build_completion_wait(struct iommu_cmd * cmd,struct amd_iommu * iommu,u64 data)928 static void build_completion_wait(struct iommu_cmd *cmd,
929 				  struct amd_iommu *iommu,
930 				  u64 data)
931 {
932 	u64 paddr = iommu_virt_to_phys((void *)iommu->cmd_sem);
933 
934 	memset(cmd, 0, sizeof(*cmd));
935 	cmd->data[0] = lower_32_bits(paddr) | CMD_COMPL_WAIT_STORE_MASK;
936 	cmd->data[1] = upper_32_bits(paddr);
937 	cmd->data[2] = lower_32_bits(data);
938 	cmd->data[3] = upper_32_bits(data);
939 	CMD_SET_TYPE(cmd, CMD_COMPL_WAIT);
940 }
941 
build_inv_dte(struct iommu_cmd * cmd,u16 devid)942 static void build_inv_dte(struct iommu_cmd *cmd, u16 devid)
943 {
944 	memset(cmd, 0, sizeof(*cmd));
945 	cmd->data[0] = devid;
946 	CMD_SET_TYPE(cmd, CMD_INV_DEV_ENTRY);
947 }
948 
949 /*
950  * Builds an invalidation address which is suitable for one page or multiple
951  * pages. Sets the size bit (S) as needed is more than one page is flushed.
952  */
build_inv_address(u64 address,size_t size)953 static inline u64 build_inv_address(u64 address, size_t size)
954 {
955 	u64 pages, end, msb_diff;
956 
957 	pages = iommu_num_pages(address, size, PAGE_SIZE);
958 
959 	if (pages == 1)
960 		return address & PAGE_MASK;
961 
962 	end = address + size - 1;
963 
964 	/*
965 	 * msb_diff would hold the index of the most significant bit that
966 	 * flipped between the start and end.
967 	 */
968 	msb_diff = fls64(end ^ address) - 1;
969 
970 	/*
971 	 * Bits 63:52 are sign extended. If for some reason bit 51 is different
972 	 * between the start and the end, invalidate everything.
973 	 */
974 	if (unlikely(msb_diff > 51)) {
975 		address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
976 	} else {
977 		/*
978 		 * The msb-bit must be clear on the address. Just set all the
979 		 * lower bits.
980 		 */
981 		address |= (1ull << msb_diff) - 1;
982 	}
983 
984 	/* Clear bits 11:0 */
985 	address &= PAGE_MASK;
986 
987 	/* Set the size bit - we flush more than one 4kb page */
988 	return address | CMD_INV_IOMMU_PAGES_SIZE_MASK;
989 }
990 
build_inv_iommu_pages(struct iommu_cmd * cmd,u64 address,size_t size,u16 domid,int pde)991 static void build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address,
992 				  size_t size, u16 domid, int pde)
993 {
994 	u64 inv_address = build_inv_address(address, size);
995 
996 	memset(cmd, 0, sizeof(*cmd));
997 	cmd->data[1] |= domid;
998 	cmd->data[2]  = lower_32_bits(inv_address);
999 	cmd->data[3]  = upper_32_bits(inv_address);
1000 	CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
1001 	if (pde) /* PDE bit - we want to flush everything, not only the PTEs */
1002 		cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
1003 }
1004 
build_inv_iotlb_pages(struct iommu_cmd * cmd,u16 devid,int qdep,u64 address,size_t size)1005 static void build_inv_iotlb_pages(struct iommu_cmd *cmd, u16 devid, int qdep,
1006 				  u64 address, size_t size)
1007 {
1008 	u64 inv_address = build_inv_address(address, size);
1009 
1010 	memset(cmd, 0, sizeof(*cmd));
1011 	cmd->data[0]  = devid;
1012 	cmd->data[0] |= (qdep & 0xff) << 24;
1013 	cmd->data[1]  = devid;
1014 	cmd->data[2]  = lower_32_bits(inv_address);
1015 	cmd->data[3]  = upper_32_bits(inv_address);
1016 	CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES);
1017 }
1018 
build_inv_iommu_pasid(struct iommu_cmd * cmd,u16 domid,u32 pasid,u64 address,bool size)1019 static void build_inv_iommu_pasid(struct iommu_cmd *cmd, u16 domid, u32 pasid,
1020 				  u64 address, bool size)
1021 {
1022 	memset(cmd, 0, sizeof(*cmd));
1023 
1024 	address &= ~(0xfffULL);
1025 
1026 	cmd->data[0]  = pasid;
1027 	cmd->data[1]  = domid;
1028 	cmd->data[2]  = lower_32_bits(address);
1029 	cmd->data[3]  = upper_32_bits(address);
1030 	cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
1031 	cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK;
1032 	if (size)
1033 		cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
1034 	CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
1035 }
1036 
build_inv_iotlb_pasid(struct iommu_cmd * cmd,u16 devid,u32 pasid,int qdep,u64 address,bool size)1037 static void build_inv_iotlb_pasid(struct iommu_cmd *cmd, u16 devid, u32 pasid,
1038 				  int qdep, u64 address, bool size)
1039 {
1040 	memset(cmd, 0, sizeof(*cmd));
1041 
1042 	address &= ~(0xfffULL);
1043 
1044 	cmd->data[0]  = devid;
1045 	cmd->data[0] |= ((pasid >> 8) & 0xff) << 16;
1046 	cmd->data[0] |= (qdep  & 0xff) << 24;
1047 	cmd->data[1]  = devid;
1048 	cmd->data[1] |= (pasid & 0xff) << 16;
1049 	cmd->data[2]  = lower_32_bits(address);
1050 	cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK;
1051 	cmd->data[3]  = upper_32_bits(address);
1052 	if (size)
1053 		cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
1054 	CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES);
1055 }
1056 
build_complete_ppr(struct iommu_cmd * cmd,u16 devid,u32 pasid,int status,int tag,bool gn)1057 static void build_complete_ppr(struct iommu_cmd *cmd, u16 devid, u32 pasid,
1058 			       int status, int tag, bool gn)
1059 {
1060 	memset(cmd, 0, sizeof(*cmd));
1061 
1062 	cmd->data[0]  = devid;
1063 	if (gn) {
1064 		cmd->data[1]  = pasid;
1065 		cmd->data[2]  = CMD_INV_IOMMU_PAGES_GN_MASK;
1066 	}
1067 	cmd->data[3]  = tag & 0x1ff;
1068 	cmd->data[3] |= (status & PPR_STATUS_MASK) << PPR_STATUS_SHIFT;
1069 
1070 	CMD_SET_TYPE(cmd, CMD_COMPLETE_PPR);
1071 }
1072 
build_inv_all(struct iommu_cmd * cmd)1073 static void build_inv_all(struct iommu_cmd *cmd)
1074 {
1075 	memset(cmd, 0, sizeof(*cmd));
1076 	CMD_SET_TYPE(cmd, CMD_INV_ALL);
1077 }
1078 
build_inv_irt(struct iommu_cmd * cmd,u16 devid)1079 static void build_inv_irt(struct iommu_cmd *cmd, u16 devid)
1080 {
1081 	memset(cmd, 0, sizeof(*cmd));
1082 	cmd->data[0] = devid;
1083 	CMD_SET_TYPE(cmd, CMD_INV_IRT);
1084 }
1085 
1086 /*
1087  * Writes the command to the IOMMUs command buffer and informs the
1088  * hardware about the new command.
1089  */
__iommu_queue_command_sync(struct amd_iommu * iommu,struct iommu_cmd * cmd,bool sync)1090 static int __iommu_queue_command_sync(struct amd_iommu *iommu,
1091 				      struct iommu_cmd *cmd,
1092 				      bool sync)
1093 {
1094 	unsigned int count = 0;
1095 	u32 left, next_tail;
1096 
1097 	next_tail = (iommu->cmd_buf_tail + sizeof(*cmd)) % CMD_BUFFER_SIZE;
1098 again:
1099 	left      = (iommu->cmd_buf_head - next_tail) % CMD_BUFFER_SIZE;
1100 
1101 	if (left <= 0x20) {
1102 		/* Skip udelay() the first time around */
1103 		if (count++) {
1104 			if (count == LOOP_TIMEOUT) {
1105 				pr_err("Command buffer timeout\n");
1106 				return -EIO;
1107 			}
1108 
1109 			udelay(1);
1110 		}
1111 
1112 		/* Update head and recheck remaining space */
1113 		iommu->cmd_buf_head = readl(iommu->mmio_base +
1114 					    MMIO_CMD_HEAD_OFFSET);
1115 
1116 		goto again;
1117 	}
1118 
1119 	copy_cmd_to_buffer(iommu, cmd);
1120 
1121 	/* Do we need to make sure all commands are processed? */
1122 	iommu->need_sync = sync;
1123 
1124 	return 0;
1125 }
1126 
iommu_queue_command_sync(struct amd_iommu * iommu,struct iommu_cmd * cmd,bool sync)1127 static int iommu_queue_command_sync(struct amd_iommu *iommu,
1128 				    struct iommu_cmd *cmd,
1129 				    bool sync)
1130 {
1131 	unsigned long flags;
1132 	int ret;
1133 
1134 	raw_spin_lock_irqsave(&iommu->lock, flags);
1135 	ret = __iommu_queue_command_sync(iommu, cmd, sync);
1136 	raw_spin_unlock_irqrestore(&iommu->lock, flags);
1137 
1138 	return ret;
1139 }
1140 
iommu_queue_command(struct amd_iommu * iommu,struct iommu_cmd * cmd)1141 static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
1142 {
1143 	return iommu_queue_command_sync(iommu, cmd, true);
1144 }
1145 
1146 /*
1147  * This function queues a completion wait command into the command
1148  * buffer of an IOMMU
1149  */
iommu_completion_wait(struct amd_iommu * iommu)1150 static int iommu_completion_wait(struct amd_iommu *iommu)
1151 {
1152 	struct iommu_cmd cmd;
1153 	unsigned long flags;
1154 	int ret;
1155 	u64 data;
1156 
1157 	if (!iommu->need_sync)
1158 		return 0;
1159 
1160 	raw_spin_lock_irqsave(&iommu->lock, flags);
1161 
1162 	data = ++iommu->cmd_sem_val;
1163 	build_completion_wait(&cmd, iommu, data);
1164 
1165 	ret = __iommu_queue_command_sync(iommu, &cmd, false);
1166 	if (ret)
1167 		goto out_unlock;
1168 
1169 	ret = wait_on_sem(iommu, data);
1170 
1171 out_unlock:
1172 	raw_spin_unlock_irqrestore(&iommu->lock, flags);
1173 
1174 	return ret;
1175 }
1176 
iommu_flush_dte(struct amd_iommu * iommu,u16 devid)1177 static int iommu_flush_dte(struct amd_iommu *iommu, u16 devid)
1178 {
1179 	struct iommu_cmd cmd;
1180 
1181 	build_inv_dte(&cmd, devid);
1182 
1183 	return iommu_queue_command(iommu, &cmd);
1184 }
1185 
amd_iommu_flush_dte_all(struct amd_iommu * iommu)1186 static void amd_iommu_flush_dte_all(struct amd_iommu *iommu)
1187 {
1188 	u32 devid;
1189 	u16 last_bdf = iommu->pci_seg->last_bdf;
1190 
1191 	for (devid = 0; devid <= last_bdf; ++devid)
1192 		iommu_flush_dte(iommu, devid);
1193 
1194 	iommu_completion_wait(iommu);
1195 }
1196 
1197 /*
1198  * This function uses heavy locking and may disable irqs for some time. But
1199  * this is no issue because it is only called during resume.
1200  */
amd_iommu_flush_tlb_all(struct amd_iommu * iommu)1201 static void amd_iommu_flush_tlb_all(struct amd_iommu *iommu)
1202 {
1203 	u32 dom_id;
1204 	u16 last_bdf = iommu->pci_seg->last_bdf;
1205 
1206 	for (dom_id = 0; dom_id <= last_bdf; ++dom_id) {
1207 		struct iommu_cmd cmd;
1208 		build_inv_iommu_pages(&cmd, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
1209 				      dom_id, 1);
1210 		iommu_queue_command(iommu, &cmd);
1211 	}
1212 
1213 	iommu_completion_wait(iommu);
1214 }
1215 
amd_iommu_flush_tlb_domid(struct amd_iommu * iommu,u32 dom_id)1216 static void amd_iommu_flush_tlb_domid(struct amd_iommu *iommu, u32 dom_id)
1217 {
1218 	struct iommu_cmd cmd;
1219 
1220 	build_inv_iommu_pages(&cmd, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
1221 			      dom_id, 1);
1222 	iommu_queue_command(iommu, &cmd);
1223 
1224 	iommu_completion_wait(iommu);
1225 }
1226 
amd_iommu_flush_all(struct amd_iommu * iommu)1227 static void amd_iommu_flush_all(struct amd_iommu *iommu)
1228 {
1229 	struct iommu_cmd cmd;
1230 
1231 	build_inv_all(&cmd);
1232 
1233 	iommu_queue_command(iommu, &cmd);
1234 	iommu_completion_wait(iommu);
1235 }
1236 
iommu_flush_irt(struct amd_iommu * iommu,u16 devid)1237 static void iommu_flush_irt(struct amd_iommu *iommu, u16 devid)
1238 {
1239 	struct iommu_cmd cmd;
1240 
1241 	build_inv_irt(&cmd, devid);
1242 
1243 	iommu_queue_command(iommu, &cmd);
1244 }
1245 
amd_iommu_flush_irt_all(struct amd_iommu * iommu)1246 static void amd_iommu_flush_irt_all(struct amd_iommu *iommu)
1247 {
1248 	u32 devid;
1249 	u16 last_bdf = iommu->pci_seg->last_bdf;
1250 
1251 	for (devid = 0; devid <= last_bdf; devid++)
1252 		iommu_flush_irt(iommu, devid);
1253 
1254 	iommu_completion_wait(iommu);
1255 }
1256 
iommu_flush_all_caches(struct amd_iommu * iommu)1257 void iommu_flush_all_caches(struct amd_iommu *iommu)
1258 {
1259 	if (iommu_feature(iommu, FEATURE_IA)) {
1260 		amd_iommu_flush_all(iommu);
1261 	} else {
1262 		amd_iommu_flush_dte_all(iommu);
1263 		amd_iommu_flush_irt_all(iommu);
1264 		amd_iommu_flush_tlb_all(iommu);
1265 	}
1266 }
1267 
1268 /*
1269  * Command send function for flushing on-device TLB
1270  */
device_flush_iotlb(struct iommu_dev_data * dev_data,u64 address,size_t size)1271 static int device_flush_iotlb(struct iommu_dev_data *dev_data,
1272 			      u64 address, size_t size)
1273 {
1274 	struct amd_iommu *iommu;
1275 	struct iommu_cmd cmd;
1276 	int qdep;
1277 
1278 	qdep     = dev_data->ats.qdep;
1279 	iommu    = rlookup_amd_iommu(dev_data->dev);
1280 	if (!iommu)
1281 		return -EINVAL;
1282 
1283 	build_inv_iotlb_pages(&cmd, dev_data->devid, qdep, address, size);
1284 
1285 	return iommu_queue_command(iommu, &cmd);
1286 }
1287 
device_flush_dte_alias(struct pci_dev * pdev,u16 alias,void * data)1288 static int device_flush_dte_alias(struct pci_dev *pdev, u16 alias, void *data)
1289 {
1290 	struct amd_iommu *iommu = data;
1291 
1292 	return iommu_flush_dte(iommu, alias);
1293 }
1294 
1295 /*
1296  * Command send function for invalidating a device table entry
1297  */
device_flush_dte(struct iommu_dev_data * dev_data)1298 static int device_flush_dte(struct iommu_dev_data *dev_data)
1299 {
1300 	struct amd_iommu *iommu;
1301 	struct pci_dev *pdev = NULL;
1302 	struct amd_iommu_pci_seg *pci_seg;
1303 	u16 alias;
1304 	int ret;
1305 
1306 	iommu = rlookup_amd_iommu(dev_data->dev);
1307 	if (!iommu)
1308 		return -EINVAL;
1309 
1310 	if (dev_is_pci(dev_data->dev))
1311 		pdev = to_pci_dev(dev_data->dev);
1312 
1313 	if (pdev)
1314 		ret = pci_for_each_dma_alias(pdev,
1315 					     device_flush_dte_alias, iommu);
1316 	else
1317 		ret = iommu_flush_dte(iommu, dev_data->devid);
1318 	if (ret)
1319 		return ret;
1320 
1321 	pci_seg = iommu->pci_seg;
1322 	alias = pci_seg->alias_table[dev_data->devid];
1323 	if (alias != dev_data->devid) {
1324 		ret = iommu_flush_dte(iommu, alias);
1325 		if (ret)
1326 			return ret;
1327 	}
1328 
1329 	if (dev_data->ats.enabled)
1330 		ret = device_flush_iotlb(dev_data, 0, ~0UL);
1331 
1332 	return ret;
1333 }
1334 
1335 /*
1336  * TLB invalidation function which is called from the mapping functions.
1337  * It invalidates a single PTE if the range to flush is within a single
1338  * page. Otherwise it flushes the whole TLB of the IOMMU.
1339  */
__domain_flush_pages(struct protection_domain * domain,u64 address,size_t size,int pde)1340 static void __domain_flush_pages(struct protection_domain *domain,
1341 				 u64 address, size_t size, int pde)
1342 {
1343 	struct iommu_dev_data *dev_data;
1344 	struct iommu_cmd cmd;
1345 	int ret = 0, i;
1346 
1347 	build_inv_iommu_pages(&cmd, address, size, domain->id, pde);
1348 
1349 	for (i = 0; i < amd_iommu_get_num_iommus(); ++i) {
1350 		if (!domain->dev_iommu[i])
1351 			continue;
1352 
1353 		/*
1354 		 * Devices of this domain are behind this IOMMU
1355 		 * We need a TLB flush
1356 		 */
1357 		ret |= iommu_queue_command(amd_iommus[i], &cmd);
1358 	}
1359 
1360 	list_for_each_entry(dev_data, &domain->dev_list, list) {
1361 
1362 		if (!dev_data->ats.enabled)
1363 			continue;
1364 
1365 		ret |= device_flush_iotlb(dev_data, address, size);
1366 	}
1367 
1368 	WARN_ON(ret);
1369 }
1370 
domain_flush_pages(struct protection_domain * domain,u64 address,size_t size,int pde)1371 static void domain_flush_pages(struct protection_domain *domain,
1372 			       u64 address, size_t size, int pde)
1373 {
1374 	if (likely(!amd_iommu_np_cache)) {
1375 		__domain_flush_pages(domain, address, size, pde);
1376 		return;
1377 	}
1378 
1379 	/*
1380 	 * When NpCache is on, we infer that we run in a VM and use a vIOMMU.
1381 	 * In such setups it is best to avoid flushes of ranges which are not
1382 	 * naturally aligned, since it would lead to flushes of unmodified
1383 	 * PTEs. Such flushes would require the hypervisor to do more work than
1384 	 * necessary. Therefore, perform repeated flushes of aligned ranges
1385 	 * until you cover the range. Each iteration flushes the smaller
1386 	 * between the natural alignment of the address that we flush and the
1387 	 * greatest naturally aligned region that fits in the range.
1388 	 */
1389 	while (size != 0) {
1390 		int addr_alignment = __ffs(address);
1391 		int size_alignment = __fls(size);
1392 		int min_alignment;
1393 		size_t flush_size;
1394 
1395 		/*
1396 		 * size is always non-zero, but address might be zero, causing
1397 		 * addr_alignment to be negative. As the casting of the
1398 		 * argument in __ffs(address) to long might trim the high bits
1399 		 * of the address on x86-32, cast to long when doing the check.
1400 		 */
1401 		if (likely((unsigned long)address != 0))
1402 			min_alignment = min(addr_alignment, size_alignment);
1403 		else
1404 			min_alignment = size_alignment;
1405 
1406 		flush_size = 1ul << min_alignment;
1407 
1408 		__domain_flush_pages(domain, address, flush_size, pde);
1409 		address += flush_size;
1410 		size -= flush_size;
1411 	}
1412 }
1413 
1414 /* Flush the whole IO/TLB for a given protection domain - including PDE */
amd_iommu_domain_flush_tlb_pde(struct protection_domain * domain)1415 void amd_iommu_domain_flush_tlb_pde(struct protection_domain *domain)
1416 {
1417 	domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 1);
1418 }
1419 
amd_iommu_domain_flush_complete(struct protection_domain * domain)1420 void amd_iommu_domain_flush_complete(struct protection_domain *domain)
1421 {
1422 	int i;
1423 
1424 	for (i = 0; i < amd_iommu_get_num_iommus(); ++i) {
1425 		if (domain && !domain->dev_iommu[i])
1426 			continue;
1427 
1428 		/*
1429 		 * Devices of this domain are behind this IOMMU
1430 		 * We need to wait for completion of all commands.
1431 		 */
1432 		iommu_completion_wait(amd_iommus[i]);
1433 	}
1434 }
1435 
1436 /* Flush the not present cache if it exists */
domain_flush_np_cache(struct protection_domain * domain,dma_addr_t iova,size_t size)1437 static void domain_flush_np_cache(struct protection_domain *domain,
1438 		dma_addr_t iova, size_t size)
1439 {
1440 	if (unlikely(amd_iommu_np_cache)) {
1441 		unsigned long flags;
1442 
1443 		spin_lock_irqsave(&domain->lock, flags);
1444 		domain_flush_pages(domain, iova, size, 1);
1445 		amd_iommu_domain_flush_complete(domain);
1446 		spin_unlock_irqrestore(&domain->lock, flags);
1447 	}
1448 }
1449 
1450 
1451 /*
1452  * This function flushes the DTEs for all devices in domain
1453  */
domain_flush_devices(struct protection_domain * domain)1454 static void domain_flush_devices(struct protection_domain *domain)
1455 {
1456 	struct iommu_dev_data *dev_data;
1457 
1458 	list_for_each_entry(dev_data, &domain->dev_list, list)
1459 		device_flush_dte(dev_data);
1460 }
1461 
1462 /****************************************************************************
1463  *
1464  * The next functions belong to the domain allocation. A domain is
1465  * allocated for every IOMMU as the default domain. If device isolation
1466  * is enabled, every device get its own domain. The most important thing
1467  * about domains is the page table mapping the DMA address space they
1468  * contain.
1469  *
1470  ****************************************************************************/
1471 
domain_id_alloc(void)1472 static u16 domain_id_alloc(void)
1473 {
1474 	int id;
1475 
1476 	spin_lock(&pd_bitmap_lock);
1477 	id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID);
1478 	BUG_ON(id == 0);
1479 	if (id > 0 && id < MAX_DOMAIN_ID)
1480 		__set_bit(id, amd_iommu_pd_alloc_bitmap);
1481 	else
1482 		id = 0;
1483 	spin_unlock(&pd_bitmap_lock);
1484 
1485 	return id;
1486 }
1487 
domain_id_free(int id)1488 static void domain_id_free(int id)
1489 {
1490 	spin_lock(&pd_bitmap_lock);
1491 	if (id > 0 && id < MAX_DOMAIN_ID)
1492 		__clear_bit(id, amd_iommu_pd_alloc_bitmap);
1493 	spin_unlock(&pd_bitmap_lock);
1494 }
1495 
free_gcr3_tbl_level1(u64 * tbl)1496 static void free_gcr3_tbl_level1(u64 *tbl)
1497 {
1498 	u64 *ptr;
1499 	int i;
1500 
1501 	for (i = 0; i < 512; ++i) {
1502 		if (!(tbl[i] & GCR3_VALID))
1503 			continue;
1504 
1505 		ptr = iommu_phys_to_virt(tbl[i] & PAGE_MASK);
1506 
1507 		free_page((unsigned long)ptr);
1508 	}
1509 }
1510 
free_gcr3_tbl_level2(u64 * tbl)1511 static void free_gcr3_tbl_level2(u64 *tbl)
1512 {
1513 	u64 *ptr;
1514 	int i;
1515 
1516 	for (i = 0; i < 512; ++i) {
1517 		if (!(tbl[i] & GCR3_VALID))
1518 			continue;
1519 
1520 		ptr = iommu_phys_to_virt(tbl[i] & PAGE_MASK);
1521 
1522 		free_gcr3_tbl_level1(ptr);
1523 	}
1524 }
1525 
free_gcr3_table(struct protection_domain * domain)1526 static void free_gcr3_table(struct protection_domain *domain)
1527 {
1528 	if (domain->glx == 2)
1529 		free_gcr3_tbl_level2(domain->gcr3_tbl);
1530 	else if (domain->glx == 1)
1531 		free_gcr3_tbl_level1(domain->gcr3_tbl);
1532 	else
1533 		BUG_ON(domain->glx != 0);
1534 
1535 	free_page((unsigned long)domain->gcr3_tbl);
1536 }
1537 
set_dte_entry(struct amd_iommu * iommu,u16 devid,struct protection_domain * domain,bool ats,bool ppr)1538 static void set_dte_entry(struct amd_iommu *iommu, u16 devid,
1539 			  struct protection_domain *domain, bool ats, bool ppr)
1540 {
1541 	u64 pte_root = 0;
1542 	u64 flags = 0;
1543 	u32 old_domid;
1544 	struct dev_table_entry *dev_table = get_dev_table(iommu);
1545 
1546 	if (domain->iop.mode != PAGE_MODE_NONE)
1547 		pte_root = iommu_virt_to_phys(domain->iop.root);
1548 
1549 	pte_root |= (domain->iop.mode & DEV_ENTRY_MODE_MASK)
1550 		    << DEV_ENTRY_MODE_SHIFT;
1551 
1552 	pte_root |= DTE_FLAG_IR | DTE_FLAG_IW | DTE_FLAG_V;
1553 
1554 	/*
1555 	 * When SNP is enabled, Only set TV bit when IOMMU
1556 	 * page translation is in use.
1557 	 */
1558 	if (!amd_iommu_snp_en || (domain->id != 0))
1559 		pte_root |= DTE_FLAG_TV;
1560 
1561 	flags = dev_table[devid].data[1];
1562 
1563 	if (ats)
1564 		flags |= DTE_FLAG_IOTLB;
1565 
1566 	if (ppr) {
1567 		if (iommu_feature(iommu, FEATURE_EPHSUP))
1568 			pte_root |= 1ULL << DEV_ENTRY_PPR;
1569 	}
1570 
1571 	if (domain->flags & PD_IOMMUV2_MASK) {
1572 		u64 gcr3 = iommu_virt_to_phys(domain->gcr3_tbl);
1573 		u64 glx  = domain->glx;
1574 		u64 tmp;
1575 
1576 		pte_root |= DTE_FLAG_GV;
1577 		pte_root |= (glx & DTE_GLX_MASK) << DTE_GLX_SHIFT;
1578 
1579 		/* First mask out possible old values for GCR3 table */
1580 		tmp = DTE_GCR3_VAL_B(~0ULL) << DTE_GCR3_SHIFT_B;
1581 		flags    &= ~tmp;
1582 
1583 		tmp = DTE_GCR3_VAL_C(~0ULL) << DTE_GCR3_SHIFT_C;
1584 		flags    &= ~tmp;
1585 
1586 		/* Encode GCR3 table into DTE */
1587 		tmp = DTE_GCR3_VAL_A(gcr3) << DTE_GCR3_SHIFT_A;
1588 		pte_root |= tmp;
1589 
1590 		tmp = DTE_GCR3_VAL_B(gcr3) << DTE_GCR3_SHIFT_B;
1591 		flags    |= tmp;
1592 
1593 		tmp = DTE_GCR3_VAL_C(gcr3) << DTE_GCR3_SHIFT_C;
1594 		flags    |= tmp;
1595 
1596 		if (domain->flags & PD_GIOV_MASK)
1597 			pte_root |= DTE_FLAG_GIOV;
1598 	}
1599 
1600 	flags &= ~DEV_DOMID_MASK;
1601 	flags |= domain->id;
1602 
1603 	old_domid = dev_table[devid].data[1] & DEV_DOMID_MASK;
1604 	dev_table[devid].data[1]  = flags;
1605 	dev_table[devid].data[0]  = pte_root;
1606 
1607 	/*
1608 	 * A kdump kernel might be replacing a domain ID that was copied from
1609 	 * the previous kernel--if so, it needs to flush the translation cache
1610 	 * entries for the old domain ID that is being overwritten
1611 	 */
1612 	if (old_domid) {
1613 		amd_iommu_flush_tlb_domid(iommu, old_domid);
1614 	}
1615 }
1616 
clear_dte_entry(struct amd_iommu * iommu,u16 devid)1617 static void clear_dte_entry(struct amd_iommu *iommu, u16 devid)
1618 {
1619 	struct dev_table_entry *dev_table = get_dev_table(iommu);
1620 
1621 	/* remove entry from the device table seen by the hardware */
1622 	dev_table[devid].data[0]  = DTE_FLAG_V;
1623 
1624 	if (!amd_iommu_snp_en)
1625 		dev_table[devid].data[0] |= DTE_FLAG_TV;
1626 
1627 	dev_table[devid].data[1] &= DTE_FLAG_MASK;
1628 
1629 	amd_iommu_apply_erratum_63(iommu, devid);
1630 }
1631 
do_attach(struct iommu_dev_data * dev_data,struct protection_domain * domain)1632 static void do_attach(struct iommu_dev_data *dev_data,
1633 		      struct protection_domain *domain)
1634 {
1635 	struct amd_iommu *iommu;
1636 	bool ats;
1637 
1638 	iommu = rlookup_amd_iommu(dev_data->dev);
1639 	if (!iommu)
1640 		return;
1641 	ats   = dev_data->ats.enabled;
1642 
1643 	/* Update data structures */
1644 	dev_data->domain = domain;
1645 	list_add(&dev_data->list, &domain->dev_list);
1646 
1647 	/* Do reference counting */
1648 	domain->dev_iommu[iommu->index] += 1;
1649 	domain->dev_cnt                 += 1;
1650 
1651 	/* Override supported page sizes */
1652 	if (domain->flags & PD_GIOV_MASK)
1653 		domain->domain.pgsize_bitmap = AMD_IOMMU_PGSIZES_V2;
1654 
1655 	/* Update device table */
1656 	set_dte_entry(iommu, dev_data->devid, domain,
1657 		      ats, dev_data->iommu_v2);
1658 	clone_aliases(iommu, dev_data->dev);
1659 
1660 	device_flush_dte(dev_data);
1661 }
1662 
do_detach(struct iommu_dev_data * dev_data)1663 static void do_detach(struct iommu_dev_data *dev_data)
1664 {
1665 	struct protection_domain *domain = dev_data->domain;
1666 	struct amd_iommu *iommu;
1667 
1668 	iommu = rlookup_amd_iommu(dev_data->dev);
1669 	if (!iommu)
1670 		return;
1671 
1672 	/* Update data structures */
1673 	dev_data->domain = NULL;
1674 	list_del(&dev_data->list);
1675 	clear_dte_entry(iommu, dev_data->devid);
1676 	clone_aliases(iommu, dev_data->dev);
1677 
1678 	/* Flush the DTE entry */
1679 	device_flush_dte(dev_data);
1680 
1681 	/* Flush IOTLB */
1682 	amd_iommu_domain_flush_tlb_pde(domain);
1683 
1684 	/* Wait for the flushes to finish */
1685 	amd_iommu_domain_flush_complete(domain);
1686 
1687 	/* decrease reference counters - needs to happen after the flushes */
1688 	domain->dev_iommu[iommu->index] -= 1;
1689 	domain->dev_cnt                 -= 1;
1690 }
1691 
pdev_iommuv2_disable(struct pci_dev * pdev)1692 static void pdev_iommuv2_disable(struct pci_dev *pdev)
1693 {
1694 	pci_disable_ats(pdev);
1695 	pci_disable_pri(pdev);
1696 	pci_disable_pasid(pdev);
1697 }
1698 
pdev_pri_ats_enable(struct pci_dev * pdev)1699 static int pdev_pri_ats_enable(struct pci_dev *pdev)
1700 {
1701 	int ret;
1702 
1703 	/* Only allow access to user-accessible pages */
1704 	ret = pci_enable_pasid(pdev, 0);
1705 	if (ret)
1706 		goto out_err;
1707 
1708 	/* First reset the PRI state of the device */
1709 	ret = pci_reset_pri(pdev);
1710 	if (ret)
1711 		goto out_err;
1712 
1713 	/* Enable PRI */
1714 	/* FIXME: Hardcode number of outstanding requests for now */
1715 	ret = pci_enable_pri(pdev, 32);
1716 	if (ret)
1717 		goto out_err;
1718 
1719 	ret = pci_enable_ats(pdev, PAGE_SHIFT);
1720 	if (ret)
1721 		goto out_err;
1722 
1723 	return 0;
1724 
1725 out_err:
1726 	pci_disable_pri(pdev);
1727 	pci_disable_pasid(pdev);
1728 
1729 	return ret;
1730 }
1731 
1732 /*
1733  * If a device is not yet associated with a domain, this function makes the
1734  * device visible in the domain
1735  */
attach_device(struct device * dev,struct protection_domain * domain)1736 static int attach_device(struct device *dev,
1737 			 struct protection_domain *domain)
1738 {
1739 	struct iommu_dev_data *dev_data;
1740 	struct pci_dev *pdev;
1741 	unsigned long flags;
1742 	int ret;
1743 
1744 	spin_lock_irqsave(&domain->lock, flags);
1745 
1746 	dev_data = dev_iommu_priv_get(dev);
1747 
1748 	spin_lock(&dev_data->lock);
1749 
1750 	ret = -EBUSY;
1751 	if (dev_data->domain != NULL)
1752 		goto out;
1753 
1754 	if (!dev_is_pci(dev))
1755 		goto skip_ats_check;
1756 
1757 	pdev = to_pci_dev(dev);
1758 	if (domain->flags & PD_IOMMUV2_MASK) {
1759 		struct iommu_domain *def_domain = iommu_get_dma_domain(dev);
1760 
1761 		ret = -EINVAL;
1762 
1763 		/*
1764 		 * In case of using AMD_IOMMU_V1 page table mode and the device
1765 		 * is enabling for PPR/ATS support (using v2 table),
1766 		 * we need to make sure that the domain type is identity map.
1767 		 */
1768 		if ((amd_iommu_pgtable == AMD_IOMMU_V1) &&
1769 		    def_domain->type != IOMMU_DOMAIN_IDENTITY) {
1770 			goto out;
1771 		}
1772 
1773 		if (dev_data->iommu_v2) {
1774 			if (pdev_pri_ats_enable(pdev) != 0)
1775 				goto out;
1776 
1777 			dev_data->ats.enabled = true;
1778 			dev_data->ats.qdep    = pci_ats_queue_depth(pdev);
1779 			dev_data->pri_tlp     = pci_prg_resp_pasid_required(pdev);
1780 		}
1781 	} else if (amd_iommu_iotlb_sup &&
1782 		   pci_enable_ats(pdev, PAGE_SHIFT) == 0) {
1783 		dev_data->ats.enabled = true;
1784 		dev_data->ats.qdep    = pci_ats_queue_depth(pdev);
1785 	}
1786 
1787 skip_ats_check:
1788 	ret = 0;
1789 
1790 	do_attach(dev_data, domain);
1791 
1792 	/*
1793 	 * We might boot into a crash-kernel here. The crashed kernel
1794 	 * left the caches in the IOMMU dirty. So we have to flush
1795 	 * here to evict all dirty stuff.
1796 	 */
1797 	amd_iommu_domain_flush_tlb_pde(domain);
1798 
1799 	amd_iommu_domain_flush_complete(domain);
1800 
1801 out:
1802 	spin_unlock(&dev_data->lock);
1803 
1804 	spin_unlock_irqrestore(&domain->lock, flags);
1805 
1806 	return ret;
1807 }
1808 
1809 /*
1810  * Removes a device from a protection domain (with devtable_lock held)
1811  */
detach_device(struct device * dev)1812 static void detach_device(struct device *dev)
1813 {
1814 	struct protection_domain *domain;
1815 	struct iommu_dev_data *dev_data;
1816 	unsigned long flags;
1817 
1818 	dev_data = dev_iommu_priv_get(dev);
1819 	domain   = dev_data->domain;
1820 
1821 	spin_lock_irqsave(&domain->lock, flags);
1822 
1823 	spin_lock(&dev_data->lock);
1824 
1825 	/*
1826 	 * First check if the device is still attached. It might already
1827 	 * be detached from its domain because the generic
1828 	 * iommu_detach_group code detached it and we try again here in
1829 	 * our alias handling.
1830 	 */
1831 	if (WARN_ON(!dev_data->domain))
1832 		goto out;
1833 
1834 	do_detach(dev_data);
1835 
1836 	if (!dev_is_pci(dev))
1837 		goto out;
1838 
1839 	if (domain->flags & PD_IOMMUV2_MASK && dev_data->iommu_v2)
1840 		pdev_iommuv2_disable(to_pci_dev(dev));
1841 	else if (dev_data->ats.enabled)
1842 		pci_disable_ats(to_pci_dev(dev));
1843 
1844 	dev_data->ats.enabled = false;
1845 
1846 out:
1847 	spin_unlock(&dev_data->lock);
1848 
1849 	spin_unlock_irqrestore(&domain->lock, flags);
1850 }
1851 
amd_iommu_probe_device(struct device * dev)1852 static struct iommu_device *amd_iommu_probe_device(struct device *dev)
1853 {
1854 	struct iommu_device *iommu_dev;
1855 	struct amd_iommu *iommu;
1856 	int ret;
1857 
1858 	if (!check_device(dev))
1859 		return ERR_PTR(-ENODEV);
1860 
1861 	iommu = rlookup_amd_iommu(dev);
1862 	if (!iommu)
1863 		return ERR_PTR(-ENODEV);
1864 
1865 	/* Not registered yet? */
1866 	if (!iommu->iommu.ops)
1867 		return ERR_PTR(-ENODEV);
1868 
1869 	if (dev_iommu_priv_get(dev))
1870 		return &iommu->iommu;
1871 
1872 	ret = iommu_init_device(iommu, dev);
1873 	if (ret) {
1874 		if (ret != -ENOTSUPP)
1875 			dev_err(dev, "Failed to initialize - trying to proceed anyway\n");
1876 		iommu_dev = ERR_PTR(ret);
1877 		iommu_ignore_device(iommu, dev);
1878 	} else {
1879 		amd_iommu_set_pci_msi_domain(dev, iommu);
1880 		iommu_dev = &iommu->iommu;
1881 	}
1882 
1883 	iommu_completion_wait(iommu);
1884 
1885 	return iommu_dev;
1886 }
1887 
amd_iommu_probe_finalize(struct device * dev)1888 static void amd_iommu_probe_finalize(struct device *dev)
1889 {
1890 	/* Domains are initialized for this device - have a look what we ended up with */
1891 	set_dma_ops(dev, NULL);
1892 	iommu_setup_dma_ops(dev, 0, U64_MAX);
1893 }
1894 
amd_iommu_release_device(struct device * dev)1895 static void amd_iommu_release_device(struct device *dev)
1896 {
1897 	struct amd_iommu *iommu;
1898 
1899 	if (!check_device(dev))
1900 		return;
1901 
1902 	iommu = rlookup_amd_iommu(dev);
1903 	if (!iommu)
1904 		return;
1905 
1906 	amd_iommu_uninit_device(dev);
1907 	iommu_completion_wait(iommu);
1908 }
1909 
amd_iommu_device_group(struct device * dev)1910 static struct iommu_group *amd_iommu_device_group(struct device *dev)
1911 {
1912 	if (dev_is_pci(dev))
1913 		return pci_device_group(dev);
1914 
1915 	return acpihid_device_group(dev);
1916 }
1917 
1918 /*****************************************************************************
1919  *
1920  * The next functions belong to the dma_ops mapping/unmapping code.
1921  *
1922  *****************************************************************************/
1923 
update_device_table(struct protection_domain * domain)1924 static void update_device_table(struct protection_domain *domain)
1925 {
1926 	struct iommu_dev_data *dev_data;
1927 
1928 	list_for_each_entry(dev_data, &domain->dev_list, list) {
1929 		struct amd_iommu *iommu = rlookup_amd_iommu(dev_data->dev);
1930 
1931 		if (!iommu)
1932 			continue;
1933 		set_dte_entry(iommu, dev_data->devid, domain,
1934 			      dev_data->ats.enabled, dev_data->iommu_v2);
1935 		clone_aliases(iommu, dev_data->dev);
1936 	}
1937 }
1938 
amd_iommu_update_and_flush_device_table(struct protection_domain * domain)1939 void amd_iommu_update_and_flush_device_table(struct protection_domain *domain)
1940 {
1941 	update_device_table(domain);
1942 	domain_flush_devices(domain);
1943 }
1944 
amd_iommu_domain_update(struct protection_domain * domain)1945 void amd_iommu_domain_update(struct protection_domain *domain)
1946 {
1947 	/* Update device table */
1948 	amd_iommu_update_and_flush_device_table(domain);
1949 
1950 	/* Flush domain TLB(s) and wait for completion */
1951 	amd_iommu_domain_flush_tlb_pde(domain);
1952 	amd_iommu_domain_flush_complete(domain);
1953 }
1954 
1955 /*****************************************************************************
1956  *
1957  * The following functions belong to the exported interface of AMD IOMMU
1958  *
1959  * This interface allows access to lower level functions of the IOMMU
1960  * like protection domain handling and assignement of devices to domains
1961  * which is not possible with the dma_ops interface.
1962  *
1963  *****************************************************************************/
1964 
cleanup_domain(struct protection_domain * domain)1965 static void cleanup_domain(struct protection_domain *domain)
1966 {
1967 	struct iommu_dev_data *entry;
1968 	unsigned long flags;
1969 
1970 	spin_lock_irqsave(&domain->lock, flags);
1971 
1972 	while (!list_empty(&domain->dev_list)) {
1973 		entry = list_first_entry(&domain->dev_list,
1974 					 struct iommu_dev_data, list);
1975 		BUG_ON(!entry->domain);
1976 		do_detach(entry);
1977 	}
1978 
1979 	spin_unlock_irqrestore(&domain->lock, flags);
1980 }
1981 
protection_domain_free(struct protection_domain * domain)1982 static void protection_domain_free(struct protection_domain *domain)
1983 {
1984 	if (!domain)
1985 		return;
1986 
1987 	if (domain->iop.pgtbl_cfg.tlb)
1988 		free_io_pgtable_ops(&domain->iop.iop.ops);
1989 
1990 	if (domain->id)
1991 		domain_id_free(domain->id);
1992 
1993 	kfree(domain);
1994 }
1995 
protection_domain_init_v1(struct protection_domain * domain,int mode)1996 static int protection_domain_init_v1(struct protection_domain *domain, int mode)
1997 {
1998 	u64 *pt_root = NULL;
1999 
2000 	BUG_ON(mode < PAGE_MODE_NONE || mode > PAGE_MODE_6_LEVEL);
2001 
2002 	spin_lock_init(&domain->lock);
2003 	domain->id = domain_id_alloc();
2004 	if (!domain->id)
2005 		return -ENOMEM;
2006 	INIT_LIST_HEAD(&domain->dev_list);
2007 
2008 	if (mode != PAGE_MODE_NONE) {
2009 		pt_root = (void *)get_zeroed_page(GFP_KERNEL);
2010 		if (!pt_root) {
2011 			domain_id_free(domain->id);
2012 			return -ENOMEM;
2013 		}
2014 	}
2015 
2016 	amd_iommu_domain_set_pgtable(domain, pt_root, mode);
2017 
2018 	return 0;
2019 }
2020 
protection_domain_init_v2(struct protection_domain * domain)2021 static int protection_domain_init_v2(struct protection_domain *domain)
2022 {
2023 	spin_lock_init(&domain->lock);
2024 	domain->id = domain_id_alloc();
2025 	if (!domain->id)
2026 		return -ENOMEM;
2027 	INIT_LIST_HEAD(&domain->dev_list);
2028 
2029 	domain->flags |= PD_GIOV_MASK;
2030 
2031 	if (domain_enable_v2(domain, 1)) {
2032 		domain_id_free(domain->id);
2033 		return -ENOMEM;
2034 	}
2035 
2036 	return 0;
2037 }
2038 
protection_domain_alloc(unsigned int type)2039 static struct protection_domain *protection_domain_alloc(unsigned int type)
2040 {
2041 	struct io_pgtable_ops *pgtbl_ops;
2042 	struct protection_domain *domain;
2043 	int pgtable = amd_iommu_pgtable;
2044 	int mode = DEFAULT_PGTABLE_LEVEL;
2045 	int ret;
2046 
2047 	domain = kzalloc(sizeof(*domain), GFP_KERNEL);
2048 	if (!domain)
2049 		return NULL;
2050 
2051 	/*
2052 	 * Force IOMMU v1 page table when iommu=pt and
2053 	 * when allocating domain for pass-through devices.
2054 	 */
2055 	if (type == IOMMU_DOMAIN_IDENTITY) {
2056 		pgtable = AMD_IOMMU_V1;
2057 		mode = PAGE_MODE_NONE;
2058 	} else if (type == IOMMU_DOMAIN_UNMANAGED) {
2059 		pgtable = AMD_IOMMU_V1;
2060 	}
2061 
2062 	switch (pgtable) {
2063 	case AMD_IOMMU_V1:
2064 		ret = protection_domain_init_v1(domain, mode);
2065 		break;
2066 	case AMD_IOMMU_V2:
2067 		ret = protection_domain_init_v2(domain);
2068 		break;
2069 	default:
2070 		ret = -EINVAL;
2071 	}
2072 
2073 	if (ret)
2074 		goto out_err;
2075 
2076 	pgtbl_ops = alloc_io_pgtable_ops(pgtable, &domain->iop.pgtbl_cfg, domain);
2077 	if (!pgtbl_ops) {
2078 		domain_id_free(domain->id);
2079 		goto out_err;
2080 	}
2081 
2082 	return domain;
2083 out_err:
2084 	kfree(domain);
2085 	return NULL;
2086 }
2087 
amd_iommu_domain_alloc(unsigned type)2088 static struct iommu_domain *amd_iommu_domain_alloc(unsigned type)
2089 {
2090 	struct protection_domain *domain;
2091 
2092 	/*
2093 	 * Since DTE[Mode]=0 is prohibited on SNP-enabled system,
2094 	 * default to use IOMMU_DOMAIN_DMA[_FQ].
2095 	 */
2096 	if (amd_iommu_snp_en && (type == IOMMU_DOMAIN_IDENTITY))
2097 		return NULL;
2098 
2099 	domain = protection_domain_alloc(type);
2100 	if (!domain)
2101 		return NULL;
2102 
2103 	domain->domain.geometry.aperture_start = 0;
2104 	domain->domain.geometry.aperture_end   = ~0ULL;
2105 	domain->domain.geometry.force_aperture = true;
2106 
2107 	return &domain->domain;
2108 }
2109 
amd_iommu_domain_free(struct iommu_domain * dom)2110 static void amd_iommu_domain_free(struct iommu_domain *dom)
2111 {
2112 	struct protection_domain *domain;
2113 
2114 	domain = to_pdomain(dom);
2115 
2116 	if (domain->dev_cnt > 0)
2117 		cleanup_domain(domain);
2118 
2119 	BUG_ON(domain->dev_cnt != 0);
2120 
2121 	if (!dom)
2122 		return;
2123 
2124 	if (domain->flags & PD_IOMMUV2_MASK)
2125 		free_gcr3_table(domain);
2126 
2127 	protection_domain_free(domain);
2128 }
2129 
amd_iommu_detach_device(struct iommu_domain * dom,struct device * dev)2130 static void amd_iommu_detach_device(struct iommu_domain *dom,
2131 				    struct device *dev)
2132 {
2133 	struct iommu_dev_data *dev_data = dev_iommu_priv_get(dev);
2134 	struct amd_iommu *iommu;
2135 
2136 	if (!check_device(dev))
2137 		return;
2138 
2139 	if (dev_data->domain != NULL)
2140 		detach_device(dev);
2141 
2142 	iommu = rlookup_amd_iommu(dev);
2143 	if (!iommu)
2144 		return;
2145 
2146 #ifdef CONFIG_IRQ_REMAP
2147 	if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) &&
2148 	    (dom->type == IOMMU_DOMAIN_UNMANAGED))
2149 		dev_data->use_vapic = 0;
2150 #endif
2151 
2152 	iommu_completion_wait(iommu);
2153 }
2154 
amd_iommu_attach_device(struct iommu_domain * dom,struct device * dev)2155 static int amd_iommu_attach_device(struct iommu_domain *dom,
2156 				   struct device *dev)
2157 {
2158 	struct protection_domain *domain = to_pdomain(dom);
2159 	struct iommu_dev_data *dev_data;
2160 	struct amd_iommu *iommu;
2161 	int ret;
2162 
2163 	if (!check_device(dev))
2164 		return -EINVAL;
2165 
2166 	dev_data = dev_iommu_priv_get(dev);
2167 	dev_data->defer_attach = false;
2168 
2169 	iommu = rlookup_amd_iommu(dev);
2170 	if (!iommu)
2171 		return -EINVAL;
2172 
2173 	if (dev_data->domain)
2174 		detach_device(dev);
2175 
2176 	ret = attach_device(dev, domain);
2177 
2178 #ifdef CONFIG_IRQ_REMAP
2179 	if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir)) {
2180 		if (dom->type == IOMMU_DOMAIN_UNMANAGED)
2181 			dev_data->use_vapic = 1;
2182 		else
2183 			dev_data->use_vapic = 0;
2184 	}
2185 #endif
2186 
2187 	iommu_completion_wait(iommu);
2188 
2189 	return ret;
2190 }
2191 
amd_iommu_iotlb_sync_map(struct iommu_domain * dom,unsigned long iova,size_t size)2192 static void amd_iommu_iotlb_sync_map(struct iommu_domain *dom,
2193 				     unsigned long iova, size_t size)
2194 {
2195 	struct protection_domain *domain = to_pdomain(dom);
2196 	struct io_pgtable_ops *ops = &domain->iop.iop.ops;
2197 
2198 	if (ops->map_pages)
2199 		domain_flush_np_cache(domain, iova, size);
2200 }
2201 
amd_iommu_map_pages(struct iommu_domain * dom,unsigned long iova,phys_addr_t paddr,size_t pgsize,size_t pgcount,int iommu_prot,gfp_t gfp,size_t * mapped)2202 static int amd_iommu_map_pages(struct iommu_domain *dom, unsigned long iova,
2203 			       phys_addr_t paddr, size_t pgsize, size_t pgcount,
2204 			       int iommu_prot, gfp_t gfp, size_t *mapped)
2205 {
2206 	struct protection_domain *domain = to_pdomain(dom);
2207 	struct io_pgtable_ops *ops = &domain->iop.iop.ops;
2208 	int prot = 0;
2209 	int ret = -EINVAL;
2210 
2211 	if ((amd_iommu_pgtable == AMD_IOMMU_V1) &&
2212 	    (domain->iop.mode == PAGE_MODE_NONE))
2213 		return -EINVAL;
2214 
2215 	if (iommu_prot & IOMMU_READ)
2216 		prot |= IOMMU_PROT_IR;
2217 	if (iommu_prot & IOMMU_WRITE)
2218 		prot |= IOMMU_PROT_IW;
2219 
2220 	if (ops->map_pages) {
2221 		ret = ops->map_pages(ops, iova, paddr, pgsize,
2222 				     pgcount, prot, gfp, mapped);
2223 	}
2224 
2225 	return ret;
2226 }
2227 
amd_iommu_iotlb_gather_add_page(struct iommu_domain * domain,struct iommu_iotlb_gather * gather,unsigned long iova,size_t size)2228 static void amd_iommu_iotlb_gather_add_page(struct iommu_domain *domain,
2229 					    struct iommu_iotlb_gather *gather,
2230 					    unsigned long iova, size_t size)
2231 {
2232 	/*
2233 	 * AMD's IOMMU can flush as many pages as necessary in a single flush.
2234 	 * Unless we run in a virtual machine, which can be inferred according
2235 	 * to whether "non-present cache" is on, it is probably best to prefer
2236 	 * (potentially) too extensive TLB flushing (i.e., more misses) over
2237 	 * mutliple TLB flushes (i.e., more flushes). For virtual machines the
2238 	 * hypervisor needs to synchronize the host IOMMU PTEs with those of
2239 	 * the guest, and the trade-off is different: unnecessary TLB flushes
2240 	 * should be avoided.
2241 	 */
2242 	if (amd_iommu_np_cache &&
2243 	    iommu_iotlb_gather_is_disjoint(gather, iova, size))
2244 		iommu_iotlb_sync(domain, gather);
2245 
2246 	iommu_iotlb_gather_add_range(gather, iova, size);
2247 }
2248 
amd_iommu_unmap_pages(struct iommu_domain * dom,unsigned long iova,size_t pgsize,size_t pgcount,struct iommu_iotlb_gather * gather)2249 static size_t amd_iommu_unmap_pages(struct iommu_domain *dom, unsigned long iova,
2250 				    size_t pgsize, size_t pgcount,
2251 				    struct iommu_iotlb_gather *gather)
2252 {
2253 	struct protection_domain *domain = to_pdomain(dom);
2254 	struct io_pgtable_ops *ops = &domain->iop.iop.ops;
2255 	size_t r;
2256 
2257 	if ((amd_iommu_pgtable == AMD_IOMMU_V1) &&
2258 	    (domain->iop.mode == PAGE_MODE_NONE))
2259 		return 0;
2260 
2261 	r = (ops->unmap_pages) ? ops->unmap_pages(ops, iova, pgsize, pgcount, NULL) : 0;
2262 
2263 	if (r)
2264 		amd_iommu_iotlb_gather_add_page(dom, gather, iova, r);
2265 
2266 	return r;
2267 }
2268 
amd_iommu_iova_to_phys(struct iommu_domain * dom,dma_addr_t iova)2269 static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom,
2270 					  dma_addr_t iova)
2271 {
2272 	struct protection_domain *domain = to_pdomain(dom);
2273 	struct io_pgtable_ops *ops = &domain->iop.iop.ops;
2274 
2275 	return ops->iova_to_phys(ops, iova);
2276 }
2277 
amd_iommu_capable(struct device * dev,enum iommu_cap cap)2278 static bool amd_iommu_capable(struct device *dev, enum iommu_cap cap)
2279 {
2280 	switch (cap) {
2281 	case IOMMU_CAP_CACHE_COHERENCY:
2282 		return true;
2283 	case IOMMU_CAP_INTR_REMAP:
2284 		return (irq_remapping_enabled == 1);
2285 	case IOMMU_CAP_NOEXEC:
2286 		return false;
2287 	case IOMMU_CAP_PRE_BOOT_PROTECTION:
2288 		return amdr_ivrs_remap_support;
2289 	default:
2290 		break;
2291 	}
2292 
2293 	return false;
2294 }
2295 
amd_iommu_get_resv_regions(struct device * dev,struct list_head * head)2296 static void amd_iommu_get_resv_regions(struct device *dev,
2297 				       struct list_head *head)
2298 {
2299 	struct iommu_resv_region *region;
2300 	struct unity_map_entry *entry;
2301 	struct amd_iommu *iommu;
2302 	struct amd_iommu_pci_seg *pci_seg;
2303 	int devid, sbdf;
2304 
2305 	sbdf = get_device_sbdf_id(dev);
2306 	if (sbdf < 0)
2307 		return;
2308 
2309 	devid = PCI_SBDF_TO_DEVID(sbdf);
2310 	iommu = rlookup_amd_iommu(dev);
2311 	if (!iommu)
2312 		return;
2313 	pci_seg = iommu->pci_seg;
2314 
2315 	list_for_each_entry(entry, &pci_seg->unity_map, list) {
2316 		int type, prot = 0;
2317 		size_t length;
2318 
2319 		if (devid < entry->devid_start || devid > entry->devid_end)
2320 			continue;
2321 
2322 		type   = IOMMU_RESV_DIRECT;
2323 		length = entry->address_end - entry->address_start;
2324 		if (entry->prot & IOMMU_PROT_IR)
2325 			prot |= IOMMU_READ;
2326 		if (entry->prot & IOMMU_PROT_IW)
2327 			prot |= IOMMU_WRITE;
2328 		if (entry->prot & IOMMU_UNITY_MAP_FLAG_EXCL_RANGE)
2329 			/* Exclusion range */
2330 			type = IOMMU_RESV_RESERVED;
2331 
2332 		region = iommu_alloc_resv_region(entry->address_start,
2333 						 length, prot, type,
2334 						 GFP_KERNEL);
2335 		if (!region) {
2336 			dev_err(dev, "Out of memory allocating dm-regions\n");
2337 			return;
2338 		}
2339 		list_add_tail(&region->list, head);
2340 	}
2341 
2342 	region = iommu_alloc_resv_region(MSI_RANGE_START,
2343 					 MSI_RANGE_END - MSI_RANGE_START + 1,
2344 					 0, IOMMU_RESV_MSI, GFP_KERNEL);
2345 	if (!region)
2346 		return;
2347 	list_add_tail(&region->list, head);
2348 
2349 	region = iommu_alloc_resv_region(HT_RANGE_START,
2350 					 HT_RANGE_END - HT_RANGE_START + 1,
2351 					 0, IOMMU_RESV_RESERVED, GFP_KERNEL);
2352 	if (!region)
2353 		return;
2354 	list_add_tail(&region->list, head);
2355 }
2356 
amd_iommu_is_attach_deferred(struct device * dev)2357 bool amd_iommu_is_attach_deferred(struct device *dev)
2358 {
2359 	struct iommu_dev_data *dev_data = dev_iommu_priv_get(dev);
2360 
2361 	return dev_data->defer_attach;
2362 }
2363 EXPORT_SYMBOL_GPL(amd_iommu_is_attach_deferred);
2364 
amd_iommu_flush_iotlb_all(struct iommu_domain * domain)2365 static void amd_iommu_flush_iotlb_all(struct iommu_domain *domain)
2366 {
2367 	struct protection_domain *dom = to_pdomain(domain);
2368 	unsigned long flags;
2369 
2370 	spin_lock_irqsave(&dom->lock, flags);
2371 	amd_iommu_domain_flush_tlb_pde(dom);
2372 	amd_iommu_domain_flush_complete(dom);
2373 	spin_unlock_irqrestore(&dom->lock, flags);
2374 }
2375 
amd_iommu_iotlb_sync(struct iommu_domain * domain,struct iommu_iotlb_gather * gather)2376 static void amd_iommu_iotlb_sync(struct iommu_domain *domain,
2377 				 struct iommu_iotlb_gather *gather)
2378 {
2379 	struct protection_domain *dom = to_pdomain(domain);
2380 	unsigned long flags;
2381 
2382 	spin_lock_irqsave(&dom->lock, flags);
2383 	domain_flush_pages(dom, gather->start, gather->end - gather->start, 1);
2384 	amd_iommu_domain_flush_complete(dom);
2385 	spin_unlock_irqrestore(&dom->lock, flags);
2386 }
2387 
amd_iommu_def_domain_type(struct device * dev)2388 static int amd_iommu_def_domain_type(struct device *dev)
2389 {
2390 	struct iommu_dev_data *dev_data;
2391 
2392 	dev_data = dev_iommu_priv_get(dev);
2393 	if (!dev_data)
2394 		return 0;
2395 
2396 	/*
2397 	 * Do not identity map IOMMUv2 capable devices when memory encryption is
2398 	 * active, because some of those devices (AMD GPUs) don't have the
2399 	 * encryption bit in their DMA-mask and require remapping.
2400 	 */
2401 	if (!cc_platform_has(CC_ATTR_MEM_ENCRYPT) && dev_data->iommu_v2)
2402 		return IOMMU_DOMAIN_IDENTITY;
2403 
2404 	return 0;
2405 }
2406 
amd_iommu_enforce_cache_coherency(struct iommu_domain * domain)2407 static bool amd_iommu_enforce_cache_coherency(struct iommu_domain *domain)
2408 {
2409 	/* IOMMU_PTE_FC is always set */
2410 	return true;
2411 }
2412 
2413 const struct iommu_ops amd_iommu_ops = {
2414 	.capable = amd_iommu_capable,
2415 	.domain_alloc = amd_iommu_domain_alloc,
2416 	.probe_device = amd_iommu_probe_device,
2417 	.release_device = amd_iommu_release_device,
2418 	.probe_finalize = amd_iommu_probe_finalize,
2419 	.device_group = amd_iommu_device_group,
2420 	.get_resv_regions = amd_iommu_get_resv_regions,
2421 	.is_attach_deferred = amd_iommu_is_attach_deferred,
2422 	.pgsize_bitmap	= AMD_IOMMU_PGSIZES,
2423 	.def_domain_type = amd_iommu_def_domain_type,
2424 	.default_domain_ops = &(const struct iommu_domain_ops) {
2425 		.attach_dev	= amd_iommu_attach_device,
2426 		.detach_dev	= amd_iommu_detach_device,
2427 		.map_pages	= amd_iommu_map_pages,
2428 		.unmap_pages	= amd_iommu_unmap_pages,
2429 		.iotlb_sync_map	= amd_iommu_iotlb_sync_map,
2430 		.iova_to_phys	= amd_iommu_iova_to_phys,
2431 		.flush_iotlb_all = amd_iommu_flush_iotlb_all,
2432 		.iotlb_sync	= amd_iommu_iotlb_sync,
2433 		.free		= amd_iommu_domain_free,
2434 		.enforce_cache_coherency = amd_iommu_enforce_cache_coherency,
2435 	}
2436 };
2437 
2438 /*****************************************************************************
2439  *
2440  * The next functions do a basic initialization of IOMMU for pass through
2441  * mode
2442  *
2443  * In passthrough mode the IOMMU is initialized and enabled but not used for
2444  * DMA-API translation.
2445  *
2446  *****************************************************************************/
2447 
2448 /* IOMMUv2 specific functions */
amd_iommu_register_ppr_notifier(struct notifier_block * nb)2449 int amd_iommu_register_ppr_notifier(struct notifier_block *nb)
2450 {
2451 	return atomic_notifier_chain_register(&ppr_notifier, nb);
2452 }
2453 EXPORT_SYMBOL(amd_iommu_register_ppr_notifier);
2454 
amd_iommu_unregister_ppr_notifier(struct notifier_block * nb)2455 int amd_iommu_unregister_ppr_notifier(struct notifier_block *nb)
2456 {
2457 	return atomic_notifier_chain_unregister(&ppr_notifier, nb);
2458 }
2459 EXPORT_SYMBOL(amd_iommu_unregister_ppr_notifier);
2460 
amd_iommu_domain_direct_map(struct iommu_domain * dom)2461 void amd_iommu_domain_direct_map(struct iommu_domain *dom)
2462 {
2463 	struct protection_domain *domain = to_pdomain(dom);
2464 	unsigned long flags;
2465 
2466 	spin_lock_irqsave(&domain->lock, flags);
2467 
2468 	if (domain->iop.pgtbl_cfg.tlb)
2469 		free_io_pgtable_ops(&domain->iop.iop.ops);
2470 
2471 	spin_unlock_irqrestore(&domain->lock, flags);
2472 }
2473 EXPORT_SYMBOL(amd_iommu_domain_direct_map);
2474 
2475 /* Note: This function expects iommu_domain->lock to be held prior calling the function. */
domain_enable_v2(struct protection_domain * domain,int pasids)2476 static int domain_enable_v2(struct protection_domain *domain, int pasids)
2477 {
2478 	int levels;
2479 
2480 	/* Number of GCR3 table levels required */
2481 	for (levels = 0; (pasids - 1) & ~0x1ff; pasids >>= 9)
2482 		levels += 1;
2483 
2484 	if (levels > amd_iommu_max_glx_val)
2485 		return -EINVAL;
2486 
2487 	domain->gcr3_tbl = (void *)get_zeroed_page(GFP_ATOMIC);
2488 	if (domain->gcr3_tbl == NULL)
2489 		return -ENOMEM;
2490 
2491 	domain->glx      = levels;
2492 	domain->flags   |= PD_IOMMUV2_MASK;
2493 
2494 	amd_iommu_domain_update(domain);
2495 
2496 	return 0;
2497 }
2498 
amd_iommu_domain_enable_v2(struct iommu_domain * dom,int pasids)2499 int amd_iommu_domain_enable_v2(struct iommu_domain *dom, int pasids)
2500 {
2501 	struct protection_domain *pdom = to_pdomain(dom);
2502 	unsigned long flags;
2503 	int ret;
2504 
2505 	spin_lock_irqsave(&pdom->lock, flags);
2506 
2507 	/*
2508 	 * Save us all sanity checks whether devices already in the
2509 	 * domain support IOMMUv2. Just force that the domain has no
2510 	 * devices attached when it is switched into IOMMUv2 mode.
2511 	 */
2512 	ret = -EBUSY;
2513 	if (pdom->dev_cnt > 0 || pdom->flags & PD_IOMMUV2_MASK)
2514 		goto out;
2515 
2516 	if (!pdom->gcr3_tbl)
2517 		ret = domain_enable_v2(pdom, pasids);
2518 
2519 out:
2520 	spin_unlock_irqrestore(&pdom->lock, flags);
2521 	return ret;
2522 }
2523 EXPORT_SYMBOL(amd_iommu_domain_enable_v2);
2524 
__flush_pasid(struct protection_domain * domain,u32 pasid,u64 address,bool size)2525 static int __flush_pasid(struct protection_domain *domain, u32 pasid,
2526 			 u64 address, bool size)
2527 {
2528 	struct iommu_dev_data *dev_data;
2529 	struct iommu_cmd cmd;
2530 	int i, ret;
2531 
2532 	if (!(domain->flags & PD_IOMMUV2_MASK))
2533 		return -EINVAL;
2534 
2535 	build_inv_iommu_pasid(&cmd, domain->id, pasid, address, size);
2536 
2537 	/*
2538 	 * IOMMU TLB needs to be flushed before Device TLB to
2539 	 * prevent device TLB refill from IOMMU TLB
2540 	 */
2541 	for (i = 0; i < amd_iommu_get_num_iommus(); ++i) {
2542 		if (domain->dev_iommu[i] == 0)
2543 			continue;
2544 
2545 		ret = iommu_queue_command(amd_iommus[i], &cmd);
2546 		if (ret != 0)
2547 			goto out;
2548 	}
2549 
2550 	/* Wait until IOMMU TLB flushes are complete */
2551 	amd_iommu_domain_flush_complete(domain);
2552 
2553 	/* Now flush device TLBs */
2554 	list_for_each_entry(dev_data, &domain->dev_list, list) {
2555 		struct amd_iommu *iommu;
2556 		int qdep;
2557 
2558 		/*
2559 		   There might be non-IOMMUv2 capable devices in an IOMMUv2
2560 		 * domain.
2561 		 */
2562 		if (!dev_data->ats.enabled)
2563 			continue;
2564 
2565 		qdep  = dev_data->ats.qdep;
2566 		iommu = rlookup_amd_iommu(dev_data->dev);
2567 		if (!iommu)
2568 			continue;
2569 		build_inv_iotlb_pasid(&cmd, dev_data->devid, pasid,
2570 				      qdep, address, size);
2571 
2572 		ret = iommu_queue_command(iommu, &cmd);
2573 		if (ret != 0)
2574 			goto out;
2575 	}
2576 
2577 	/* Wait until all device TLBs are flushed */
2578 	amd_iommu_domain_flush_complete(domain);
2579 
2580 	ret = 0;
2581 
2582 out:
2583 
2584 	return ret;
2585 }
2586 
__amd_iommu_flush_page(struct protection_domain * domain,u32 pasid,u64 address)2587 static int __amd_iommu_flush_page(struct protection_domain *domain, u32 pasid,
2588 				  u64 address)
2589 {
2590 	return __flush_pasid(domain, pasid, address, false);
2591 }
2592 
amd_iommu_flush_page(struct iommu_domain * dom,u32 pasid,u64 address)2593 int amd_iommu_flush_page(struct iommu_domain *dom, u32 pasid,
2594 			 u64 address)
2595 {
2596 	struct protection_domain *domain = to_pdomain(dom);
2597 	unsigned long flags;
2598 	int ret;
2599 
2600 	spin_lock_irqsave(&domain->lock, flags);
2601 	ret = __amd_iommu_flush_page(domain, pasid, address);
2602 	spin_unlock_irqrestore(&domain->lock, flags);
2603 
2604 	return ret;
2605 }
2606 EXPORT_SYMBOL(amd_iommu_flush_page);
2607 
__amd_iommu_flush_tlb(struct protection_domain * domain,u32 pasid)2608 static int __amd_iommu_flush_tlb(struct protection_domain *domain, u32 pasid)
2609 {
2610 	return __flush_pasid(domain, pasid, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
2611 			     true);
2612 }
2613 
amd_iommu_flush_tlb(struct iommu_domain * dom,u32 pasid)2614 int amd_iommu_flush_tlb(struct iommu_domain *dom, u32 pasid)
2615 {
2616 	struct protection_domain *domain = to_pdomain(dom);
2617 	unsigned long flags;
2618 	int ret;
2619 
2620 	spin_lock_irqsave(&domain->lock, flags);
2621 	ret = __amd_iommu_flush_tlb(domain, pasid);
2622 	spin_unlock_irqrestore(&domain->lock, flags);
2623 
2624 	return ret;
2625 }
2626 EXPORT_SYMBOL(amd_iommu_flush_tlb);
2627 
__get_gcr3_pte(u64 * root,int level,u32 pasid,bool alloc)2628 static u64 *__get_gcr3_pte(u64 *root, int level, u32 pasid, bool alloc)
2629 {
2630 	int index;
2631 	u64 *pte;
2632 
2633 	while (true) {
2634 
2635 		index = (pasid >> (9 * level)) & 0x1ff;
2636 		pte   = &root[index];
2637 
2638 		if (level == 0)
2639 			break;
2640 
2641 		if (!(*pte & GCR3_VALID)) {
2642 			if (!alloc)
2643 				return NULL;
2644 
2645 			root = (void *)get_zeroed_page(GFP_ATOMIC);
2646 			if (root == NULL)
2647 				return NULL;
2648 
2649 			*pte = iommu_virt_to_phys(root) | GCR3_VALID;
2650 		}
2651 
2652 		root = iommu_phys_to_virt(*pte & PAGE_MASK);
2653 
2654 		level -= 1;
2655 	}
2656 
2657 	return pte;
2658 }
2659 
__set_gcr3(struct protection_domain * domain,u32 pasid,unsigned long cr3)2660 static int __set_gcr3(struct protection_domain *domain, u32 pasid,
2661 		      unsigned long cr3)
2662 {
2663 	u64 *pte;
2664 
2665 	if (domain->iop.mode != PAGE_MODE_NONE)
2666 		return -EINVAL;
2667 
2668 	pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, true);
2669 	if (pte == NULL)
2670 		return -ENOMEM;
2671 
2672 	*pte = (cr3 & PAGE_MASK) | GCR3_VALID;
2673 
2674 	return __amd_iommu_flush_tlb(domain, pasid);
2675 }
2676 
__clear_gcr3(struct protection_domain * domain,u32 pasid)2677 static int __clear_gcr3(struct protection_domain *domain, u32 pasid)
2678 {
2679 	u64 *pte;
2680 
2681 	if (domain->iop.mode != PAGE_MODE_NONE)
2682 		return -EINVAL;
2683 
2684 	pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, false);
2685 	if (pte == NULL)
2686 		return 0;
2687 
2688 	*pte = 0;
2689 
2690 	return __amd_iommu_flush_tlb(domain, pasid);
2691 }
2692 
amd_iommu_domain_set_gcr3(struct iommu_domain * dom,u32 pasid,unsigned long cr3)2693 int amd_iommu_domain_set_gcr3(struct iommu_domain *dom, u32 pasid,
2694 			      unsigned long cr3)
2695 {
2696 	struct protection_domain *domain = to_pdomain(dom);
2697 	unsigned long flags;
2698 	int ret;
2699 
2700 	spin_lock_irqsave(&domain->lock, flags);
2701 	ret = __set_gcr3(domain, pasid, cr3);
2702 	spin_unlock_irqrestore(&domain->lock, flags);
2703 
2704 	return ret;
2705 }
2706 EXPORT_SYMBOL(amd_iommu_domain_set_gcr3);
2707 
amd_iommu_domain_clear_gcr3(struct iommu_domain * dom,u32 pasid)2708 int amd_iommu_domain_clear_gcr3(struct iommu_domain *dom, u32 pasid)
2709 {
2710 	struct protection_domain *domain = to_pdomain(dom);
2711 	unsigned long flags;
2712 	int ret;
2713 
2714 	spin_lock_irqsave(&domain->lock, flags);
2715 	ret = __clear_gcr3(domain, pasid);
2716 	spin_unlock_irqrestore(&domain->lock, flags);
2717 
2718 	return ret;
2719 }
2720 EXPORT_SYMBOL(amd_iommu_domain_clear_gcr3);
2721 
amd_iommu_complete_ppr(struct pci_dev * pdev,u32 pasid,int status,int tag)2722 int amd_iommu_complete_ppr(struct pci_dev *pdev, u32 pasid,
2723 			   int status, int tag)
2724 {
2725 	struct iommu_dev_data *dev_data;
2726 	struct amd_iommu *iommu;
2727 	struct iommu_cmd cmd;
2728 
2729 	dev_data = dev_iommu_priv_get(&pdev->dev);
2730 	iommu    = rlookup_amd_iommu(&pdev->dev);
2731 	if (!iommu)
2732 		return -ENODEV;
2733 
2734 	build_complete_ppr(&cmd, dev_data->devid, pasid, status,
2735 			   tag, dev_data->pri_tlp);
2736 
2737 	return iommu_queue_command(iommu, &cmd);
2738 }
2739 EXPORT_SYMBOL(amd_iommu_complete_ppr);
2740 
amd_iommu_device_info(struct pci_dev * pdev,struct amd_iommu_device_info * info)2741 int amd_iommu_device_info(struct pci_dev *pdev,
2742                           struct amd_iommu_device_info *info)
2743 {
2744 	int max_pasids;
2745 	int pos;
2746 
2747 	if (pdev == NULL || info == NULL)
2748 		return -EINVAL;
2749 
2750 	if (!amd_iommu_v2_supported())
2751 		return -EINVAL;
2752 
2753 	memset(info, 0, sizeof(*info));
2754 
2755 	if (pci_ats_supported(pdev))
2756 		info->flags |= AMD_IOMMU_DEVICE_FLAG_ATS_SUP;
2757 
2758 	pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
2759 	if (pos)
2760 		info->flags |= AMD_IOMMU_DEVICE_FLAG_PRI_SUP;
2761 
2762 	pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID);
2763 	if (pos) {
2764 		int features;
2765 
2766 		max_pasids = 1 << (9 * (amd_iommu_max_glx_val + 1));
2767 		max_pasids = min(max_pasids, (1 << 20));
2768 
2769 		info->flags |= AMD_IOMMU_DEVICE_FLAG_PASID_SUP;
2770 		info->max_pasids = min(pci_max_pasids(pdev), max_pasids);
2771 
2772 		features = pci_pasid_features(pdev);
2773 		if (features & PCI_PASID_CAP_EXEC)
2774 			info->flags |= AMD_IOMMU_DEVICE_FLAG_EXEC_SUP;
2775 		if (features & PCI_PASID_CAP_PRIV)
2776 			info->flags |= AMD_IOMMU_DEVICE_FLAG_PRIV_SUP;
2777 	}
2778 
2779 	return 0;
2780 }
2781 EXPORT_SYMBOL(amd_iommu_device_info);
2782 
2783 #ifdef CONFIG_IRQ_REMAP
2784 
2785 /*****************************************************************************
2786  *
2787  * Interrupt Remapping Implementation
2788  *
2789  *****************************************************************************/
2790 
2791 static struct irq_chip amd_ir_chip;
2792 static DEFINE_SPINLOCK(iommu_table_lock);
2793 
set_dte_irq_entry(struct amd_iommu * iommu,u16 devid,struct irq_remap_table * table)2794 static void set_dte_irq_entry(struct amd_iommu *iommu, u16 devid,
2795 			      struct irq_remap_table *table)
2796 {
2797 	u64 dte;
2798 	struct dev_table_entry *dev_table = get_dev_table(iommu);
2799 
2800 	dte	= dev_table[devid].data[2];
2801 	dte	&= ~DTE_IRQ_PHYS_ADDR_MASK;
2802 	dte	|= iommu_virt_to_phys(table->table);
2803 	dte	|= DTE_IRQ_REMAP_INTCTL;
2804 	dte	|= DTE_INTTABLEN;
2805 	dte	|= DTE_IRQ_REMAP_ENABLE;
2806 
2807 	dev_table[devid].data[2] = dte;
2808 }
2809 
get_irq_table(struct amd_iommu * iommu,u16 devid)2810 static struct irq_remap_table *get_irq_table(struct amd_iommu *iommu, u16 devid)
2811 {
2812 	struct irq_remap_table *table;
2813 	struct amd_iommu_pci_seg *pci_seg = iommu->pci_seg;
2814 
2815 	if (WARN_ONCE(!pci_seg->rlookup_table[devid],
2816 		      "%s: no iommu for devid %x:%x\n",
2817 		      __func__, pci_seg->id, devid))
2818 		return NULL;
2819 
2820 	table = pci_seg->irq_lookup_table[devid];
2821 	if (WARN_ONCE(!table, "%s: no table for devid %x:%x\n",
2822 		      __func__, pci_seg->id, devid))
2823 		return NULL;
2824 
2825 	return table;
2826 }
2827 
__alloc_irq_table(void)2828 static struct irq_remap_table *__alloc_irq_table(void)
2829 {
2830 	struct irq_remap_table *table;
2831 
2832 	table = kzalloc(sizeof(*table), GFP_KERNEL);
2833 	if (!table)
2834 		return NULL;
2835 
2836 	table->table = kmem_cache_alloc(amd_iommu_irq_cache, GFP_KERNEL);
2837 	if (!table->table) {
2838 		kfree(table);
2839 		return NULL;
2840 	}
2841 	raw_spin_lock_init(&table->lock);
2842 
2843 	if (!AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir))
2844 		memset(table->table, 0,
2845 		       MAX_IRQS_PER_TABLE * sizeof(u32));
2846 	else
2847 		memset(table->table, 0,
2848 		       (MAX_IRQS_PER_TABLE * (sizeof(u64) * 2)));
2849 	return table;
2850 }
2851 
set_remap_table_entry(struct amd_iommu * iommu,u16 devid,struct irq_remap_table * table)2852 static void set_remap_table_entry(struct amd_iommu *iommu, u16 devid,
2853 				  struct irq_remap_table *table)
2854 {
2855 	struct amd_iommu_pci_seg *pci_seg = iommu->pci_seg;
2856 
2857 	pci_seg->irq_lookup_table[devid] = table;
2858 	set_dte_irq_entry(iommu, devid, table);
2859 	iommu_flush_dte(iommu, devid);
2860 }
2861 
set_remap_table_entry_alias(struct pci_dev * pdev,u16 alias,void * data)2862 static int set_remap_table_entry_alias(struct pci_dev *pdev, u16 alias,
2863 				       void *data)
2864 {
2865 	struct irq_remap_table *table = data;
2866 	struct amd_iommu_pci_seg *pci_seg;
2867 	struct amd_iommu *iommu = rlookup_amd_iommu(&pdev->dev);
2868 
2869 	if (!iommu)
2870 		return -EINVAL;
2871 
2872 	pci_seg = iommu->pci_seg;
2873 	pci_seg->irq_lookup_table[alias] = table;
2874 	set_dte_irq_entry(iommu, alias, table);
2875 	iommu_flush_dte(pci_seg->rlookup_table[alias], alias);
2876 
2877 	return 0;
2878 }
2879 
alloc_irq_table(struct amd_iommu * iommu,u16 devid,struct pci_dev * pdev)2880 static struct irq_remap_table *alloc_irq_table(struct amd_iommu *iommu,
2881 					       u16 devid, struct pci_dev *pdev)
2882 {
2883 	struct irq_remap_table *table = NULL;
2884 	struct irq_remap_table *new_table = NULL;
2885 	struct amd_iommu_pci_seg *pci_seg;
2886 	unsigned long flags;
2887 	u16 alias;
2888 
2889 	spin_lock_irqsave(&iommu_table_lock, flags);
2890 
2891 	pci_seg = iommu->pci_seg;
2892 	table = pci_seg->irq_lookup_table[devid];
2893 	if (table)
2894 		goto out_unlock;
2895 
2896 	alias = pci_seg->alias_table[devid];
2897 	table = pci_seg->irq_lookup_table[alias];
2898 	if (table) {
2899 		set_remap_table_entry(iommu, devid, table);
2900 		goto out_wait;
2901 	}
2902 	spin_unlock_irqrestore(&iommu_table_lock, flags);
2903 
2904 	/* Nothing there yet, allocate new irq remapping table */
2905 	new_table = __alloc_irq_table();
2906 	if (!new_table)
2907 		return NULL;
2908 
2909 	spin_lock_irqsave(&iommu_table_lock, flags);
2910 
2911 	table = pci_seg->irq_lookup_table[devid];
2912 	if (table)
2913 		goto out_unlock;
2914 
2915 	table = pci_seg->irq_lookup_table[alias];
2916 	if (table) {
2917 		set_remap_table_entry(iommu, devid, table);
2918 		goto out_wait;
2919 	}
2920 
2921 	table = new_table;
2922 	new_table = NULL;
2923 
2924 	if (pdev)
2925 		pci_for_each_dma_alias(pdev, set_remap_table_entry_alias,
2926 				       table);
2927 	else
2928 		set_remap_table_entry(iommu, devid, table);
2929 
2930 	if (devid != alias)
2931 		set_remap_table_entry(iommu, alias, table);
2932 
2933 out_wait:
2934 	iommu_completion_wait(iommu);
2935 
2936 out_unlock:
2937 	spin_unlock_irqrestore(&iommu_table_lock, flags);
2938 
2939 	if (new_table) {
2940 		kmem_cache_free(amd_iommu_irq_cache, new_table->table);
2941 		kfree(new_table);
2942 	}
2943 	return table;
2944 }
2945 
alloc_irq_index(struct amd_iommu * iommu,u16 devid,int count,bool align,struct pci_dev * pdev)2946 static int alloc_irq_index(struct amd_iommu *iommu, u16 devid, int count,
2947 			   bool align, struct pci_dev *pdev)
2948 {
2949 	struct irq_remap_table *table;
2950 	int index, c, alignment = 1;
2951 	unsigned long flags;
2952 
2953 	table = alloc_irq_table(iommu, devid, pdev);
2954 	if (!table)
2955 		return -ENODEV;
2956 
2957 	if (align)
2958 		alignment = roundup_pow_of_two(count);
2959 
2960 	raw_spin_lock_irqsave(&table->lock, flags);
2961 
2962 	/* Scan table for free entries */
2963 	for (index = ALIGN(table->min_index, alignment), c = 0;
2964 	     index < MAX_IRQS_PER_TABLE;) {
2965 		if (!iommu->irte_ops->is_allocated(table, index)) {
2966 			c += 1;
2967 		} else {
2968 			c     = 0;
2969 			index = ALIGN(index + 1, alignment);
2970 			continue;
2971 		}
2972 
2973 		if (c == count)	{
2974 			for (; c != 0; --c)
2975 				iommu->irte_ops->set_allocated(table, index - c + 1);
2976 
2977 			index -= count - 1;
2978 			goto out;
2979 		}
2980 
2981 		index++;
2982 	}
2983 
2984 	index = -ENOSPC;
2985 
2986 out:
2987 	raw_spin_unlock_irqrestore(&table->lock, flags);
2988 
2989 	return index;
2990 }
2991 
modify_irte_ga(struct amd_iommu * iommu,u16 devid,int index,struct irte_ga * irte,struct amd_ir_data * data)2992 static int modify_irte_ga(struct amd_iommu *iommu, u16 devid, int index,
2993 			  struct irte_ga *irte, struct amd_ir_data *data)
2994 {
2995 	bool ret;
2996 	struct irq_remap_table *table;
2997 	unsigned long flags;
2998 	struct irte_ga *entry;
2999 
3000 	table = get_irq_table(iommu, devid);
3001 	if (!table)
3002 		return -ENOMEM;
3003 
3004 	raw_spin_lock_irqsave(&table->lock, flags);
3005 
3006 	entry = (struct irte_ga *)table->table;
3007 	entry = &entry[index];
3008 
3009 	ret = cmpxchg_double(&entry->lo.val, &entry->hi.val,
3010 			     entry->lo.val, entry->hi.val,
3011 			     irte->lo.val, irte->hi.val);
3012 	/*
3013 	 * We use cmpxchg16 to atomically update the 128-bit IRTE,
3014 	 * and it cannot be updated by the hardware or other processors
3015 	 * behind us, so the return value of cmpxchg16 should be the
3016 	 * same as the old value.
3017 	 */
3018 	WARN_ON(!ret);
3019 
3020 	if (data)
3021 		data->ref = entry;
3022 
3023 	raw_spin_unlock_irqrestore(&table->lock, flags);
3024 
3025 	iommu_flush_irt(iommu, devid);
3026 	iommu_completion_wait(iommu);
3027 
3028 	return 0;
3029 }
3030 
modify_irte(struct amd_iommu * iommu,u16 devid,int index,union irte * irte)3031 static int modify_irte(struct amd_iommu *iommu,
3032 		       u16 devid, int index, union irte *irte)
3033 {
3034 	struct irq_remap_table *table;
3035 	unsigned long flags;
3036 
3037 	table = get_irq_table(iommu, devid);
3038 	if (!table)
3039 		return -ENOMEM;
3040 
3041 	raw_spin_lock_irqsave(&table->lock, flags);
3042 	table->table[index] = irte->val;
3043 	raw_spin_unlock_irqrestore(&table->lock, flags);
3044 
3045 	iommu_flush_irt(iommu, devid);
3046 	iommu_completion_wait(iommu);
3047 
3048 	return 0;
3049 }
3050 
free_irte(struct amd_iommu * iommu,u16 devid,int index)3051 static void free_irte(struct amd_iommu *iommu, u16 devid, int index)
3052 {
3053 	struct irq_remap_table *table;
3054 	unsigned long flags;
3055 
3056 	table = get_irq_table(iommu, devid);
3057 	if (!table)
3058 		return;
3059 
3060 	raw_spin_lock_irqsave(&table->lock, flags);
3061 	iommu->irte_ops->clear_allocated(table, index);
3062 	raw_spin_unlock_irqrestore(&table->lock, flags);
3063 
3064 	iommu_flush_irt(iommu, devid);
3065 	iommu_completion_wait(iommu);
3066 }
3067 
irte_prepare(void * entry,u32 delivery_mode,bool dest_mode,u8 vector,u32 dest_apicid,int devid)3068 static void irte_prepare(void *entry,
3069 			 u32 delivery_mode, bool dest_mode,
3070 			 u8 vector, u32 dest_apicid, int devid)
3071 {
3072 	union irte *irte = (union irte *) entry;
3073 
3074 	irte->val                = 0;
3075 	irte->fields.vector      = vector;
3076 	irte->fields.int_type    = delivery_mode;
3077 	irte->fields.destination = dest_apicid;
3078 	irte->fields.dm          = dest_mode;
3079 	irte->fields.valid       = 1;
3080 }
3081 
irte_ga_prepare(void * entry,u32 delivery_mode,bool dest_mode,u8 vector,u32 dest_apicid,int devid)3082 static void irte_ga_prepare(void *entry,
3083 			    u32 delivery_mode, bool dest_mode,
3084 			    u8 vector, u32 dest_apicid, int devid)
3085 {
3086 	struct irte_ga *irte = (struct irte_ga *) entry;
3087 
3088 	irte->lo.val                      = 0;
3089 	irte->hi.val                      = 0;
3090 	irte->lo.fields_remap.int_type    = delivery_mode;
3091 	irte->lo.fields_remap.dm          = dest_mode;
3092 	irte->hi.fields.vector            = vector;
3093 	irte->lo.fields_remap.destination = APICID_TO_IRTE_DEST_LO(dest_apicid);
3094 	irte->hi.fields.destination       = APICID_TO_IRTE_DEST_HI(dest_apicid);
3095 	irte->lo.fields_remap.valid       = 1;
3096 }
3097 
irte_activate(struct amd_iommu * iommu,void * entry,u16 devid,u16 index)3098 static void irte_activate(struct amd_iommu *iommu, void *entry, u16 devid, u16 index)
3099 {
3100 	union irte *irte = (union irte *) entry;
3101 
3102 	irte->fields.valid = 1;
3103 	modify_irte(iommu, devid, index, irte);
3104 }
3105 
irte_ga_activate(struct amd_iommu * iommu,void * entry,u16 devid,u16 index)3106 static void irte_ga_activate(struct amd_iommu *iommu, void *entry, u16 devid, u16 index)
3107 {
3108 	struct irte_ga *irte = (struct irte_ga *) entry;
3109 
3110 	irte->lo.fields_remap.valid = 1;
3111 	modify_irte_ga(iommu, devid, index, irte, NULL);
3112 }
3113 
irte_deactivate(struct amd_iommu * iommu,void * entry,u16 devid,u16 index)3114 static void irte_deactivate(struct amd_iommu *iommu, void *entry, u16 devid, u16 index)
3115 {
3116 	union irte *irte = (union irte *) entry;
3117 
3118 	irte->fields.valid = 0;
3119 	modify_irte(iommu, devid, index, irte);
3120 }
3121 
irte_ga_deactivate(struct amd_iommu * iommu,void * entry,u16 devid,u16 index)3122 static void irte_ga_deactivate(struct amd_iommu *iommu, void *entry, u16 devid, u16 index)
3123 {
3124 	struct irte_ga *irte = (struct irte_ga *) entry;
3125 
3126 	irte->lo.fields_remap.valid = 0;
3127 	modify_irte_ga(iommu, devid, index, irte, NULL);
3128 }
3129 
irte_set_affinity(struct amd_iommu * iommu,void * entry,u16 devid,u16 index,u8 vector,u32 dest_apicid)3130 static void irte_set_affinity(struct amd_iommu *iommu, void *entry, u16 devid, u16 index,
3131 			      u8 vector, u32 dest_apicid)
3132 {
3133 	union irte *irte = (union irte *) entry;
3134 
3135 	irte->fields.vector = vector;
3136 	irte->fields.destination = dest_apicid;
3137 	modify_irte(iommu, devid, index, irte);
3138 }
3139 
irte_ga_set_affinity(struct amd_iommu * iommu,void * entry,u16 devid,u16 index,u8 vector,u32 dest_apicid)3140 static void irte_ga_set_affinity(struct amd_iommu *iommu, void *entry, u16 devid, u16 index,
3141 				 u8 vector, u32 dest_apicid)
3142 {
3143 	struct irte_ga *irte = (struct irte_ga *) entry;
3144 
3145 	if (!irte->lo.fields_remap.guest_mode) {
3146 		irte->hi.fields.vector = vector;
3147 		irte->lo.fields_remap.destination =
3148 					APICID_TO_IRTE_DEST_LO(dest_apicid);
3149 		irte->hi.fields.destination =
3150 					APICID_TO_IRTE_DEST_HI(dest_apicid);
3151 		modify_irte_ga(iommu, devid, index, irte, NULL);
3152 	}
3153 }
3154 
3155 #define IRTE_ALLOCATED (~1U)
irte_set_allocated(struct irq_remap_table * table,int index)3156 static void irte_set_allocated(struct irq_remap_table *table, int index)
3157 {
3158 	table->table[index] = IRTE_ALLOCATED;
3159 }
3160 
irte_ga_set_allocated(struct irq_remap_table * table,int index)3161 static void irte_ga_set_allocated(struct irq_remap_table *table, int index)
3162 {
3163 	struct irte_ga *ptr = (struct irte_ga *)table->table;
3164 	struct irte_ga *irte = &ptr[index];
3165 
3166 	memset(&irte->lo.val, 0, sizeof(u64));
3167 	memset(&irte->hi.val, 0, sizeof(u64));
3168 	irte->hi.fields.vector = 0xff;
3169 }
3170 
irte_is_allocated(struct irq_remap_table * table,int index)3171 static bool irte_is_allocated(struct irq_remap_table *table, int index)
3172 {
3173 	union irte *ptr = (union irte *)table->table;
3174 	union irte *irte = &ptr[index];
3175 
3176 	return irte->val != 0;
3177 }
3178 
irte_ga_is_allocated(struct irq_remap_table * table,int index)3179 static bool irte_ga_is_allocated(struct irq_remap_table *table, int index)
3180 {
3181 	struct irte_ga *ptr = (struct irte_ga *)table->table;
3182 	struct irte_ga *irte = &ptr[index];
3183 
3184 	return irte->hi.fields.vector != 0;
3185 }
3186 
irte_clear_allocated(struct irq_remap_table * table,int index)3187 static void irte_clear_allocated(struct irq_remap_table *table, int index)
3188 {
3189 	table->table[index] = 0;
3190 }
3191 
irte_ga_clear_allocated(struct irq_remap_table * table,int index)3192 static void irte_ga_clear_allocated(struct irq_remap_table *table, int index)
3193 {
3194 	struct irte_ga *ptr = (struct irte_ga *)table->table;
3195 	struct irte_ga *irte = &ptr[index];
3196 
3197 	memset(&irte->lo.val, 0, sizeof(u64));
3198 	memset(&irte->hi.val, 0, sizeof(u64));
3199 }
3200 
get_devid(struct irq_alloc_info * info)3201 static int get_devid(struct irq_alloc_info *info)
3202 {
3203 	switch (info->type) {
3204 	case X86_IRQ_ALLOC_TYPE_IOAPIC:
3205 		return get_ioapic_devid(info->devid);
3206 	case X86_IRQ_ALLOC_TYPE_HPET:
3207 		return get_hpet_devid(info->devid);
3208 	case X86_IRQ_ALLOC_TYPE_PCI_MSI:
3209 	case X86_IRQ_ALLOC_TYPE_PCI_MSIX:
3210 		return get_device_sbdf_id(msi_desc_to_dev(info->desc));
3211 	default:
3212 		WARN_ON_ONCE(1);
3213 		return -1;
3214 	}
3215 }
3216 
3217 struct irq_remap_ops amd_iommu_irq_ops = {
3218 	.prepare		= amd_iommu_prepare,
3219 	.enable			= amd_iommu_enable,
3220 	.disable		= amd_iommu_disable,
3221 	.reenable		= amd_iommu_reenable,
3222 	.enable_faulting	= amd_iommu_enable_faulting,
3223 };
3224 
fill_msi_msg(struct msi_msg * msg,u32 index)3225 static void fill_msi_msg(struct msi_msg *msg, u32 index)
3226 {
3227 	msg->data = index;
3228 	msg->address_lo = 0;
3229 	msg->arch_addr_lo.base_address = X86_MSI_BASE_ADDRESS_LOW;
3230 	msg->address_hi = X86_MSI_BASE_ADDRESS_HIGH;
3231 }
3232 
irq_remapping_prepare_irte(struct amd_ir_data * data,struct irq_cfg * irq_cfg,struct irq_alloc_info * info,int devid,int index,int sub_handle)3233 static void irq_remapping_prepare_irte(struct amd_ir_data *data,
3234 				       struct irq_cfg *irq_cfg,
3235 				       struct irq_alloc_info *info,
3236 				       int devid, int index, int sub_handle)
3237 {
3238 	struct irq_2_irte *irte_info = &data->irq_2_irte;
3239 	struct amd_iommu *iommu = data->iommu;
3240 
3241 	if (!iommu)
3242 		return;
3243 
3244 	data->irq_2_irte.devid = devid;
3245 	data->irq_2_irte.index = index + sub_handle;
3246 	iommu->irte_ops->prepare(data->entry, apic->delivery_mode,
3247 				 apic->dest_mode_logical, irq_cfg->vector,
3248 				 irq_cfg->dest_apicid, devid);
3249 
3250 	switch (info->type) {
3251 	case X86_IRQ_ALLOC_TYPE_IOAPIC:
3252 	case X86_IRQ_ALLOC_TYPE_HPET:
3253 	case X86_IRQ_ALLOC_TYPE_PCI_MSI:
3254 	case X86_IRQ_ALLOC_TYPE_PCI_MSIX:
3255 		fill_msi_msg(&data->msi_entry, irte_info->index);
3256 		break;
3257 
3258 	default:
3259 		BUG_ON(1);
3260 		break;
3261 	}
3262 }
3263 
3264 struct amd_irte_ops irte_32_ops = {
3265 	.prepare = irte_prepare,
3266 	.activate = irte_activate,
3267 	.deactivate = irte_deactivate,
3268 	.set_affinity = irte_set_affinity,
3269 	.set_allocated = irte_set_allocated,
3270 	.is_allocated = irte_is_allocated,
3271 	.clear_allocated = irte_clear_allocated,
3272 };
3273 
3274 struct amd_irte_ops irte_128_ops = {
3275 	.prepare = irte_ga_prepare,
3276 	.activate = irte_ga_activate,
3277 	.deactivate = irte_ga_deactivate,
3278 	.set_affinity = irte_ga_set_affinity,
3279 	.set_allocated = irte_ga_set_allocated,
3280 	.is_allocated = irte_ga_is_allocated,
3281 	.clear_allocated = irte_ga_clear_allocated,
3282 };
3283 
irq_remapping_alloc(struct irq_domain * domain,unsigned int virq,unsigned int nr_irqs,void * arg)3284 static int irq_remapping_alloc(struct irq_domain *domain, unsigned int virq,
3285 			       unsigned int nr_irqs, void *arg)
3286 {
3287 	struct irq_alloc_info *info = arg;
3288 	struct irq_data *irq_data;
3289 	struct amd_ir_data *data = NULL;
3290 	struct amd_iommu *iommu;
3291 	struct irq_cfg *cfg;
3292 	int i, ret, devid, seg, sbdf;
3293 	int index;
3294 
3295 	if (!info)
3296 		return -EINVAL;
3297 	if (nr_irqs > 1 && info->type != X86_IRQ_ALLOC_TYPE_PCI_MSI &&
3298 	    info->type != X86_IRQ_ALLOC_TYPE_PCI_MSIX)
3299 		return -EINVAL;
3300 
3301 	/*
3302 	 * With IRQ remapping enabled, don't need contiguous CPU vectors
3303 	 * to support multiple MSI interrupts.
3304 	 */
3305 	if (info->type == X86_IRQ_ALLOC_TYPE_PCI_MSI)
3306 		info->flags &= ~X86_IRQ_ALLOC_CONTIGUOUS_VECTORS;
3307 
3308 	sbdf = get_devid(info);
3309 	if (sbdf < 0)
3310 		return -EINVAL;
3311 
3312 	seg = PCI_SBDF_TO_SEGID(sbdf);
3313 	devid = PCI_SBDF_TO_DEVID(sbdf);
3314 	iommu = __rlookup_amd_iommu(seg, devid);
3315 	if (!iommu)
3316 		return -EINVAL;
3317 
3318 	ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg);
3319 	if (ret < 0)
3320 		return ret;
3321 
3322 	if (info->type == X86_IRQ_ALLOC_TYPE_IOAPIC) {
3323 		struct irq_remap_table *table;
3324 
3325 		table = alloc_irq_table(iommu, devid, NULL);
3326 		if (table) {
3327 			if (!table->min_index) {
3328 				/*
3329 				 * Keep the first 32 indexes free for IOAPIC
3330 				 * interrupts.
3331 				 */
3332 				table->min_index = 32;
3333 				for (i = 0; i < 32; ++i)
3334 					iommu->irte_ops->set_allocated(table, i);
3335 			}
3336 			WARN_ON(table->min_index != 32);
3337 			index = info->ioapic.pin;
3338 		} else {
3339 			index = -ENOMEM;
3340 		}
3341 	} else if (info->type == X86_IRQ_ALLOC_TYPE_PCI_MSI ||
3342 		   info->type == X86_IRQ_ALLOC_TYPE_PCI_MSIX) {
3343 		bool align = (info->type == X86_IRQ_ALLOC_TYPE_PCI_MSI);
3344 
3345 		index = alloc_irq_index(iommu, devid, nr_irqs, align,
3346 					msi_desc_to_pci_dev(info->desc));
3347 	} else {
3348 		index = alloc_irq_index(iommu, devid, nr_irqs, false, NULL);
3349 	}
3350 
3351 	if (index < 0) {
3352 		pr_warn("Failed to allocate IRTE\n");
3353 		ret = index;
3354 		goto out_free_parent;
3355 	}
3356 
3357 	for (i = 0; i < nr_irqs; i++) {
3358 		irq_data = irq_domain_get_irq_data(domain, virq + i);
3359 		cfg = irq_data ? irqd_cfg(irq_data) : NULL;
3360 		if (!cfg) {
3361 			ret = -EINVAL;
3362 			goto out_free_data;
3363 		}
3364 
3365 		ret = -ENOMEM;
3366 		data = kzalloc(sizeof(*data), GFP_KERNEL);
3367 		if (!data)
3368 			goto out_free_data;
3369 
3370 		if (!AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir))
3371 			data->entry = kzalloc(sizeof(union irte), GFP_KERNEL);
3372 		else
3373 			data->entry = kzalloc(sizeof(struct irte_ga),
3374 						     GFP_KERNEL);
3375 		if (!data->entry) {
3376 			kfree(data);
3377 			goto out_free_data;
3378 		}
3379 
3380 		data->iommu = iommu;
3381 		irq_data->hwirq = (devid << 16) + i;
3382 		irq_data->chip_data = data;
3383 		irq_data->chip = &amd_ir_chip;
3384 		irq_remapping_prepare_irte(data, cfg, info, devid, index, i);
3385 		irq_set_status_flags(virq + i, IRQ_MOVE_PCNTXT);
3386 	}
3387 
3388 	return 0;
3389 
3390 out_free_data:
3391 	for (i--; i >= 0; i--) {
3392 		irq_data = irq_domain_get_irq_data(domain, virq + i);
3393 		if (irq_data)
3394 			kfree(irq_data->chip_data);
3395 	}
3396 	for (i = 0; i < nr_irqs; i++)
3397 		free_irte(iommu, devid, index + i);
3398 out_free_parent:
3399 	irq_domain_free_irqs_common(domain, virq, nr_irqs);
3400 	return ret;
3401 }
3402 
irq_remapping_free(struct irq_domain * domain,unsigned int virq,unsigned int nr_irqs)3403 static void irq_remapping_free(struct irq_domain *domain, unsigned int virq,
3404 			       unsigned int nr_irqs)
3405 {
3406 	struct irq_2_irte *irte_info;
3407 	struct irq_data *irq_data;
3408 	struct amd_ir_data *data;
3409 	int i;
3410 
3411 	for (i = 0; i < nr_irqs; i++) {
3412 		irq_data = irq_domain_get_irq_data(domain, virq  + i);
3413 		if (irq_data && irq_data->chip_data) {
3414 			data = irq_data->chip_data;
3415 			irte_info = &data->irq_2_irte;
3416 			free_irte(data->iommu, irte_info->devid, irte_info->index);
3417 			kfree(data->entry);
3418 			kfree(data);
3419 		}
3420 	}
3421 	irq_domain_free_irqs_common(domain, virq, nr_irqs);
3422 }
3423 
3424 static void amd_ir_update_irte(struct irq_data *irqd, struct amd_iommu *iommu,
3425 			       struct amd_ir_data *ir_data,
3426 			       struct irq_2_irte *irte_info,
3427 			       struct irq_cfg *cfg);
3428 
irq_remapping_activate(struct irq_domain * domain,struct irq_data * irq_data,bool reserve)3429 static int irq_remapping_activate(struct irq_domain *domain,
3430 				  struct irq_data *irq_data, bool reserve)
3431 {
3432 	struct amd_ir_data *data = irq_data->chip_data;
3433 	struct irq_2_irte *irte_info = &data->irq_2_irte;
3434 	struct amd_iommu *iommu = data->iommu;
3435 	struct irq_cfg *cfg = irqd_cfg(irq_data);
3436 
3437 	if (!iommu)
3438 		return 0;
3439 
3440 	iommu->irte_ops->activate(iommu, data->entry, irte_info->devid,
3441 				  irte_info->index);
3442 	amd_ir_update_irte(irq_data, iommu, data, irte_info, cfg);
3443 	return 0;
3444 }
3445 
irq_remapping_deactivate(struct irq_domain * domain,struct irq_data * irq_data)3446 static void irq_remapping_deactivate(struct irq_domain *domain,
3447 				     struct irq_data *irq_data)
3448 {
3449 	struct amd_ir_data *data = irq_data->chip_data;
3450 	struct irq_2_irte *irte_info = &data->irq_2_irte;
3451 	struct amd_iommu *iommu = data->iommu;
3452 
3453 	if (iommu)
3454 		iommu->irte_ops->deactivate(iommu, data->entry, irte_info->devid,
3455 					    irte_info->index);
3456 }
3457 
irq_remapping_select(struct irq_domain * d,struct irq_fwspec * fwspec,enum irq_domain_bus_token bus_token)3458 static int irq_remapping_select(struct irq_domain *d, struct irq_fwspec *fwspec,
3459 				enum irq_domain_bus_token bus_token)
3460 {
3461 	struct amd_iommu *iommu;
3462 	int devid = -1;
3463 
3464 	if (!amd_iommu_irq_remap)
3465 		return 0;
3466 
3467 	if (x86_fwspec_is_ioapic(fwspec))
3468 		devid = get_ioapic_devid(fwspec->param[0]);
3469 	else if (x86_fwspec_is_hpet(fwspec))
3470 		devid = get_hpet_devid(fwspec->param[0]);
3471 
3472 	if (devid < 0)
3473 		return 0;
3474 	iommu = __rlookup_amd_iommu((devid >> 16), (devid & 0xffff));
3475 
3476 	return iommu && iommu->ir_domain == d;
3477 }
3478 
3479 static const struct irq_domain_ops amd_ir_domain_ops = {
3480 	.select = irq_remapping_select,
3481 	.alloc = irq_remapping_alloc,
3482 	.free = irq_remapping_free,
3483 	.activate = irq_remapping_activate,
3484 	.deactivate = irq_remapping_deactivate,
3485 };
3486 
amd_iommu_activate_guest_mode(void * data)3487 int amd_iommu_activate_guest_mode(void *data)
3488 {
3489 	struct amd_ir_data *ir_data = (struct amd_ir_data *)data;
3490 	struct irte_ga *entry = (struct irte_ga *) ir_data->entry;
3491 	u64 valid;
3492 
3493 	if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) ||
3494 	    !entry || entry->lo.fields_vapic.guest_mode)
3495 		return 0;
3496 
3497 	valid = entry->lo.fields_vapic.valid;
3498 
3499 	entry->lo.val = 0;
3500 	entry->hi.val = 0;
3501 
3502 	entry->lo.fields_vapic.valid       = valid;
3503 	entry->lo.fields_vapic.guest_mode  = 1;
3504 	entry->lo.fields_vapic.ga_log_intr = 1;
3505 	entry->hi.fields.ga_root_ptr       = ir_data->ga_root_ptr;
3506 	entry->hi.fields.vector            = ir_data->ga_vector;
3507 	entry->lo.fields_vapic.ga_tag      = ir_data->ga_tag;
3508 
3509 	return modify_irte_ga(ir_data->iommu, ir_data->irq_2_irte.devid,
3510 			      ir_data->irq_2_irte.index, entry, ir_data);
3511 }
3512 EXPORT_SYMBOL(amd_iommu_activate_guest_mode);
3513 
amd_iommu_deactivate_guest_mode(void * data)3514 int amd_iommu_deactivate_guest_mode(void *data)
3515 {
3516 	struct amd_ir_data *ir_data = (struct amd_ir_data *)data;
3517 	struct irte_ga *entry = (struct irte_ga *) ir_data->entry;
3518 	struct irq_cfg *cfg = ir_data->cfg;
3519 	u64 valid;
3520 
3521 	if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) ||
3522 	    !entry || !entry->lo.fields_vapic.guest_mode)
3523 		return 0;
3524 
3525 	valid = entry->lo.fields_remap.valid;
3526 
3527 	entry->lo.val = 0;
3528 	entry->hi.val = 0;
3529 
3530 	entry->lo.fields_remap.valid       = valid;
3531 	entry->lo.fields_remap.dm          = apic->dest_mode_logical;
3532 	entry->lo.fields_remap.int_type    = apic->delivery_mode;
3533 	entry->hi.fields.vector            = cfg->vector;
3534 	entry->lo.fields_remap.destination =
3535 				APICID_TO_IRTE_DEST_LO(cfg->dest_apicid);
3536 	entry->hi.fields.destination =
3537 				APICID_TO_IRTE_DEST_HI(cfg->dest_apicid);
3538 
3539 	return modify_irte_ga(ir_data->iommu, ir_data->irq_2_irte.devid,
3540 			      ir_data->irq_2_irte.index, entry, ir_data);
3541 }
3542 EXPORT_SYMBOL(amd_iommu_deactivate_guest_mode);
3543 
amd_ir_set_vcpu_affinity(struct irq_data * data,void * vcpu_info)3544 static int amd_ir_set_vcpu_affinity(struct irq_data *data, void *vcpu_info)
3545 {
3546 	int ret;
3547 	struct amd_iommu_pi_data *pi_data = vcpu_info;
3548 	struct vcpu_data *vcpu_pi_info = pi_data->vcpu_data;
3549 	struct amd_ir_data *ir_data = data->chip_data;
3550 	struct irq_2_irte *irte_info = &ir_data->irq_2_irte;
3551 	struct iommu_dev_data *dev_data;
3552 
3553 	if (ir_data->iommu == NULL)
3554 		return -EINVAL;
3555 
3556 	dev_data = search_dev_data(ir_data->iommu, irte_info->devid);
3557 
3558 	/* Note:
3559 	 * This device has never been set up for guest mode.
3560 	 * we should not modify the IRTE
3561 	 */
3562 	if (!dev_data || !dev_data->use_vapic)
3563 		return 0;
3564 
3565 	ir_data->cfg = irqd_cfg(data);
3566 	pi_data->ir_data = ir_data;
3567 
3568 	/* Note:
3569 	 * SVM tries to set up for VAPIC mode, but we are in
3570 	 * legacy mode. So, we force legacy mode instead.
3571 	 */
3572 	if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir)) {
3573 		pr_debug("%s: Fall back to using intr legacy remap\n",
3574 			 __func__);
3575 		pi_data->is_guest_mode = false;
3576 	}
3577 
3578 	pi_data->prev_ga_tag = ir_data->cached_ga_tag;
3579 	if (pi_data->is_guest_mode) {
3580 		ir_data->ga_root_ptr = (pi_data->base >> 12);
3581 		ir_data->ga_vector = vcpu_pi_info->vector;
3582 		ir_data->ga_tag = pi_data->ga_tag;
3583 		ret = amd_iommu_activate_guest_mode(ir_data);
3584 		if (!ret)
3585 			ir_data->cached_ga_tag = pi_data->ga_tag;
3586 	} else {
3587 		ret = amd_iommu_deactivate_guest_mode(ir_data);
3588 
3589 		/*
3590 		 * This communicates the ga_tag back to the caller
3591 		 * so that it can do all the necessary clean up.
3592 		 */
3593 		if (!ret)
3594 			ir_data->cached_ga_tag = 0;
3595 	}
3596 
3597 	return ret;
3598 }
3599 
3600 
amd_ir_update_irte(struct irq_data * irqd,struct amd_iommu * iommu,struct amd_ir_data * ir_data,struct irq_2_irte * irte_info,struct irq_cfg * cfg)3601 static void amd_ir_update_irte(struct irq_data *irqd, struct amd_iommu *iommu,
3602 			       struct amd_ir_data *ir_data,
3603 			       struct irq_2_irte *irte_info,
3604 			       struct irq_cfg *cfg)
3605 {
3606 
3607 	/*
3608 	 * Atomically updates the IRTE with the new destination, vector
3609 	 * and flushes the interrupt entry cache.
3610 	 */
3611 	iommu->irte_ops->set_affinity(iommu, ir_data->entry, irte_info->devid,
3612 				      irte_info->index, cfg->vector,
3613 				      cfg->dest_apicid);
3614 }
3615 
amd_ir_set_affinity(struct irq_data * data,const struct cpumask * mask,bool force)3616 static int amd_ir_set_affinity(struct irq_data *data,
3617 			       const struct cpumask *mask, bool force)
3618 {
3619 	struct amd_ir_data *ir_data = data->chip_data;
3620 	struct irq_2_irte *irte_info = &ir_data->irq_2_irte;
3621 	struct irq_cfg *cfg = irqd_cfg(data);
3622 	struct irq_data *parent = data->parent_data;
3623 	struct amd_iommu *iommu = ir_data->iommu;
3624 	int ret;
3625 
3626 	if (!iommu)
3627 		return -ENODEV;
3628 
3629 	ret = parent->chip->irq_set_affinity(parent, mask, force);
3630 	if (ret < 0 || ret == IRQ_SET_MASK_OK_DONE)
3631 		return ret;
3632 
3633 	amd_ir_update_irte(data, iommu, ir_data, irte_info, cfg);
3634 	/*
3635 	 * After this point, all the interrupts will start arriving
3636 	 * at the new destination. So, time to cleanup the previous
3637 	 * vector allocation.
3638 	 */
3639 	send_cleanup_vector(cfg);
3640 
3641 	return IRQ_SET_MASK_OK_DONE;
3642 }
3643 
ir_compose_msi_msg(struct irq_data * irq_data,struct msi_msg * msg)3644 static void ir_compose_msi_msg(struct irq_data *irq_data, struct msi_msg *msg)
3645 {
3646 	struct amd_ir_data *ir_data = irq_data->chip_data;
3647 
3648 	*msg = ir_data->msi_entry;
3649 }
3650 
3651 static struct irq_chip amd_ir_chip = {
3652 	.name			= "AMD-IR",
3653 	.irq_ack		= apic_ack_irq,
3654 	.irq_set_affinity	= amd_ir_set_affinity,
3655 	.irq_set_vcpu_affinity	= amd_ir_set_vcpu_affinity,
3656 	.irq_compose_msi_msg	= ir_compose_msi_msg,
3657 };
3658 
amd_iommu_create_irq_domain(struct amd_iommu * iommu)3659 int amd_iommu_create_irq_domain(struct amd_iommu *iommu)
3660 {
3661 	struct fwnode_handle *fn;
3662 
3663 	fn = irq_domain_alloc_named_id_fwnode("AMD-IR", iommu->index);
3664 	if (!fn)
3665 		return -ENOMEM;
3666 	iommu->ir_domain = irq_domain_create_tree(fn, &amd_ir_domain_ops, iommu);
3667 	if (!iommu->ir_domain) {
3668 		irq_domain_free_fwnode(fn);
3669 		return -ENOMEM;
3670 	}
3671 
3672 	iommu->ir_domain->parent = arch_get_ir_parent_domain();
3673 	iommu->msi_domain = arch_create_remap_msi_irq_domain(iommu->ir_domain,
3674 							     "AMD-IR-MSI",
3675 							     iommu->index);
3676 	return 0;
3677 }
3678 
amd_iommu_update_ga(int cpu,bool is_run,void * data)3679 int amd_iommu_update_ga(int cpu, bool is_run, void *data)
3680 {
3681 	unsigned long flags;
3682 	struct amd_iommu *iommu;
3683 	struct irq_remap_table *table;
3684 	struct amd_ir_data *ir_data = (struct amd_ir_data *)data;
3685 	int devid = ir_data->irq_2_irte.devid;
3686 	struct irte_ga *entry = (struct irte_ga *) ir_data->entry;
3687 	struct irte_ga *ref = (struct irte_ga *) ir_data->ref;
3688 
3689 	if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) ||
3690 	    !ref || !entry || !entry->lo.fields_vapic.guest_mode)
3691 		return 0;
3692 
3693 	iommu = ir_data->iommu;
3694 	if (!iommu)
3695 		return -ENODEV;
3696 
3697 	table = get_irq_table(iommu, devid);
3698 	if (!table)
3699 		return -ENODEV;
3700 
3701 	raw_spin_lock_irqsave(&table->lock, flags);
3702 
3703 	if (ref->lo.fields_vapic.guest_mode) {
3704 		if (cpu >= 0) {
3705 			ref->lo.fields_vapic.destination =
3706 						APICID_TO_IRTE_DEST_LO(cpu);
3707 			ref->hi.fields.destination =
3708 						APICID_TO_IRTE_DEST_HI(cpu);
3709 		}
3710 		ref->lo.fields_vapic.is_run = is_run;
3711 		barrier();
3712 	}
3713 
3714 	raw_spin_unlock_irqrestore(&table->lock, flags);
3715 
3716 	iommu_flush_irt(iommu, devid);
3717 	iommu_completion_wait(iommu);
3718 	return 0;
3719 }
3720 EXPORT_SYMBOL(amd_iommu_update_ga);
3721 #endif
3722