1 /*
2  * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
3  *
4  * This software is available to you under a choice of one of two
5  * licenses.  You may choose to be licensed under the terms of the GNU
6  * General Public License (GPL) Version 2, available from the file
7  * COPYING in the main directory of this source tree, or the
8  * OpenIB.org BSD license below:
9  *
10  *     Redistribution and use in source and binary forms, with or
11  *     without modification, are permitted provided that the following
12  *     conditions are met:
13  *
14  *      - Redistributions of source code must retain the above
15  *        copyright notice, this list of conditions and the following
16  *        disclaimer.
17  *
18  *      - Redistributions in binary form must reproduce the above
19  *        copyright notice, this list of conditions and the following
20  *        disclaimer in the documentation and/or other materials
21  *        provided with the distribution.
22  *
23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30  * SOFTWARE.
31  */
32 
33 #include <linux/kref.h>
34 #include <rdma/ib_umem.h>
35 #include <rdma/ib_user_verbs.h>
36 #include <rdma/ib_cache.h>
37 #include "mlx5_ib.h"
38 #include "srq.h"
39 #include "qp.h"
40 
mlx5_ib_cq_comp(struct mlx5_core_cq * cq,struct mlx5_eqe * eqe)41 static void mlx5_ib_cq_comp(struct mlx5_core_cq *cq, struct mlx5_eqe *eqe)
42 {
43 	struct ib_cq *ibcq = &to_mibcq(cq)->ibcq;
44 
45 	ibcq->comp_handler(ibcq, ibcq->cq_context);
46 }
47 
mlx5_ib_cq_event(struct mlx5_core_cq * mcq,enum mlx5_event type)48 static void mlx5_ib_cq_event(struct mlx5_core_cq *mcq, enum mlx5_event type)
49 {
50 	struct mlx5_ib_cq *cq = container_of(mcq, struct mlx5_ib_cq, mcq);
51 	struct mlx5_ib_dev *dev = to_mdev(cq->ibcq.device);
52 	struct ib_cq *ibcq = &cq->ibcq;
53 	struct ib_event event;
54 
55 	if (type != MLX5_EVENT_TYPE_CQ_ERROR) {
56 		mlx5_ib_warn(dev, "Unexpected event type %d on CQ %06x\n",
57 			     type, mcq->cqn);
58 		return;
59 	}
60 
61 	if (ibcq->event_handler) {
62 		event.device     = &dev->ib_dev;
63 		event.event      = IB_EVENT_CQ_ERR;
64 		event.element.cq = ibcq;
65 		ibcq->event_handler(&event, ibcq->cq_context);
66 	}
67 }
68 
get_cqe(struct mlx5_ib_cq * cq,int n)69 static void *get_cqe(struct mlx5_ib_cq *cq, int n)
70 {
71 	return mlx5_frag_buf_get_wqe(&cq->buf.fbc, n);
72 }
73 
sw_ownership_bit(int n,int nent)74 static u8 sw_ownership_bit(int n, int nent)
75 {
76 	return (n & nent) ? 1 : 0;
77 }
78 
get_sw_cqe(struct mlx5_ib_cq * cq,int n)79 static void *get_sw_cqe(struct mlx5_ib_cq *cq, int n)
80 {
81 	void *cqe = get_cqe(cq, n & cq->ibcq.cqe);
82 	struct mlx5_cqe64 *cqe64;
83 
84 	cqe64 = (cq->mcq.cqe_sz == 64) ? cqe : cqe + 64;
85 
86 	if (likely(get_cqe_opcode(cqe64) != MLX5_CQE_INVALID) &&
87 	    !((cqe64->op_own & MLX5_CQE_OWNER_MASK) ^ !!(n & (cq->ibcq.cqe + 1)))) {
88 		return cqe;
89 	} else {
90 		return NULL;
91 	}
92 }
93 
next_cqe_sw(struct mlx5_ib_cq * cq)94 static void *next_cqe_sw(struct mlx5_ib_cq *cq)
95 {
96 	return get_sw_cqe(cq, cq->mcq.cons_index);
97 }
98 
get_umr_comp(struct mlx5_ib_wq * wq,int idx)99 static enum ib_wc_opcode get_umr_comp(struct mlx5_ib_wq *wq, int idx)
100 {
101 	switch (wq->wr_data[idx]) {
102 	case MLX5_IB_WR_UMR:
103 		return 0;
104 
105 	case IB_WR_LOCAL_INV:
106 		return IB_WC_LOCAL_INV;
107 
108 	case IB_WR_REG_MR:
109 		return IB_WC_REG_MR;
110 
111 	default:
112 		pr_warn("unknown completion status\n");
113 		return 0;
114 	}
115 }
116 
handle_good_req(struct ib_wc * wc,struct mlx5_cqe64 * cqe,struct mlx5_ib_wq * wq,int idx)117 static void handle_good_req(struct ib_wc *wc, struct mlx5_cqe64 *cqe,
118 			    struct mlx5_ib_wq *wq, int idx)
119 {
120 	wc->wc_flags = 0;
121 	switch (be32_to_cpu(cqe->sop_drop_qpn) >> 24) {
122 	case MLX5_OPCODE_RDMA_WRITE_IMM:
123 		wc->wc_flags |= IB_WC_WITH_IMM;
124 		fallthrough;
125 	case MLX5_OPCODE_RDMA_WRITE:
126 		wc->opcode    = IB_WC_RDMA_WRITE;
127 		break;
128 	case MLX5_OPCODE_SEND_IMM:
129 		wc->wc_flags |= IB_WC_WITH_IMM;
130 		fallthrough;
131 	case MLX5_OPCODE_SEND:
132 	case MLX5_OPCODE_SEND_INVAL:
133 		wc->opcode    = IB_WC_SEND;
134 		break;
135 	case MLX5_OPCODE_RDMA_READ:
136 		wc->opcode    = IB_WC_RDMA_READ;
137 		wc->byte_len  = be32_to_cpu(cqe->byte_cnt);
138 		break;
139 	case MLX5_OPCODE_ATOMIC_CS:
140 		wc->opcode    = IB_WC_COMP_SWAP;
141 		wc->byte_len  = 8;
142 		break;
143 	case MLX5_OPCODE_ATOMIC_FA:
144 		wc->opcode    = IB_WC_FETCH_ADD;
145 		wc->byte_len  = 8;
146 		break;
147 	case MLX5_OPCODE_ATOMIC_MASKED_CS:
148 		wc->opcode    = IB_WC_MASKED_COMP_SWAP;
149 		wc->byte_len  = 8;
150 		break;
151 	case MLX5_OPCODE_ATOMIC_MASKED_FA:
152 		wc->opcode    = IB_WC_MASKED_FETCH_ADD;
153 		wc->byte_len  = 8;
154 		break;
155 	case MLX5_OPCODE_UMR:
156 		wc->opcode = get_umr_comp(wq, idx);
157 		break;
158 	}
159 }
160 
161 enum {
162 	MLX5_GRH_IN_BUFFER = 1,
163 	MLX5_GRH_IN_CQE	   = 2,
164 };
165 
handle_responder(struct ib_wc * wc,struct mlx5_cqe64 * cqe,struct mlx5_ib_qp * qp)166 static void handle_responder(struct ib_wc *wc, struct mlx5_cqe64 *cqe,
167 			     struct mlx5_ib_qp *qp)
168 {
169 	enum rdma_link_layer ll = rdma_port_get_link_layer(qp->ibqp.device, 1);
170 	struct mlx5_ib_dev *dev = to_mdev(qp->ibqp.device);
171 	struct mlx5_ib_srq *srq = NULL;
172 	struct mlx5_ib_wq *wq;
173 	u16 wqe_ctr;
174 	u8  roce_packet_type;
175 	bool vlan_present;
176 	u8 g;
177 
178 	if (qp->ibqp.srq || qp->ibqp.xrcd) {
179 		struct mlx5_core_srq *msrq = NULL;
180 
181 		if (qp->ibqp.xrcd) {
182 			msrq = mlx5_cmd_get_srq(dev, be32_to_cpu(cqe->srqn));
183 			if (msrq)
184 				srq = to_mibsrq(msrq);
185 		} else {
186 			srq = to_msrq(qp->ibqp.srq);
187 		}
188 		if (srq) {
189 			wqe_ctr = be16_to_cpu(cqe->wqe_counter);
190 			wc->wr_id = srq->wrid[wqe_ctr];
191 			mlx5_ib_free_srq_wqe(srq, wqe_ctr);
192 			if (msrq)
193 				mlx5_core_res_put(&msrq->common);
194 		}
195 	} else {
196 		wq	  = &qp->rq;
197 		wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
198 		++wq->tail;
199 	}
200 	wc->byte_len = be32_to_cpu(cqe->byte_cnt);
201 
202 	switch (get_cqe_opcode(cqe)) {
203 	case MLX5_CQE_RESP_WR_IMM:
204 		wc->opcode	= IB_WC_RECV_RDMA_WITH_IMM;
205 		wc->wc_flags	= IB_WC_WITH_IMM;
206 		wc->ex.imm_data = cqe->immediate;
207 		break;
208 	case MLX5_CQE_RESP_SEND:
209 		wc->opcode   = IB_WC_RECV;
210 		wc->wc_flags = IB_WC_IP_CSUM_OK;
211 		if (unlikely(!((cqe->hds_ip_ext & CQE_L3_OK) &&
212 			       (cqe->hds_ip_ext & CQE_L4_OK))))
213 			wc->wc_flags = 0;
214 		break;
215 	case MLX5_CQE_RESP_SEND_IMM:
216 		wc->opcode	= IB_WC_RECV;
217 		wc->wc_flags	= IB_WC_WITH_IMM;
218 		wc->ex.imm_data = cqe->immediate;
219 		break;
220 	case MLX5_CQE_RESP_SEND_INV:
221 		wc->opcode	= IB_WC_RECV;
222 		wc->wc_flags	= IB_WC_WITH_INVALIDATE;
223 		wc->ex.invalidate_rkey = be32_to_cpu(cqe->inval_rkey);
224 		break;
225 	}
226 	wc->src_qp	   = be32_to_cpu(cqe->flags_rqpn) & 0xffffff;
227 	wc->dlid_path_bits = cqe->ml_path;
228 	g = (be32_to_cpu(cqe->flags_rqpn) >> 28) & 3;
229 	wc->wc_flags |= g ? IB_WC_GRH : 0;
230 	if (is_qp1(qp->type)) {
231 		u16 pkey = be32_to_cpu(cqe->pkey) & 0xffff;
232 
233 		ib_find_cached_pkey(&dev->ib_dev, qp->port, pkey,
234 				    &wc->pkey_index);
235 	} else {
236 		wc->pkey_index = 0;
237 	}
238 
239 	if (ll != IB_LINK_LAYER_ETHERNET) {
240 		wc->slid = be16_to_cpu(cqe->slid);
241 		wc->sl = (be32_to_cpu(cqe->flags_rqpn) >> 24) & 0xf;
242 		return;
243 	}
244 
245 	wc->slid = 0;
246 	vlan_present = cqe->l4_l3_hdr_type & 0x1;
247 	roce_packet_type   = (be32_to_cpu(cqe->flags_rqpn) >> 24) & 0x3;
248 	if (vlan_present) {
249 		wc->vlan_id = (be16_to_cpu(cqe->vlan_info)) & 0xfff;
250 		wc->sl = (be16_to_cpu(cqe->vlan_info) >> 13) & 0x7;
251 		wc->wc_flags |= IB_WC_WITH_VLAN;
252 	} else {
253 		wc->sl = 0;
254 	}
255 
256 	switch (roce_packet_type) {
257 	case MLX5_CQE_ROCE_L3_HEADER_TYPE_GRH:
258 		wc->network_hdr_type = RDMA_NETWORK_ROCE_V1;
259 		break;
260 	case MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV6:
261 		wc->network_hdr_type = RDMA_NETWORK_IPV6;
262 		break;
263 	case MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV4:
264 		wc->network_hdr_type = RDMA_NETWORK_IPV4;
265 		break;
266 	}
267 	wc->wc_flags |= IB_WC_WITH_NETWORK_HDR_TYPE;
268 }
269 
dump_cqe(struct mlx5_ib_dev * dev,struct mlx5_err_cqe * cqe)270 static void dump_cqe(struct mlx5_ib_dev *dev, struct mlx5_err_cqe *cqe)
271 {
272 	mlx5_ib_warn(dev, "dump error cqe\n");
273 	mlx5_dump_err_cqe(dev->mdev, cqe);
274 }
275 
mlx5_handle_error_cqe(struct mlx5_ib_dev * dev,struct mlx5_err_cqe * cqe,struct ib_wc * wc)276 static void mlx5_handle_error_cqe(struct mlx5_ib_dev *dev,
277 				  struct mlx5_err_cqe *cqe,
278 				  struct ib_wc *wc)
279 {
280 	int dump = 1;
281 
282 	switch (cqe->syndrome) {
283 	case MLX5_CQE_SYNDROME_LOCAL_LENGTH_ERR:
284 		wc->status = IB_WC_LOC_LEN_ERR;
285 		break;
286 	case MLX5_CQE_SYNDROME_LOCAL_QP_OP_ERR:
287 		wc->status = IB_WC_LOC_QP_OP_ERR;
288 		break;
289 	case MLX5_CQE_SYNDROME_LOCAL_PROT_ERR:
290 		wc->status = IB_WC_LOC_PROT_ERR;
291 		break;
292 	case MLX5_CQE_SYNDROME_WR_FLUSH_ERR:
293 		dump = 0;
294 		wc->status = IB_WC_WR_FLUSH_ERR;
295 		break;
296 	case MLX5_CQE_SYNDROME_MW_BIND_ERR:
297 		wc->status = IB_WC_MW_BIND_ERR;
298 		break;
299 	case MLX5_CQE_SYNDROME_BAD_RESP_ERR:
300 		wc->status = IB_WC_BAD_RESP_ERR;
301 		break;
302 	case MLX5_CQE_SYNDROME_LOCAL_ACCESS_ERR:
303 		wc->status = IB_WC_LOC_ACCESS_ERR;
304 		break;
305 	case MLX5_CQE_SYNDROME_REMOTE_INVAL_REQ_ERR:
306 		wc->status = IB_WC_REM_INV_REQ_ERR;
307 		break;
308 	case MLX5_CQE_SYNDROME_REMOTE_ACCESS_ERR:
309 		wc->status = IB_WC_REM_ACCESS_ERR;
310 		break;
311 	case MLX5_CQE_SYNDROME_REMOTE_OP_ERR:
312 		wc->status = IB_WC_REM_OP_ERR;
313 		break;
314 	case MLX5_CQE_SYNDROME_TRANSPORT_RETRY_EXC_ERR:
315 		wc->status = IB_WC_RETRY_EXC_ERR;
316 		dump = 0;
317 		break;
318 	case MLX5_CQE_SYNDROME_RNR_RETRY_EXC_ERR:
319 		wc->status = IB_WC_RNR_RETRY_EXC_ERR;
320 		dump = 0;
321 		break;
322 	case MLX5_CQE_SYNDROME_REMOTE_ABORTED_ERR:
323 		wc->status = IB_WC_REM_ABORT_ERR;
324 		break;
325 	default:
326 		wc->status = IB_WC_GENERAL_ERR;
327 		break;
328 	}
329 
330 	wc->vendor_err = cqe->vendor_err_synd;
331 	if (dump) {
332 		mlx5_ib_warn(dev, "WC error: %d, Message: %s\n", wc->status,
333 			     ib_wc_status_msg(wc->status));
334 		dump_cqe(dev, cqe);
335 	}
336 }
337 
handle_atomics(struct mlx5_ib_qp * qp,struct mlx5_cqe64 * cqe64,u16 tail,u16 head)338 static void handle_atomics(struct mlx5_ib_qp *qp, struct mlx5_cqe64 *cqe64,
339 			   u16 tail, u16 head)
340 {
341 	u16 idx;
342 
343 	do {
344 		idx = tail & (qp->sq.wqe_cnt - 1);
345 		if (idx == head)
346 			break;
347 
348 		tail = qp->sq.w_list[idx].next;
349 	} while (1);
350 	tail = qp->sq.w_list[idx].next;
351 	qp->sq.last_poll = tail;
352 }
353 
free_cq_buf(struct mlx5_ib_dev * dev,struct mlx5_ib_cq_buf * buf)354 static void free_cq_buf(struct mlx5_ib_dev *dev, struct mlx5_ib_cq_buf *buf)
355 {
356 	mlx5_frag_buf_free(dev->mdev, &buf->frag_buf);
357 }
358 
get_sig_err_item(struct mlx5_sig_err_cqe * cqe,struct ib_sig_err * item)359 static void get_sig_err_item(struct mlx5_sig_err_cqe *cqe,
360 			     struct ib_sig_err *item)
361 {
362 	u16 syndrome = be16_to_cpu(cqe->syndrome);
363 
364 #define GUARD_ERR   (1 << 13)
365 #define APPTAG_ERR  (1 << 12)
366 #define REFTAG_ERR  (1 << 11)
367 
368 	if (syndrome & GUARD_ERR) {
369 		item->err_type = IB_SIG_BAD_GUARD;
370 		item->expected = be32_to_cpu(cqe->expected_trans_sig) >> 16;
371 		item->actual = be32_to_cpu(cqe->actual_trans_sig) >> 16;
372 	} else
373 	if (syndrome & REFTAG_ERR) {
374 		item->err_type = IB_SIG_BAD_REFTAG;
375 		item->expected = be32_to_cpu(cqe->expected_reftag);
376 		item->actual = be32_to_cpu(cqe->actual_reftag);
377 	} else
378 	if (syndrome & APPTAG_ERR) {
379 		item->err_type = IB_SIG_BAD_APPTAG;
380 		item->expected = be32_to_cpu(cqe->expected_trans_sig) & 0xffff;
381 		item->actual = be32_to_cpu(cqe->actual_trans_sig) & 0xffff;
382 	} else {
383 		pr_err("Got signature completion error with bad syndrome %04x\n",
384 		       syndrome);
385 	}
386 
387 	item->sig_err_offset = be64_to_cpu(cqe->err_offset);
388 	item->key = be32_to_cpu(cqe->mkey);
389 }
390 
sw_comp(struct mlx5_ib_qp * qp,int num_entries,struct ib_wc * wc,int * npolled,bool is_send)391 static void sw_comp(struct mlx5_ib_qp *qp, int num_entries, struct ib_wc *wc,
392 		    int *npolled, bool is_send)
393 {
394 	struct mlx5_ib_wq *wq;
395 	unsigned int cur;
396 	int np;
397 	int i;
398 
399 	wq = (is_send) ? &qp->sq : &qp->rq;
400 	cur = wq->head - wq->tail;
401 	np = *npolled;
402 
403 	if (cur == 0)
404 		return;
405 
406 	for (i = 0;  i < cur && np < num_entries; i++) {
407 		unsigned int idx;
408 
409 		idx = (is_send) ? wq->last_poll : wq->tail;
410 		idx &= (wq->wqe_cnt - 1);
411 		wc->wr_id = wq->wrid[idx];
412 		wc->status = IB_WC_WR_FLUSH_ERR;
413 		wc->vendor_err = MLX5_CQE_SYNDROME_WR_FLUSH_ERR;
414 		wq->tail++;
415 		if (is_send)
416 			wq->last_poll = wq->w_list[idx].next;
417 		np++;
418 		wc->qp = &qp->ibqp;
419 		wc++;
420 	}
421 	*npolled = np;
422 }
423 
mlx5_ib_poll_sw_comp(struct mlx5_ib_cq * cq,int num_entries,struct ib_wc * wc,int * npolled)424 static void mlx5_ib_poll_sw_comp(struct mlx5_ib_cq *cq, int num_entries,
425 				 struct ib_wc *wc, int *npolled)
426 {
427 	struct mlx5_ib_qp *qp;
428 
429 	*npolled = 0;
430 	/* Find uncompleted WQEs belonging to that cq and return mmics ones */
431 	list_for_each_entry(qp, &cq->list_send_qp, cq_send_list) {
432 		sw_comp(qp, num_entries, wc + *npolled, npolled, true);
433 		if (*npolled >= num_entries)
434 			return;
435 	}
436 
437 	list_for_each_entry(qp, &cq->list_recv_qp, cq_recv_list) {
438 		sw_comp(qp, num_entries, wc + *npolled, npolled, false);
439 		if (*npolled >= num_entries)
440 			return;
441 	}
442 }
443 
mlx5_poll_one(struct mlx5_ib_cq * cq,struct mlx5_ib_qp ** cur_qp,struct ib_wc * wc)444 static int mlx5_poll_one(struct mlx5_ib_cq *cq,
445 			 struct mlx5_ib_qp **cur_qp,
446 			 struct ib_wc *wc)
447 {
448 	struct mlx5_ib_dev *dev = to_mdev(cq->ibcq.device);
449 	struct mlx5_err_cqe *err_cqe;
450 	struct mlx5_cqe64 *cqe64;
451 	struct mlx5_core_qp *mqp;
452 	struct mlx5_ib_wq *wq;
453 	uint8_t opcode;
454 	uint32_t qpn;
455 	u16 wqe_ctr;
456 	void *cqe;
457 	int idx;
458 
459 repoll:
460 	cqe = next_cqe_sw(cq);
461 	if (!cqe)
462 		return -EAGAIN;
463 
464 	cqe64 = (cq->mcq.cqe_sz == 64) ? cqe : cqe + 64;
465 
466 	++cq->mcq.cons_index;
467 
468 	/* Make sure we read CQ entry contents after we've checked the
469 	 * ownership bit.
470 	 */
471 	rmb();
472 
473 	opcode = get_cqe_opcode(cqe64);
474 	if (unlikely(opcode == MLX5_CQE_RESIZE_CQ)) {
475 		if (likely(cq->resize_buf)) {
476 			free_cq_buf(dev, &cq->buf);
477 			cq->buf = *cq->resize_buf;
478 			kfree(cq->resize_buf);
479 			cq->resize_buf = NULL;
480 			goto repoll;
481 		} else {
482 			mlx5_ib_warn(dev, "unexpected resize cqe\n");
483 		}
484 	}
485 
486 	qpn = ntohl(cqe64->sop_drop_qpn) & 0xffffff;
487 	if (!*cur_qp || (qpn != (*cur_qp)->ibqp.qp_num)) {
488 		/* We do not have to take the QP table lock here,
489 		 * because CQs will be locked while QPs are removed
490 		 * from the table.
491 		 */
492 		mqp = radix_tree_lookup(&dev->qp_table.tree, qpn);
493 		*cur_qp = to_mibqp(mqp);
494 	}
495 
496 	wc->qp  = &(*cur_qp)->ibqp;
497 	switch (opcode) {
498 	case MLX5_CQE_REQ:
499 		wq = &(*cur_qp)->sq;
500 		wqe_ctr = be16_to_cpu(cqe64->wqe_counter);
501 		idx = wqe_ctr & (wq->wqe_cnt - 1);
502 		handle_good_req(wc, cqe64, wq, idx);
503 		handle_atomics(*cur_qp, cqe64, wq->last_poll, idx);
504 		wc->wr_id = wq->wrid[idx];
505 		wq->tail = wq->wqe_head[idx] + 1;
506 		wc->status = IB_WC_SUCCESS;
507 		break;
508 	case MLX5_CQE_RESP_WR_IMM:
509 	case MLX5_CQE_RESP_SEND:
510 	case MLX5_CQE_RESP_SEND_IMM:
511 	case MLX5_CQE_RESP_SEND_INV:
512 		handle_responder(wc, cqe64, *cur_qp);
513 		wc->status = IB_WC_SUCCESS;
514 		break;
515 	case MLX5_CQE_RESIZE_CQ:
516 		break;
517 	case MLX5_CQE_REQ_ERR:
518 	case MLX5_CQE_RESP_ERR:
519 		err_cqe = (struct mlx5_err_cqe *)cqe64;
520 		mlx5_handle_error_cqe(dev, err_cqe, wc);
521 		mlx5_ib_dbg(dev, "%s error cqe on cqn 0x%x:\n",
522 			    opcode == MLX5_CQE_REQ_ERR ?
523 			    "Requestor" : "Responder", cq->mcq.cqn);
524 		mlx5_ib_dbg(dev, "syndrome 0x%x, vendor syndrome 0x%x\n",
525 			    err_cqe->syndrome, err_cqe->vendor_err_synd);
526 		if (wc->status != IB_WC_WR_FLUSH_ERR &&
527 		    (*cur_qp)->type == MLX5_IB_QPT_REG_UMR)
528 			dev->umrc.state = MLX5_UMR_STATE_RECOVER;
529 
530 		if (opcode == MLX5_CQE_REQ_ERR) {
531 			wq = &(*cur_qp)->sq;
532 			wqe_ctr = be16_to_cpu(cqe64->wqe_counter);
533 			idx = wqe_ctr & (wq->wqe_cnt - 1);
534 			wc->wr_id = wq->wrid[idx];
535 			wq->tail = wq->wqe_head[idx] + 1;
536 		} else {
537 			struct mlx5_ib_srq *srq;
538 
539 			if ((*cur_qp)->ibqp.srq) {
540 				srq = to_msrq((*cur_qp)->ibqp.srq);
541 				wqe_ctr = be16_to_cpu(cqe64->wqe_counter);
542 				wc->wr_id = srq->wrid[wqe_ctr];
543 				mlx5_ib_free_srq_wqe(srq, wqe_ctr);
544 			} else {
545 				wq = &(*cur_qp)->rq;
546 				wc->wr_id = wq->wrid[wq->tail & (wq->wqe_cnt - 1)];
547 				++wq->tail;
548 			}
549 		}
550 		break;
551 	case MLX5_CQE_SIG_ERR: {
552 		struct mlx5_sig_err_cqe *sig_err_cqe =
553 			(struct mlx5_sig_err_cqe *)cqe64;
554 		struct mlx5_core_sig_ctx *sig;
555 
556 		xa_lock(&dev->sig_mrs);
557 		sig = xa_load(&dev->sig_mrs,
558 				mlx5_base_mkey(be32_to_cpu(sig_err_cqe->mkey)));
559 		get_sig_err_item(sig_err_cqe, &sig->err_item);
560 		sig->sig_err_exists = true;
561 		sig->sigerr_count++;
562 
563 		mlx5_ib_warn(dev, "CQN: 0x%x Got SIGERR on key: 0x%x err_type %x err_offset %llx expected %x actual %x\n",
564 			     cq->mcq.cqn, sig->err_item.key,
565 			     sig->err_item.err_type,
566 			     sig->err_item.sig_err_offset,
567 			     sig->err_item.expected,
568 			     sig->err_item.actual);
569 
570 		xa_unlock(&dev->sig_mrs);
571 		goto repoll;
572 	}
573 	}
574 
575 	return 0;
576 }
577 
poll_soft_wc(struct mlx5_ib_cq * cq,int num_entries,struct ib_wc * wc,bool is_fatal_err)578 static int poll_soft_wc(struct mlx5_ib_cq *cq, int num_entries,
579 			struct ib_wc *wc, bool is_fatal_err)
580 {
581 	struct mlx5_ib_dev *dev = to_mdev(cq->ibcq.device);
582 	struct mlx5_ib_wc *soft_wc, *next;
583 	int npolled = 0;
584 
585 	list_for_each_entry_safe(soft_wc, next, &cq->wc_list, list) {
586 		if (npolled >= num_entries)
587 			break;
588 
589 		mlx5_ib_dbg(dev, "polled software generated completion on CQ 0x%x\n",
590 			    cq->mcq.cqn);
591 
592 		if (unlikely(is_fatal_err)) {
593 			soft_wc->wc.status = IB_WC_WR_FLUSH_ERR;
594 			soft_wc->wc.vendor_err = MLX5_CQE_SYNDROME_WR_FLUSH_ERR;
595 		}
596 		wc[npolled++] = soft_wc->wc;
597 		list_del(&soft_wc->list);
598 		kfree(soft_wc);
599 	}
600 
601 	return npolled;
602 }
603 
mlx5_ib_poll_cq(struct ib_cq * ibcq,int num_entries,struct ib_wc * wc)604 int mlx5_ib_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc)
605 {
606 	struct mlx5_ib_cq *cq = to_mcq(ibcq);
607 	struct mlx5_ib_qp *cur_qp = NULL;
608 	struct mlx5_ib_dev *dev = to_mdev(cq->ibcq.device);
609 	struct mlx5_core_dev *mdev = dev->mdev;
610 	unsigned long flags;
611 	int soft_polled = 0;
612 	int npolled;
613 
614 	spin_lock_irqsave(&cq->lock, flags);
615 	if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
616 		/* make sure no soft wqe's are waiting */
617 		if (unlikely(!list_empty(&cq->wc_list)))
618 			soft_polled = poll_soft_wc(cq, num_entries, wc, true);
619 
620 		mlx5_ib_poll_sw_comp(cq, num_entries - soft_polled,
621 				     wc + soft_polled, &npolled);
622 		goto out;
623 	}
624 
625 	if (unlikely(!list_empty(&cq->wc_list)))
626 		soft_polled = poll_soft_wc(cq, num_entries, wc, false);
627 
628 	for (npolled = 0; npolled < num_entries - soft_polled; npolled++) {
629 		if (mlx5_poll_one(cq, &cur_qp, wc + soft_polled + npolled))
630 			break;
631 	}
632 
633 	if (npolled)
634 		mlx5_cq_set_ci(&cq->mcq);
635 out:
636 	spin_unlock_irqrestore(&cq->lock, flags);
637 
638 	return soft_polled + npolled;
639 }
640 
mlx5_ib_arm_cq(struct ib_cq * ibcq,enum ib_cq_notify_flags flags)641 int mlx5_ib_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags)
642 {
643 	struct mlx5_core_dev *mdev = to_mdev(ibcq->device)->mdev;
644 	struct mlx5_ib_cq *cq = to_mcq(ibcq);
645 	void __iomem *uar_page = mdev->priv.uar->map;
646 	unsigned long irq_flags;
647 	int ret = 0;
648 
649 	spin_lock_irqsave(&cq->lock, irq_flags);
650 	if (cq->notify_flags != IB_CQ_NEXT_COMP)
651 		cq->notify_flags = flags & IB_CQ_SOLICITED_MASK;
652 
653 	if ((flags & IB_CQ_REPORT_MISSED_EVENTS) && !list_empty(&cq->wc_list))
654 		ret = 1;
655 	spin_unlock_irqrestore(&cq->lock, irq_flags);
656 
657 	mlx5_cq_arm(&cq->mcq,
658 		    (flags & IB_CQ_SOLICITED_MASK) == IB_CQ_SOLICITED ?
659 		    MLX5_CQ_DB_REQ_NOT_SOL : MLX5_CQ_DB_REQ_NOT,
660 		    uar_page, to_mcq(ibcq)->mcq.cons_index);
661 
662 	return ret;
663 }
664 
alloc_cq_frag_buf(struct mlx5_ib_dev * dev,struct mlx5_ib_cq_buf * buf,int nent,int cqe_size)665 static int alloc_cq_frag_buf(struct mlx5_ib_dev *dev,
666 			     struct mlx5_ib_cq_buf *buf,
667 			     int nent,
668 			     int cqe_size)
669 {
670 	struct mlx5_frag_buf *frag_buf = &buf->frag_buf;
671 	u8 log_wq_stride = 6 + (cqe_size == 128 ? 1 : 0);
672 	u8 log_wq_sz     = ilog2(cqe_size);
673 	int err;
674 
675 	err = mlx5_frag_buf_alloc_node(dev->mdev,
676 				       nent * cqe_size,
677 				       frag_buf,
678 				       dev->mdev->priv.numa_node);
679 	if (err)
680 		return err;
681 
682 	mlx5_init_fbc(frag_buf->frags, log_wq_stride, log_wq_sz, &buf->fbc);
683 
684 	buf->cqe_size = cqe_size;
685 	buf->nent = nent;
686 
687 	return 0;
688 }
689 
690 enum {
691 	MLX5_CQE_RES_FORMAT_HASH = 0,
692 	MLX5_CQE_RES_FORMAT_CSUM = 1,
693 	MLX5_CQE_RES_FORMAT_CSUM_STRIDX = 3,
694 };
695 
mini_cqe_res_format_to_hw(struct mlx5_ib_dev * dev,u8 format)696 static int mini_cqe_res_format_to_hw(struct mlx5_ib_dev *dev, u8 format)
697 {
698 	switch (format) {
699 	case MLX5_IB_CQE_RES_FORMAT_HASH:
700 		return MLX5_CQE_RES_FORMAT_HASH;
701 	case MLX5_IB_CQE_RES_FORMAT_CSUM:
702 		return MLX5_CQE_RES_FORMAT_CSUM;
703 	case MLX5_IB_CQE_RES_FORMAT_CSUM_STRIDX:
704 		if (MLX5_CAP_GEN(dev->mdev, mini_cqe_resp_stride_index))
705 			return MLX5_CQE_RES_FORMAT_CSUM_STRIDX;
706 		return -EOPNOTSUPP;
707 	default:
708 		return -EINVAL;
709 	}
710 }
711 
create_cq_user(struct mlx5_ib_dev * dev,struct ib_udata * udata,struct mlx5_ib_cq * cq,int entries,u32 ** cqb,int * cqe_size,int * index,int * inlen)712 static int create_cq_user(struct mlx5_ib_dev *dev, struct ib_udata *udata,
713 			  struct mlx5_ib_cq *cq, int entries, u32 **cqb,
714 			  int *cqe_size, int *index, int *inlen)
715 {
716 	struct mlx5_ib_create_cq ucmd = {};
717 	unsigned long page_size;
718 	unsigned int page_offset_quantized;
719 	size_t ucmdlen;
720 	__be64 *pas;
721 	int ncont;
722 	void *cqc;
723 	int err;
724 	struct mlx5_ib_ucontext *context = rdma_udata_to_drv_context(
725 		udata, struct mlx5_ib_ucontext, ibucontext);
726 
727 	ucmdlen = min(udata->inlen, sizeof(ucmd));
728 	if (ucmdlen < offsetof(struct mlx5_ib_create_cq, flags))
729 		return -EINVAL;
730 
731 	if (ib_copy_from_udata(&ucmd, udata, ucmdlen))
732 		return -EFAULT;
733 
734 	if ((ucmd.flags & ~(MLX5_IB_CREATE_CQ_FLAGS_CQE_128B_PAD |
735 			    MLX5_IB_CREATE_CQ_FLAGS_UAR_PAGE_INDEX |
736 			    MLX5_IB_CREATE_CQ_FLAGS_REAL_TIME_TS)))
737 		return -EINVAL;
738 
739 	if ((ucmd.cqe_size != 64 && ucmd.cqe_size != 128) ||
740 	    ucmd.reserved0 || ucmd.reserved1)
741 		return -EINVAL;
742 
743 	*cqe_size = ucmd.cqe_size;
744 
745 	cq->buf.umem =
746 		ib_umem_get(&dev->ib_dev, ucmd.buf_addr,
747 			    entries * ucmd.cqe_size, IB_ACCESS_LOCAL_WRITE);
748 	if (IS_ERR(cq->buf.umem)) {
749 		err = PTR_ERR(cq->buf.umem);
750 		return err;
751 	}
752 
753 	page_size = mlx5_umem_find_best_cq_quantized_pgoff(
754 		cq->buf.umem, cqc, log_page_size, MLX5_ADAPTER_PAGE_SHIFT,
755 		page_offset, 64, &page_offset_quantized);
756 	if (!page_size) {
757 		err = -EINVAL;
758 		goto err_umem;
759 	}
760 
761 	err = mlx5_ib_db_map_user(context, ucmd.db_addr, &cq->db);
762 	if (err)
763 		goto err_umem;
764 
765 	ncont = ib_umem_num_dma_blocks(cq->buf.umem, page_size);
766 	mlx5_ib_dbg(
767 		dev,
768 		"addr 0x%llx, size %u, npages %zu, page_size %lu, ncont %d\n",
769 		ucmd.buf_addr, entries * ucmd.cqe_size,
770 		ib_umem_num_pages(cq->buf.umem), page_size, ncont);
771 
772 	*inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
773 		 MLX5_FLD_SZ_BYTES(create_cq_in, pas[0]) * ncont;
774 	*cqb = kvzalloc(*inlen, GFP_KERNEL);
775 	if (!*cqb) {
776 		err = -ENOMEM;
777 		goto err_db;
778 	}
779 
780 	pas = (__be64 *)MLX5_ADDR_OF(create_cq_in, *cqb, pas);
781 	mlx5_ib_populate_pas(cq->buf.umem, page_size, pas, 0);
782 
783 	cqc = MLX5_ADDR_OF(create_cq_in, *cqb, cq_context);
784 	MLX5_SET(cqc, cqc, log_page_size,
785 		 order_base_2(page_size) - MLX5_ADAPTER_PAGE_SHIFT);
786 	MLX5_SET(cqc, cqc, page_offset, page_offset_quantized);
787 
788 	if (ucmd.flags & MLX5_IB_CREATE_CQ_FLAGS_UAR_PAGE_INDEX) {
789 		*index = ucmd.uar_page_index;
790 	} else if (context->bfregi.lib_uar_dyn) {
791 		err = -EINVAL;
792 		goto err_cqb;
793 	} else {
794 		*index = context->bfregi.sys_pages[0];
795 	}
796 
797 	if (ucmd.cqe_comp_en == 1) {
798 		int mini_cqe_format;
799 
800 		if (!((*cqe_size == 128 &&
801 		       MLX5_CAP_GEN(dev->mdev, cqe_compression_128)) ||
802 		      (*cqe_size == 64  &&
803 		       MLX5_CAP_GEN(dev->mdev, cqe_compression)))) {
804 			err = -EOPNOTSUPP;
805 			mlx5_ib_warn(dev, "CQE compression is not supported for size %d!\n",
806 				     *cqe_size);
807 			goto err_cqb;
808 		}
809 
810 		mini_cqe_format =
811 			mini_cqe_res_format_to_hw(dev,
812 						  ucmd.cqe_comp_res_format);
813 		if (mini_cqe_format < 0) {
814 			err = mini_cqe_format;
815 			mlx5_ib_dbg(dev, "CQE compression res format %d error: %d\n",
816 				    ucmd.cqe_comp_res_format, err);
817 			goto err_cqb;
818 		}
819 
820 		MLX5_SET(cqc, cqc, cqe_comp_en, 1);
821 		MLX5_SET(cqc, cqc, mini_cqe_res_format, mini_cqe_format);
822 	}
823 
824 	if (ucmd.flags & MLX5_IB_CREATE_CQ_FLAGS_CQE_128B_PAD) {
825 		if (*cqe_size != 128 ||
826 		    !MLX5_CAP_GEN(dev->mdev, cqe_128_always)) {
827 			err = -EOPNOTSUPP;
828 			mlx5_ib_warn(dev,
829 				     "CQE padding is not supported for CQE size of %dB!\n",
830 				     *cqe_size);
831 			goto err_cqb;
832 		}
833 
834 		cq->private_flags |= MLX5_IB_CQ_PR_FLAGS_CQE_128_PAD;
835 	}
836 
837 	if (ucmd.flags & MLX5_IB_CREATE_CQ_FLAGS_REAL_TIME_TS)
838 		cq->private_flags |= MLX5_IB_CQ_PR_FLAGS_REAL_TIME_TS;
839 
840 	MLX5_SET(create_cq_in, *cqb, uid, context->devx_uid);
841 	return 0;
842 
843 err_cqb:
844 	kvfree(*cqb);
845 
846 err_db:
847 	mlx5_ib_db_unmap_user(context, &cq->db);
848 
849 err_umem:
850 	ib_umem_release(cq->buf.umem);
851 	return err;
852 }
853 
destroy_cq_user(struct mlx5_ib_cq * cq,struct ib_udata * udata)854 static void destroy_cq_user(struct mlx5_ib_cq *cq, struct ib_udata *udata)
855 {
856 	struct mlx5_ib_ucontext *context = rdma_udata_to_drv_context(
857 		udata, struct mlx5_ib_ucontext, ibucontext);
858 
859 	mlx5_ib_db_unmap_user(context, &cq->db);
860 	ib_umem_release(cq->buf.umem);
861 }
862 
init_cq_frag_buf(struct mlx5_ib_cq_buf * buf)863 static void init_cq_frag_buf(struct mlx5_ib_cq_buf *buf)
864 {
865 	int i;
866 	void *cqe;
867 	struct mlx5_cqe64 *cqe64;
868 
869 	for (i = 0; i < buf->nent; i++) {
870 		cqe = mlx5_frag_buf_get_wqe(&buf->fbc, i);
871 		cqe64 = buf->cqe_size == 64 ? cqe : cqe + 64;
872 		cqe64->op_own = MLX5_CQE_INVALID << 4;
873 	}
874 }
875 
create_cq_kernel(struct mlx5_ib_dev * dev,struct mlx5_ib_cq * cq,int entries,int cqe_size,u32 ** cqb,int * index,int * inlen)876 static int create_cq_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_cq *cq,
877 			    int entries, int cqe_size,
878 			    u32 **cqb, int *index, int *inlen)
879 {
880 	__be64 *pas;
881 	void *cqc;
882 	int err;
883 
884 	err = mlx5_db_alloc(dev->mdev, &cq->db);
885 	if (err)
886 		return err;
887 
888 	cq->mcq.set_ci_db  = cq->db.db;
889 	cq->mcq.arm_db     = cq->db.db + 1;
890 	cq->mcq.cqe_sz = cqe_size;
891 
892 	err = alloc_cq_frag_buf(dev, &cq->buf, entries, cqe_size);
893 	if (err)
894 		goto err_db;
895 
896 	init_cq_frag_buf(&cq->buf);
897 
898 	*inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
899 		 MLX5_FLD_SZ_BYTES(create_cq_in, pas[0]) *
900 		 cq->buf.frag_buf.npages;
901 	*cqb = kvzalloc(*inlen, GFP_KERNEL);
902 	if (!*cqb) {
903 		err = -ENOMEM;
904 		goto err_buf;
905 	}
906 
907 	pas = (__be64 *)MLX5_ADDR_OF(create_cq_in, *cqb, pas);
908 	mlx5_fill_page_frag_array(&cq->buf.frag_buf, pas);
909 
910 	cqc = MLX5_ADDR_OF(create_cq_in, *cqb, cq_context);
911 	MLX5_SET(cqc, cqc, log_page_size,
912 		 cq->buf.frag_buf.page_shift -
913 		 MLX5_ADAPTER_PAGE_SHIFT);
914 
915 	*index = dev->mdev->priv.uar->index;
916 
917 	return 0;
918 
919 err_buf:
920 	free_cq_buf(dev, &cq->buf);
921 
922 err_db:
923 	mlx5_db_free(dev->mdev, &cq->db);
924 	return err;
925 }
926 
destroy_cq_kernel(struct mlx5_ib_dev * dev,struct mlx5_ib_cq * cq)927 static void destroy_cq_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_cq *cq)
928 {
929 	free_cq_buf(dev, &cq->buf);
930 	mlx5_db_free(dev->mdev, &cq->db);
931 }
932 
notify_soft_wc_handler(struct work_struct * work)933 static void notify_soft_wc_handler(struct work_struct *work)
934 {
935 	struct mlx5_ib_cq *cq = container_of(work, struct mlx5_ib_cq,
936 					     notify_work);
937 
938 	cq->ibcq.comp_handler(&cq->ibcq, cq->ibcq.cq_context);
939 }
940 
mlx5_ib_create_cq(struct ib_cq * ibcq,const struct ib_cq_init_attr * attr,struct ib_udata * udata)941 int mlx5_ib_create_cq(struct ib_cq *ibcq, const struct ib_cq_init_attr *attr,
942 		      struct ib_udata *udata)
943 {
944 	struct ib_device *ibdev = ibcq->device;
945 	int entries = attr->cqe;
946 	int vector = attr->comp_vector;
947 	struct mlx5_ib_dev *dev = to_mdev(ibdev);
948 	struct mlx5_ib_cq *cq = to_mcq(ibcq);
949 	u32 out[MLX5_ST_SZ_DW(create_cq_out)];
950 	int index;
951 	int inlen;
952 	u32 *cqb = NULL;
953 	void *cqc;
954 	int cqe_size;
955 	int eqn;
956 	int err;
957 
958 	if (entries < 0 ||
959 	    (entries > (1 << MLX5_CAP_GEN(dev->mdev, log_max_cq_sz))))
960 		return -EINVAL;
961 
962 	if (check_cq_create_flags(attr->flags))
963 		return -EOPNOTSUPP;
964 
965 	entries = roundup_pow_of_two(entries + 1);
966 	if (entries > (1 << MLX5_CAP_GEN(dev->mdev, log_max_cq_sz)))
967 		return -EINVAL;
968 
969 	cq->ibcq.cqe = entries - 1;
970 	mutex_init(&cq->resize_mutex);
971 	spin_lock_init(&cq->lock);
972 	cq->resize_buf = NULL;
973 	cq->resize_umem = NULL;
974 	cq->create_flags = attr->flags;
975 	INIT_LIST_HEAD(&cq->list_send_qp);
976 	INIT_LIST_HEAD(&cq->list_recv_qp);
977 
978 	if (udata) {
979 		err = create_cq_user(dev, udata, cq, entries, &cqb, &cqe_size,
980 				     &index, &inlen);
981 		if (err)
982 			return err;
983 	} else {
984 		cqe_size = cache_line_size() == 128 ? 128 : 64;
985 		err = create_cq_kernel(dev, cq, entries, cqe_size, &cqb,
986 				       &index, &inlen);
987 		if (err)
988 			return err;
989 
990 		INIT_WORK(&cq->notify_work, notify_soft_wc_handler);
991 	}
992 
993 	err = mlx5_vector2eqn(dev->mdev, vector, &eqn);
994 	if (err)
995 		goto err_cqb;
996 
997 	cq->cqe_size = cqe_size;
998 
999 	cqc = MLX5_ADDR_OF(create_cq_in, cqb, cq_context);
1000 	MLX5_SET(cqc, cqc, cqe_sz,
1001 		 cqe_sz_to_mlx_sz(cqe_size,
1002 				  cq->private_flags &
1003 				  MLX5_IB_CQ_PR_FLAGS_CQE_128_PAD));
1004 	MLX5_SET(cqc, cqc, log_cq_size, ilog2(entries));
1005 	MLX5_SET(cqc, cqc, uar_page, index);
1006 	MLX5_SET(cqc, cqc, c_eqn_or_apu_element, eqn);
1007 	MLX5_SET64(cqc, cqc, dbr_addr, cq->db.dma);
1008 	if (cq->create_flags & IB_UVERBS_CQ_FLAGS_IGNORE_OVERRUN)
1009 		MLX5_SET(cqc, cqc, oi, 1);
1010 
1011 	err = mlx5_core_create_cq(dev->mdev, &cq->mcq, cqb, inlen, out, sizeof(out));
1012 	if (err)
1013 		goto err_cqb;
1014 
1015 	mlx5_ib_dbg(dev, "cqn 0x%x\n", cq->mcq.cqn);
1016 	if (udata)
1017 		cq->mcq.tasklet_ctx.comp = mlx5_ib_cq_comp;
1018 	else
1019 		cq->mcq.comp  = mlx5_ib_cq_comp;
1020 	cq->mcq.event = mlx5_ib_cq_event;
1021 
1022 	INIT_LIST_HEAD(&cq->wc_list);
1023 
1024 	if (udata)
1025 		if (ib_copy_to_udata(udata, &cq->mcq.cqn, sizeof(__u32))) {
1026 			err = -EFAULT;
1027 			goto err_cmd;
1028 		}
1029 
1030 
1031 	kvfree(cqb);
1032 	return 0;
1033 
1034 err_cmd:
1035 	mlx5_core_destroy_cq(dev->mdev, &cq->mcq);
1036 
1037 err_cqb:
1038 	kvfree(cqb);
1039 	if (udata)
1040 		destroy_cq_user(cq, udata);
1041 	else
1042 		destroy_cq_kernel(dev, cq);
1043 	return err;
1044 }
1045 
mlx5_ib_destroy_cq(struct ib_cq * cq,struct ib_udata * udata)1046 int mlx5_ib_destroy_cq(struct ib_cq *cq, struct ib_udata *udata)
1047 {
1048 	struct mlx5_ib_dev *dev = to_mdev(cq->device);
1049 	struct mlx5_ib_cq *mcq = to_mcq(cq);
1050 	int ret;
1051 
1052 	ret = mlx5_core_destroy_cq(dev->mdev, &mcq->mcq);
1053 	if (ret)
1054 		return ret;
1055 
1056 	if (udata)
1057 		destroy_cq_user(mcq, udata);
1058 	else
1059 		destroy_cq_kernel(dev, mcq);
1060 	return 0;
1061 }
1062 
is_equal_rsn(struct mlx5_cqe64 * cqe64,u32 rsn)1063 static int is_equal_rsn(struct mlx5_cqe64 *cqe64, u32 rsn)
1064 {
1065 	return rsn == (ntohl(cqe64->sop_drop_qpn) & 0xffffff);
1066 }
1067 
__mlx5_ib_cq_clean(struct mlx5_ib_cq * cq,u32 rsn,struct mlx5_ib_srq * srq)1068 void __mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 rsn, struct mlx5_ib_srq *srq)
1069 {
1070 	struct mlx5_cqe64 *cqe64, *dest64;
1071 	void *cqe, *dest;
1072 	u32 prod_index;
1073 	int nfreed = 0;
1074 	u8 owner_bit;
1075 
1076 	if (!cq)
1077 		return;
1078 
1079 	/* First we need to find the current producer index, so we
1080 	 * know where to start cleaning from.  It doesn't matter if HW
1081 	 * adds new entries after this loop -- the QP we're worried
1082 	 * about is already in RESET, so the new entries won't come
1083 	 * from our QP and therefore don't need to be checked.
1084 	 */
1085 	for (prod_index = cq->mcq.cons_index; get_sw_cqe(cq, prod_index); prod_index++)
1086 		if (prod_index == cq->mcq.cons_index + cq->ibcq.cqe)
1087 			break;
1088 
1089 	/* Now sweep backwards through the CQ, removing CQ entries
1090 	 * that match our QP by copying older entries on top of them.
1091 	 */
1092 	while ((int) --prod_index - (int) cq->mcq.cons_index >= 0) {
1093 		cqe = get_cqe(cq, prod_index & cq->ibcq.cqe);
1094 		cqe64 = (cq->mcq.cqe_sz == 64) ? cqe : cqe + 64;
1095 		if (is_equal_rsn(cqe64, rsn)) {
1096 			if (srq && (ntohl(cqe64->srqn) & 0xffffff))
1097 				mlx5_ib_free_srq_wqe(srq, be16_to_cpu(cqe64->wqe_counter));
1098 			++nfreed;
1099 		} else if (nfreed) {
1100 			dest = get_cqe(cq, (prod_index + nfreed) & cq->ibcq.cqe);
1101 			dest64 = (cq->mcq.cqe_sz == 64) ? dest : dest + 64;
1102 			owner_bit = dest64->op_own & MLX5_CQE_OWNER_MASK;
1103 			memcpy(dest, cqe, cq->mcq.cqe_sz);
1104 			dest64->op_own = owner_bit |
1105 				(dest64->op_own & ~MLX5_CQE_OWNER_MASK);
1106 		}
1107 	}
1108 
1109 	if (nfreed) {
1110 		cq->mcq.cons_index += nfreed;
1111 		/* Make sure update of buffer contents is done before
1112 		 * updating consumer index.
1113 		 */
1114 		wmb();
1115 		mlx5_cq_set_ci(&cq->mcq);
1116 	}
1117 }
1118 
mlx5_ib_cq_clean(struct mlx5_ib_cq * cq,u32 qpn,struct mlx5_ib_srq * srq)1119 void mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 qpn, struct mlx5_ib_srq *srq)
1120 {
1121 	if (!cq)
1122 		return;
1123 
1124 	spin_lock_irq(&cq->lock);
1125 	__mlx5_ib_cq_clean(cq, qpn, srq);
1126 	spin_unlock_irq(&cq->lock);
1127 }
1128 
mlx5_ib_modify_cq(struct ib_cq * cq,u16 cq_count,u16 cq_period)1129 int mlx5_ib_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period)
1130 {
1131 	struct mlx5_ib_dev *dev = to_mdev(cq->device);
1132 	struct mlx5_ib_cq *mcq = to_mcq(cq);
1133 	int err;
1134 
1135 	if (!MLX5_CAP_GEN(dev->mdev, cq_moderation))
1136 		return -EOPNOTSUPP;
1137 
1138 	if (cq_period > MLX5_MAX_CQ_PERIOD)
1139 		return -EINVAL;
1140 
1141 	err = mlx5_core_modify_cq_moderation(dev->mdev, &mcq->mcq,
1142 					     cq_period, cq_count);
1143 	if (err)
1144 		mlx5_ib_warn(dev, "modify cq 0x%x failed\n", mcq->mcq.cqn);
1145 
1146 	return err;
1147 }
1148 
resize_user(struct mlx5_ib_dev * dev,struct mlx5_ib_cq * cq,int entries,struct ib_udata * udata,int * cqe_size)1149 static int resize_user(struct mlx5_ib_dev *dev, struct mlx5_ib_cq *cq,
1150 		       int entries, struct ib_udata *udata,
1151 		       int *cqe_size)
1152 {
1153 	struct mlx5_ib_resize_cq ucmd;
1154 	struct ib_umem *umem;
1155 	int err;
1156 
1157 	err = ib_copy_from_udata(&ucmd, udata, sizeof(ucmd));
1158 	if (err)
1159 		return err;
1160 
1161 	if (ucmd.reserved0 || ucmd.reserved1)
1162 		return -EINVAL;
1163 
1164 	/* check multiplication overflow */
1165 	if (ucmd.cqe_size && SIZE_MAX / ucmd.cqe_size <= entries - 1)
1166 		return -EINVAL;
1167 
1168 	umem = ib_umem_get(&dev->ib_dev, ucmd.buf_addr,
1169 			   (size_t)ucmd.cqe_size * entries,
1170 			   IB_ACCESS_LOCAL_WRITE);
1171 	if (IS_ERR(umem)) {
1172 		err = PTR_ERR(umem);
1173 		return err;
1174 	}
1175 
1176 	cq->resize_umem = umem;
1177 	*cqe_size = ucmd.cqe_size;
1178 
1179 	return 0;
1180 }
1181 
resize_kernel(struct mlx5_ib_dev * dev,struct mlx5_ib_cq * cq,int entries,int cqe_size)1182 static int resize_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_cq *cq,
1183 			 int entries, int cqe_size)
1184 {
1185 	int err;
1186 
1187 	cq->resize_buf = kzalloc(sizeof(*cq->resize_buf), GFP_KERNEL);
1188 	if (!cq->resize_buf)
1189 		return -ENOMEM;
1190 
1191 	err = alloc_cq_frag_buf(dev, cq->resize_buf, entries, cqe_size);
1192 	if (err)
1193 		goto ex;
1194 
1195 	init_cq_frag_buf(cq->resize_buf);
1196 
1197 	return 0;
1198 
1199 ex:
1200 	kfree(cq->resize_buf);
1201 	return err;
1202 }
1203 
copy_resize_cqes(struct mlx5_ib_cq * cq)1204 static int copy_resize_cqes(struct mlx5_ib_cq *cq)
1205 {
1206 	struct mlx5_ib_dev *dev = to_mdev(cq->ibcq.device);
1207 	struct mlx5_cqe64 *scqe64;
1208 	struct mlx5_cqe64 *dcqe64;
1209 	void *start_cqe;
1210 	void *scqe;
1211 	void *dcqe;
1212 	int ssize;
1213 	int dsize;
1214 	int i;
1215 	u8 sw_own;
1216 
1217 	ssize = cq->buf.cqe_size;
1218 	dsize = cq->resize_buf->cqe_size;
1219 	if (ssize != dsize) {
1220 		mlx5_ib_warn(dev, "resize from different cqe size is not supported\n");
1221 		return -EINVAL;
1222 	}
1223 
1224 	i = cq->mcq.cons_index;
1225 	scqe = get_sw_cqe(cq, i);
1226 	scqe64 = ssize == 64 ? scqe : scqe + 64;
1227 	start_cqe = scqe;
1228 	if (!scqe) {
1229 		mlx5_ib_warn(dev, "expected cqe in sw ownership\n");
1230 		return -EINVAL;
1231 	}
1232 
1233 	while (get_cqe_opcode(scqe64) != MLX5_CQE_RESIZE_CQ) {
1234 		dcqe = mlx5_frag_buf_get_wqe(&cq->resize_buf->fbc,
1235 					     (i + 1) & cq->resize_buf->nent);
1236 		dcqe64 = dsize == 64 ? dcqe : dcqe + 64;
1237 		sw_own = sw_ownership_bit(i + 1, cq->resize_buf->nent);
1238 		memcpy(dcqe, scqe, dsize);
1239 		dcqe64->op_own = (dcqe64->op_own & ~MLX5_CQE_OWNER_MASK) | sw_own;
1240 
1241 		++i;
1242 		scqe = get_sw_cqe(cq, i);
1243 		scqe64 = ssize == 64 ? scqe : scqe + 64;
1244 		if (!scqe) {
1245 			mlx5_ib_warn(dev, "expected cqe in sw ownership\n");
1246 			return -EINVAL;
1247 		}
1248 
1249 		if (scqe == start_cqe) {
1250 			pr_warn("resize CQ failed to get resize CQE, CQN 0x%x\n",
1251 				cq->mcq.cqn);
1252 			return -ENOMEM;
1253 		}
1254 	}
1255 	++cq->mcq.cons_index;
1256 	return 0;
1257 }
1258 
mlx5_ib_resize_cq(struct ib_cq * ibcq,int entries,struct ib_udata * udata)1259 int mlx5_ib_resize_cq(struct ib_cq *ibcq, int entries, struct ib_udata *udata)
1260 {
1261 	struct mlx5_ib_dev *dev = to_mdev(ibcq->device);
1262 	struct mlx5_ib_cq *cq = to_mcq(ibcq);
1263 	void *cqc;
1264 	u32 *in;
1265 	int err;
1266 	int npas;
1267 	__be64 *pas;
1268 	unsigned int page_offset_quantized = 0;
1269 	unsigned int page_shift;
1270 	int inlen;
1271 	int cqe_size;
1272 	unsigned long flags;
1273 
1274 	if (!MLX5_CAP_GEN(dev->mdev, cq_resize)) {
1275 		pr_info("Firmware does not support resize CQ\n");
1276 		return -ENOSYS;
1277 	}
1278 
1279 	if (entries < 1 ||
1280 	    entries > (1 << MLX5_CAP_GEN(dev->mdev, log_max_cq_sz))) {
1281 		mlx5_ib_warn(dev, "wrong entries number %d, max %d\n",
1282 			     entries,
1283 			     1 << MLX5_CAP_GEN(dev->mdev, log_max_cq_sz));
1284 		return -EINVAL;
1285 	}
1286 
1287 	entries = roundup_pow_of_two(entries + 1);
1288 	if (entries > (1 << MLX5_CAP_GEN(dev->mdev, log_max_cq_sz)) + 1)
1289 		return -EINVAL;
1290 
1291 	if (entries == ibcq->cqe + 1)
1292 		return 0;
1293 
1294 	mutex_lock(&cq->resize_mutex);
1295 	if (udata) {
1296 		unsigned long page_size;
1297 
1298 		err = resize_user(dev, cq, entries, udata, &cqe_size);
1299 		if (err)
1300 			goto ex;
1301 
1302 		page_size = mlx5_umem_find_best_cq_quantized_pgoff(
1303 			cq->resize_umem, cqc, log_page_size,
1304 			MLX5_ADAPTER_PAGE_SHIFT, page_offset, 64,
1305 			&page_offset_quantized);
1306 		if (!page_size) {
1307 			err = -EINVAL;
1308 			goto ex_resize;
1309 		}
1310 		npas = ib_umem_num_dma_blocks(cq->resize_umem, page_size);
1311 		page_shift = order_base_2(page_size);
1312 	} else {
1313 		struct mlx5_frag_buf *frag_buf;
1314 
1315 		cqe_size = 64;
1316 		err = resize_kernel(dev, cq, entries, cqe_size);
1317 		if (err)
1318 			goto ex;
1319 		frag_buf = &cq->resize_buf->frag_buf;
1320 		npas = frag_buf->npages;
1321 		page_shift = frag_buf->page_shift;
1322 	}
1323 
1324 	inlen = MLX5_ST_SZ_BYTES(modify_cq_in) +
1325 		MLX5_FLD_SZ_BYTES(modify_cq_in, pas[0]) * npas;
1326 
1327 	in = kvzalloc(inlen, GFP_KERNEL);
1328 	if (!in) {
1329 		err = -ENOMEM;
1330 		goto ex_resize;
1331 	}
1332 
1333 	pas = (__be64 *)MLX5_ADDR_OF(modify_cq_in, in, pas);
1334 	if (udata)
1335 		mlx5_ib_populate_pas(cq->resize_umem, 1UL << page_shift, pas,
1336 				     0);
1337 	else
1338 		mlx5_fill_page_frag_array(&cq->resize_buf->frag_buf, pas);
1339 
1340 	MLX5_SET(modify_cq_in, in,
1341 		 modify_field_select_resize_field_select.resize_field_select.resize_field_select,
1342 		 MLX5_MODIFY_CQ_MASK_LOG_SIZE  |
1343 		 MLX5_MODIFY_CQ_MASK_PG_OFFSET |
1344 		 MLX5_MODIFY_CQ_MASK_PG_SIZE);
1345 
1346 	cqc = MLX5_ADDR_OF(modify_cq_in, in, cq_context);
1347 
1348 	MLX5_SET(cqc, cqc, log_page_size,
1349 		 page_shift - MLX5_ADAPTER_PAGE_SHIFT);
1350 	MLX5_SET(cqc, cqc, page_offset, page_offset_quantized);
1351 	MLX5_SET(cqc, cqc, cqe_sz,
1352 		 cqe_sz_to_mlx_sz(cqe_size,
1353 				  cq->private_flags &
1354 				  MLX5_IB_CQ_PR_FLAGS_CQE_128_PAD));
1355 	MLX5_SET(cqc, cqc, log_cq_size, ilog2(entries));
1356 
1357 	MLX5_SET(modify_cq_in, in, op_mod, MLX5_CQ_OPMOD_RESIZE);
1358 	MLX5_SET(modify_cq_in, in, cqn, cq->mcq.cqn);
1359 
1360 	err = mlx5_core_modify_cq(dev->mdev, &cq->mcq, in, inlen);
1361 	if (err)
1362 		goto ex_alloc;
1363 
1364 	if (udata) {
1365 		cq->ibcq.cqe = entries - 1;
1366 		ib_umem_release(cq->buf.umem);
1367 		cq->buf.umem = cq->resize_umem;
1368 		cq->resize_umem = NULL;
1369 	} else {
1370 		struct mlx5_ib_cq_buf tbuf;
1371 		int resized = 0;
1372 
1373 		spin_lock_irqsave(&cq->lock, flags);
1374 		if (cq->resize_buf) {
1375 			err = copy_resize_cqes(cq);
1376 			if (!err) {
1377 				tbuf = cq->buf;
1378 				cq->buf = *cq->resize_buf;
1379 				kfree(cq->resize_buf);
1380 				cq->resize_buf = NULL;
1381 				resized = 1;
1382 			}
1383 		}
1384 		cq->ibcq.cqe = entries - 1;
1385 		spin_unlock_irqrestore(&cq->lock, flags);
1386 		if (resized)
1387 			free_cq_buf(dev, &tbuf);
1388 	}
1389 	mutex_unlock(&cq->resize_mutex);
1390 
1391 	kvfree(in);
1392 	return 0;
1393 
1394 ex_alloc:
1395 	kvfree(in);
1396 
1397 ex_resize:
1398 	ib_umem_release(cq->resize_umem);
1399 	if (!udata) {
1400 		free_cq_buf(dev, cq->resize_buf);
1401 		cq->resize_buf = NULL;
1402 	}
1403 ex:
1404 	mutex_unlock(&cq->resize_mutex);
1405 	return err;
1406 }
1407 
mlx5_ib_get_cqe_size(struct ib_cq * ibcq)1408 int mlx5_ib_get_cqe_size(struct ib_cq *ibcq)
1409 {
1410 	struct mlx5_ib_cq *cq;
1411 
1412 	if (!ibcq)
1413 		return 128;
1414 
1415 	cq = to_mcq(ibcq);
1416 	return cq->cqe_size;
1417 }
1418 
1419 /* Called from atomic context */
mlx5_ib_generate_wc(struct ib_cq * ibcq,struct ib_wc * wc)1420 int mlx5_ib_generate_wc(struct ib_cq *ibcq, struct ib_wc *wc)
1421 {
1422 	struct mlx5_ib_wc *soft_wc;
1423 	struct mlx5_ib_cq *cq = to_mcq(ibcq);
1424 	unsigned long flags;
1425 
1426 	soft_wc = kmalloc(sizeof(*soft_wc), GFP_ATOMIC);
1427 	if (!soft_wc)
1428 		return -ENOMEM;
1429 
1430 	soft_wc->wc = *wc;
1431 	spin_lock_irqsave(&cq->lock, flags);
1432 	list_add_tail(&soft_wc->list, &cq->wc_list);
1433 	if (cq->notify_flags == IB_CQ_NEXT_COMP ||
1434 	    wc->status != IB_WC_SUCCESS) {
1435 		cq->notify_flags = 0;
1436 		schedule_work(&cq->notify_work);
1437 	}
1438 	spin_unlock_irqrestore(&cq->lock, flags);
1439 
1440 	return 0;
1441 }
1442