1 /* SPDX-License-Identifier: MIT */ 2 #ifndef __NVIF_CL5070_H__ 3 #define __NVIF_CL5070_H__ 4 5 #define NV50_DISP_MTHD 0x00 6 7 struct nv50_disp_mthd_v0 { 8 __u8 version; 9 #define NV50_DISP_SCANOUTPOS 0x00 10 __u8 method; 11 __u8 head; 12 __u8 pad03[5]; 13 }; 14 15 struct nv50_disp_scanoutpos_v0 { 16 __u8 version; 17 __u8 pad01[7]; 18 __s64 time[2]; 19 __u16 vblanks; 20 __u16 vblanke; 21 __u16 vtotal; 22 __u16 vline; 23 __u16 hblanks; 24 __u16 hblanke; 25 __u16 htotal; 26 __u16 hline; 27 }; 28 29 struct nv50_disp_mthd_v1 { 30 __u8 version; 31 #define NV50_DISP_MTHD_V1_ACQUIRE 0x01 32 #define NV50_DISP_MTHD_V1_RELEASE 0x02 33 #define NV50_DISP_MTHD_V1_SOR_HDA_ELD 0x21 34 #define NV50_DISP_MTHD_V1_SOR_HDMI_PWR 0x22 35 #define NV50_DISP_MTHD_V1_SOR_LVDS_SCRIPT 0x23 36 #define NV50_DISP_MTHD_V1_SOR_DP_MST_LINK 0x25 37 #define NV50_DISP_MTHD_V1_SOR_DP_MST_VCPI 0x26 38 __u8 method; 39 __u16 hasht; 40 __u16 hashm; 41 __u8 pad06[2]; 42 }; 43 44 struct nv50_disp_acquire_v0 { 45 __u8 version; 46 __u8 or; 47 __u8 link; 48 __u8 hda; 49 __u8 pad04[4]; 50 }; 51 52 struct nv50_disp_sor_hda_eld_v0 { 53 __u8 version; 54 __u8 pad01[7]; 55 __u8 data[]; 56 }; 57 58 struct nv50_disp_sor_hdmi_pwr_v0 { 59 __u8 version; 60 __u8 state; 61 __u8 max_ac_packet; 62 __u8 rekey; 63 __u8 avi_infoframe_length; 64 __u8 vendor_infoframe_length; 65 #define NV50_DISP_SOR_HDMI_PWR_V0_SCDC_SCRAMBLE (1 << 0) 66 #define NV50_DISP_SOR_HDMI_PWR_V0_SCDC_DIV_BY_4 (1 << 1) 67 __u8 scdc; 68 __u8 pad07[1]; 69 }; 70 71 struct nv50_disp_sor_lvds_script_v0 { 72 __u8 version; 73 __u8 pad01[1]; 74 __u16 script; 75 __u8 pad04[4]; 76 }; 77 78 struct nv50_disp_sor_dp_mst_link_v0 { 79 __u8 version; 80 __u8 state; 81 __u8 pad02[6]; 82 }; 83 84 struct nv50_disp_sor_dp_mst_vcpi_v0 { 85 __u8 version; 86 __u8 pad01[1]; 87 __u8 start_slot; 88 __u8 num_slots; 89 __u16 pbn; 90 __u16 aligned_pbn; 91 }; 92 #endif 93