1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2017-2019 The Linux Foundation. All rights reserved. */
3
4
5 #include "msm_gem.h"
6 #include "msm_mmu.h"
7 #include "msm_gpu_trace.h"
8 #include "a6xx_gpu.h"
9 #include "a6xx_gmu.xml.h"
10
11 #include <linux/bitfield.h>
12 #include <linux/devfreq.h>
13 #include <linux/reset.h>
14 #include <linux/soc/qcom/llcc-qcom.h>
15
16 #define GPU_PAS_ID 13
17
_a6xx_check_idle(struct msm_gpu * gpu)18 static inline bool _a6xx_check_idle(struct msm_gpu *gpu)
19 {
20 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
21 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
22
23 /* Check that the GMU is idle */
24 if (!a6xx_gmu_isidle(&a6xx_gpu->gmu))
25 return false;
26
27 /* Check tha the CX master is idle */
28 if (gpu_read(gpu, REG_A6XX_RBBM_STATUS) &
29 ~A6XX_RBBM_STATUS_CP_AHB_BUSY_CX_MASTER)
30 return false;
31
32 return !(gpu_read(gpu, REG_A6XX_RBBM_INT_0_STATUS) &
33 A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT);
34 }
35
a6xx_idle(struct msm_gpu * gpu,struct msm_ringbuffer * ring)36 static bool a6xx_idle(struct msm_gpu *gpu, struct msm_ringbuffer *ring)
37 {
38 /* wait for CP to drain ringbuffer: */
39 if (!adreno_idle(gpu, ring))
40 return false;
41
42 if (spin_until(_a6xx_check_idle(gpu))) {
43 DRM_ERROR("%s: %ps: timeout waiting for GPU to idle: status %8.8X irq %8.8X rptr/wptr %d/%d\n",
44 gpu->name, __builtin_return_address(0),
45 gpu_read(gpu, REG_A6XX_RBBM_STATUS),
46 gpu_read(gpu, REG_A6XX_RBBM_INT_0_STATUS),
47 gpu_read(gpu, REG_A6XX_CP_RB_RPTR),
48 gpu_read(gpu, REG_A6XX_CP_RB_WPTR));
49 return false;
50 }
51
52 return true;
53 }
54
update_shadow_rptr(struct msm_gpu * gpu,struct msm_ringbuffer * ring)55 static void update_shadow_rptr(struct msm_gpu *gpu, struct msm_ringbuffer *ring)
56 {
57 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
58 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
59
60 /* Expanded APRIV doesn't need to issue the WHERE_AM_I opcode */
61 if (a6xx_gpu->has_whereami && !adreno_gpu->base.hw_apriv) {
62 OUT_PKT7(ring, CP_WHERE_AM_I, 2);
63 OUT_RING(ring, lower_32_bits(shadowptr(a6xx_gpu, ring)));
64 OUT_RING(ring, upper_32_bits(shadowptr(a6xx_gpu, ring)));
65 }
66 }
67
a6xx_flush(struct msm_gpu * gpu,struct msm_ringbuffer * ring)68 static void a6xx_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring)
69 {
70 uint32_t wptr;
71 unsigned long flags;
72
73 update_shadow_rptr(gpu, ring);
74
75 spin_lock_irqsave(&ring->preempt_lock, flags);
76
77 /* Copy the shadow to the actual register */
78 ring->cur = ring->next;
79
80 /* Make sure to wrap wptr if we need to */
81 wptr = get_wptr(ring);
82
83 spin_unlock_irqrestore(&ring->preempt_lock, flags);
84
85 /* Make sure everything is posted before making a decision */
86 mb();
87
88 gpu_write(gpu, REG_A6XX_CP_RB_WPTR, wptr);
89 }
90
get_stats_counter(struct msm_ringbuffer * ring,u32 counter,u64 iova)91 static void get_stats_counter(struct msm_ringbuffer *ring, u32 counter,
92 u64 iova)
93 {
94 OUT_PKT7(ring, CP_REG_TO_MEM, 3);
95 OUT_RING(ring, CP_REG_TO_MEM_0_REG(counter) |
96 CP_REG_TO_MEM_0_CNT(2) |
97 CP_REG_TO_MEM_0_64B);
98 OUT_RING(ring, lower_32_bits(iova));
99 OUT_RING(ring, upper_32_bits(iova));
100 }
101
a6xx_set_pagetable(struct a6xx_gpu * a6xx_gpu,struct msm_ringbuffer * ring,struct msm_file_private * ctx)102 static void a6xx_set_pagetable(struct a6xx_gpu *a6xx_gpu,
103 struct msm_ringbuffer *ring, struct msm_file_private *ctx)
104 {
105 bool sysprof = refcount_read(&a6xx_gpu->base.base.sysprof_active) > 1;
106 phys_addr_t ttbr;
107 u32 asid;
108 u64 memptr = rbmemptr(ring, ttbr0);
109
110 if (ctx->seqno == a6xx_gpu->base.base.cur_ctx_seqno)
111 return;
112
113 if (msm_iommu_pagetable_params(ctx->aspace->mmu, &ttbr, &asid))
114 return;
115
116 if (!sysprof) {
117 /* Turn off protected mode to write to special registers */
118 OUT_PKT7(ring, CP_SET_PROTECTED_MODE, 1);
119 OUT_RING(ring, 0);
120
121 OUT_PKT4(ring, REG_A6XX_RBBM_PERFCTR_SRAM_INIT_CMD, 1);
122 OUT_RING(ring, 1);
123 }
124
125 /* Execute the table update */
126 OUT_PKT7(ring, CP_SMMU_TABLE_UPDATE, 4);
127 OUT_RING(ring, CP_SMMU_TABLE_UPDATE_0_TTBR0_LO(lower_32_bits(ttbr)));
128
129 OUT_RING(ring,
130 CP_SMMU_TABLE_UPDATE_1_TTBR0_HI(upper_32_bits(ttbr)) |
131 CP_SMMU_TABLE_UPDATE_1_ASID(asid));
132 OUT_RING(ring, CP_SMMU_TABLE_UPDATE_2_CONTEXTIDR(0));
133 OUT_RING(ring, CP_SMMU_TABLE_UPDATE_3_CONTEXTBANK(0));
134
135 /*
136 * Write the new TTBR0 to the memstore. This is good for debugging.
137 */
138 OUT_PKT7(ring, CP_MEM_WRITE, 4);
139 OUT_RING(ring, CP_MEM_WRITE_0_ADDR_LO(lower_32_bits(memptr)));
140 OUT_RING(ring, CP_MEM_WRITE_1_ADDR_HI(upper_32_bits(memptr)));
141 OUT_RING(ring, lower_32_bits(ttbr));
142 OUT_RING(ring, (asid << 16) | upper_32_bits(ttbr));
143
144 /*
145 * And finally, trigger a uche flush to be sure there isn't anything
146 * lingering in that part of the GPU
147 */
148
149 OUT_PKT7(ring, CP_EVENT_WRITE, 1);
150 OUT_RING(ring, CACHE_INVALIDATE);
151
152 if (!sysprof) {
153 /*
154 * Wait for SRAM clear after the pgtable update, so the
155 * two can happen in parallel:
156 */
157 OUT_PKT7(ring, CP_WAIT_REG_MEM, 6);
158 OUT_RING(ring, CP_WAIT_REG_MEM_0_FUNCTION(WRITE_EQ));
159 OUT_RING(ring, CP_WAIT_REG_MEM_1_POLL_ADDR_LO(
160 REG_A6XX_RBBM_PERFCTR_SRAM_INIT_STATUS));
161 OUT_RING(ring, CP_WAIT_REG_MEM_2_POLL_ADDR_HI(0));
162 OUT_RING(ring, CP_WAIT_REG_MEM_3_REF(0x1));
163 OUT_RING(ring, CP_WAIT_REG_MEM_4_MASK(0x1));
164 OUT_RING(ring, CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES(0));
165
166 /* Re-enable protected mode: */
167 OUT_PKT7(ring, CP_SET_PROTECTED_MODE, 1);
168 OUT_RING(ring, 1);
169 }
170 }
171
a6xx_submit(struct msm_gpu * gpu,struct msm_gem_submit * submit)172 static void a6xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit)
173 {
174 unsigned int index = submit->seqno % MSM_GPU_SUBMIT_STATS_COUNT;
175 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
176 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
177 struct msm_ringbuffer *ring = submit->ring;
178 unsigned int i, ibs = 0;
179
180 a6xx_set_pagetable(a6xx_gpu, ring, submit->queue->ctx);
181
182 get_stats_counter(ring, REG_A6XX_RBBM_PERFCTR_CP(0),
183 rbmemptr_stats(ring, index, cpcycles_start));
184
185 /*
186 * For PM4 the GMU register offsets are calculated from the base of the
187 * GPU registers so we need to add 0x1a800 to the register value on A630
188 * to get the right value from PM4.
189 */
190 get_stats_counter(ring, REG_A6XX_CP_ALWAYS_ON_COUNTER_LO,
191 rbmemptr_stats(ring, index, alwayson_start));
192
193 /* Invalidate CCU depth and color */
194 OUT_PKT7(ring, CP_EVENT_WRITE, 1);
195 OUT_RING(ring, CP_EVENT_WRITE_0_EVENT(PC_CCU_INVALIDATE_DEPTH));
196
197 OUT_PKT7(ring, CP_EVENT_WRITE, 1);
198 OUT_RING(ring, CP_EVENT_WRITE_0_EVENT(PC_CCU_INVALIDATE_COLOR));
199
200 /* Submit the commands */
201 for (i = 0; i < submit->nr_cmds; i++) {
202 switch (submit->cmd[i].type) {
203 case MSM_SUBMIT_CMD_IB_TARGET_BUF:
204 break;
205 case MSM_SUBMIT_CMD_CTX_RESTORE_BUF:
206 if (gpu->cur_ctx_seqno == submit->queue->ctx->seqno)
207 break;
208 fallthrough;
209 case MSM_SUBMIT_CMD_BUF:
210 OUT_PKT7(ring, CP_INDIRECT_BUFFER_PFE, 3);
211 OUT_RING(ring, lower_32_bits(submit->cmd[i].iova));
212 OUT_RING(ring, upper_32_bits(submit->cmd[i].iova));
213 OUT_RING(ring, submit->cmd[i].size);
214 ibs++;
215 break;
216 }
217
218 /*
219 * Periodically update shadow-wptr if needed, so that we
220 * can see partial progress of submits with large # of
221 * cmds.. otherwise we could needlessly stall waiting for
222 * ringbuffer state, simply due to looking at a shadow
223 * rptr value that has not been updated
224 */
225 if ((ibs % 32) == 0)
226 update_shadow_rptr(gpu, ring);
227 }
228
229 get_stats_counter(ring, REG_A6XX_RBBM_PERFCTR_CP(0),
230 rbmemptr_stats(ring, index, cpcycles_end));
231 get_stats_counter(ring, REG_A6XX_CP_ALWAYS_ON_COUNTER_LO,
232 rbmemptr_stats(ring, index, alwayson_end));
233
234 /* Write the fence to the scratch register */
235 OUT_PKT4(ring, REG_A6XX_CP_SCRATCH_REG(2), 1);
236 OUT_RING(ring, submit->seqno);
237
238 /*
239 * Execute a CACHE_FLUSH_TS event. This will ensure that the
240 * timestamp is written to the memory and then triggers the interrupt
241 */
242 OUT_PKT7(ring, CP_EVENT_WRITE, 4);
243 OUT_RING(ring, CP_EVENT_WRITE_0_EVENT(CACHE_FLUSH_TS) |
244 CP_EVENT_WRITE_0_IRQ);
245 OUT_RING(ring, lower_32_bits(rbmemptr(ring, fence)));
246 OUT_RING(ring, upper_32_bits(rbmemptr(ring, fence)));
247 OUT_RING(ring, submit->seqno);
248
249 trace_msm_gpu_submit_flush(submit,
250 gpu_read64(gpu, REG_A6XX_CP_ALWAYS_ON_COUNTER_LO,
251 REG_A6XX_CP_ALWAYS_ON_COUNTER_HI));
252
253 a6xx_flush(gpu, ring);
254 }
255
256 /* For a615 family (a615, a616, a618 and a619) */
257 const struct adreno_reglist a615_hwcg[] = {
258 {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222},
259 {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220},
260 {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080},
261 {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000F3CF},
262 {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x02222222},
263 {REG_A6XX_RBBM_CLOCK_CNTL_TP1, 0x02222222},
264 {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222},
265 {REG_A6XX_RBBM_CLOCK_CNTL2_TP1, 0x22222222},
266 {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222},
267 {REG_A6XX_RBBM_CLOCK_CNTL3_TP1, 0x22222222},
268 {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222},
269 {REG_A6XX_RBBM_CLOCK_CNTL4_TP1, 0x00022222},
270 {REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777},
271 {REG_A6XX_RBBM_CLOCK_HYST_TP1, 0x77777777},
272 {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777},
273 {REG_A6XX_RBBM_CLOCK_HYST2_TP1, 0x77777777},
274 {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777},
275 {REG_A6XX_RBBM_CLOCK_HYST3_TP1, 0x77777777},
276 {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777},
277 {REG_A6XX_RBBM_CLOCK_HYST4_TP1, 0x00077777},
278 {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111},
279 {REG_A6XX_RBBM_CLOCK_DELAY_TP1, 0x11111111},
280 {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111},
281 {REG_A6XX_RBBM_CLOCK_DELAY2_TP1, 0x11111111},
282 {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111},
283 {REG_A6XX_RBBM_CLOCK_DELAY3_TP1, 0x11111111},
284 {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111},
285 {REG_A6XX_RBBM_CLOCK_DELAY4_TP1, 0x00011111},
286 {REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222},
287 {REG_A6XX_RBBM_CLOCK_CNTL2_UCHE, 0x22222222},
288 {REG_A6XX_RBBM_CLOCK_CNTL3_UCHE, 0x22222222},
289 {REG_A6XX_RBBM_CLOCK_CNTL4_UCHE, 0x00222222},
290 {REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004},
291 {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002},
292 {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222},
293 {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x00002222},
294 {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002020},
295 {REG_A6XX_RBBM_CLOCK_CNTL_CCU1, 0x00002220},
296 {REG_A6XX_RBBM_CLOCK_CNTL_CCU2, 0x00002220},
297 {REG_A6XX_RBBM_CLOCK_CNTL_CCU3, 0x00002220},
298 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040F00},
299 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU1, 0x00040F00},
300 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU2, 0x00040F00},
301 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU3, 0x00040F00},
302 {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x05022022},
303 {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555},
304 {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011},
305 {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044},
306 {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222},
307 {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222},
308 {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222},
309 {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000},
310 {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004},
311 {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000},
312 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000},
313 {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000},
314 {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200},
315 {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222},
316 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002},
317 {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222},
318 {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222},
319 {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111},
320 {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555},
321 {},
322 };
323
324 const struct adreno_reglist a630_hwcg[] = {
325 {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x22222222},
326 {REG_A6XX_RBBM_CLOCK_CNTL_SP1, 0x22222222},
327 {REG_A6XX_RBBM_CLOCK_CNTL_SP2, 0x22222222},
328 {REG_A6XX_RBBM_CLOCK_CNTL_SP3, 0x22222222},
329 {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02022220},
330 {REG_A6XX_RBBM_CLOCK_CNTL2_SP1, 0x02022220},
331 {REG_A6XX_RBBM_CLOCK_CNTL2_SP2, 0x02022220},
332 {REG_A6XX_RBBM_CLOCK_CNTL2_SP3, 0x02022220},
333 {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080},
334 {REG_A6XX_RBBM_CLOCK_DELAY_SP1, 0x00000080},
335 {REG_A6XX_RBBM_CLOCK_DELAY_SP2, 0x00000080},
336 {REG_A6XX_RBBM_CLOCK_DELAY_SP3, 0x00000080},
337 {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000f3cf},
338 {REG_A6XX_RBBM_CLOCK_HYST_SP1, 0x0000f3cf},
339 {REG_A6XX_RBBM_CLOCK_HYST_SP2, 0x0000f3cf},
340 {REG_A6XX_RBBM_CLOCK_HYST_SP3, 0x0000f3cf},
341 {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x02222222},
342 {REG_A6XX_RBBM_CLOCK_CNTL_TP1, 0x02222222},
343 {REG_A6XX_RBBM_CLOCK_CNTL_TP2, 0x02222222},
344 {REG_A6XX_RBBM_CLOCK_CNTL_TP3, 0x02222222},
345 {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222},
346 {REG_A6XX_RBBM_CLOCK_CNTL2_TP1, 0x22222222},
347 {REG_A6XX_RBBM_CLOCK_CNTL2_TP2, 0x22222222},
348 {REG_A6XX_RBBM_CLOCK_CNTL2_TP3, 0x22222222},
349 {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222},
350 {REG_A6XX_RBBM_CLOCK_CNTL3_TP1, 0x22222222},
351 {REG_A6XX_RBBM_CLOCK_CNTL3_TP2, 0x22222222},
352 {REG_A6XX_RBBM_CLOCK_CNTL3_TP3, 0x22222222},
353 {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222},
354 {REG_A6XX_RBBM_CLOCK_CNTL4_TP1, 0x00022222},
355 {REG_A6XX_RBBM_CLOCK_CNTL4_TP2, 0x00022222},
356 {REG_A6XX_RBBM_CLOCK_CNTL4_TP3, 0x00022222},
357 {REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777},
358 {REG_A6XX_RBBM_CLOCK_HYST_TP1, 0x77777777},
359 {REG_A6XX_RBBM_CLOCK_HYST_TP2, 0x77777777},
360 {REG_A6XX_RBBM_CLOCK_HYST_TP3, 0x77777777},
361 {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777},
362 {REG_A6XX_RBBM_CLOCK_HYST2_TP1, 0x77777777},
363 {REG_A6XX_RBBM_CLOCK_HYST2_TP2, 0x77777777},
364 {REG_A6XX_RBBM_CLOCK_HYST2_TP3, 0x77777777},
365 {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777},
366 {REG_A6XX_RBBM_CLOCK_HYST3_TP1, 0x77777777},
367 {REG_A6XX_RBBM_CLOCK_HYST3_TP2, 0x77777777},
368 {REG_A6XX_RBBM_CLOCK_HYST3_TP3, 0x77777777},
369 {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777},
370 {REG_A6XX_RBBM_CLOCK_HYST4_TP1, 0x00077777},
371 {REG_A6XX_RBBM_CLOCK_HYST4_TP2, 0x00077777},
372 {REG_A6XX_RBBM_CLOCK_HYST4_TP3, 0x00077777},
373 {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111},
374 {REG_A6XX_RBBM_CLOCK_DELAY_TP1, 0x11111111},
375 {REG_A6XX_RBBM_CLOCK_DELAY_TP2, 0x11111111},
376 {REG_A6XX_RBBM_CLOCK_DELAY_TP3, 0x11111111},
377 {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111},
378 {REG_A6XX_RBBM_CLOCK_DELAY2_TP1, 0x11111111},
379 {REG_A6XX_RBBM_CLOCK_DELAY2_TP2, 0x11111111},
380 {REG_A6XX_RBBM_CLOCK_DELAY2_TP3, 0x11111111},
381 {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111},
382 {REG_A6XX_RBBM_CLOCK_DELAY3_TP1, 0x11111111},
383 {REG_A6XX_RBBM_CLOCK_DELAY3_TP2, 0x11111111},
384 {REG_A6XX_RBBM_CLOCK_DELAY3_TP3, 0x11111111},
385 {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111},
386 {REG_A6XX_RBBM_CLOCK_DELAY4_TP1, 0x00011111},
387 {REG_A6XX_RBBM_CLOCK_DELAY4_TP2, 0x00011111},
388 {REG_A6XX_RBBM_CLOCK_DELAY4_TP3, 0x00011111},
389 {REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222},
390 {REG_A6XX_RBBM_CLOCK_CNTL2_UCHE, 0x22222222},
391 {REG_A6XX_RBBM_CLOCK_CNTL3_UCHE, 0x22222222},
392 {REG_A6XX_RBBM_CLOCK_CNTL4_UCHE, 0x00222222},
393 {REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004},
394 {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002},
395 {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222},
396 {REG_A6XX_RBBM_CLOCK_CNTL_RB1, 0x22222222},
397 {REG_A6XX_RBBM_CLOCK_CNTL_RB2, 0x22222222},
398 {REG_A6XX_RBBM_CLOCK_CNTL_RB3, 0x22222222},
399 {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x00002222},
400 {REG_A6XX_RBBM_CLOCK_CNTL2_RB1, 0x00002222},
401 {REG_A6XX_RBBM_CLOCK_CNTL2_RB2, 0x00002222},
402 {REG_A6XX_RBBM_CLOCK_CNTL2_RB3, 0x00002222},
403 {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220},
404 {REG_A6XX_RBBM_CLOCK_CNTL_CCU1, 0x00002220},
405 {REG_A6XX_RBBM_CLOCK_CNTL_CCU2, 0x00002220},
406 {REG_A6XX_RBBM_CLOCK_CNTL_CCU3, 0x00002220},
407 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040f00},
408 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU1, 0x00040f00},
409 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU2, 0x00040f00},
410 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU3, 0x00040f00},
411 {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x05022022},
412 {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555},
413 {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011},
414 {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044},
415 {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222},
416 {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222},
417 {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222},
418 {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000},
419 {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004},
420 {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000},
421 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000},
422 {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000},
423 {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200},
424 {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222},
425 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002},
426 {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222},
427 {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222},
428 {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111},
429 {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555},
430 {},
431 };
432
433 const struct adreno_reglist a640_hwcg[] = {
434 {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222},
435 {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220},
436 {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080},
437 {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000F3CF},
438 {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x02222222},
439 {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222},
440 {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222},
441 {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222},
442 {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111},
443 {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111},
444 {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111},
445 {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111},
446 {REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777},
447 {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777},
448 {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777},
449 {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777},
450 {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222},
451 {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01002222},
452 {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220},
453 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040F00},
454 {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x05222022},
455 {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555},
456 {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011},
457 {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044},
458 {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222},
459 {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222},
460 {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222},
461 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002},
462 {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222},
463 {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000},
464 {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222},
465 {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200},
466 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000},
467 {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000},
468 {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000},
469 {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004},
470 {REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000},
471 {REG_A6XX_RBBM_CLOCK_CNTL_TEX_FCHE, 0x00000222},
472 {REG_A6XX_RBBM_CLOCK_DELAY_TEX_FCHE, 0x00000111},
473 {REG_A6XX_RBBM_CLOCK_HYST_TEX_FCHE, 0x00000000},
474 {REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222},
475 {REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004},
476 {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002},
477 {REG_A6XX_RBBM_ISDB_CNT, 0x00000182},
478 {REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000},
479 {REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000},
480 {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222},
481 {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111},
482 {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555},
483 {},
484 };
485
486 const struct adreno_reglist a650_hwcg[] = {
487 {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222},
488 {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220},
489 {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080},
490 {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000F3CF},
491 {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x02222222},
492 {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222},
493 {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222},
494 {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222},
495 {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111},
496 {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111},
497 {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111},
498 {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111},
499 {REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777},
500 {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777},
501 {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777},
502 {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777},
503 {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222},
504 {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01002222},
505 {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220},
506 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040F00},
507 {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x25222022},
508 {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555},
509 {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011},
510 {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044},
511 {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222},
512 {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222},
513 {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222},
514 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002},
515 {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222},
516 {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000},
517 {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222},
518 {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200},
519 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000},
520 {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000},
521 {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000},
522 {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004},
523 {REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000},
524 {REG_A6XX_RBBM_CLOCK_CNTL_TEX_FCHE, 0x00000222},
525 {REG_A6XX_RBBM_CLOCK_DELAY_TEX_FCHE, 0x00000111},
526 {REG_A6XX_RBBM_CLOCK_HYST_TEX_FCHE, 0x00000777},
527 {REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222},
528 {REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004},
529 {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002},
530 {REG_A6XX_RBBM_ISDB_CNT, 0x00000182},
531 {REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000},
532 {REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000},
533 {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222},
534 {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111},
535 {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555},
536 {},
537 };
538
539 const struct adreno_reglist a660_hwcg[] = {
540 {REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222},
541 {REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220},
542 {REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080},
543 {REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000F3CF},
544 {REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x22222222},
545 {REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222},
546 {REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222},
547 {REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222},
548 {REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111},
549 {REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111},
550 {REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111},
551 {REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111},
552 {REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777},
553 {REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777},
554 {REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777},
555 {REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777},
556 {REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222},
557 {REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01002222},
558 {REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220},
559 {REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040F00},
560 {REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x25222022},
561 {REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555},
562 {REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011},
563 {REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044},
564 {REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222},
565 {REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222},
566 {REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222},
567 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002},
568 {REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222},
569 {REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000},
570 {REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222},
571 {REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200},
572 {REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000},
573 {REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000},
574 {REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000},
575 {REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004},
576 {REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000},
577 {REG_A6XX_RBBM_CLOCK_CNTL_TEX_FCHE, 0x00000222},
578 {REG_A6XX_RBBM_CLOCK_DELAY_TEX_FCHE, 0x00000111},
579 {REG_A6XX_RBBM_CLOCK_HYST_TEX_FCHE, 0x00000000},
580 {REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222},
581 {REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004},
582 {REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002},
583 {REG_A6XX_RBBM_ISDB_CNT, 0x00000182},
584 {REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000},
585 {REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000},
586 {REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222},
587 {REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111},
588 {REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555},
589 {},
590 };
591
a6xx_set_hwcg(struct msm_gpu * gpu,bool state)592 static void a6xx_set_hwcg(struct msm_gpu *gpu, bool state)
593 {
594 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
595 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
596 struct a6xx_gmu *gmu = &a6xx_gpu->gmu;
597 const struct adreno_reglist *reg;
598 unsigned int i;
599 u32 val, clock_cntl_on;
600
601 if (!adreno_gpu->info->hwcg)
602 return;
603
604 if (adreno_is_a630(adreno_gpu))
605 clock_cntl_on = 0x8aa8aa02;
606 else
607 clock_cntl_on = 0x8aa8aa82;
608
609 val = gpu_read(gpu, REG_A6XX_RBBM_CLOCK_CNTL);
610
611 /* Don't re-program the registers if they are already correct */
612 if ((!state && !val) || (state && (val == clock_cntl_on)))
613 return;
614
615 /* Disable SP clock before programming HWCG registers */
616 gmu_rmw(gmu, REG_A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL, 1, 0);
617
618 for (i = 0; (reg = &adreno_gpu->info->hwcg[i], reg->offset); i++)
619 gpu_write(gpu, reg->offset, state ? reg->value : 0);
620
621 /* Enable SP clock */
622 gmu_rmw(gmu, REG_A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL, 0, 1);
623
624 gpu_write(gpu, REG_A6XX_RBBM_CLOCK_CNTL, state ? clock_cntl_on : 0);
625 }
626
627 /* For a615, a616, a618, a619, a630, a640 and a680 */
628 static const u32 a6xx_protect[] = {
629 A6XX_PROTECT_RDONLY(0x00000, 0x04ff),
630 A6XX_PROTECT_RDONLY(0x00501, 0x0005),
631 A6XX_PROTECT_RDONLY(0x0050b, 0x02f4),
632 A6XX_PROTECT_NORDWR(0x0050e, 0x0000),
633 A6XX_PROTECT_NORDWR(0x00510, 0x0000),
634 A6XX_PROTECT_NORDWR(0x00534, 0x0000),
635 A6XX_PROTECT_NORDWR(0x00800, 0x0082),
636 A6XX_PROTECT_NORDWR(0x008a0, 0x0008),
637 A6XX_PROTECT_NORDWR(0x008ab, 0x0024),
638 A6XX_PROTECT_RDONLY(0x008de, 0x00ae),
639 A6XX_PROTECT_NORDWR(0x00900, 0x004d),
640 A6XX_PROTECT_NORDWR(0x0098d, 0x0272),
641 A6XX_PROTECT_NORDWR(0x00e00, 0x0001),
642 A6XX_PROTECT_NORDWR(0x00e03, 0x000c),
643 A6XX_PROTECT_NORDWR(0x03c00, 0x00c3),
644 A6XX_PROTECT_RDONLY(0x03cc4, 0x1fff),
645 A6XX_PROTECT_NORDWR(0x08630, 0x01cf),
646 A6XX_PROTECT_NORDWR(0x08e00, 0x0000),
647 A6XX_PROTECT_NORDWR(0x08e08, 0x0000),
648 A6XX_PROTECT_NORDWR(0x08e50, 0x001f),
649 A6XX_PROTECT_NORDWR(0x09624, 0x01db),
650 A6XX_PROTECT_NORDWR(0x09e70, 0x0001),
651 A6XX_PROTECT_NORDWR(0x09e78, 0x0187),
652 A6XX_PROTECT_NORDWR(0x0a630, 0x01cf),
653 A6XX_PROTECT_NORDWR(0x0ae02, 0x0000),
654 A6XX_PROTECT_NORDWR(0x0ae50, 0x032f),
655 A6XX_PROTECT_NORDWR(0x0b604, 0x0000),
656 A6XX_PROTECT_NORDWR(0x0be02, 0x0001),
657 A6XX_PROTECT_NORDWR(0x0be20, 0x17df),
658 A6XX_PROTECT_NORDWR(0x0f000, 0x0bff),
659 A6XX_PROTECT_RDONLY(0x0fc00, 0x1fff),
660 A6XX_PROTECT_NORDWR(0x11c00, 0x0000), /* note: infinite range */
661 };
662
663 /* These are for a620 and a650 */
664 static const u32 a650_protect[] = {
665 A6XX_PROTECT_RDONLY(0x00000, 0x04ff),
666 A6XX_PROTECT_RDONLY(0x00501, 0x0005),
667 A6XX_PROTECT_RDONLY(0x0050b, 0x02f4),
668 A6XX_PROTECT_NORDWR(0x0050e, 0x0000),
669 A6XX_PROTECT_NORDWR(0x00510, 0x0000),
670 A6XX_PROTECT_NORDWR(0x00534, 0x0000),
671 A6XX_PROTECT_NORDWR(0x00800, 0x0082),
672 A6XX_PROTECT_NORDWR(0x008a0, 0x0008),
673 A6XX_PROTECT_NORDWR(0x008ab, 0x0024),
674 A6XX_PROTECT_RDONLY(0x008de, 0x00ae),
675 A6XX_PROTECT_NORDWR(0x00900, 0x004d),
676 A6XX_PROTECT_NORDWR(0x0098d, 0x0272),
677 A6XX_PROTECT_NORDWR(0x00e00, 0x0001),
678 A6XX_PROTECT_NORDWR(0x00e03, 0x000c),
679 A6XX_PROTECT_NORDWR(0x03c00, 0x00c3),
680 A6XX_PROTECT_RDONLY(0x03cc4, 0x1fff),
681 A6XX_PROTECT_NORDWR(0x08630, 0x01cf),
682 A6XX_PROTECT_NORDWR(0x08e00, 0x0000),
683 A6XX_PROTECT_NORDWR(0x08e08, 0x0000),
684 A6XX_PROTECT_NORDWR(0x08e50, 0x001f),
685 A6XX_PROTECT_NORDWR(0x08e80, 0x027f),
686 A6XX_PROTECT_NORDWR(0x09624, 0x01db),
687 A6XX_PROTECT_NORDWR(0x09e60, 0x0011),
688 A6XX_PROTECT_NORDWR(0x09e78, 0x0187),
689 A6XX_PROTECT_NORDWR(0x0a630, 0x01cf),
690 A6XX_PROTECT_NORDWR(0x0ae02, 0x0000),
691 A6XX_PROTECT_NORDWR(0x0ae50, 0x032f),
692 A6XX_PROTECT_NORDWR(0x0b604, 0x0000),
693 A6XX_PROTECT_NORDWR(0x0b608, 0x0007),
694 A6XX_PROTECT_NORDWR(0x0be02, 0x0001),
695 A6XX_PROTECT_NORDWR(0x0be20, 0x17df),
696 A6XX_PROTECT_NORDWR(0x0f000, 0x0bff),
697 A6XX_PROTECT_RDONLY(0x0fc00, 0x1fff),
698 A6XX_PROTECT_NORDWR(0x18400, 0x1fff),
699 A6XX_PROTECT_NORDWR(0x1a800, 0x1fff),
700 A6XX_PROTECT_NORDWR(0x1f400, 0x0443),
701 A6XX_PROTECT_RDONLY(0x1f844, 0x007b),
702 A6XX_PROTECT_NORDWR(0x1f887, 0x001b),
703 A6XX_PROTECT_NORDWR(0x1f8c0, 0x0000), /* note: infinite range */
704 };
705
706 /* These are for a635 and a660 */
707 static const u32 a660_protect[] = {
708 A6XX_PROTECT_RDONLY(0x00000, 0x04ff),
709 A6XX_PROTECT_RDONLY(0x00501, 0x0005),
710 A6XX_PROTECT_RDONLY(0x0050b, 0x02f4),
711 A6XX_PROTECT_NORDWR(0x0050e, 0x0000),
712 A6XX_PROTECT_NORDWR(0x00510, 0x0000),
713 A6XX_PROTECT_NORDWR(0x00534, 0x0000),
714 A6XX_PROTECT_NORDWR(0x00800, 0x0082),
715 A6XX_PROTECT_NORDWR(0x008a0, 0x0008),
716 A6XX_PROTECT_NORDWR(0x008ab, 0x0024),
717 A6XX_PROTECT_RDONLY(0x008de, 0x00ae),
718 A6XX_PROTECT_NORDWR(0x00900, 0x004d),
719 A6XX_PROTECT_NORDWR(0x0098d, 0x0272),
720 A6XX_PROTECT_NORDWR(0x00e00, 0x0001),
721 A6XX_PROTECT_NORDWR(0x00e03, 0x000c),
722 A6XX_PROTECT_NORDWR(0x03c00, 0x00c3),
723 A6XX_PROTECT_RDONLY(0x03cc4, 0x1fff),
724 A6XX_PROTECT_NORDWR(0x08630, 0x01cf),
725 A6XX_PROTECT_NORDWR(0x08e00, 0x0000),
726 A6XX_PROTECT_NORDWR(0x08e08, 0x0000),
727 A6XX_PROTECT_NORDWR(0x08e50, 0x001f),
728 A6XX_PROTECT_NORDWR(0x08e80, 0x027f),
729 A6XX_PROTECT_NORDWR(0x09624, 0x01db),
730 A6XX_PROTECT_NORDWR(0x09e60, 0x0011),
731 A6XX_PROTECT_NORDWR(0x09e78, 0x0187),
732 A6XX_PROTECT_NORDWR(0x0a630, 0x01cf),
733 A6XX_PROTECT_NORDWR(0x0ae02, 0x0000),
734 A6XX_PROTECT_NORDWR(0x0ae50, 0x012f),
735 A6XX_PROTECT_NORDWR(0x0b604, 0x0000),
736 A6XX_PROTECT_NORDWR(0x0b608, 0x0006),
737 A6XX_PROTECT_NORDWR(0x0be02, 0x0001),
738 A6XX_PROTECT_NORDWR(0x0be20, 0x015f),
739 A6XX_PROTECT_NORDWR(0x0d000, 0x05ff),
740 A6XX_PROTECT_NORDWR(0x0f000, 0x0bff),
741 A6XX_PROTECT_RDONLY(0x0fc00, 0x1fff),
742 A6XX_PROTECT_NORDWR(0x18400, 0x1fff),
743 A6XX_PROTECT_NORDWR(0x1a400, 0x1fff),
744 A6XX_PROTECT_NORDWR(0x1f400, 0x0443),
745 A6XX_PROTECT_RDONLY(0x1f844, 0x007b),
746 A6XX_PROTECT_NORDWR(0x1f860, 0x0000),
747 A6XX_PROTECT_NORDWR(0x1f887, 0x001b),
748 A6XX_PROTECT_NORDWR(0x1f8c0, 0x0000), /* note: infinite range */
749 };
750
a6xx_set_cp_protect(struct msm_gpu * gpu)751 static void a6xx_set_cp_protect(struct msm_gpu *gpu)
752 {
753 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
754 const u32 *regs = a6xx_protect;
755 unsigned i, count, count_max;
756
757 if (adreno_is_a650(adreno_gpu)) {
758 regs = a650_protect;
759 count = ARRAY_SIZE(a650_protect);
760 count_max = 48;
761 BUILD_BUG_ON(ARRAY_SIZE(a650_protect) > 48);
762 } else if (adreno_is_a660_family(adreno_gpu)) {
763 regs = a660_protect;
764 count = ARRAY_SIZE(a660_protect);
765 count_max = 48;
766 BUILD_BUG_ON(ARRAY_SIZE(a660_protect) > 48);
767 } else {
768 regs = a6xx_protect;
769 count = ARRAY_SIZE(a6xx_protect);
770 count_max = 32;
771 BUILD_BUG_ON(ARRAY_SIZE(a6xx_protect) > 32);
772 }
773
774 /*
775 * Enable access protection to privileged registers, fault on an access
776 * protect violation and select the last span to protect from the start
777 * address all the way to the end of the register address space
778 */
779 gpu_write(gpu, REG_A6XX_CP_PROTECT_CNTL, BIT(0) | BIT(1) | BIT(3));
780
781 for (i = 0; i < count - 1; i++)
782 gpu_write(gpu, REG_A6XX_CP_PROTECT(i), regs[i]);
783 /* last CP_PROTECT to have "infinite" length on the last entry */
784 gpu_write(gpu, REG_A6XX_CP_PROTECT(count_max - 1), regs[i]);
785 }
786
a6xx_set_ubwc_config(struct msm_gpu * gpu)787 static void a6xx_set_ubwc_config(struct msm_gpu *gpu)
788 {
789 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
790 u32 lower_bit = 2;
791 u32 amsbc = 0;
792 u32 rgb565_predicator = 0;
793 u32 uavflagprd_inv = 0;
794
795 /* a618 is using the hw default values */
796 if (adreno_is_a618(adreno_gpu))
797 return;
798
799 if (adreno_is_a640_family(adreno_gpu))
800 amsbc = 1;
801
802 if (adreno_is_a650(adreno_gpu) || adreno_is_a660(adreno_gpu)) {
803 /* TODO: get ddr type from bootloader and use 2 for LPDDR4 */
804 lower_bit = 3;
805 amsbc = 1;
806 rgb565_predicator = 1;
807 uavflagprd_inv = 2;
808 }
809
810 if (adreno_is_7c3(adreno_gpu)) {
811 lower_bit = 1;
812 amsbc = 1;
813 rgb565_predicator = 1;
814 uavflagprd_inv = 2;
815 }
816
817 gpu_write(gpu, REG_A6XX_RB_NC_MODE_CNTL,
818 rgb565_predicator << 11 | amsbc << 4 | lower_bit << 1);
819 gpu_write(gpu, REG_A6XX_TPL1_NC_MODE_CNTL, lower_bit << 1);
820 gpu_write(gpu, REG_A6XX_SP_NC_MODE_CNTL,
821 uavflagprd_inv << 4 | lower_bit << 1);
822 gpu_write(gpu, REG_A6XX_UCHE_MODE_CNTL, lower_bit << 21);
823 }
824
a6xx_cp_init(struct msm_gpu * gpu)825 static int a6xx_cp_init(struct msm_gpu *gpu)
826 {
827 struct msm_ringbuffer *ring = gpu->rb[0];
828
829 OUT_PKT7(ring, CP_ME_INIT, 8);
830
831 OUT_RING(ring, 0x0000002f);
832
833 /* Enable multiple hardware contexts */
834 OUT_RING(ring, 0x00000003);
835
836 /* Enable error detection */
837 OUT_RING(ring, 0x20000000);
838
839 /* Don't enable header dump */
840 OUT_RING(ring, 0x00000000);
841 OUT_RING(ring, 0x00000000);
842
843 /* No workarounds enabled */
844 OUT_RING(ring, 0x00000000);
845
846 /* Pad rest of the cmds with 0's */
847 OUT_RING(ring, 0x00000000);
848 OUT_RING(ring, 0x00000000);
849
850 a6xx_flush(gpu, ring);
851 return a6xx_idle(gpu, ring) ? 0 : -EINVAL;
852 }
853
854 /*
855 * Check that the microcode version is new enough to include several key
856 * security fixes. Return true if the ucode is safe.
857 */
a6xx_ucode_check_version(struct a6xx_gpu * a6xx_gpu,struct drm_gem_object * obj)858 static bool a6xx_ucode_check_version(struct a6xx_gpu *a6xx_gpu,
859 struct drm_gem_object *obj)
860 {
861 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
862 struct msm_gpu *gpu = &adreno_gpu->base;
863 const char *sqe_name = adreno_gpu->info->fw[ADRENO_FW_SQE];
864 u32 *buf = msm_gem_get_vaddr(obj);
865 bool ret = false;
866
867 if (IS_ERR(buf))
868 return false;
869
870 /*
871 * Targets up to a640 (a618, a630 and a640) need to check for a
872 * microcode version that is patched to support the whereami opcode or
873 * one that is new enough to include it by default.
874 *
875 * a650 tier targets don't need whereami but still need to be
876 * equal to or newer than 0.95 for other security fixes
877 *
878 * a660 targets have all the critical security fixes from the start
879 */
880 if (!strcmp(sqe_name, "a630_sqe.fw")) {
881 /*
882 * If the lowest nibble is 0xa that is an indication that this
883 * microcode has been patched. The actual version is in dword
884 * [3] but we only care about the patchlevel which is the lowest
885 * nibble of dword [3]
886 *
887 * Otherwise check that the firmware is greater than or equal
888 * to 1.90 which was the first version that had this fix built
889 * in
890 */
891 if ((((buf[0] & 0xf) == 0xa) && (buf[2] & 0xf) >= 1) ||
892 (buf[0] & 0xfff) >= 0x190) {
893 a6xx_gpu->has_whereami = true;
894 ret = true;
895 goto out;
896 }
897
898 DRM_DEV_ERROR(&gpu->pdev->dev,
899 "a630 SQE ucode is too old. Have version %x need at least %x\n",
900 buf[0] & 0xfff, 0x190);
901 } else if (!strcmp(sqe_name, "a650_sqe.fw")) {
902 if ((buf[0] & 0xfff) >= 0x095) {
903 ret = true;
904 goto out;
905 }
906
907 DRM_DEV_ERROR(&gpu->pdev->dev,
908 "a650 SQE ucode is too old. Have version %x need at least %x\n",
909 buf[0] & 0xfff, 0x095);
910 } else if (!strcmp(sqe_name, "a660_sqe.fw")) {
911 ret = true;
912 } else {
913 DRM_DEV_ERROR(&gpu->pdev->dev,
914 "unknown GPU, add it to a6xx_ucode_check_version()!!\n");
915 }
916 out:
917 msm_gem_put_vaddr(obj);
918 return ret;
919 }
920
a6xx_ucode_init(struct msm_gpu * gpu)921 static int a6xx_ucode_init(struct msm_gpu *gpu)
922 {
923 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
924 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
925
926 if (!a6xx_gpu->sqe_bo) {
927 a6xx_gpu->sqe_bo = adreno_fw_create_bo(gpu,
928 adreno_gpu->fw[ADRENO_FW_SQE], &a6xx_gpu->sqe_iova);
929
930 if (IS_ERR(a6xx_gpu->sqe_bo)) {
931 int ret = PTR_ERR(a6xx_gpu->sqe_bo);
932
933 a6xx_gpu->sqe_bo = NULL;
934 DRM_DEV_ERROR(&gpu->pdev->dev,
935 "Could not allocate SQE ucode: %d\n", ret);
936
937 return ret;
938 }
939
940 msm_gem_object_set_name(a6xx_gpu->sqe_bo, "sqefw");
941 if (!a6xx_ucode_check_version(a6xx_gpu, a6xx_gpu->sqe_bo)) {
942 msm_gem_unpin_iova(a6xx_gpu->sqe_bo, gpu->aspace);
943 drm_gem_object_put(a6xx_gpu->sqe_bo);
944
945 a6xx_gpu->sqe_bo = NULL;
946 return -EPERM;
947 }
948 }
949
950 gpu_write64(gpu, REG_A6XX_CP_SQE_INSTR_BASE,
951 REG_A6XX_CP_SQE_INSTR_BASE+1, a6xx_gpu->sqe_iova);
952
953 return 0;
954 }
955
a6xx_zap_shader_init(struct msm_gpu * gpu)956 static int a6xx_zap_shader_init(struct msm_gpu *gpu)
957 {
958 static bool loaded;
959 int ret;
960
961 if (loaded)
962 return 0;
963
964 ret = adreno_zap_shader_load(gpu, GPU_PAS_ID);
965
966 loaded = !ret;
967 return ret;
968 }
969
970 #define A6XX_INT_MASK (A6XX_RBBM_INT_0_MASK_CP_AHB_ERROR | \
971 A6XX_RBBM_INT_0_MASK_RBBM_ATB_ASYNCFIFO_OVERFLOW | \
972 A6XX_RBBM_INT_0_MASK_CP_HW_ERROR | \
973 A6XX_RBBM_INT_0_MASK_CP_IB2 | \
974 A6XX_RBBM_INT_0_MASK_CP_IB1 | \
975 A6XX_RBBM_INT_0_MASK_CP_RB | \
976 A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS | \
977 A6XX_RBBM_INT_0_MASK_RBBM_ATB_BUS_OVERFLOW | \
978 A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT | \
979 A6XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS | \
980 A6XX_RBBM_INT_0_MASK_UCHE_TRAP_INTR)
981
hw_init(struct msm_gpu * gpu)982 static int hw_init(struct msm_gpu *gpu)
983 {
984 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
985 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
986 int ret;
987
988 /* Make sure the GMU keeps the GPU on while we set it up */
989 a6xx_gmu_set_oob(&a6xx_gpu->gmu, GMU_OOB_GPU_SET);
990
991 /* Clear GBIF halt in case GX domain was not collapsed */
992 if (a6xx_has_gbif(adreno_gpu))
993 gpu_write(gpu, REG_A6XX_RBBM_GBIF_HALT, 0);
994
995 gpu_write(gpu, REG_A6XX_RBBM_SECVID_TSB_CNTL, 0);
996
997 /*
998 * Disable the trusted memory range - we don't actually supported secure
999 * memory rendering at this point in time and we don't want to block off
1000 * part of the virtual memory space.
1001 */
1002 gpu_write64(gpu, REG_A6XX_RBBM_SECVID_TSB_TRUSTED_BASE_LO,
1003 REG_A6XX_RBBM_SECVID_TSB_TRUSTED_BASE_HI, 0x00000000);
1004 gpu_write(gpu, REG_A6XX_RBBM_SECVID_TSB_TRUSTED_SIZE, 0x00000000);
1005
1006 /* Turn on 64 bit addressing for all blocks */
1007 gpu_write(gpu, REG_A6XX_CP_ADDR_MODE_CNTL, 0x1);
1008 gpu_write(gpu, REG_A6XX_VSC_ADDR_MODE_CNTL, 0x1);
1009 gpu_write(gpu, REG_A6XX_GRAS_ADDR_MODE_CNTL, 0x1);
1010 gpu_write(gpu, REG_A6XX_RB_ADDR_MODE_CNTL, 0x1);
1011 gpu_write(gpu, REG_A6XX_PC_ADDR_MODE_CNTL, 0x1);
1012 gpu_write(gpu, REG_A6XX_HLSQ_ADDR_MODE_CNTL, 0x1);
1013 gpu_write(gpu, REG_A6XX_VFD_ADDR_MODE_CNTL, 0x1);
1014 gpu_write(gpu, REG_A6XX_VPC_ADDR_MODE_CNTL, 0x1);
1015 gpu_write(gpu, REG_A6XX_UCHE_ADDR_MODE_CNTL, 0x1);
1016 gpu_write(gpu, REG_A6XX_SP_ADDR_MODE_CNTL, 0x1);
1017 gpu_write(gpu, REG_A6XX_TPL1_ADDR_MODE_CNTL, 0x1);
1018 gpu_write(gpu, REG_A6XX_RBBM_SECVID_TSB_ADDR_MODE_CNTL, 0x1);
1019
1020 /* enable hardware clockgating */
1021 a6xx_set_hwcg(gpu, true);
1022
1023 /* VBIF/GBIF start*/
1024 if (adreno_is_a640_family(adreno_gpu) ||
1025 adreno_is_a650_family(adreno_gpu)) {
1026 gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE0, 0x00071620);
1027 gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE1, 0x00071620);
1028 gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE2, 0x00071620);
1029 gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE3, 0x00071620);
1030 gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE3, 0x00071620);
1031 gpu_write(gpu, REG_A6XX_RBBM_GBIF_CLIENT_QOS_CNTL, 0x3);
1032 } else {
1033 gpu_write(gpu, REG_A6XX_RBBM_VBIF_CLIENT_QOS_CNTL, 0x3);
1034 }
1035
1036 if (adreno_is_a630(adreno_gpu))
1037 gpu_write(gpu, REG_A6XX_VBIF_GATE_OFF_WRREQ_EN, 0x00000009);
1038
1039 /* Make all blocks contribute to the GPU BUSY perf counter */
1040 gpu_write(gpu, REG_A6XX_RBBM_PERFCTR_GPU_BUSY_MASKED, 0xffffffff);
1041
1042 /* Disable L2 bypass in the UCHE */
1043 gpu_write(gpu, REG_A6XX_UCHE_WRITE_RANGE_MAX_LO, 0xffffffc0);
1044 gpu_write(gpu, REG_A6XX_UCHE_WRITE_RANGE_MAX_HI, 0x0001ffff);
1045 gpu_write(gpu, REG_A6XX_UCHE_TRAP_BASE_LO, 0xfffff000);
1046 gpu_write(gpu, REG_A6XX_UCHE_TRAP_BASE_HI, 0x0001ffff);
1047 gpu_write(gpu, REG_A6XX_UCHE_WRITE_THRU_BASE_LO, 0xfffff000);
1048 gpu_write(gpu, REG_A6XX_UCHE_WRITE_THRU_BASE_HI, 0x0001ffff);
1049
1050 if (!adreno_is_a650_family(adreno_gpu)) {
1051 /* Set the GMEM VA range [0x100000:0x100000 + gpu->gmem - 1] */
1052 gpu_write64(gpu, REG_A6XX_UCHE_GMEM_RANGE_MIN_LO,
1053 REG_A6XX_UCHE_GMEM_RANGE_MIN_HI, 0x00100000);
1054
1055 gpu_write64(gpu, REG_A6XX_UCHE_GMEM_RANGE_MAX_LO,
1056 REG_A6XX_UCHE_GMEM_RANGE_MAX_HI,
1057 0x00100000 + adreno_gpu->gmem - 1);
1058 }
1059
1060 gpu_write(gpu, REG_A6XX_UCHE_FILTER_CNTL, 0x804);
1061 gpu_write(gpu, REG_A6XX_UCHE_CACHE_WAYS, 0x4);
1062
1063 if (adreno_is_a640_family(adreno_gpu) ||
1064 adreno_is_a650_family(adreno_gpu))
1065 gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_2, 0x02000140);
1066 else
1067 gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_2, 0x010000c0);
1068 gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_1, 0x8040362c);
1069
1070 if (adreno_is_a660_family(adreno_gpu))
1071 gpu_write(gpu, REG_A6XX_CP_LPAC_PROG_FIFO_SIZE, 0x00000020);
1072
1073 /* Setting the mem pool size */
1074 gpu_write(gpu, REG_A6XX_CP_MEM_POOL_SIZE, 128);
1075
1076 /* Setting the primFifo thresholds default values,
1077 * and vccCacheSkipDis=1 bit (0x200) for A640 and newer
1078 */
1079 if (adreno_is_a650(adreno_gpu) || adreno_is_a660(adreno_gpu))
1080 gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00300200);
1081 else if (adreno_is_a640_family(adreno_gpu) || adreno_is_7c3(adreno_gpu))
1082 gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00200200);
1083 else if (adreno_is_a650(adreno_gpu) || adreno_is_a660(adreno_gpu))
1084 gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00300200);
1085 else
1086 gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00180000);
1087
1088 /* Set the AHB default slave response to "ERROR" */
1089 gpu_write(gpu, REG_A6XX_CP_AHB_CNTL, 0x1);
1090
1091 /* Turn on performance counters */
1092 gpu_write(gpu, REG_A6XX_RBBM_PERFCTR_CNTL, 0x1);
1093
1094 /* Select CP0 to always count cycles */
1095 gpu_write(gpu, REG_A6XX_CP_PERFCTR_CP_SEL(0), PERF_CP_ALWAYS_COUNT);
1096
1097 a6xx_set_ubwc_config(gpu);
1098
1099 /* Enable fault detection */
1100 gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL,
1101 (1 << 30) | 0x1fffff);
1102
1103 gpu_write(gpu, REG_A6XX_UCHE_CLIENT_PF, 1);
1104
1105 /* Set weights for bicubic filtering */
1106 if (adreno_is_a650_family(adreno_gpu)) {
1107 gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_0, 0);
1108 gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_1,
1109 0x3fe05ff4);
1110 gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_2,
1111 0x3fa0ebee);
1112 gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_3,
1113 0x3f5193ed);
1114 gpu_write(gpu, REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_4,
1115 0x3f0243f0);
1116 }
1117
1118 /* Protect registers from the CP */
1119 a6xx_set_cp_protect(gpu);
1120
1121 if (adreno_is_a660_family(adreno_gpu)) {
1122 gpu_write(gpu, REG_A6XX_CP_CHICKEN_DBG, 0x1);
1123 gpu_write(gpu, REG_A6XX_RBBM_GBIF_CLIENT_QOS_CNTL, 0x0);
1124 }
1125
1126 /* Set dualQ + disable afull for A660 GPU */
1127 if (adreno_is_a660(adreno_gpu))
1128 gpu_write(gpu, REG_A6XX_UCHE_CMDQ_CONFIG, 0x66906);
1129
1130 /* Enable expanded apriv for targets that support it */
1131 if (gpu->hw_apriv) {
1132 gpu_write(gpu, REG_A6XX_CP_APRIV_CNTL,
1133 (1 << 6) | (1 << 5) | (1 << 3) | (1 << 2) | (1 << 1));
1134 }
1135
1136 /* Enable interrupts */
1137 gpu_write(gpu, REG_A6XX_RBBM_INT_0_MASK, A6XX_INT_MASK);
1138
1139 ret = adreno_hw_init(gpu);
1140 if (ret)
1141 goto out;
1142
1143 ret = a6xx_ucode_init(gpu);
1144 if (ret)
1145 goto out;
1146
1147 /* Set the ringbuffer address */
1148 gpu_write64(gpu, REG_A6XX_CP_RB_BASE, REG_A6XX_CP_RB_BASE_HI,
1149 gpu->rb[0]->iova);
1150
1151 /* Targets that support extended APRIV can use the RPTR shadow from
1152 * hardware but all the other ones need to disable the feature. Targets
1153 * that support the WHERE_AM_I opcode can use that instead
1154 */
1155 if (adreno_gpu->base.hw_apriv)
1156 gpu_write(gpu, REG_A6XX_CP_RB_CNTL, MSM_GPU_RB_CNTL_DEFAULT);
1157 else
1158 gpu_write(gpu, REG_A6XX_CP_RB_CNTL,
1159 MSM_GPU_RB_CNTL_DEFAULT | AXXX_CP_RB_CNTL_NO_UPDATE);
1160
1161 /*
1162 * Expanded APRIV and targets that support WHERE_AM_I both need a
1163 * privileged buffer to store the RPTR shadow
1164 */
1165
1166 if (adreno_gpu->base.hw_apriv || a6xx_gpu->has_whereami) {
1167 if (!a6xx_gpu->shadow_bo) {
1168 a6xx_gpu->shadow = msm_gem_kernel_new(gpu->dev,
1169 sizeof(u32) * gpu->nr_rings,
1170 MSM_BO_WC | MSM_BO_MAP_PRIV,
1171 gpu->aspace, &a6xx_gpu->shadow_bo,
1172 &a6xx_gpu->shadow_iova);
1173
1174 if (IS_ERR(a6xx_gpu->shadow))
1175 return PTR_ERR(a6xx_gpu->shadow);
1176
1177 msm_gem_object_set_name(a6xx_gpu->shadow_bo, "shadow");
1178 }
1179
1180 gpu_write64(gpu, REG_A6XX_CP_RB_RPTR_ADDR_LO,
1181 REG_A6XX_CP_RB_RPTR_ADDR_HI,
1182 shadowptr(a6xx_gpu, gpu->rb[0]));
1183 }
1184
1185 /* Always come up on rb 0 */
1186 a6xx_gpu->cur_ring = gpu->rb[0];
1187
1188 gpu->cur_ctx_seqno = 0;
1189
1190 /* Enable the SQE_to start the CP engine */
1191 gpu_write(gpu, REG_A6XX_CP_SQE_CNTL, 1);
1192
1193 ret = a6xx_cp_init(gpu);
1194 if (ret)
1195 goto out;
1196
1197 /*
1198 * Try to load a zap shader into the secure world. If successful
1199 * we can use the CP to switch out of secure mode. If not then we
1200 * have no resource but to try to switch ourselves out manually. If we
1201 * guessed wrong then access to the RBBM_SECVID_TRUST_CNTL register will
1202 * be blocked and a permissions violation will soon follow.
1203 */
1204 ret = a6xx_zap_shader_init(gpu);
1205 if (!ret) {
1206 OUT_PKT7(gpu->rb[0], CP_SET_SECURE_MODE, 1);
1207 OUT_RING(gpu->rb[0], 0x00000000);
1208
1209 a6xx_flush(gpu, gpu->rb[0]);
1210 if (!a6xx_idle(gpu, gpu->rb[0]))
1211 return -EINVAL;
1212 } else if (ret == -ENODEV) {
1213 /*
1214 * This device does not use zap shader (but print a warning
1215 * just in case someone got their dt wrong.. hopefully they
1216 * have a debug UART to realize the error of their ways...
1217 * if you mess this up you are about to crash horribly)
1218 */
1219 dev_warn_once(gpu->dev->dev,
1220 "Zap shader not enabled - using SECVID_TRUST_CNTL instead\n");
1221 gpu_write(gpu, REG_A6XX_RBBM_SECVID_TRUST_CNTL, 0x0);
1222 ret = 0;
1223 } else {
1224 return ret;
1225 }
1226
1227 out:
1228 /*
1229 * Tell the GMU that we are done touching the GPU and it can start power
1230 * management
1231 */
1232 a6xx_gmu_clear_oob(&a6xx_gpu->gmu, GMU_OOB_GPU_SET);
1233
1234 if (a6xx_gpu->gmu.legacy) {
1235 /* Take the GMU out of its special boot mode */
1236 a6xx_gmu_clear_oob(&a6xx_gpu->gmu, GMU_OOB_BOOT_SLUMBER);
1237 }
1238
1239 return ret;
1240 }
1241
a6xx_hw_init(struct msm_gpu * gpu)1242 static int a6xx_hw_init(struct msm_gpu *gpu)
1243 {
1244 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
1245 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
1246 int ret;
1247
1248 mutex_lock(&a6xx_gpu->gmu.lock);
1249 ret = hw_init(gpu);
1250 mutex_unlock(&a6xx_gpu->gmu.lock);
1251
1252 return ret;
1253 }
1254
a6xx_dump(struct msm_gpu * gpu)1255 static void a6xx_dump(struct msm_gpu *gpu)
1256 {
1257 DRM_DEV_INFO(&gpu->pdev->dev, "status: %08x\n",
1258 gpu_read(gpu, REG_A6XX_RBBM_STATUS));
1259 adreno_dump(gpu);
1260 }
1261
1262 #define VBIF_RESET_ACK_TIMEOUT 100
1263 #define VBIF_RESET_ACK_MASK 0x00f0
1264
a6xx_recover(struct msm_gpu * gpu)1265 static void a6xx_recover(struct msm_gpu *gpu)
1266 {
1267 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
1268 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
1269 int i, active_submits;
1270
1271 adreno_dump_info(gpu);
1272
1273 for (i = 0; i < 8; i++)
1274 DRM_DEV_INFO(&gpu->pdev->dev, "CP_SCRATCH_REG%d: %u\n", i,
1275 gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(i)));
1276
1277 if (hang_debug)
1278 a6xx_dump(gpu);
1279
1280 /*
1281 * To handle recovery specific sequences during the rpm suspend we are
1282 * about to trigger
1283 */
1284 a6xx_gpu->hung = true;
1285
1286 /* Halt SQE first */
1287 gpu_write(gpu, REG_A6XX_CP_SQE_CNTL, 3);
1288
1289 /*
1290 * Turn off keep alive that might have been enabled by the hang
1291 * interrupt
1292 */
1293 gmu_write(&a6xx_gpu->gmu, REG_A6XX_GMU_GMU_PWR_COL_KEEPALIVE, 0);
1294
1295 pm_runtime_dont_use_autosuspend(&gpu->pdev->dev);
1296
1297 /* active_submit won't change until we make a submission */
1298 mutex_lock(&gpu->active_lock);
1299 active_submits = gpu->active_submits;
1300
1301 /*
1302 * Temporarily clear active_submits count to silence a WARN() in the
1303 * runtime suspend cb
1304 */
1305 gpu->active_submits = 0;
1306
1307 /* Drop the rpm refcount from active submits */
1308 if (active_submits)
1309 pm_runtime_put(&gpu->pdev->dev);
1310
1311 /* And the final one from recover worker */
1312 pm_runtime_put_sync(&gpu->pdev->dev);
1313
1314 /* Call into gpucc driver to poll for cx gdsc collapse */
1315 reset_control_reset(gpu->cx_collapse);
1316
1317 pm_runtime_use_autosuspend(&gpu->pdev->dev);
1318
1319 if (active_submits)
1320 pm_runtime_get(&gpu->pdev->dev);
1321
1322 pm_runtime_get_sync(&gpu->pdev->dev);
1323
1324 gpu->active_submits = active_submits;
1325 mutex_unlock(&gpu->active_lock);
1326
1327 msm_gpu_hw_init(gpu);
1328 a6xx_gpu->hung = false;
1329 }
1330
a6xx_uche_fault_block(struct msm_gpu * gpu,u32 mid)1331 static const char *a6xx_uche_fault_block(struct msm_gpu *gpu, u32 mid)
1332 {
1333 static const char *uche_clients[7] = {
1334 "VFD", "SP", "VSC", "VPC", "HLSQ", "PC", "LRZ",
1335 };
1336 u32 val;
1337
1338 if (mid < 1 || mid > 3)
1339 return "UNKNOWN";
1340
1341 /*
1342 * The source of the data depends on the mid ID read from FSYNR1.
1343 * and the client ID read from the UCHE block
1344 */
1345 val = gpu_read(gpu, REG_A6XX_UCHE_CLIENT_PF);
1346
1347 /* mid = 3 is most precise and refers to only one block per client */
1348 if (mid == 3)
1349 return uche_clients[val & 7];
1350
1351 /* For mid=2 the source is TP or VFD except when the client id is 0 */
1352 if (mid == 2)
1353 return ((val & 7) == 0) ? "TP" : "TP|VFD";
1354
1355 /* For mid=1 just return "UCHE" as a catchall for everything else */
1356 return "UCHE";
1357 }
1358
a6xx_fault_block(struct msm_gpu * gpu,u32 id)1359 static const char *a6xx_fault_block(struct msm_gpu *gpu, u32 id)
1360 {
1361 if (id == 0)
1362 return "CP";
1363 else if (id == 4)
1364 return "CCU";
1365 else if (id == 6)
1366 return "CDP Prefetch";
1367
1368 return a6xx_uche_fault_block(gpu, id);
1369 }
1370
1371 #define ARM_SMMU_FSR_TF BIT(1)
1372 #define ARM_SMMU_FSR_PF BIT(3)
1373 #define ARM_SMMU_FSR_EF BIT(4)
1374
a6xx_fault_handler(void * arg,unsigned long iova,int flags,void * data)1375 static int a6xx_fault_handler(void *arg, unsigned long iova, int flags, void *data)
1376 {
1377 struct msm_gpu *gpu = arg;
1378 struct adreno_smmu_fault_info *info = data;
1379 const char *type = "UNKNOWN";
1380 const char *block;
1381 bool do_devcoredump = info && !READ_ONCE(gpu->crashstate);
1382
1383 /*
1384 * If we aren't going to be resuming later from fault_worker, then do
1385 * it now.
1386 */
1387 if (!do_devcoredump) {
1388 gpu->aspace->mmu->funcs->resume_translation(gpu->aspace->mmu);
1389 }
1390
1391 /*
1392 * Print a default message if we couldn't get the data from the
1393 * adreno-smmu-priv
1394 */
1395 if (!info) {
1396 pr_warn_ratelimited("*** gpu fault: iova=%.16lx flags=%d (%u,%u,%u,%u)\n",
1397 iova, flags,
1398 gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(4)),
1399 gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(5)),
1400 gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(6)),
1401 gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(7)));
1402
1403 return 0;
1404 }
1405
1406 if (info->fsr & ARM_SMMU_FSR_TF)
1407 type = "TRANSLATION";
1408 else if (info->fsr & ARM_SMMU_FSR_PF)
1409 type = "PERMISSION";
1410 else if (info->fsr & ARM_SMMU_FSR_EF)
1411 type = "EXTERNAL";
1412
1413 block = a6xx_fault_block(gpu, info->fsynr1 & 0xff);
1414
1415 pr_warn_ratelimited("*** gpu fault: ttbr0=%.16llx iova=%.16lx dir=%s type=%s source=%s (%u,%u,%u,%u)\n",
1416 info->ttbr0, iova,
1417 flags & IOMMU_FAULT_WRITE ? "WRITE" : "READ",
1418 type, block,
1419 gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(4)),
1420 gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(5)),
1421 gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(6)),
1422 gpu_read(gpu, REG_A6XX_CP_SCRATCH_REG(7)));
1423
1424 if (do_devcoredump) {
1425 /* Turn off the hangcheck timer to keep it from bothering us */
1426 del_timer(&gpu->hangcheck_timer);
1427
1428 gpu->fault_info.ttbr0 = info->ttbr0;
1429 gpu->fault_info.iova = iova;
1430 gpu->fault_info.flags = flags;
1431 gpu->fault_info.type = type;
1432 gpu->fault_info.block = block;
1433
1434 kthread_queue_work(gpu->worker, &gpu->fault_work);
1435 }
1436
1437 return 0;
1438 }
1439
a6xx_cp_hw_err_irq(struct msm_gpu * gpu)1440 static void a6xx_cp_hw_err_irq(struct msm_gpu *gpu)
1441 {
1442 u32 status = gpu_read(gpu, REG_A6XX_CP_INTERRUPT_STATUS);
1443
1444 if (status & A6XX_CP_INT_CP_OPCODE_ERROR) {
1445 u32 val;
1446
1447 gpu_write(gpu, REG_A6XX_CP_SQE_STAT_ADDR, 1);
1448 val = gpu_read(gpu, REG_A6XX_CP_SQE_STAT_DATA);
1449 dev_err_ratelimited(&gpu->pdev->dev,
1450 "CP | opcode error | possible opcode=0x%8.8X\n",
1451 val);
1452 }
1453
1454 if (status & A6XX_CP_INT_CP_UCODE_ERROR)
1455 dev_err_ratelimited(&gpu->pdev->dev,
1456 "CP ucode error interrupt\n");
1457
1458 if (status & A6XX_CP_INT_CP_HW_FAULT_ERROR)
1459 dev_err_ratelimited(&gpu->pdev->dev, "CP | HW fault | status=0x%8.8X\n",
1460 gpu_read(gpu, REG_A6XX_CP_HW_FAULT));
1461
1462 if (status & A6XX_CP_INT_CP_REGISTER_PROTECTION_ERROR) {
1463 u32 val = gpu_read(gpu, REG_A6XX_CP_PROTECT_STATUS);
1464
1465 dev_err_ratelimited(&gpu->pdev->dev,
1466 "CP | protected mode error | %s | addr=0x%8.8X | status=0x%8.8X\n",
1467 val & (1 << 20) ? "READ" : "WRITE",
1468 (val & 0x3ffff), val);
1469 }
1470
1471 if (status & A6XX_CP_INT_CP_AHB_ERROR)
1472 dev_err_ratelimited(&gpu->pdev->dev, "CP AHB error interrupt\n");
1473
1474 if (status & A6XX_CP_INT_CP_VSD_PARITY_ERROR)
1475 dev_err_ratelimited(&gpu->pdev->dev, "CP VSD decoder parity error\n");
1476
1477 if (status & A6XX_CP_INT_CP_ILLEGAL_INSTR_ERROR)
1478 dev_err_ratelimited(&gpu->pdev->dev, "CP illegal instruction error\n");
1479
1480 }
1481
a6xx_fault_detect_irq(struct msm_gpu * gpu)1482 static void a6xx_fault_detect_irq(struct msm_gpu *gpu)
1483 {
1484 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
1485 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
1486 struct msm_ringbuffer *ring = gpu->funcs->active_ring(gpu);
1487
1488 /*
1489 * If stalled on SMMU fault, we could trip the GPU's hang detection,
1490 * but the fault handler will trigger the devcore dump, and we want
1491 * to otherwise resume normally rather than killing the submit, so
1492 * just bail.
1493 */
1494 if (gpu_read(gpu, REG_A6XX_RBBM_STATUS3) & A6XX_RBBM_STATUS3_SMMU_STALLED_ON_FAULT)
1495 return;
1496
1497 /*
1498 * Force the GPU to stay on until after we finish
1499 * collecting information
1500 */
1501 gmu_write(&a6xx_gpu->gmu, REG_A6XX_GMU_GMU_PWR_COL_KEEPALIVE, 1);
1502
1503 DRM_DEV_ERROR(&gpu->pdev->dev,
1504 "gpu fault ring %d fence %x status %8.8X rb %4.4x/%4.4x ib1 %16.16llX/%4.4x ib2 %16.16llX/%4.4x\n",
1505 ring ? ring->id : -1, ring ? ring->fctx->last_fence : 0,
1506 gpu_read(gpu, REG_A6XX_RBBM_STATUS),
1507 gpu_read(gpu, REG_A6XX_CP_RB_RPTR),
1508 gpu_read(gpu, REG_A6XX_CP_RB_WPTR),
1509 gpu_read64(gpu, REG_A6XX_CP_IB1_BASE, REG_A6XX_CP_IB1_BASE_HI),
1510 gpu_read(gpu, REG_A6XX_CP_IB1_REM_SIZE),
1511 gpu_read64(gpu, REG_A6XX_CP_IB2_BASE, REG_A6XX_CP_IB2_BASE_HI),
1512 gpu_read(gpu, REG_A6XX_CP_IB2_REM_SIZE));
1513
1514 /* Turn off the hangcheck timer to keep it from bothering us */
1515 del_timer(&gpu->hangcheck_timer);
1516
1517 kthread_queue_work(gpu->worker, &gpu->recover_work);
1518 }
1519
a6xx_irq(struct msm_gpu * gpu)1520 static irqreturn_t a6xx_irq(struct msm_gpu *gpu)
1521 {
1522 struct msm_drm_private *priv = gpu->dev->dev_private;
1523 u32 status = gpu_read(gpu, REG_A6XX_RBBM_INT_0_STATUS);
1524
1525 gpu_write(gpu, REG_A6XX_RBBM_INT_CLEAR_CMD, status);
1526
1527 if (priv->disable_err_irq)
1528 status &= A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS;
1529
1530 if (status & A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT)
1531 a6xx_fault_detect_irq(gpu);
1532
1533 if (status & A6XX_RBBM_INT_0_MASK_CP_AHB_ERROR)
1534 dev_err_ratelimited(&gpu->pdev->dev, "CP | AHB bus error\n");
1535
1536 if (status & A6XX_RBBM_INT_0_MASK_CP_HW_ERROR)
1537 a6xx_cp_hw_err_irq(gpu);
1538
1539 if (status & A6XX_RBBM_INT_0_MASK_RBBM_ATB_ASYNCFIFO_OVERFLOW)
1540 dev_err_ratelimited(&gpu->pdev->dev, "RBBM | ATB ASYNC overflow\n");
1541
1542 if (status & A6XX_RBBM_INT_0_MASK_RBBM_ATB_BUS_OVERFLOW)
1543 dev_err_ratelimited(&gpu->pdev->dev, "RBBM | ATB bus overflow\n");
1544
1545 if (status & A6XX_RBBM_INT_0_MASK_UCHE_OOB_ACCESS)
1546 dev_err_ratelimited(&gpu->pdev->dev, "UCHE | Out of bounds access\n");
1547
1548 if (status & A6XX_RBBM_INT_0_MASK_CP_CACHE_FLUSH_TS)
1549 msm_gpu_retire(gpu);
1550
1551 return IRQ_HANDLED;
1552 }
1553
a6xx_llc_rmw(struct a6xx_gpu * a6xx_gpu,u32 reg,u32 mask,u32 or)1554 static void a6xx_llc_rmw(struct a6xx_gpu *a6xx_gpu, u32 reg, u32 mask, u32 or)
1555 {
1556 return msm_rmw(a6xx_gpu->llc_mmio + (reg << 2), mask, or);
1557 }
1558
a6xx_llc_write(struct a6xx_gpu * a6xx_gpu,u32 reg,u32 value)1559 static void a6xx_llc_write(struct a6xx_gpu *a6xx_gpu, u32 reg, u32 value)
1560 {
1561 msm_writel(value, a6xx_gpu->llc_mmio + (reg << 2));
1562 }
1563
a6xx_llc_deactivate(struct a6xx_gpu * a6xx_gpu)1564 static void a6xx_llc_deactivate(struct a6xx_gpu *a6xx_gpu)
1565 {
1566 llcc_slice_deactivate(a6xx_gpu->llc_slice);
1567 llcc_slice_deactivate(a6xx_gpu->htw_llc_slice);
1568 }
1569
a6xx_llc_activate(struct a6xx_gpu * a6xx_gpu)1570 static void a6xx_llc_activate(struct a6xx_gpu *a6xx_gpu)
1571 {
1572 struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
1573 struct msm_gpu *gpu = &adreno_gpu->base;
1574 u32 cntl1_regval = 0;
1575
1576 if (IS_ERR(a6xx_gpu->llc_mmio))
1577 return;
1578
1579 if (!llcc_slice_activate(a6xx_gpu->llc_slice)) {
1580 u32 gpu_scid = llcc_get_slice_id(a6xx_gpu->llc_slice);
1581
1582 gpu_scid &= 0x1f;
1583 cntl1_regval = (gpu_scid << 0) | (gpu_scid << 5) | (gpu_scid << 10) |
1584 (gpu_scid << 15) | (gpu_scid << 20);
1585
1586 /* On A660, the SCID programming for UCHE traffic is done in
1587 * A6XX_GBIF_SCACHE_CNTL0[14:10]
1588 */
1589 if (adreno_is_a660_family(adreno_gpu))
1590 gpu_rmw(gpu, REG_A6XX_GBIF_SCACHE_CNTL0, (0x1f << 10) |
1591 (1 << 8), (gpu_scid << 10) | (1 << 8));
1592 }
1593
1594 /*
1595 * For targets with a MMU500, activate the slice but don't program the
1596 * register. The XBL will take care of that.
1597 */
1598 if (!llcc_slice_activate(a6xx_gpu->htw_llc_slice)) {
1599 if (!a6xx_gpu->have_mmu500) {
1600 u32 gpuhtw_scid = llcc_get_slice_id(a6xx_gpu->htw_llc_slice);
1601
1602 gpuhtw_scid &= 0x1f;
1603 cntl1_regval |= FIELD_PREP(GENMASK(29, 25), gpuhtw_scid);
1604 }
1605 }
1606
1607 if (!cntl1_regval)
1608 return;
1609
1610 /*
1611 * Program the slice IDs for the various GPU blocks and GPU MMU
1612 * pagetables
1613 */
1614 if (!a6xx_gpu->have_mmu500) {
1615 a6xx_llc_write(a6xx_gpu,
1616 REG_A6XX_CX_MISC_SYSTEM_CACHE_CNTL_1, cntl1_regval);
1617
1618 /*
1619 * Program cacheability overrides to not allocate cache
1620 * lines on a write miss
1621 */
1622 a6xx_llc_rmw(a6xx_gpu,
1623 REG_A6XX_CX_MISC_SYSTEM_CACHE_CNTL_0, 0xF, 0x03);
1624 return;
1625 }
1626
1627 gpu_rmw(gpu, REG_A6XX_GBIF_SCACHE_CNTL1, GENMASK(24, 0), cntl1_regval);
1628 }
1629
a6xx_llc_slices_destroy(struct a6xx_gpu * a6xx_gpu)1630 static void a6xx_llc_slices_destroy(struct a6xx_gpu *a6xx_gpu)
1631 {
1632 llcc_slice_putd(a6xx_gpu->llc_slice);
1633 llcc_slice_putd(a6xx_gpu->htw_llc_slice);
1634 }
1635
a6xx_llc_slices_init(struct platform_device * pdev,struct a6xx_gpu * a6xx_gpu)1636 static void a6xx_llc_slices_init(struct platform_device *pdev,
1637 struct a6xx_gpu *a6xx_gpu)
1638 {
1639 struct device_node *phandle;
1640
1641 /*
1642 * There is a different programming path for targets with an mmu500
1643 * attached, so detect if that is the case
1644 */
1645 phandle = of_parse_phandle(pdev->dev.of_node, "iommus", 0);
1646 a6xx_gpu->have_mmu500 = (phandle &&
1647 of_device_is_compatible(phandle, "arm,mmu-500"));
1648 of_node_put(phandle);
1649
1650 if (a6xx_gpu->have_mmu500)
1651 a6xx_gpu->llc_mmio = NULL;
1652 else
1653 a6xx_gpu->llc_mmio = msm_ioremap(pdev, "cx_mem");
1654
1655 a6xx_gpu->llc_slice = llcc_slice_getd(LLCC_GPU);
1656 a6xx_gpu->htw_llc_slice = llcc_slice_getd(LLCC_GPUHTW);
1657
1658 if (IS_ERR_OR_NULL(a6xx_gpu->llc_slice) && IS_ERR_OR_NULL(a6xx_gpu->htw_llc_slice))
1659 a6xx_gpu->llc_mmio = ERR_PTR(-EINVAL);
1660 }
1661
a6xx_pm_resume(struct msm_gpu * gpu)1662 static int a6xx_pm_resume(struct msm_gpu *gpu)
1663 {
1664 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
1665 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
1666 int ret;
1667
1668 gpu->needs_hw_init = true;
1669
1670 trace_msm_gpu_resume(0);
1671
1672 mutex_lock(&a6xx_gpu->gmu.lock);
1673 ret = a6xx_gmu_resume(a6xx_gpu);
1674 mutex_unlock(&a6xx_gpu->gmu.lock);
1675 if (ret)
1676 return ret;
1677
1678 msm_devfreq_resume(gpu);
1679
1680 a6xx_llc_activate(a6xx_gpu);
1681
1682 return 0;
1683 }
1684
a6xx_pm_suspend(struct msm_gpu * gpu)1685 static int a6xx_pm_suspend(struct msm_gpu *gpu)
1686 {
1687 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
1688 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
1689 int i, ret;
1690
1691 trace_msm_gpu_suspend(0);
1692
1693 a6xx_llc_deactivate(a6xx_gpu);
1694
1695 msm_devfreq_suspend(gpu);
1696
1697 mutex_lock(&a6xx_gpu->gmu.lock);
1698 ret = a6xx_gmu_stop(a6xx_gpu);
1699 mutex_unlock(&a6xx_gpu->gmu.lock);
1700 if (ret)
1701 return ret;
1702
1703 if (a6xx_gpu->shadow_bo)
1704 for (i = 0; i < gpu->nr_rings; i++)
1705 a6xx_gpu->shadow[i] = 0;
1706
1707 gpu->suspend_count++;
1708
1709 return 0;
1710 }
1711
a6xx_get_timestamp(struct msm_gpu * gpu,uint64_t * value)1712 static int a6xx_get_timestamp(struct msm_gpu *gpu, uint64_t *value)
1713 {
1714 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
1715 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
1716
1717 mutex_lock(&a6xx_gpu->gmu.lock);
1718
1719 /* Force the GPU power on so we can read this register */
1720 a6xx_gmu_set_oob(&a6xx_gpu->gmu, GMU_OOB_PERFCOUNTER_SET);
1721
1722 *value = gpu_read64(gpu, REG_A6XX_CP_ALWAYS_ON_COUNTER_LO,
1723 REG_A6XX_CP_ALWAYS_ON_COUNTER_HI);
1724
1725 a6xx_gmu_clear_oob(&a6xx_gpu->gmu, GMU_OOB_PERFCOUNTER_SET);
1726
1727 mutex_unlock(&a6xx_gpu->gmu.lock);
1728
1729 return 0;
1730 }
1731
a6xx_active_ring(struct msm_gpu * gpu)1732 static struct msm_ringbuffer *a6xx_active_ring(struct msm_gpu *gpu)
1733 {
1734 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
1735 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
1736
1737 return a6xx_gpu->cur_ring;
1738 }
1739
a6xx_destroy(struct msm_gpu * gpu)1740 static void a6xx_destroy(struct msm_gpu *gpu)
1741 {
1742 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
1743 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
1744
1745 if (a6xx_gpu->sqe_bo) {
1746 msm_gem_unpin_iova(a6xx_gpu->sqe_bo, gpu->aspace);
1747 drm_gem_object_put(a6xx_gpu->sqe_bo);
1748 }
1749
1750 if (a6xx_gpu->shadow_bo) {
1751 msm_gem_unpin_iova(a6xx_gpu->shadow_bo, gpu->aspace);
1752 drm_gem_object_put(a6xx_gpu->shadow_bo);
1753 }
1754
1755 a6xx_llc_slices_destroy(a6xx_gpu);
1756
1757 a6xx_gmu_remove(a6xx_gpu);
1758
1759 adreno_gpu_cleanup(adreno_gpu);
1760
1761 kfree(a6xx_gpu);
1762 }
1763
a6xx_gpu_busy(struct msm_gpu * gpu,unsigned long * out_sample_rate)1764 static u64 a6xx_gpu_busy(struct msm_gpu *gpu, unsigned long *out_sample_rate)
1765 {
1766 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
1767 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
1768 u64 busy_cycles;
1769
1770 /* 19.2MHz */
1771 *out_sample_rate = 19200000;
1772
1773 busy_cycles = gmu_read64(&a6xx_gpu->gmu,
1774 REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_0_L,
1775 REG_A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_0_H);
1776
1777 return busy_cycles;
1778 }
1779
a6xx_gpu_set_freq(struct msm_gpu * gpu,struct dev_pm_opp * opp,bool suspended)1780 static void a6xx_gpu_set_freq(struct msm_gpu *gpu, struct dev_pm_opp *opp,
1781 bool suspended)
1782 {
1783 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
1784 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
1785
1786 mutex_lock(&a6xx_gpu->gmu.lock);
1787 a6xx_gmu_set_freq(gpu, opp, suspended);
1788 mutex_unlock(&a6xx_gpu->gmu.lock);
1789 }
1790
1791 static struct msm_gem_address_space *
a6xx_create_address_space(struct msm_gpu * gpu,struct platform_device * pdev)1792 a6xx_create_address_space(struct msm_gpu *gpu, struct platform_device *pdev)
1793 {
1794 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
1795 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
1796 struct iommu_domain *iommu;
1797 struct msm_mmu *mmu;
1798 struct msm_gem_address_space *aspace;
1799 u64 start, size;
1800
1801 iommu = iommu_domain_alloc(&platform_bus_type);
1802 if (!iommu)
1803 return NULL;
1804
1805 /*
1806 * This allows GPU to set the bus attributes required to use system
1807 * cache on behalf of the iommu page table walker.
1808 */
1809 if (!IS_ERR_OR_NULL(a6xx_gpu->htw_llc_slice))
1810 adreno_set_llc_attributes(iommu);
1811
1812 mmu = msm_iommu_new(&pdev->dev, iommu);
1813 if (IS_ERR(mmu)) {
1814 iommu_domain_free(iommu);
1815 return ERR_CAST(mmu);
1816 }
1817
1818 /*
1819 * Use the aperture start or SZ_16M, whichever is greater. This will
1820 * ensure that we align with the allocated pagetable range while still
1821 * allowing room in the lower 32 bits for GMEM and whatnot
1822 */
1823 start = max_t(u64, SZ_16M, iommu->geometry.aperture_start);
1824 size = iommu->geometry.aperture_end - start + 1;
1825
1826 aspace = msm_gem_address_space_create(mmu, "gpu",
1827 start & GENMASK_ULL(48, 0), size);
1828
1829 if (IS_ERR(aspace) && !IS_ERR(mmu))
1830 mmu->funcs->destroy(mmu);
1831
1832 return aspace;
1833 }
1834
1835 static struct msm_gem_address_space *
a6xx_create_private_address_space(struct msm_gpu * gpu)1836 a6xx_create_private_address_space(struct msm_gpu *gpu)
1837 {
1838 struct msm_mmu *mmu;
1839
1840 mmu = msm_iommu_pagetable_create(gpu->aspace->mmu);
1841
1842 if (IS_ERR(mmu))
1843 return ERR_CAST(mmu);
1844
1845 return msm_gem_address_space_create(mmu,
1846 "gpu", 0x100000000ULL,
1847 adreno_private_address_space_size(gpu));
1848 }
1849
a6xx_get_rptr(struct msm_gpu * gpu,struct msm_ringbuffer * ring)1850 static uint32_t a6xx_get_rptr(struct msm_gpu *gpu, struct msm_ringbuffer *ring)
1851 {
1852 struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
1853 struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
1854
1855 if (adreno_gpu->base.hw_apriv || a6xx_gpu->has_whereami)
1856 return a6xx_gpu->shadow[ring->id];
1857
1858 return ring->memptrs->rptr = gpu_read(gpu, REG_A6XX_CP_RB_RPTR);
1859 }
1860
a618_get_speed_bin(u32 fuse)1861 static u32 a618_get_speed_bin(u32 fuse)
1862 {
1863 if (fuse == 0)
1864 return 0;
1865 else if (fuse == 169)
1866 return 1;
1867 else if (fuse == 174)
1868 return 2;
1869
1870 return UINT_MAX;
1871 }
1872
a619_get_speed_bin(u32 fuse)1873 static u32 a619_get_speed_bin(u32 fuse)
1874 {
1875 if (fuse == 0)
1876 return 0;
1877 else if (fuse == 120)
1878 return 4;
1879 else if (fuse == 138)
1880 return 3;
1881 else if (fuse == 169)
1882 return 2;
1883 else if (fuse == 180)
1884 return 1;
1885
1886 return UINT_MAX;
1887 }
1888
adreno_7c3_get_speed_bin(u32 fuse)1889 static u32 adreno_7c3_get_speed_bin(u32 fuse)
1890 {
1891 if (fuse == 0)
1892 return 0;
1893 else if (fuse == 117)
1894 return 0;
1895 else if (fuse == 190)
1896 return 1;
1897
1898 return UINT_MAX;
1899 }
1900
fuse_to_supp_hw(struct device * dev,struct adreno_rev rev,u32 fuse)1901 static u32 fuse_to_supp_hw(struct device *dev, struct adreno_rev rev, u32 fuse)
1902 {
1903 u32 val = UINT_MAX;
1904
1905 if (adreno_cmp_rev(ADRENO_REV(6, 1, 8, ANY_ID), rev))
1906 val = a618_get_speed_bin(fuse);
1907
1908 if (adreno_cmp_rev(ADRENO_REV(6, 1, 9, ANY_ID), rev))
1909 val = a619_get_speed_bin(fuse);
1910
1911 if (adreno_cmp_rev(ADRENO_REV(6, 3, 5, ANY_ID), rev))
1912 val = adreno_7c3_get_speed_bin(fuse);
1913
1914 if (val == UINT_MAX) {
1915 DRM_DEV_ERROR(dev,
1916 "missing support for speed-bin: %u. Some OPPs may not be supported by hardware\n",
1917 fuse);
1918 return UINT_MAX;
1919 }
1920
1921 return (1 << val);
1922 }
1923
a6xx_set_supported_hw(struct device * dev,struct adreno_rev rev)1924 static int a6xx_set_supported_hw(struct device *dev, struct adreno_rev rev)
1925 {
1926 u32 supp_hw;
1927 u32 speedbin;
1928 int ret;
1929
1930 ret = adreno_read_speedbin(dev, &speedbin);
1931 /*
1932 * -ENOENT means that the platform doesn't support speedbin which is
1933 * fine
1934 */
1935 if (ret == -ENOENT) {
1936 return 0;
1937 } else if (ret) {
1938 dev_err_probe(dev, ret,
1939 "failed to read speed-bin. Some OPPs may not be supported by hardware\n");
1940 return ret;
1941 }
1942
1943 supp_hw = fuse_to_supp_hw(dev, rev, speedbin);
1944
1945 ret = devm_pm_opp_set_supported_hw(dev, &supp_hw, 1);
1946 if (ret)
1947 return ret;
1948
1949 return 0;
1950 }
1951
1952 static const struct adreno_gpu_funcs funcs = {
1953 .base = {
1954 .get_param = adreno_get_param,
1955 .set_param = adreno_set_param,
1956 .hw_init = a6xx_hw_init,
1957 .pm_suspend = a6xx_pm_suspend,
1958 .pm_resume = a6xx_pm_resume,
1959 .recover = a6xx_recover,
1960 .submit = a6xx_submit,
1961 .active_ring = a6xx_active_ring,
1962 .irq = a6xx_irq,
1963 .destroy = a6xx_destroy,
1964 #if defined(CONFIG_DRM_MSM_GPU_STATE)
1965 .show = a6xx_show,
1966 #endif
1967 .gpu_busy = a6xx_gpu_busy,
1968 .gpu_get_freq = a6xx_gmu_get_freq,
1969 .gpu_set_freq = a6xx_gpu_set_freq,
1970 #if defined(CONFIG_DRM_MSM_GPU_STATE)
1971 .gpu_state_get = a6xx_gpu_state_get,
1972 .gpu_state_put = a6xx_gpu_state_put,
1973 #endif
1974 .create_address_space = a6xx_create_address_space,
1975 .create_private_address_space = a6xx_create_private_address_space,
1976 .get_rptr = a6xx_get_rptr,
1977 },
1978 .get_timestamp = a6xx_get_timestamp,
1979 };
1980
a6xx_gpu_init(struct drm_device * dev)1981 struct msm_gpu *a6xx_gpu_init(struct drm_device *dev)
1982 {
1983 struct msm_drm_private *priv = dev->dev_private;
1984 struct platform_device *pdev = priv->gpu_pdev;
1985 struct adreno_platform_config *config = pdev->dev.platform_data;
1986 const struct adreno_info *info;
1987 struct device_node *node;
1988 struct a6xx_gpu *a6xx_gpu;
1989 struct adreno_gpu *adreno_gpu;
1990 struct msm_gpu *gpu;
1991 int ret;
1992
1993 a6xx_gpu = kzalloc(sizeof(*a6xx_gpu), GFP_KERNEL);
1994 if (!a6xx_gpu)
1995 return ERR_PTR(-ENOMEM);
1996
1997 adreno_gpu = &a6xx_gpu->base;
1998 gpu = &adreno_gpu->base;
1999
2000 adreno_gpu->registers = NULL;
2001
2002 /*
2003 * We need to know the platform type before calling into adreno_gpu_init
2004 * so that the hw_apriv flag can be correctly set. Snoop into the info
2005 * and grab the revision number
2006 */
2007 info = adreno_info(config->rev);
2008
2009 if (info && (info->revn == 650 || info->revn == 660 ||
2010 adreno_cmp_rev(ADRENO_REV(6, 3, 5, ANY_ID), info->rev)))
2011 adreno_gpu->base.hw_apriv = true;
2012
2013 /*
2014 * For now only clamp to idle freq for devices where this is known not
2015 * to cause power supply issues:
2016 */
2017 if (info && (info->revn == 618))
2018 gpu->clamp_to_idle = true;
2019
2020 a6xx_llc_slices_init(pdev, a6xx_gpu);
2021
2022 ret = a6xx_set_supported_hw(&pdev->dev, config->rev);
2023 if (ret) {
2024 a6xx_destroy(&(a6xx_gpu->base.base));
2025 return ERR_PTR(ret);
2026 }
2027
2028 ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs, 1);
2029 if (ret) {
2030 a6xx_destroy(&(a6xx_gpu->base.base));
2031 return ERR_PTR(ret);
2032 }
2033
2034 /* Check if there is a GMU phandle and set it up */
2035 node = of_parse_phandle(pdev->dev.of_node, "qcom,gmu", 0);
2036
2037 /* FIXME: How do we gracefully handle this? */
2038 BUG_ON(!node);
2039
2040 ret = a6xx_gmu_init(a6xx_gpu, node);
2041 of_node_put(node);
2042 if (ret) {
2043 a6xx_destroy(&(a6xx_gpu->base.base));
2044 return ERR_PTR(ret);
2045 }
2046
2047 if (gpu->aspace)
2048 msm_mmu_set_fault_handler(gpu->aspace->mmu, gpu,
2049 a6xx_fault_handler);
2050
2051 return gpu;
2052 }
2053