1 /*
2  * Copyright 2012 Red Hat Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the
6  * "Software"), to deal in the Software without restriction, including
7  * without limitation the rights to use, copy, modify, merge, publish,
8  * distribute, sub license, and/or sell copies of the Software, and to
9  * permit persons to whom the Software is furnished to do so, subject to
10  * the following conditions:
11  *
12  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
13  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
14  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
15  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
16  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
17  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
18  * USE OR OTHER DEALINGS IN THE SOFTWARE.
19  *
20  * The above copyright notice and this permission notice (including the
21  * next paragraph) shall be included in all copies or substantial portions
22  * of the Software.
23  *
24  */
25 /*
26  * Authors: Dave Airlie <airlied@redhat.com>
27  */
28 #ifndef __AST_DRV_H__
29 #define __AST_DRV_H__
30 
31 #include <linux/i2c.h>
32 #include <linux/i2c-algo-bit.h>
33 #include <linux/io.h>
34 #include <linux/types.h>
35 
36 #include <drm/drm_connector.h>
37 #include <drm/drm_crtc.h>
38 #include <drm/drm_encoder.h>
39 #include <drm/drm_mode.h>
40 #include <drm/drm_framebuffer.h>
41 #include <drm/drm_fb_helper.h>
42 
43 #define DRIVER_AUTHOR		"Dave Airlie"
44 
45 #define DRIVER_NAME		"ast"
46 #define DRIVER_DESC		"AST"
47 #define DRIVER_DATE		"20120228"
48 
49 #define DRIVER_MAJOR		0
50 #define DRIVER_MINOR		1
51 #define DRIVER_PATCHLEVEL	0
52 
53 #define PCI_CHIP_AST2000 0x2000
54 #define PCI_CHIP_AST2100 0x2010
55 
56 
57 enum ast_chip {
58 	AST2000,
59 	AST2100,
60 	AST1100,
61 	AST2200,
62 	AST2150,
63 	AST2300,
64 	AST2400,
65 	AST2500,
66 	AST2600,
67 };
68 
69 enum ast_tx_chip {
70 	AST_TX_NONE,
71 	AST_TX_SIL164,
72 	AST_TX_DP501,
73 	AST_TX_ASTDP,
74 };
75 
76 #define AST_TX_NONE_BIT		BIT(AST_TX_NONE)
77 #define AST_TX_SIL164_BIT	BIT(AST_TX_SIL164)
78 #define AST_TX_DP501_BIT	BIT(AST_TX_DP501)
79 #define AST_TX_ASTDP_BIT	BIT(AST_TX_ASTDP)
80 
81 #define AST_DRAM_512Mx16 0
82 #define AST_DRAM_1Gx16   1
83 #define AST_DRAM_512Mx32 2
84 #define AST_DRAM_1Gx32   3
85 #define AST_DRAM_2Gx16   6
86 #define AST_DRAM_4Gx16   7
87 #define AST_DRAM_8Gx16   8
88 
89 /*
90  * Cursor plane
91  */
92 
93 #define AST_MAX_HWC_WIDTH	64
94 #define AST_MAX_HWC_HEIGHT	64
95 
96 #define AST_HWC_SIZE		(AST_MAX_HWC_WIDTH * AST_MAX_HWC_HEIGHT * 2)
97 #define AST_HWC_SIGNATURE_SIZE	32
98 
99 #define AST_DEFAULT_HWC_NUM	2
100 
101 /* define for signature structure */
102 #define AST_HWC_SIGNATURE_CHECKSUM	0x00
103 #define AST_HWC_SIGNATURE_SizeX		0x04
104 #define AST_HWC_SIGNATURE_SizeY		0x08
105 #define AST_HWC_SIGNATURE_X		0x0C
106 #define AST_HWC_SIGNATURE_Y		0x10
107 #define AST_HWC_SIGNATURE_HOTSPOTX	0x14
108 #define AST_HWC_SIGNATURE_HOTSPOTY	0x18
109 
110 struct ast_cursor_plane {
111 	struct drm_plane base;
112 
113 	struct {
114 		struct drm_gem_vram_object *gbo;
115 		struct iosys_map map;
116 		u64 off;
117 	} hwc[AST_DEFAULT_HWC_NUM];
118 
119 	unsigned int next_hwc_index;
120 };
121 
122 static inline struct ast_cursor_plane *
to_ast_cursor_plane(struct drm_plane * plane)123 to_ast_cursor_plane(struct drm_plane *plane)
124 {
125 	return container_of(plane, struct ast_cursor_plane, base);
126 }
127 
128 /*
129  * Connector with i2c channel
130  */
131 
132 struct ast_i2c_chan {
133 	struct i2c_adapter adapter;
134 	struct drm_device *dev;
135 	struct i2c_algo_bit_data bit;
136 };
137 
138 struct ast_vga_connector {
139 	struct drm_connector base;
140 	struct ast_i2c_chan *i2c;
141 };
142 
143 static inline struct ast_vga_connector *
to_ast_vga_connector(struct drm_connector * connector)144 to_ast_vga_connector(struct drm_connector *connector)
145 {
146 	return container_of(connector, struct ast_vga_connector, base);
147 }
148 
149 struct ast_sil164_connector {
150 	struct drm_connector base;
151 	struct ast_i2c_chan *i2c;
152 };
153 
154 static inline struct ast_sil164_connector *
to_ast_sil164_connector(struct drm_connector * connector)155 to_ast_sil164_connector(struct drm_connector *connector)
156 {
157 	return container_of(connector, struct ast_sil164_connector, base);
158 }
159 
160 /*
161  * Device
162  */
163 
164 struct ast_private {
165 	struct drm_device base;
166 
167 	struct mutex ioregs_lock; /* Protects access to I/O registers in ioregs */
168 	void __iomem *regs;
169 	void __iomem *ioregs;
170 	void __iomem *dp501_fw_buf;
171 
172 	enum ast_chip chip;
173 	bool vga2_clone;
174 	uint32_t dram_bus_width;
175 	uint32_t dram_type;
176 	uint32_t mclk;
177 
178 	struct drm_plane primary_plane;
179 	struct ast_cursor_plane cursor_plane;
180 	struct drm_crtc crtc;
181 	struct {
182 		struct {
183 			struct drm_encoder encoder;
184 			struct ast_vga_connector vga_connector;
185 		} vga;
186 		struct {
187 			struct drm_encoder encoder;
188 			struct ast_sil164_connector sil164_connector;
189 		} sil164;
190 		struct {
191 			struct drm_encoder encoder;
192 			struct drm_connector connector;
193 		} dp501;
194 		struct {
195 			struct drm_encoder encoder;
196 			struct drm_connector connector;
197 		} astdp;
198 	} output;
199 
200 	bool support_wide_screen;
201 	enum {
202 		ast_use_p2a,
203 		ast_use_dt,
204 		ast_use_defaults
205 	} config_mode;
206 
207 	unsigned long tx_chip_types;		/* bitfield of enum ast_chip_type */
208 	u8 *dp501_fw_addr;
209 	const struct firmware *dp501_fw;	/* dp501 fw */
210 };
211 
to_ast_private(struct drm_device * dev)212 static inline struct ast_private *to_ast_private(struct drm_device *dev)
213 {
214 	return container_of(dev, struct ast_private, base);
215 }
216 
217 struct ast_private *ast_device_create(const struct drm_driver *drv,
218 				      struct pci_dev *pdev,
219 				      unsigned long flags);
220 
221 #define AST_IO_AR_PORT_WRITE		(0x40)
222 #define AST_IO_MISC_PORT_WRITE		(0x42)
223 #define AST_IO_VGA_ENABLE_PORT		(0x43)
224 #define AST_IO_SEQ_PORT			(0x44)
225 #define AST_IO_DAC_INDEX_READ		(0x47)
226 #define AST_IO_DAC_INDEX_WRITE		(0x48)
227 #define AST_IO_DAC_DATA		        (0x49)
228 #define AST_IO_GR_PORT			(0x4E)
229 #define AST_IO_CRTC_PORT		(0x54)
230 #define AST_IO_INPUT_STATUS1_READ	(0x5A)
231 #define AST_IO_MISC_PORT_READ		(0x4C)
232 
233 #define AST_IO_MM_OFFSET		(0x380)
234 
235 #define AST_IO_VGAIR1_VREFRESH		BIT(3)
236 
237 #define AST_IO_VGACRCB_HWC_ENABLED     BIT(1)
238 #define AST_IO_VGACRCB_HWC_16BPP       BIT(0) /* set: ARGB4444, cleared: 2bpp palette */
239 
240 #define __ast_read(x) \
241 static inline u##x ast_read##x(struct ast_private *ast, u32 reg) { \
242 u##x val = 0;\
243 val = ioread##x(ast->regs + reg); \
244 return val;\
245 }
246 
247 __ast_read(8);
248 __ast_read(16);
249 __ast_read(32)
250 
251 #define __ast_io_read(x) \
252 static inline u##x ast_io_read##x(struct ast_private *ast, u32 reg) { \
253 u##x val = 0;\
254 val = ioread##x(ast->ioregs + reg); \
255 return val;\
256 }
257 
258 __ast_io_read(8);
259 __ast_io_read(16);
260 __ast_io_read(32);
261 
262 #define __ast_write(x) \
263 static inline void ast_write##x(struct ast_private *ast, u32 reg, u##x val) {\
264 	iowrite##x(val, ast->regs + reg);\
265 	}
266 
267 __ast_write(8);
268 __ast_write(16);
269 __ast_write(32);
270 
271 #define __ast_io_write(x) \
272 static inline void ast_io_write##x(struct ast_private *ast, u32 reg, u##x val) {\
273 	iowrite##x(val, ast->ioregs + reg);\
274 	}
275 
276 __ast_io_write(8);
277 __ast_io_write(16);
278 #undef __ast_io_write
279 
ast_set_index_reg(struct ast_private * ast,uint32_t base,uint8_t index,uint8_t val)280 static inline void ast_set_index_reg(struct ast_private *ast,
281 				     uint32_t base, uint8_t index,
282 				     uint8_t val)
283 {
284 	ast_io_write16(ast, base, ((u16)val << 8) | index);
285 }
286 
287 void ast_set_index_reg_mask(struct ast_private *ast,
288 			    uint32_t base, uint8_t index,
289 			    uint8_t mask, uint8_t val);
290 uint8_t ast_get_index_reg(struct ast_private *ast,
291 			  uint32_t base, uint8_t index);
292 uint8_t ast_get_index_reg_mask(struct ast_private *ast,
293 			       uint32_t base, uint8_t index, uint8_t mask);
294 
ast_open_key(struct ast_private * ast)295 static inline void ast_open_key(struct ast_private *ast)
296 {
297 	ast_set_index_reg(ast, AST_IO_CRTC_PORT, 0x80, 0xA8);
298 }
299 
300 #define AST_VIDMEM_SIZE_8M    0x00800000
301 #define AST_VIDMEM_SIZE_16M   0x01000000
302 #define AST_VIDMEM_SIZE_32M   0x02000000
303 #define AST_VIDMEM_SIZE_64M   0x04000000
304 #define AST_VIDMEM_SIZE_128M  0x08000000
305 
306 #define AST_VIDMEM_DEFAULT_SIZE AST_VIDMEM_SIZE_8M
307 
308 struct ast_vbios_stdtable {
309 	u8 misc;
310 	u8 seq[4];
311 	u8 crtc[25];
312 	u8 ar[20];
313 	u8 gr[9];
314 };
315 
316 struct ast_vbios_enhtable {
317 	u32 ht;
318 	u32 hde;
319 	u32 hfp;
320 	u32 hsync;
321 	u32 vt;
322 	u32 vde;
323 	u32 vfp;
324 	u32 vsync;
325 	u32 dclk_index;
326 	u32 flags;
327 	u32 refresh_rate;
328 	u32 refresh_rate_index;
329 	u32 mode_id;
330 };
331 
332 struct ast_vbios_dclk_info {
333 	u8 param1;
334 	u8 param2;
335 	u8 param3;
336 };
337 
338 struct ast_vbios_mode_info {
339 	const struct ast_vbios_stdtable *std_table;
340 	const struct ast_vbios_enhtable *enh_table;
341 };
342 
343 struct ast_crtc_state {
344 	struct drm_crtc_state base;
345 
346 	/* Last known format of primary plane */
347 	const struct drm_format_info *format;
348 
349 	struct ast_vbios_mode_info vbios_mode_info;
350 };
351 
352 #define to_ast_crtc_state(state) container_of(state, struct ast_crtc_state, base)
353 
354 int ast_mode_config_init(struct ast_private *ast);
355 
356 #define AST_MM_ALIGN_SHIFT 4
357 #define AST_MM_ALIGN_MASK ((1 << AST_MM_ALIGN_SHIFT) - 1)
358 
359 #define AST_DP501_FW_VERSION_MASK	GENMASK(7, 4)
360 #define AST_DP501_FW_VERSION_1		BIT(4)
361 #define AST_DP501_PNP_CONNECTED		BIT(1)
362 
363 #define AST_DP501_DEFAULT_DCLK	65
364 
365 #define AST_DP501_GBL_VERSION	0xf000
366 #define AST_DP501_PNPMONITOR	0xf010
367 #define AST_DP501_LINKRATE	0xf014
368 #define AST_DP501_EDID_DATA	0xf020
369 
370 /* Define for Soc scratched reg */
371 #define COPROCESSOR_LAUNCH			BIT(5)
372 
373 /*
374  * Display Transmitter Type:
375  */
376 #define TX_TYPE_MASK				GENMASK(3, 1)
377 #define NO_TX						(0 << 1)
378 #define ITE66121_VBIOS_TX			(1 << 1)
379 #define SI164_VBIOS_TX				(2 << 1)
380 #define CH7003_VBIOS_TX			(3 << 1)
381 #define DP501_VBIOS_TX				(4 << 1)
382 #define ANX9807_VBIOS_TX			(5 << 1)
383 #define TX_FW_EMBEDDED_FW_TX		(6 << 1)
384 #define ASTDP_DPMCU_TX				(7 << 1)
385 
386 #define AST_VRAM_INIT_STATUS_MASK	GENMASK(7, 6)
387 //#define AST_VRAM_INIT_BY_BMC		BIT(7)
388 //#define AST_VRAM_INIT_READY		BIT(6)
389 
390 /* Define for Soc scratched reg used on ASTDP */
391 #define AST_DP_PHY_SLEEP			BIT(4)
392 #define AST_DP_VIDEO_ENABLE		BIT(0)
393 
394 #define AST_DP_POWER_ON			true
395 #define AST_DP_POWER_OFF			false
396 
397 /*
398  * CRD1[b5]: DP MCU FW is executing
399  * CRDC[b0]: DP link success
400  * CRDF[b0]: DP HPD
401  * CRE5[b0]: Host reading EDID process is done
402  */
403 #define ASTDP_MCU_FW_EXECUTING			BIT(5)
404 #define ASTDP_LINK_SUCCESS				BIT(0)
405 #define ASTDP_HPD						BIT(0)
406 #define ASTDP_HOST_EDID_READ_DONE		BIT(0)
407 #define ASTDP_HOST_EDID_READ_DONE_MASK	GENMASK(0, 0)
408 
409 /*
410  * CRB8[b1]: Enable VSYNC off
411  * CRB8[b0]: Enable HSYNC off
412  */
413 #define AST_DPMS_VSYNC_OFF				BIT(1)
414 #define AST_DPMS_HSYNC_OFF				BIT(0)
415 
416 /*
417  * CRDF[b4]: Mirror of AST_DP_VIDEO_ENABLE
418  * Precondition:	A. ~AST_DP_PHY_SLEEP  &&
419  *			B. DP_HPD &&
420  *			C. DP_LINK_SUCCESS
421  */
422 #define ASTDP_MIRROR_VIDEO_ENABLE		BIT(4)
423 
424 #define ASTDP_EDID_READ_POINTER_MASK	GENMASK(7, 0)
425 #define ASTDP_EDID_VALID_FLAG_MASK		GENMASK(0, 0)
426 #define ASTDP_EDID_READ_DATA_MASK		GENMASK(7, 0)
427 
428 /*
429  * ASTDP setmode registers:
430  * CRE0[7:0]: MISC0 ((0x00: 18-bpp) or (0x20: 24-bpp)
431  * CRE1[7:0]: MISC1 (default: 0x00)
432  * CRE2[7:0]: video format index (0x00 ~ 0x20 or 0x40 ~ 0x50)
433  */
434 #define ASTDP_MISC0_24bpp			BIT(5)
435 #define ASTDP_MISC1				0
436 #define ASTDP_AND_CLEAR_MASK		0x00
437 
438 /*
439  * ASTDP resoultion table:
440  * EX:	ASTDP_A_B_C:
441  *		A: Resolution
442  *		B: Refresh Rate
443  *		C: Misc information, such as CVT, Reduce Blanked
444  */
445 #define ASTDP_640x480_60		0x00
446 #define ASTDP_640x480_72		0x01
447 #define ASTDP_640x480_75		0x02
448 #define ASTDP_640x480_85		0x03
449 #define ASTDP_800x600_56		0x04
450 #define ASTDP_800x600_60		0x05
451 #define ASTDP_800x600_72		0x06
452 #define ASTDP_800x600_75		0x07
453 #define ASTDP_800x600_85		0x08
454 #define ASTDP_1024x768_60		0x09
455 #define ASTDP_1024x768_70		0x0A
456 #define ASTDP_1024x768_75		0x0B
457 #define ASTDP_1024x768_85		0x0C
458 #define ASTDP_1280x1024_60		0x0D
459 #define ASTDP_1280x1024_75		0x0E
460 #define ASTDP_1280x1024_85		0x0F
461 #define ASTDP_1600x1200_60		0x10
462 #define ASTDP_320x240_60		0x11
463 #define ASTDP_400x300_60		0x12
464 #define ASTDP_512x384_60		0x13
465 #define ASTDP_1920x1200_60		0x14
466 #define ASTDP_1920x1080_60		0x15
467 #define ASTDP_1280x800_60		0x16
468 #define ASTDP_1280x800_60_RB	0x17
469 #define ASTDP_1440x900_60		0x18
470 #define ASTDP_1440x900_60_RB	0x19
471 #define ASTDP_1680x1050_60		0x1A
472 #define ASTDP_1680x1050_60_RB	0x1B
473 #define ASTDP_1600x900_60		0x1C
474 #define ASTDP_1600x900_60_RB	0x1D
475 #define ASTDP_1366x768_60		0x1E
476 #define ASTDP_1152x864_75		0x1F
477 
478 int ast_mm_init(struct ast_private *ast);
479 
480 /* ast post */
481 void ast_enable_vga(struct drm_device *dev);
482 void ast_enable_mmio(struct drm_device *dev);
483 bool ast_is_vga_enabled(struct drm_device *dev);
484 void ast_post_gpu(struct drm_device *dev);
485 u32 ast_mindwm(struct ast_private *ast, u32 r);
486 void ast_moutdwm(struct ast_private *ast, u32 r, u32 v);
487 void ast_patch_ahb_2500(struct ast_private *ast);
488 /* ast dp501 */
489 void ast_set_dp501_video_output(struct drm_device *dev, u8 mode);
490 bool ast_backup_fw(struct drm_device *dev, u8 *addr, u32 size);
491 bool ast_dp501_read_edid(struct drm_device *dev, u8 *ediddata);
492 u8 ast_get_dp501_max_clk(struct drm_device *dev);
493 void ast_init_3rdtx(struct drm_device *dev);
494 
495 /* ast_i2c.c */
496 struct ast_i2c_chan *ast_i2c_create(struct drm_device *dev);
497 
498 /* aspeed DP */
499 int ast_astdp_read_edid(struct drm_device *dev, u8 *ediddata);
500 void ast_dp_launch(struct drm_device *dev, u8 bPower);
501 void ast_dp_power_on_off(struct drm_device *dev, bool no);
502 void ast_dp_set_on_off(struct drm_device *dev, bool no);
503 void ast_dp_set_mode(struct drm_crtc *crtc, struct ast_vbios_mode_info *vbios_mode);
504 
505 #endif
506