1 /*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #include <linux/delay.h>
25 #include <linux/kernel.h>
26 #include <linux/firmware.h>
27 #include <linux/module.h>
28 #include <linux/pci.h>
29 #include "amdgpu.h"
30 #include "amdgpu_gfx.h"
31 #include "amdgpu_psp.h"
32 #include "nv.h"
33 #include "nvd.h"
34
35 #include "gc/gc_10_1_0_offset.h"
36 #include "gc/gc_10_1_0_sh_mask.h"
37 #include "smuio/smuio_11_0_0_offset.h"
38 #include "smuio/smuio_11_0_0_sh_mask.h"
39 #include "navi10_enum.h"
40 #include "ivsrcid/gfx/irqsrcs_gfx_10_1.h"
41
42 #include "soc15.h"
43 #include "soc15d.h"
44 #include "soc15_common.h"
45 #include "clearstate_gfx10.h"
46 #include "v10_structs.h"
47 #include "gfx_v10_0.h"
48 #include "nbio_v2_3.h"
49
50 /*
51 * Navi10 has two graphic rings to share each graphic pipe.
52 * 1. Primary ring
53 * 2. Async ring
54 */
55 #define GFX10_NUM_GFX_RINGS_NV1X 1
56 #define GFX10_NUM_GFX_RINGS_Sienna_Cichlid 2
57 #define GFX10_MEC_HPD_SIZE 2048
58
59 #define F32_CE_PROGRAM_RAM_SIZE 65536
60 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L
61
62 #define mmCGTT_GS_NGG_CLK_CTRL 0x5087
63 #define mmCGTT_GS_NGG_CLK_CTRL_BASE_IDX 1
64 #define mmCGTT_SPI_RA0_CLK_CTRL 0x507a
65 #define mmCGTT_SPI_RA0_CLK_CTRL_BASE_IDX 1
66 #define mmCGTT_SPI_RA1_CLK_CTRL 0x507b
67 #define mmCGTT_SPI_RA1_CLK_CTRL_BASE_IDX 1
68
69 #define GB_ADDR_CONFIG__NUM_PKRS__SHIFT 0x8
70 #define GB_ADDR_CONFIG__NUM_PKRS_MASK 0x00000700L
71
72 #define mmCGTS_TCC_DISABLE_gc_10_3 0x5006
73 #define mmCGTS_TCC_DISABLE_gc_10_3_BASE_IDX 1
74 #define mmCGTS_USER_TCC_DISABLE_gc_10_3 0x5007
75 #define mmCGTS_USER_TCC_DISABLE_gc_10_3_BASE_IDX 1
76
77 #define mmCP_MEC_CNTL_Sienna_Cichlid 0x0f55
78 #define mmCP_MEC_CNTL_Sienna_Cichlid_BASE_IDX 0
79 #define mmRLC_SAFE_MODE_Sienna_Cichlid 0x4ca0
80 #define mmRLC_SAFE_MODE_Sienna_Cichlid_BASE_IDX 1
81 #define mmRLC_CP_SCHEDULERS_Sienna_Cichlid 0x4ca1
82 #define mmRLC_CP_SCHEDULERS_Sienna_Cichlid_BASE_IDX 1
83 #define mmSPI_CONFIG_CNTL_Sienna_Cichlid 0x11ec
84 #define mmSPI_CONFIG_CNTL_Sienna_Cichlid_BASE_IDX 0
85 #define mmVGT_ESGS_RING_SIZE_Sienna_Cichlid 0x0fc1
86 #define mmVGT_ESGS_RING_SIZE_Sienna_Cichlid_BASE_IDX 0
87 #define mmVGT_GSVS_RING_SIZE_Sienna_Cichlid 0x0fc2
88 #define mmVGT_GSVS_RING_SIZE_Sienna_Cichlid_BASE_IDX 0
89 #define mmVGT_TF_RING_SIZE_Sienna_Cichlid 0x0fc3
90 #define mmVGT_TF_RING_SIZE_Sienna_Cichlid_BASE_IDX 0
91 #define mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid 0x0fc4
92 #define mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid_BASE_IDX 0
93 #define mmVGT_TF_MEMORY_BASE_Sienna_Cichlid 0x0fc5
94 #define mmVGT_TF_MEMORY_BASE_Sienna_Cichlid_BASE_IDX 0
95 #define mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid 0x0fc6
96 #define mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid_BASE_IDX 0
97 #define GRBM_STATUS2__RLC_BUSY_Sienna_Cichlid__SHIFT 0x1a
98 #define GRBM_STATUS2__RLC_BUSY_Sienna_Cichlid_MASK 0x04000000L
99 #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_Sienna_Cichlid_MASK 0x00000FFCL
100 #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_Sienna_Cichlid__SHIFT 0x2
101 #define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_Sienna_Cichlid_MASK 0x00000FFCL
102 #define mmGCR_GENERAL_CNTL_Sienna_Cichlid 0x1580
103 #define mmGCR_GENERAL_CNTL_Sienna_Cichlid_BASE_IDX 0
104
105 #define mmGOLDEN_TSC_COUNT_UPPER_Vangogh 0x0025
106 #define mmGOLDEN_TSC_COUNT_UPPER_Vangogh_BASE_IDX 1
107 #define mmGOLDEN_TSC_COUNT_LOWER_Vangogh 0x0026
108 #define mmGOLDEN_TSC_COUNT_LOWER_Vangogh_BASE_IDX 1
109
110 #define mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6 0x002d
111 #define mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6_BASE_IDX 1
112 #define mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6 0x002e
113 #define mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6_BASE_IDX 1
114
115 #define mmSPI_CONFIG_CNTL_1_Vangogh 0x2441
116 #define mmSPI_CONFIG_CNTL_1_Vangogh_BASE_IDX 1
117 #define mmVGT_TF_MEMORY_BASE_HI_Vangogh 0x2261
118 #define mmVGT_TF_MEMORY_BASE_HI_Vangogh_BASE_IDX 1
119 #define mmVGT_HS_OFFCHIP_PARAM_Vangogh 0x224f
120 #define mmVGT_HS_OFFCHIP_PARAM_Vangogh_BASE_IDX 1
121 #define mmVGT_TF_RING_SIZE_Vangogh 0x224e
122 #define mmVGT_TF_RING_SIZE_Vangogh_BASE_IDX 1
123 #define mmVGT_GSVS_RING_SIZE_Vangogh 0x2241
124 #define mmVGT_GSVS_RING_SIZE_Vangogh_BASE_IDX 1
125 #define mmVGT_TF_MEMORY_BASE_Vangogh 0x2250
126 #define mmVGT_TF_MEMORY_BASE_Vangogh_BASE_IDX 1
127 #define mmVGT_ESGS_RING_SIZE_Vangogh 0x2240
128 #define mmVGT_ESGS_RING_SIZE_Vangogh_BASE_IDX 1
129 #define mmSPI_CONFIG_CNTL_Vangogh 0x2440
130 #define mmSPI_CONFIG_CNTL_Vangogh_BASE_IDX 1
131 #define mmGCR_GENERAL_CNTL_Vangogh 0x1580
132 #define mmGCR_GENERAL_CNTL_Vangogh_BASE_IDX 0
133 #define RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK_Vangogh 0x0000FFFFL
134
135 #define mmCP_HYP_PFP_UCODE_ADDR 0x5814
136 #define mmCP_HYP_PFP_UCODE_ADDR_BASE_IDX 1
137 #define mmCP_HYP_PFP_UCODE_DATA 0x5815
138 #define mmCP_HYP_PFP_UCODE_DATA_BASE_IDX 1
139 #define mmCP_HYP_CE_UCODE_ADDR 0x5818
140 #define mmCP_HYP_CE_UCODE_ADDR_BASE_IDX 1
141 #define mmCP_HYP_CE_UCODE_DATA 0x5819
142 #define mmCP_HYP_CE_UCODE_DATA_BASE_IDX 1
143 #define mmCP_HYP_ME_UCODE_ADDR 0x5816
144 #define mmCP_HYP_ME_UCODE_ADDR_BASE_IDX 1
145 #define mmCP_HYP_ME_UCODE_DATA 0x5817
146 #define mmCP_HYP_ME_UCODE_DATA_BASE_IDX 1
147
148 #define mmCPG_PSP_DEBUG 0x5c10
149 #define mmCPG_PSP_DEBUG_BASE_IDX 1
150 #define mmCPC_PSP_DEBUG 0x5c11
151 #define mmCPC_PSP_DEBUG_BASE_IDX 1
152 #define CPC_PSP_DEBUG__GPA_OVERRIDE_MASK 0x00000008L
153 #define CPG_PSP_DEBUG__GPA_OVERRIDE_MASK 0x00000008L
154
155 //CC_GC_SA_UNIT_DISABLE
156 #define mmCC_GC_SA_UNIT_DISABLE 0x0fe9
157 #define mmCC_GC_SA_UNIT_DISABLE_BASE_IDX 0
158 #define CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT 0x8
159 #define CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK 0x0000FF00L
160 //GC_USER_SA_UNIT_DISABLE
161 #define mmGC_USER_SA_UNIT_DISABLE 0x0fea
162 #define mmGC_USER_SA_UNIT_DISABLE_BASE_IDX 0
163 #define GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT 0x8
164 #define GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK 0x0000FF00L
165 //PA_SC_ENHANCE_3
166 #define mmPA_SC_ENHANCE_3 0x1085
167 #define mmPA_SC_ENHANCE_3_BASE_IDX 0
168 #define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO__SHIFT 0x3
169 #define PA_SC_ENHANCE_3__FORCE_PBB_WORKLOAD_MODE_TO_ZERO_MASK 0x00000008L
170
171 #define mmCGTT_SPI_CS_CLK_CTRL 0x507c
172 #define mmCGTT_SPI_CS_CLK_CTRL_BASE_IDX 1
173
174 #define mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid 0x16f3
175 #define mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid_BASE_IDX 0
176 #define mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid 0x15db
177 #define mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid_BASE_IDX 0
178
179 #define mmGC_THROTTLE_CTRL_Sienna_Cichlid 0x2030
180 #define mmGC_THROTTLE_CTRL_Sienna_Cichlid_BASE_IDX 0
181
182 #define mmRLC_SPARE_INT_0_Sienna_Cichlid 0x4ca5
183 #define mmRLC_SPARE_INT_0_Sienna_Cichlid_BASE_IDX 1
184
185 MODULE_FIRMWARE("amdgpu/navi10_ce.bin");
186 MODULE_FIRMWARE("amdgpu/navi10_pfp.bin");
187 MODULE_FIRMWARE("amdgpu/navi10_me.bin");
188 MODULE_FIRMWARE("amdgpu/navi10_mec.bin");
189 MODULE_FIRMWARE("amdgpu/navi10_mec2.bin");
190 MODULE_FIRMWARE("amdgpu/navi10_rlc.bin");
191
192 MODULE_FIRMWARE("amdgpu/navi14_ce_wks.bin");
193 MODULE_FIRMWARE("amdgpu/navi14_pfp_wks.bin");
194 MODULE_FIRMWARE("amdgpu/navi14_me_wks.bin");
195 MODULE_FIRMWARE("amdgpu/navi14_mec_wks.bin");
196 MODULE_FIRMWARE("amdgpu/navi14_mec2_wks.bin");
197 MODULE_FIRMWARE("amdgpu/navi14_ce.bin");
198 MODULE_FIRMWARE("amdgpu/navi14_pfp.bin");
199 MODULE_FIRMWARE("amdgpu/navi14_me.bin");
200 MODULE_FIRMWARE("amdgpu/navi14_mec.bin");
201 MODULE_FIRMWARE("amdgpu/navi14_mec2.bin");
202 MODULE_FIRMWARE("amdgpu/navi14_rlc.bin");
203
204 MODULE_FIRMWARE("amdgpu/navi12_ce.bin");
205 MODULE_FIRMWARE("amdgpu/navi12_pfp.bin");
206 MODULE_FIRMWARE("amdgpu/navi12_me.bin");
207 MODULE_FIRMWARE("amdgpu/navi12_mec.bin");
208 MODULE_FIRMWARE("amdgpu/navi12_mec2.bin");
209 MODULE_FIRMWARE("amdgpu/navi12_rlc.bin");
210
211 MODULE_FIRMWARE("amdgpu/sienna_cichlid_ce.bin");
212 MODULE_FIRMWARE("amdgpu/sienna_cichlid_pfp.bin");
213 MODULE_FIRMWARE("amdgpu/sienna_cichlid_me.bin");
214 MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec.bin");
215 MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec2.bin");
216 MODULE_FIRMWARE("amdgpu/sienna_cichlid_rlc.bin");
217
218 MODULE_FIRMWARE("amdgpu/navy_flounder_ce.bin");
219 MODULE_FIRMWARE("amdgpu/navy_flounder_pfp.bin");
220 MODULE_FIRMWARE("amdgpu/navy_flounder_me.bin");
221 MODULE_FIRMWARE("amdgpu/navy_flounder_mec.bin");
222 MODULE_FIRMWARE("amdgpu/navy_flounder_mec2.bin");
223 MODULE_FIRMWARE("amdgpu/navy_flounder_rlc.bin");
224
225 MODULE_FIRMWARE("amdgpu/vangogh_ce.bin");
226 MODULE_FIRMWARE("amdgpu/vangogh_pfp.bin");
227 MODULE_FIRMWARE("amdgpu/vangogh_me.bin");
228 MODULE_FIRMWARE("amdgpu/vangogh_mec.bin");
229 MODULE_FIRMWARE("amdgpu/vangogh_mec2.bin");
230 MODULE_FIRMWARE("amdgpu/vangogh_rlc.bin");
231
232 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_ce.bin");
233 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_pfp.bin");
234 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_me.bin");
235 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_mec.bin");
236 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_mec2.bin");
237 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_rlc.bin");
238
239 MODULE_FIRMWARE("amdgpu/beige_goby_ce.bin");
240 MODULE_FIRMWARE("amdgpu/beige_goby_pfp.bin");
241 MODULE_FIRMWARE("amdgpu/beige_goby_me.bin");
242 MODULE_FIRMWARE("amdgpu/beige_goby_mec.bin");
243 MODULE_FIRMWARE("amdgpu/beige_goby_mec2.bin");
244 MODULE_FIRMWARE("amdgpu/beige_goby_rlc.bin");
245
246 MODULE_FIRMWARE("amdgpu/yellow_carp_ce.bin");
247 MODULE_FIRMWARE("amdgpu/yellow_carp_pfp.bin");
248 MODULE_FIRMWARE("amdgpu/yellow_carp_me.bin");
249 MODULE_FIRMWARE("amdgpu/yellow_carp_mec.bin");
250 MODULE_FIRMWARE("amdgpu/yellow_carp_mec2.bin");
251 MODULE_FIRMWARE("amdgpu/yellow_carp_rlc.bin");
252
253 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_ce.bin");
254 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_pfp.bin");
255 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_me.bin");
256 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_mec.bin");
257 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_mec2.bin");
258 MODULE_FIRMWARE("amdgpu/cyan_skillfish2_rlc.bin");
259
260 MODULE_FIRMWARE("amdgpu/gc_10_3_6_ce.bin");
261 MODULE_FIRMWARE("amdgpu/gc_10_3_6_pfp.bin");
262 MODULE_FIRMWARE("amdgpu/gc_10_3_6_me.bin");
263 MODULE_FIRMWARE("amdgpu/gc_10_3_6_mec.bin");
264 MODULE_FIRMWARE("amdgpu/gc_10_3_6_mec2.bin");
265 MODULE_FIRMWARE("amdgpu/gc_10_3_6_rlc.bin");
266
267 MODULE_FIRMWARE("amdgpu/gc_10_3_7_ce.bin");
268 MODULE_FIRMWARE("amdgpu/gc_10_3_7_pfp.bin");
269 MODULE_FIRMWARE("amdgpu/gc_10_3_7_me.bin");
270 MODULE_FIRMWARE("amdgpu/gc_10_3_7_mec.bin");
271 MODULE_FIRMWARE("amdgpu/gc_10_3_7_mec2.bin");
272 MODULE_FIRMWARE("amdgpu/gc_10_3_7_rlc.bin");
273
274 static const struct soc15_reg_golden golden_settings_gc_10_1[] =
275 {
276 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x00400014),
277 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 0xf8000100),
278 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100),
279 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0x60000ff0, 0x60000100),
280 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000000, 0x40000100),
281 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
282 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xfeff8fff, 0xfeff8100),
283 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
284 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000),
285 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x000007ff, 0x000005ff),
286 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0x20000000, 0x20000000),
287 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
288 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200),
289 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07900000, 0x04900000),
290 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
291 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
292 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
293 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe),
294 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
295 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032),
296 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231),
297 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
298 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
299 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0x10000000, 0x10000100),
300 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
301 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffff9fff, 0x00001188),
302 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
303 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
304 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000),
305 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820),
306 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
307 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
308 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070104),
309 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
310 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000100, 0x00000130),
311 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
312 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
313 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010),
314 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CGTT_CLK_CTRL, 0xfeff0fff, 0x40000100),
315 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000)
316 };
317
318 static const struct soc15_reg_golden golden_settings_gc_10_0_nv10[] =
319 {
320 /* Pending on emulation bring up */
321 };
322
323 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_0_nv10[] =
324 {
325 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000, 0x0),
326 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
327 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
328 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
329 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
330 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
331 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
332 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
333 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
334 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
335 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
336 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
337 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
338 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
339 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
340 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
341 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
342 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
343 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
344 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
345 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
346 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
347 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
348 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
349 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
350 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
351 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
352 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
353 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
354 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
355 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
356 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
357 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
358 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
359 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
360 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
361 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
362 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
363 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
364 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
365 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
366 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
367 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
368 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
369 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
370 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
371 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
372 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
373 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
374 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
375 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
376 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
377 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
378 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
379 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
380 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
381 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
382 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
383 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
384 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
385 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
386 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
387 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
388 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
389 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
390 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
391 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
392 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
393 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
394 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
395 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
396 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
397 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
398 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
399 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
400 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
401 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
402 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
403 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
404 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
405 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
406 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
407 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
408 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
409 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
410 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
411 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
412 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
413 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
414 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
415 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
416 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
417 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
418 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
419 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
420 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
421 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
422 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
423 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
424 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
425 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
426 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
427 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
428 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
429 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
430 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
431 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
432 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
433 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
434 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
435 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
436 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
437 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
438 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
439 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
440 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
441 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
442 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
443 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
444 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
445 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
446 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
447 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
448 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
449 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
450 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
451 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
452 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
453 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
454 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
455 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
456 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
457 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
458 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
459 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
460 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
461 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
462 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
463 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
464 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
465 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
466 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
467 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
468 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
469 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
470 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
471 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
472 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
473 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
474 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
475 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
476 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
477 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
478 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
479 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
480 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
481 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
482 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
483 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
484 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
485 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
486 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
487 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
488 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
489 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
490 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
491 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
492 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
493 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
494 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
495 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
496 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
497 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
498 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
499 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
500 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
501 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
502 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
503 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
504 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
505 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
506 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
507 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
508 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
509 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
510 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
511 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
512 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
513 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
514 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
515 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
516 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
517 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
518 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
519 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
520 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
521 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
522 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
523 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
524 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
525 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
526 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
527 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
528 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
529 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
530 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
531 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
532 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
533 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
534 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
535 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
536 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
537 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
538 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
539 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
540 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
541 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
542 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
543 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c),
544 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
545 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
546 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
547 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
548 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
549 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
550 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
551 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
552 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
553 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
554 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
555 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
556 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
557 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
558 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
559 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
560 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
561 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
562 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
563 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
564 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
565 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
566 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
567 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
568 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
569 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
570 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
571 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
572 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
573 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
574 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
575 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
576 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
577 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
578 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
579 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
580 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
581 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
582 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
583 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
584 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
585 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
586 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
587 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
588 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
589 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
590 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
591 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
592 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
593 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
594 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
595 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
596 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
597 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
598 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
599 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
600 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
601 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
602 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
603 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
604 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
605 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
606 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
607 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
608 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
609 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
610 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
611 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
612 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
613 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
614 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
615 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
616 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
617 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
618 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
619 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
620 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
621 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
622 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
623 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
624 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
625 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
626 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
627 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
628 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
629 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
630 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
631 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
632 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
633 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
634 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
635 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
636 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
637 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
638 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
639 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
640 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
641 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
642 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
643 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
644 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
645 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
646 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
647 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
648 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
649 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
650 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
651 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
652 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
653 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
654 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
655 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
656 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
657 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
658 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
659 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
660 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
661 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
662 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
663 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
664 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
665 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
666 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
667 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
668 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
669 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
670 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
671 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
672 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
673 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
674 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
675 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
676 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
677 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
678 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
679 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
680 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
681 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
682 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
683 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
684 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
685 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
686 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
687 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
688 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
689 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
690 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
691 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
692 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
693 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
694 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
695 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
696 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
697 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
698 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
699 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
700 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
701 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
702 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
703 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
704 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
705 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
706 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
707 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
708 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
709 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
710 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
711 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
712 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
713 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
714 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
715 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
716 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
717 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
718 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
719 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
720 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
721 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
722 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
723 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
724 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
725 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
726 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
727 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
728 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
729 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
730 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
731 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
732 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
733 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
734 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
735 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
736 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
737 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
738 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
739 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
740 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
741 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
742 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
743 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
744 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
745 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
746 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
747 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
748 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
749 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
750 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
751 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
752 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
753 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
754 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
755 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
756 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
757 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
758 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
759 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
760 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
761 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
762 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
763 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
764 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
765 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
766 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
767 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
768 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
769 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
770 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
771 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
772 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
773 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
774 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
775 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
776 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
777 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
778 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
779 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
780 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
781 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
782 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
783 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
784 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
785 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
786 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
787 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
788 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
789 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
790 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
791 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
792 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
793 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
794 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
795 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
796 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
797 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
798 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
799 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
800 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
801 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
802 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
803 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
804 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
805 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
806 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
807 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
808 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
809 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
810 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
811 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
812 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
813 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
814 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
815 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
816 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
817 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
818 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
819 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
820 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
821 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
822 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
823 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
824 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
825 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
826 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
827 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
828 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
829 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
830 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
831 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
832 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
833 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
834 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
835 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
836 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
837 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
838 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
839 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
840 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
841 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
842 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
843 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
844 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
845 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
846 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
847 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
848 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
849 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
850 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
851 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
852 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
853 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
854 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
855 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
856 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
857 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
858 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
859 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
860 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
861 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
862 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
863 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
864 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
865 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
866 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
867 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
868 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
869 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
870 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
871 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
872 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
873 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
874 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
875 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
876 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
877 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
878 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
879 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
880 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
881 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
882 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
883 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
884 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
885 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
886 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
887 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
888 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
889 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
890 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
891 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
892 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
893 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
894 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
895 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
896 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
897 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
898 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
899 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
900 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
901 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
902 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
903 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
904 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
905 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
906 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
907 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
908 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
909 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
910 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
911 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
912 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
913 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
914 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
915 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
916 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
917 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
918 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
919 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
920 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
921 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
922 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
923 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
924 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
925 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
926 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
927 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
928 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
929 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
930 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
931 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
932 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
933 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
934 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
935 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
936 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
937 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
938 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
939 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
940 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
941 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
942 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
943 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
944 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
945 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
946 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
947 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
948 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
949 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
950 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
951 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
952 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
953 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
954 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
955 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
956 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
957 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
958 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
959 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
960 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
961 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
962 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
963 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
964 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
965 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
966 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
967 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
968 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
969 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
970 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
971 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
972 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
973 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
974 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
975 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
976 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
977 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
978 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
979 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
980 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
981 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
982 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
983 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
984 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
985 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
986 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
987 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
988 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
989 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
990 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
991 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
992 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
993 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
994 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
995 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
996 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
997 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
998 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
999 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
1000 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1001 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1002 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1003 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
1004 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1005 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1006 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1007 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
1008 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1009 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1010 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1011 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
1012 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1013 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1014 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1015 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
1016 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1017 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1018 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1019 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
1020 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1021 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1022 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1023 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
1024 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1025 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1026 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1027 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
1028 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1029 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1030 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1031 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
1032 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1033 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1034 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1035 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
1036 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1037 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1038 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1039 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
1040 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1041 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1042 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1043 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
1044 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1045 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
1046 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1047 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
1048 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1049 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
1050 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1051 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
1052 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1053 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
1054 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1055 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
1056 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1057 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1058 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1059 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
1060 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1061 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1062 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1063 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
1064 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1065 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1066 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1067 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
1068 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1069 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1070 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1071 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
1072 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1073 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1074 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1075 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
1076 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1077 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1078 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1079 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
1080 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1081 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1082 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1083 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
1084 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1085 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1086 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1087 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
1088 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1089 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
1090 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1091 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
1092 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1093 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
1094 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1095 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
1096 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1097 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1098 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1099 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
1100 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1101 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1102 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1103 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
1104 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1105 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1106 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1107 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
1108 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1109 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1110 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1111 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
1112 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1113 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1114 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1115 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
1116 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1117 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1118 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1119 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
1120 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1121 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1122 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1123 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
1124 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1125 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1126 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1127 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
1128 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1129 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1130 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1131 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
1132 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1133 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1134 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1135 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
1136 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1137 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1138 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1139 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
1140 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1141 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1142 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1143 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
1144 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1145 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1146 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1147 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
1148 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1149 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1150 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1151 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
1152 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1153 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1154 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1155 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
1156 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1157 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1158 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1159 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
1160 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1161 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1162 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1163 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
1164 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1165 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1166 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1167 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
1168 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1169 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1170 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1171 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
1172 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1173 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1174 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1175 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
1176 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1177 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1178 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1179 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
1180 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1181 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1182 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1183 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
1184 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1185 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1186 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1187 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
1188 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1189 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1190 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1191 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
1192 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1193 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
1194 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1195 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
1196 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1197 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
1198 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1199 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
1200 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1201 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1202 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1203 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
1204 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1205 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1206 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1207 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
1208 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1209 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
1210 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1211 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
1212 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1213 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
1214 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1215 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
1216 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1217 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1218 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1219 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
1220 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1221 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1222 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1223 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
1224 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1225 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1226 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1227 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
1228 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1229 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1230 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1231 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
1232 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1233 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1234 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1235 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
1236 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1237 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1238 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1239 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
1240 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1241 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1242 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1243 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
1244 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1245 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1246 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1247 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
1248 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1249 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1250 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1251 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
1252 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1253 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1254 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1255 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
1256 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1257 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1258 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1259 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
1260 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1261 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1262 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1263 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
1264 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1265 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1266 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1267 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
1268 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1269 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1270 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1271 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
1272 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1273 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1274 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1275 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
1276 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1277 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1278 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1279 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
1280 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1281 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1282 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1283 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
1284 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1285 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1286 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1287 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
1288 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1289 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1290 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1291 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
1292 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1293 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1294 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1295 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
1296 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1297 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1298 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1299 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
1300 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1301 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1302 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1303 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
1304 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1305 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1306 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1307 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
1308 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1309 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1310 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1311 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
1312 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1313 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1314 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1315 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
1316 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1317 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1318 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1319 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
1320 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1321 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1322 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1323 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
1324 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1325 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1326 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1327 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
1328 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1329 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1330 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1331 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
1332 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1333 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1334 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1335 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
1336 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1337 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1338 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1339 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
1340 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1341 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1342 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1343 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
1344 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1345 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
1346 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1347 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
1348 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1349 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
1350 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1351 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
1352 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1353 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
1354 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1355 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
1356 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1357 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
1358 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1359 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
1360 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1361 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
1362 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1363 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x19),
1364 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1365 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x20),
1366 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1367 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x5),
1368 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1369 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0xa),
1370 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1371 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x14),
1372 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1373 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x19),
1374 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1375 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x33),
1376 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000)
1377 };
1378
1379 static const struct soc15_reg_golden golden_settings_gc_10_1_1[] =
1380 {
1381 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x003c0014),
1382 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100),
1383 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100),
1384 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100),
1385 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xf8ff0fff, 0x60000100),
1386 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000ff0, 0x40000100),
1387 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
1388 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100),
1389 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1390 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000),
1391 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff),
1392 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000),
1393 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
1394 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200),
1395 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04900000),
1396 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
1397 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
1398 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
1399 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe),
1400 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1401 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7),
1402 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7),
1403 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100),
1404 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
1405 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188),
1406 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
1407 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
1408 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000),
1409 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820),
1410 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
1411 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
1412 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070105),
1413 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
1414 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130),
1415 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
1416 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
1417 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010),
1418 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000),
1419 };
1420
1421 static const struct soc15_reg_golden golden_settings_gc_10_1_2[] =
1422 {
1423 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0x003e001f, 0x003c0014),
1424 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100),
1425 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100),
1426 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xff7f0fff, 0x0d000100),
1427 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xffffcfff, 0x60000100),
1428 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0xffff0fff, 0x40000100),
1429 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
1430 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100),
1431 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1432 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000003, 0x00000000),
1433 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff),
1434 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000),
1435 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
1436 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200),
1437 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04900000),
1438 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
1439 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
1440 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1800ff, 0x00000044),
1441 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
1442 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x00007fff, 0x000001fe),
1443 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1444 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032),
1445 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231),
1446 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
1447 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
1448 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100),
1449 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
1450 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188),
1451 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_0, 0xffffffff, 0x842a4c02),
1452 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
1453 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
1454 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04440000),
1455 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000820, 0x00000820),
1456 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
1457 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
1458 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070104),
1459 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
1460 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130),
1461 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
1462 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
1463 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0xffdf80ff, 0x479c0010),
1464 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00c00000)
1465 };
1466
1467 static const struct soc15_reg_golden golden_settings_gc_10_1_nv14[] =
1468 {
1469 /* Pending on emulation bring up */
1470 };
1471
1472 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_nv14[] =
1473 {
1474 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000L, 0x0),
1475 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1476 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
1477 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1478 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1479 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1480 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
1481 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1482 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1483 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1484 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
1485 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1486 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1487 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1488 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
1489 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1490 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1491 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1492 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
1493 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1494 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1495 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1496 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
1497 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1498 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1499 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1500 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
1501 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1502 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1503 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1504 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
1505 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1506 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1507 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1508 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
1509 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1510 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1511 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1512 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
1513 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1514 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1515 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1516 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
1517 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1518 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1519 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1520 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
1521 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1522 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1523 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1524 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
1525 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1526 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
1527 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1528 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
1529 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1530 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1531 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1532 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
1533 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1534 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1535 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1536 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
1537 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1538 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1539 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1540 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
1541 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1542 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1543 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1544 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
1545 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1546 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1547 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1548 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
1549 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1550 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1551 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1552 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
1553 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1554 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1555 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1556 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
1557 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1558 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1559 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1560 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
1561 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1562 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1563 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1564 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
1565 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1566 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1567 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1568 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
1569 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1570 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1571 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1572 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
1573 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1574 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1575 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1576 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
1577 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1578 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1579 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1580 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
1581 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1582 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1583 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1584 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
1585 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1586 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1587 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1588 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
1589 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1590 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1591 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1592 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
1593 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1594 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1595 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1596 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
1597 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1598 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1599 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1600 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
1601 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1602 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1603 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1604 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
1605 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1606 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1607 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1608 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
1609 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1610 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1611 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1612 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c),
1613 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1614 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1615 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1616 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
1617 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1618 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1619 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1620 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
1621 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1622 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1623 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1624 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
1625 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1626 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1627 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1628 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
1629 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1630 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1631 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1632 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
1633 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1634 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1635 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1636 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
1637 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1638 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1639 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1640 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
1641 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1642 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1643 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1644 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
1645 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1646 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1647 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1648 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
1649 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1650 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1651 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1652 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
1653 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1654 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
1655 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1656 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
1657 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1658 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1659 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1660 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
1661 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1662 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1663 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1664 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
1665 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1666 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1667 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1668 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
1669 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1670 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1671 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1672 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
1673 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1674 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
1675 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1676 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
1677 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1678 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1679 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1680 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
1681 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1682 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1683 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1684 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
1685 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1686 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1687 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1688 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
1689 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1690 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1691 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1692 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
1693 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1694 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1695 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1696 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
1697 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1698 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1699 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1700 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
1701 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1702 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1703 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1704 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
1705 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1706 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1707 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1708 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
1709 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1710 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1711 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1712 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
1713 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1714 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1715 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1716 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
1717 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1718 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1719 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1720 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
1721 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1722 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1723 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1724 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
1725 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1726 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1727 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1728 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
1729 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1730 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1731 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1732 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
1733 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1734 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1735 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1736 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
1737 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1738 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1739 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1740 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
1741 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1742 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1743 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1744 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
1745 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1746 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1747 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1748 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
1749 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1750 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1751 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1752 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
1753 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1754 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1755 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1756 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
1757 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1758 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1759 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1760 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
1761 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1762 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1763 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1764 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
1765 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1766 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1767 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1768 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
1769 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1770 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1771 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1772 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
1773 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1774 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1775 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1776 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
1777 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1778 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1779 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1780 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
1781 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1782 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1783 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1784 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
1785 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1786 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1787 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1788 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
1789 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1790 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1791 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1792 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
1793 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1794 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1795 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1796 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
1797 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1798 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1799 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1800 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
1801 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1802 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1803 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1804 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
1805 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1806 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1807 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1808 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
1809 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1810 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1811 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1812 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
1813 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1814 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1815 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1816 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
1817 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1818 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1819 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1820 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
1821 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1822 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1823 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1824 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
1825 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1826 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1827 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1828 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
1829 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1830 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1831 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1832 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
1833 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1834 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1835 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1836 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe4),
1837 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1838 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1839 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1840 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
1841 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1842 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1843 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1844 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
1845 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1846 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1847 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1848 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
1849 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1850 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1851 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1852 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
1853 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1854 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1855 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1856 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
1857 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1858 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1859 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1860 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
1861 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1862 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1863 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1864 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
1865 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1866 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1867 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1868 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
1869 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1870 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1871 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1872 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
1873 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1874 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
1875 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1876 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
1877 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1878 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1879 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1880 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
1881 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1882 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1883 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1884 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
1885 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1886 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1887 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1888 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
1889 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1890 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1891 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1892 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
1893 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1894 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
1895 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1896 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
1897 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1898 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1899 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1900 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
1901 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1902 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1903 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1904 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
1905 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1906 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1907 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1908 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
1909 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1910 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1911 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1912 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
1913 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1914 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1915 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1916 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
1917 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1918 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1919 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1920 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
1921 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1922 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1923 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1924 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
1925 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1926 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1927 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1928 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
1929 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1930 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1931 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1932 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
1933 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1934 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1935 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1936 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
1937 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1938 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1939 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1940 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
1941 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1942 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1943 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1944 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
1945 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1946 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1947 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1948 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
1949 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1950 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1951 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1952 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
1953 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1954 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1955 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1956 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
1957 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1958 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1959 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1960 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
1961 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1962 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1963 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1964 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
1965 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1966 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1967 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1968 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
1969 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1970 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1971 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1972 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
1973 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1974 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1975 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1976 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
1977 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1978 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1979 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1980 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
1981 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1982 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1983 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1984 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
1985 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1986 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1987 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1988 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
1989 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1990 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1991 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1992 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
1993 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1994 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1995 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1996 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
1997 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1998 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1999 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2000 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
2001 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2002 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2003 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2004 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
2005 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2006 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2007 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2008 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
2009 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2010 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2011 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2012 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a0),
2013 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2014 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2015 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2016 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a4),
2017 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2018 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2019 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2020 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b0),
2021 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2022 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2023 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2024 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b4),
2025 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2026 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2027 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2028 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a8),
2029 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2030 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2031 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2032 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1ac),
2033 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2034 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2035 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2036 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b8),
2037 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2038 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2039 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2040 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1bc),
2041 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2042 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2043 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2044 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c8),
2045 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2046 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2047 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2048 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1cc),
2049 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2050 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2051 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2052 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c0),
2053 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2054 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2055 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2056 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c4),
2057 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2058 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2059 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2060 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
2061 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2062 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2063 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2064 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
2065 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2066 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2067 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2068 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
2069 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2070 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
2071 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2072 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
2073 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2074 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
2075 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2076 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
2077 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2078 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2079 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2080 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x26),
2081 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2082 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x28),
2083 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2084 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0xf),
2085 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2086 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x15),
2087 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2088 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x1f),
2089 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2090 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x25),
2091 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2092 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x3b),
2093 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000)
2094 };
2095
2096 static const struct soc15_reg_golden golden_settings_gc_10_1_2_nv12[] =
2097 {
2098 /* Pending on emulation bring up */
2099 };
2100
2101 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_2_nv12[] =
2102 {
2103 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000L, 0x0),
2104 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2105 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
2106 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2107 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2108 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2109 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
2110 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2111 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2112 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2113 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
2114 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2115 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2116 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2117 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
2118 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2119 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2120 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2121 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
2122 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2123 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2124 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2125 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
2126 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2127 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2128 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2129 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
2130 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2131 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2132 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2133 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
2134 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2135 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2136 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2137 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2138 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2139 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2140 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2141 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2142 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2143 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2144 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2145 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
2146 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2147 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2148 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2149 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
2150 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2151 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2152 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2153 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
2154 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2155 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2156 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2157 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
2158 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2159 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2160 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2161 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
2162 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2163 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2164 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2165 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
2166 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2167 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2168 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2169 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
2170 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2171 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
2172 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2173 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
2174 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2175 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
2176 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2177 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
2178 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2179 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
2180 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2181 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
2182 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2183 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2184 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2185 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
2186 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2187 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2188 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2189 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
2190 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2191 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2192 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2193 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
2194 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2195 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2196 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2197 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
2198 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2199 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
2200 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2201 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
2202 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2203 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
2204 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2205 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
2206 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2207 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2208 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2209 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
2210 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2211 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2212 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2213 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
2214 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2215 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
2216 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2217 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
2218 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2219 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2220 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2221 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
2222 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2223 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2224 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2225 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
2226 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2227 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2228 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2229 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
2230 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2231 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2232 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2233 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
2234 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2235 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2236 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2237 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
2238 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2239 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2240 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2241 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
2242 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2243 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2244 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2245 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
2246 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2247 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2248 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2249 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
2250 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2251 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2252 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2253 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
2254 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2255 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2256 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2257 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
2258 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2259 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2260 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2261 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
2262 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2263 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2264 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2265 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
2266 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2267 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2268 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2269 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
2270 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2271 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2272 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2273 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
2274 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2275 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
2276 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2277 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
2278 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2279 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2280 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2281 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
2282 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2283 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2284 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2285 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
2286 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2287 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2288 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2289 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
2290 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2291 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2292 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2293 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
2294 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2295 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
2296 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2297 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
2298 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2299 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2300 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2301 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
2302 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2303 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2304 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2305 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
2306 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2307 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2308 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2309 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
2310 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2311 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2312 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2313 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
2314 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2315 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2316 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2317 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
2318 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2319 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2320 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2321 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c),
2322 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2323 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
2324 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2325 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
2326 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2327 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2328 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2329 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
2330 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2331 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
2332 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2333 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
2334 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2335 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
2336 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2337 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2338 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2339 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2340 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2341 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2342 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2343 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2344 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2345 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
2346 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2347 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2348 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2349 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
2350 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2351 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2352 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2353 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
2354 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2355 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2356 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2357 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
2358 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2359 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2360 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2361 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
2362 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2363 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
2364 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2365 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
2366 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2367 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
2368 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2369 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
2370 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2371 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2372 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2373 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
2374 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2375 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2376 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2377 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
2378 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2379 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2380 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2381 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
2382 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2383 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2384 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2385 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
2386 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2387 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2388 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2389 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
2390 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2391 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2392 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2393 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
2394 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2395 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2396 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2397 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
2398 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2399 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2400 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2401 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
2402 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2403 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2404 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2405 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
2406 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2407 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2408 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2409 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
2410 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2411 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2412 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2413 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
2414 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2415 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2416 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2417 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
2418 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2419 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2420 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2421 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
2422 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2423 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2424 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2425 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
2426 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2427 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2428 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2429 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
2430 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2431 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2432 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2433 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
2434 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2435 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2436 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2437 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
2438 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2439 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2440 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2441 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
2442 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2443 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2444 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2445 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
2446 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2447 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2448 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2449 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
2450 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2451 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2452 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2453 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
2454 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2455 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2456 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2457 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
2458 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2459 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2460 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2461 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
2462 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2463 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2464 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2465 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
2466 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2467 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2468 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2469 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
2470 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2471 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2472 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2473 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
2474 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2475 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2476 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2477 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
2478 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2479 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2480 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2481 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
2482 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2483 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2484 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2485 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
2486 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2487 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2488 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2489 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
2490 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2491 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2492 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2493 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
2494 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2495 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2496 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2497 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
2498 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2499 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2500 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2501 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
2502 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2503 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2504 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2505 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
2506 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2507 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2508 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2509 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
2510 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2511 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2512 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2513 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
2514 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2515 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2516 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2517 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
2518 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2519 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2520 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2521 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
2522 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2523 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2524 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2525 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
2526 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2527 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2528 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2529 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
2530 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2531 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2532 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2533 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
2534 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2535 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2536 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2537 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
2538 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2539 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2540 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2541 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
2542 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2543 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2544 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2545 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
2546 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2547 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2548 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2549 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
2550 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2551 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2552 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2553 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
2554 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2555 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2556 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2557 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
2558 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2559 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2560 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2561 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
2562 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2563 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2564 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2565 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
2566 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2567 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2568 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2569 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
2570 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2571 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2572 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2573 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
2574 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2575 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2576 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2577 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
2578 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2579 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2580 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2581 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
2582 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2583 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2584 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2585 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
2586 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2587 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2588 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2589 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
2590 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2591 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2592 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2593 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
2594 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2595 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2596 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2597 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
2598 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2599 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2600 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2601 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
2602 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2603 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2604 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2605 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
2606 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2607 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2608 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2609 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
2610 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2611 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2612 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2613 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
2614 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2615 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2616 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2617 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
2618 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2619 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2620 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2621 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
2622 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2623 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2624 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2625 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
2626 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2627 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2628 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2629 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
2630 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2631 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2632 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2633 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
2634 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2635 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2636 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2637 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
2638 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2639 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2640 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2641 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
2642 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2643 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2644 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2645 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
2646 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2647 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2648 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2649 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
2650 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2651 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2652 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2653 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
2654 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2655 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2656 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2657 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
2658 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2659 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2660 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2661 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
2662 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2663 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2664 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2665 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
2666 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2667 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2668 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2669 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
2670 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2671 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2672 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2673 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
2674 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2675 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2676 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2677 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
2678 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2679 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2680 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2681 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
2682 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2683 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2684 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2685 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
2686 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2687 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2688 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2689 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
2690 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2691 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2692 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2693 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
2694 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2695 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2696 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2697 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
2698 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2699 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2700 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2701 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
2702 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2703 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2704 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2705 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
2706 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2707 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2708 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2709 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
2710 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2711 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2712 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2713 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
2714 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2715 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2716 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2717 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
2718 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2719 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2720 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2721 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
2722 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2723 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2724 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2725 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
2726 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2727 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2728 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2729 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
2730 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2731 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2732 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2733 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
2734 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2735 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2736 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2737 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
2738 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2739 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2740 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2741 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
2742 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2743 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2744 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2745 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
2746 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2747 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2748 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2749 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
2750 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2751 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2752 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2753 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
2754 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2755 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2756 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2757 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
2758 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2759 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2760 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2761 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
2762 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2763 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
2764 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2765 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
2766 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2767 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
2768 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2769 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
2770 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2771 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2772 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2773 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
2774 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2775 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2776 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2777 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
2778 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2779 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2780 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2781 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
2782 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2783 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2784 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2785 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
2786 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2787 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2788 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2789 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
2790 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2791 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2792 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2793 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
2794 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2795 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2796 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2797 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
2798 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2799 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2800 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2801 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
2802 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2803 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2804 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2805 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
2806 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2807 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2808 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2809 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
2810 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2811 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2812 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2813 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
2814 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2815 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2816 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2817 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
2818 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2819 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2820 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2821 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
2822 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2823 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2824 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2825 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
2826 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2827 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2828 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2829 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
2830 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2831 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2832 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2833 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
2834 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2835 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2836 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2837 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
2838 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2839 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2840 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2841 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
2842 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2843 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2844 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2845 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
2846 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2847 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2848 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2849 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
2850 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2851 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2852 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2853 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
2854 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2855 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2856 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2857 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
2858 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2859 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2860 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2861 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
2862 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2863 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2864 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2865 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
2866 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2867 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2868 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2869 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
2870 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2871 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2872 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2873 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
2874 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2875 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2876 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2877 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
2878 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2879 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2880 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2881 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
2882 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2883 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2884 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2885 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
2886 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2887 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2888 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2889 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
2890 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2891 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2892 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2893 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
2894 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2895 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2896 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2897 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
2898 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2899 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2900 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2901 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
2902 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2903 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2904 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2905 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
2906 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2907 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2908 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2909 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
2910 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2911 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2912 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2913 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
2914 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2915 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
2916 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2917 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
2918 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2919 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
2920 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2921 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
2922 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2923 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2924 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2925 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
2926 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2927 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2928 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2929 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
2930 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2931 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2932 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2933 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
2934 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2935 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2936 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2937 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
2938 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2939 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2940 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2941 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
2942 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2943 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2944 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2945 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
2946 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2947 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2948 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2949 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
2950 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2951 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2952 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2953 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
2954 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2955 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2956 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2957 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
2958 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2959 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2960 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2961 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
2962 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2963 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2964 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2965 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
2966 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2967 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2968 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2969 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
2970 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2971 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2972 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2973 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
2974 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2975 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2976 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2977 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
2978 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2979 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2980 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2981 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
2982 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2983 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2984 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2985 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
2986 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2987 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2988 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2989 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
2990 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2991 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2992 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2993 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
2994 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2995 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2996 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2997 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
2998 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2999 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
3000 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3001 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
3002 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3003 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3004 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3005 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
3006 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3007 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3008 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3009 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
3010 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3011 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
3012 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3013 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
3014 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3015 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
3016 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3017 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
3018 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3019 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3020 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3021 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
3022 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3023 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3024 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3025 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
3026 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3027 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3028 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3029 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
3030 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3031 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3032 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3033 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
3034 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3035 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3036 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3037 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
3038 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3039 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3040 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3041 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
3042 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3043 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3044 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3045 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
3046 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3047 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3048 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3049 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
3050 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3051 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3052 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3053 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
3054 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3055 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
3056 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3057 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
3058 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3059 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3060 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3061 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
3062 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3063 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3064 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3065 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
3066 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3067 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3068 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3069 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
3070 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3071 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3072 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3073 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
3074 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3075 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3076 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3077 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
3078 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3079 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3080 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3081 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
3082 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3083 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
3084 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3085 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
3086 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3087 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
3088 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3089 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
3090 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3091 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
3092 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3093 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
3094 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3095 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
3096 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3097 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
3098 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3099 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3100 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3101 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
3102 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3103 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3104 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3105 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
3106 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3107 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
3108 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3109 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
3110 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3111 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
3112 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3113 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
3114 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3115 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
3116 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3117 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
3118 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3119 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
3120 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3121 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
3122 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3123 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
3124 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3125 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
3126 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3127 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
3128 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3129 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
3130 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3131 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
3132 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3133 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
3134 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3135 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
3136 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3137 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
3138 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3139 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
3140 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3141 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x1f),
3142 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3143 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x22),
3144 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3145 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x1),
3146 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3147 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x6),
3148 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3149 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x10),
3150 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3151 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x15),
3152 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3153 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x35),
3154 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000)
3155 };
3156
3157 static const struct soc15_reg_golden golden_settings_gc_10_3[] =
3158 {
3159 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100),
3160 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_PS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3161 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100),
3162 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100),
3163 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),
3164 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3165 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3166 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000),
3167 SOC15_REG_GOLDEN_VALUE(GC, 0 ,mmGCEA_SDP_TAG_RESERVE0, 0xffffffff, 0x10100100),
3168 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCEA_SDP_TAG_RESERVE1, 0xffffffff, 0x17000088),
3169 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500),
3170 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xff000000, 0xff008080),
3171 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xff000000, 0xff008080),
3172 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003fffff, 0x00280400),
3173 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3174 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3175 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3176 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x10f80988),
3177 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x00000020, 0x00000020),
3178 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3179 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3180 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
3181 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffffffff, 0x00070104),
3182 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070),
3183 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000),
3184 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000),
3185 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000),
3186 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000),
3187 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000),
3188 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000),
3189 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000),
3190 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000),
3191 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000),
3192 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000),
3193 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000),
3194 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000),
3195 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000),
3196 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),
3197 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),
3198 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),
3199 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0x00010000, 0x00010020),
3200 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3201 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000)
3202 };
3203
3204 static const struct soc15_reg_golden golden_settings_gc_10_3_sienna_cichlid[] =
3205 {
3206 /* Pending on emulation bring up */
3207 };
3208
3209 static const struct soc15_reg_golden golden_settings_gc_10_3_2[] =
3210 {
3211 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3212 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_PS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3213 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100),
3214 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100),
3215 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),
3216 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3217 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3218 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000),
3219 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500),
3220 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCUTCL2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xffffffff, 0xff008080),
3221 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCVM_L2_CGTT_CLK_CTRL_Sienna_Cichlid, 0xffff8fff, 0xff008080),
3222 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003fffff, 0x00280400),
3223 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3224 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3225 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3226 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
3227 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3228 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3229 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
3230 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffffffff, 0x00070104),
3231 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_START_PHASE, 0x000000ff, 0x00000004),
3232 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070),
3233 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000),
3234 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000),
3235 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000),
3236 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000),
3237 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000),
3238 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000),
3239 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000),
3240 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000),
3241 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000),
3242 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000),
3243 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000),
3244 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000),
3245 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000),
3246 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),
3247 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),
3248 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),
3249 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3250 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000),
3251 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000003ff),
3252
3253 /* This is not in GDB yet. Don't remove it. It fixes a GPU hang on Navy Flounder. */
3254 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x00000020, 0x00000020),
3255 };
3256
3257 static const struct soc15_reg_golden golden_settings_gc_10_3_vangogh[] =
3258 {
3259 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100),
3260 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100),
3261 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4),
3262 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200),
3263 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3264 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000),
3265 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000142),
3266 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500),
3267 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4),
3268 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210),
3269 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210),
3270 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
3271 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
3272 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3273 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
3274 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3275 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3276 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000020),
3277 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1_Vangogh, 0xffffffff, 0x00070103),
3278 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x000017ff, 0x00001000),
3279 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0x00010000, 0x00010020),
3280 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3281 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00400000),
3282 SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000000ff),
3283
3284 /* This is not in GDB yet. Don't remove it. It fixes a GPU hang on VanGogh. */
3285 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x00000020, 0x00000020),
3286 };
3287
3288 static const struct soc15_reg_golden golden_settings_gc_10_3_3[] =
3289 {
3290 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3291 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4),
3292 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c200),
3293 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3294 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3295 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000242),
3296 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500),
3297 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4),
3298 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210),
3299 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210),
3300 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
3301 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
3302 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3303 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
3304 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020),
3305 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3306 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3307 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
3308 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3309 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00100000)
3310 };
3311
3312 static const struct soc15_reg_golden golden_settings_gc_10_3_4[] =
3313 {
3314 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100),
3315 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0x30000000, 0x30000100),
3316 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0x7e000000, 0x7e000100),
3317 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),
3318 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000280, 0x00000280),
3319 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07800000, 0x00800000),
3320 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x00001d00, 0x00000500),
3321 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003c0000, 0x00280400),
3322 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3323 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3324 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0x40000000, 0x580f1008),
3325 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0x00040000, 0x00f80988),
3326 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0x01000000, 0x01200007),
3327 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3328 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820),
3329 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0x0000001f, 0x00180070),
3330 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000),
3331 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000),
3332 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000),
3333 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000),
3334 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000),
3335 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000),
3336 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000),
3337 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000),
3338 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000),
3339 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000),
3340 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000),
3341 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000),
3342 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000),
3343 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),
3344 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),
3345 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),
3346 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0x00010000, 0x00010020),
3347 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0x01030000, 0x01030000),
3348 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x03a00000, 0x00a00000),
3349 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x00000020, 0x00000020)
3350 };
3351
3352 static const struct soc15_reg_golden golden_settings_gc_10_3_5[] = {
3353 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0x78000000, 0x78000100),
3354 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xb0000ff0, 0x30000100),
3355 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff000000, 0x7e000100),
3356 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),
3357 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3358 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3359 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500),
3360 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3361 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3362 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3363 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
3364 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020),
3365 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3366 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070),
3367 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000),
3368 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000),
3369 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000),
3370 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000),
3371 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000),
3372 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000),
3373 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000),
3374 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000),
3375 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000),
3376 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000),
3377 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000),
3378 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000),
3379 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000),
3380 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),
3381 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),
3382 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),
3383 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX,0xfff7ffff, 0x01030000),
3384 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000)
3385 };
3386
3387 static const struct soc15_reg_golden golden_settings_gc_10_0_cyan_skillfish[] = {
3388 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000),
3389 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_FAST_CLKS, 0x3fffffff, 0x0000493e),
3390 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 0xf8000100),
3391 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xff7f0fff, 0x3c000100),
3392 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_3, 0xa0000000, 0xa0000000),
3393 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0x00008000, 0x003c8014),
3394 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_DRAM_BURST_CTRL, 0x00000010, 0x00000017),
3395 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xd8d8d8d8),
3396 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000003, 0x00000003),
3397 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff),
3398 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000),
3399 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200),
3400 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04800000),
3401 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860210),
3402 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1800ff, 0x00000044),
3403 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x00009d00, 0x00008500),
3404 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCMC_VM_CACHEABLE_DRAM_ADDRESS_END, 0xffffffff, 0x000fffff),
3405 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_DRAM_BURST_CTRL, 0x00000010, 0x00000017),
3406 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xfcfcfcfc, 0xd8d8d8d8),
3407 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77707770, 0x21302130),
3408 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77707770, 0x21302130),
3409 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3410 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3411 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0x10000000, 0x10000100),
3412 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xfc02002f, 0x9402002f),
3413 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0x00002188, 0x00000188),
3414 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x08000009, 0x08000009),
3415 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_0, 0xcc3fcc03, 0x842a4c02),
3416 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000000f, 0x00000000),
3417 SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffff3109, 0xffff3101),
3418 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000100, 0x00000130),
3419 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
3420 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0x00030008, 0x01030000),
3421 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00800000, 0x00800000)
3422 };
3423
3424 static const struct soc15_reg_golden golden_settings_gc_10_3_6[] =
3425 {
3426 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3427 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x00000044),
3428 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c200),
3429 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3430 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3431 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000042),
3432 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500),
3433 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x00000044),
3434 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210),
3435 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210),
3436 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
3437 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
3438 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3439 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
3440 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020),
3441 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3442 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3443 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
3444 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x000017ff, 0x00001000),
3445 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0xffffff7f, 0x00010020),
3446 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3447 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00100000)
3448 };
3449
3450 static const struct soc15_reg_golden golden_settings_gc_10_3_7[] = {
3451 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3452 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0x000000ff, 0x000000e4),
3453 SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c200),
3454 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3455 SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3456 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0x0c1807ff, 0x00000041),
3457 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Vangogh, 0x1ff1ffff, 0x00000500),
3458 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0x000000ff, 0x000000e4),
3459 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x32103210),
3460 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x32103210),
3461 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffff),
3462 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffff),
3463 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3464 SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
3465 SOC15_REG_GOLDEN_VALUE(GC, 0, mmLDS_CONFIG, 0x000001ff, 0x00000020),
3466 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf000003f, 0x01200007),
3467 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3468 SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
3469 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQG_CONFIG, 0x000017ff, 0x00001000),
3470 SOC15_REG_GOLDEN_VALUE(GC, 0, mmSX_DEBUG_1, 0xffffff7f, 0x00010020),
3471 SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3472 SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00100000)
3473 };
3474
3475 #define DEFAULT_SH_MEM_CONFIG \
3476 ((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \
3477 (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \
3478 (SH_MEM_RETRY_MODE_ALL << SH_MEM_CONFIG__RETRY_MODE__SHIFT) | \
3479 (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT))
3480
3481 /* TODO: pending on golden setting value of gb address config */
3482 #define CYAN_SKILLFISH_GB_ADDR_CONFIG_GOLDEN 0x00100044
3483
3484 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev);
3485 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev);
3486 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev);
3487 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev);
3488 static void gfx_v10_0_set_mqd_funcs(struct amdgpu_device *adev);
3489 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev,
3490 struct amdgpu_cu_info *cu_info);
3491 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev);
3492 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
3493 u32 sh_num, u32 instance);
3494 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev);
3495
3496 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev);
3497 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev);
3498 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev);
3499 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev);
3500 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume);
3501 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume);
3502 static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, bool secure);
3503 static u32 gfx_v10_3_get_disabled_sa(struct amdgpu_device *adev);
3504 static void gfx_v10_3_program_pbb_mode(struct amdgpu_device *adev);
3505 static void gfx_v10_3_set_power_brake_sequence(struct amdgpu_device *adev);
3506 static void gfx_v10_0_ring_invalidate_tlbs(struct amdgpu_ring *ring,
3507 uint16_t pasid, uint32_t flush_type,
3508 bool all_hub, uint8_t dst_sel);
3509
gfx10_kiq_set_resources(struct amdgpu_ring * kiq_ring,uint64_t queue_mask)3510 static void gfx10_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t queue_mask)
3511 {
3512 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6));
3513 amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) |
3514 PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */
3515 amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */
3516 amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */
3517 amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */
3518 amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */
3519 amdgpu_ring_write(kiq_ring, 0); /* oac mask */
3520 amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */
3521 }
3522
gfx10_kiq_map_queues(struct amdgpu_ring * kiq_ring,struct amdgpu_ring * ring)3523 static void gfx10_kiq_map_queues(struct amdgpu_ring *kiq_ring,
3524 struct amdgpu_ring *ring)
3525 {
3526 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj);
3527 uint64_t wptr_addr = ring->wptr_gpu_addr;
3528 uint32_t eng_sel = 0;
3529
3530 switch (ring->funcs->type) {
3531 case AMDGPU_RING_TYPE_COMPUTE:
3532 eng_sel = 0;
3533 break;
3534 case AMDGPU_RING_TYPE_GFX:
3535 eng_sel = 4;
3536 break;
3537 case AMDGPU_RING_TYPE_MES:
3538 eng_sel = 5;
3539 break;
3540 default:
3541 WARN_ON(1);
3542 }
3543
3544 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));
3545 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/
3546 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
3547 PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */
3548 PACKET3_MAP_QUEUES_VMID(0) | /* VMID */
3549 PACKET3_MAP_QUEUES_QUEUE(ring->queue) |
3550 PACKET3_MAP_QUEUES_PIPE(ring->pipe) |
3551 PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) |
3552 PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */
3553 PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */
3554 PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) |
3555 PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */
3556 amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index));
3557 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr));
3558 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr));
3559 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr));
3560 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr));
3561 }
3562
gfx10_kiq_unmap_queues(struct amdgpu_ring * kiq_ring,struct amdgpu_ring * ring,enum amdgpu_unmap_queues_action action,u64 gpu_addr,u64 seq)3563 static void gfx10_kiq_unmap_queues(struct amdgpu_ring *kiq_ring,
3564 struct amdgpu_ring *ring,
3565 enum amdgpu_unmap_queues_action action,
3566 u64 gpu_addr, u64 seq)
3567 {
3568 struct amdgpu_device *adev = kiq_ring->adev;
3569 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
3570
3571 if (adev->enable_mes && !adev->gfx.kiq.ring.sched.ready) {
3572 amdgpu_mes_unmap_legacy_queue(adev, ring, action, gpu_addr, seq);
3573 return;
3574 }
3575
3576 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4));
3577 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
3578 PACKET3_UNMAP_QUEUES_ACTION(action) |
3579 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) |
3580 PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) |
3581 PACKET3_UNMAP_QUEUES_NUM_QUEUES(1));
3582 amdgpu_ring_write(kiq_ring,
3583 PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index));
3584
3585 if (action == PREEMPT_QUEUES_NO_UNMAP) {
3586 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr));
3587 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr));
3588 amdgpu_ring_write(kiq_ring, seq);
3589 } else {
3590 amdgpu_ring_write(kiq_ring, 0);
3591 amdgpu_ring_write(kiq_ring, 0);
3592 amdgpu_ring_write(kiq_ring, 0);
3593 }
3594 }
3595
gfx10_kiq_query_status(struct amdgpu_ring * kiq_ring,struct amdgpu_ring * ring,u64 addr,u64 seq)3596 static void gfx10_kiq_query_status(struct amdgpu_ring *kiq_ring,
3597 struct amdgpu_ring *ring,
3598 u64 addr,
3599 u64 seq)
3600 {
3601 uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
3602
3603 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5));
3604 amdgpu_ring_write(kiq_ring,
3605 PACKET3_QUERY_STATUS_CONTEXT_ID(0) |
3606 PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) |
3607 PACKET3_QUERY_STATUS_COMMAND(2));
3608 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
3609 PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) |
3610 PACKET3_QUERY_STATUS_ENG_SEL(eng_sel));
3611 amdgpu_ring_write(kiq_ring, lower_32_bits(addr));
3612 amdgpu_ring_write(kiq_ring, upper_32_bits(addr));
3613 amdgpu_ring_write(kiq_ring, lower_32_bits(seq));
3614 amdgpu_ring_write(kiq_ring, upper_32_bits(seq));
3615 }
3616
gfx10_kiq_invalidate_tlbs(struct amdgpu_ring * kiq_ring,uint16_t pasid,uint32_t flush_type,bool all_hub)3617 static void gfx10_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring,
3618 uint16_t pasid, uint32_t flush_type,
3619 bool all_hub)
3620 {
3621 gfx_v10_0_ring_invalidate_tlbs(kiq_ring, pasid, flush_type, all_hub, 1);
3622 }
3623
3624 static const struct kiq_pm4_funcs gfx_v10_0_kiq_pm4_funcs = {
3625 .kiq_set_resources = gfx10_kiq_set_resources,
3626 .kiq_map_queues = gfx10_kiq_map_queues,
3627 .kiq_unmap_queues = gfx10_kiq_unmap_queues,
3628 .kiq_query_status = gfx10_kiq_query_status,
3629 .kiq_invalidate_tlbs = gfx10_kiq_invalidate_tlbs,
3630 .set_resources_size = 8,
3631 .map_queues_size = 7,
3632 .unmap_queues_size = 6,
3633 .query_status_size = 7,
3634 .invalidate_tlbs_size = 2,
3635 };
3636
gfx_v10_0_set_kiq_pm4_funcs(struct amdgpu_device * adev)3637 static void gfx_v10_0_set_kiq_pm4_funcs(struct amdgpu_device *adev)
3638 {
3639 adev->gfx.kiq.pmf = &gfx_v10_0_kiq_pm4_funcs;
3640 }
3641
gfx_v10_0_init_spm_golden_registers(struct amdgpu_device * adev)3642 static void gfx_v10_0_init_spm_golden_registers(struct amdgpu_device *adev)
3643 {
3644 switch (adev->ip_versions[GC_HWIP][0]) {
3645 case IP_VERSION(10, 1, 10):
3646 soc15_program_register_sequence(adev,
3647 golden_settings_gc_rlc_spm_10_0_nv10,
3648 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_0_nv10));
3649 break;
3650 case IP_VERSION(10, 1, 1):
3651 soc15_program_register_sequence(adev,
3652 golden_settings_gc_rlc_spm_10_1_nv14,
3653 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_nv14));
3654 break;
3655 case IP_VERSION(10, 1, 2):
3656 soc15_program_register_sequence(adev,
3657 golden_settings_gc_rlc_spm_10_1_2_nv12,
3658 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_2_nv12));
3659 break;
3660 default:
3661 break;
3662 }
3663 }
3664
gfx_v10_0_init_golden_registers(struct amdgpu_device * adev)3665 static void gfx_v10_0_init_golden_registers(struct amdgpu_device *adev)
3666 {
3667 switch (adev->ip_versions[GC_HWIP][0]) {
3668 case IP_VERSION(10, 1, 10):
3669 soc15_program_register_sequence(adev,
3670 golden_settings_gc_10_1,
3671 (const u32)ARRAY_SIZE(golden_settings_gc_10_1));
3672 soc15_program_register_sequence(adev,
3673 golden_settings_gc_10_0_nv10,
3674 (const u32)ARRAY_SIZE(golden_settings_gc_10_0_nv10));
3675 break;
3676 case IP_VERSION(10, 1, 1):
3677 soc15_program_register_sequence(adev,
3678 golden_settings_gc_10_1_1,
3679 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_1));
3680 soc15_program_register_sequence(adev,
3681 golden_settings_gc_10_1_nv14,
3682 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_nv14));
3683 break;
3684 case IP_VERSION(10, 1, 2):
3685 soc15_program_register_sequence(adev,
3686 golden_settings_gc_10_1_2,
3687 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2));
3688 soc15_program_register_sequence(adev,
3689 golden_settings_gc_10_1_2_nv12,
3690 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2_nv12));
3691 break;
3692 case IP_VERSION(10, 3, 0):
3693 soc15_program_register_sequence(adev,
3694 golden_settings_gc_10_3,
3695 (const u32)ARRAY_SIZE(golden_settings_gc_10_3));
3696 soc15_program_register_sequence(adev,
3697 golden_settings_gc_10_3_sienna_cichlid,
3698 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_sienna_cichlid));
3699 break;
3700 case IP_VERSION(10, 3, 2):
3701 soc15_program_register_sequence(adev,
3702 golden_settings_gc_10_3_2,
3703 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_2));
3704 break;
3705 case IP_VERSION(10, 3, 1):
3706 soc15_program_register_sequence(adev,
3707 golden_settings_gc_10_3_vangogh,
3708 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_vangogh));
3709 break;
3710 case IP_VERSION(10, 3, 3):
3711 soc15_program_register_sequence(adev,
3712 golden_settings_gc_10_3_3,
3713 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_3));
3714 break;
3715 case IP_VERSION(10, 3, 4):
3716 soc15_program_register_sequence(adev,
3717 golden_settings_gc_10_3_4,
3718 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_4));
3719 break;
3720 case IP_VERSION(10, 3, 5):
3721 soc15_program_register_sequence(adev,
3722 golden_settings_gc_10_3_5,
3723 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_5));
3724 break;
3725 case IP_VERSION(10, 1, 3):
3726 case IP_VERSION(10, 1, 4):
3727 soc15_program_register_sequence(adev,
3728 golden_settings_gc_10_0_cyan_skillfish,
3729 (const u32)ARRAY_SIZE(golden_settings_gc_10_0_cyan_skillfish));
3730 break;
3731 case IP_VERSION(10, 3, 6):
3732 soc15_program_register_sequence(adev,
3733 golden_settings_gc_10_3_6,
3734 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_6));
3735 break;
3736 case IP_VERSION(10, 3, 7):
3737 soc15_program_register_sequence(adev,
3738 golden_settings_gc_10_3_7,
3739 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_7));
3740 break;
3741 default:
3742 break;
3743 }
3744 gfx_v10_0_init_spm_golden_registers(adev);
3745 }
3746
gfx_v10_0_write_data_to_reg(struct amdgpu_ring * ring,int eng_sel,bool wc,uint32_t reg,uint32_t val)3747 static void gfx_v10_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel,
3748 bool wc, uint32_t reg, uint32_t val)
3749 {
3750 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3751 amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) |
3752 WRITE_DATA_DST_SEL(0) | (wc ? WR_CONFIRM : 0));
3753 amdgpu_ring_write(ring, reg);
3754 amdgpu_ring_write(ring, 0);
3755 amdgpu_ring_write(ring, val);
3756 }
3757
gfx_v10_0_wait_reg_mem(struct amdgpu_ring * ring,int eng_sel,int mem_space,int opt,uint32_t addr0,uint32_t addr1,uint32_t ref,uint32_t mask,uint32_t inv)3758 static void gfx_v10_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel,
3759 int mem_space, int opt, uint32_t addr0,
3760 uint32_t addr1, uint32_t ref, uint32_t mask,
3761 uint32_t inv)
3762 {
3763 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
3764 amdgpu_ring_write(ring,
3765 /* memory (1) or register (0) */
3766 (WAIT_REG_MEM_MEM_SPACE(mem_space) |
3767 WAIT_REG_MEM_OPERATION(opt) | /* wait */
3768 WAIT_REG_MEM_FUNCTION(3) | /* equal */
3769 WAIT_REG_MEM_ENGINE(eng_sel)));
3770
3771 if (mem_space)
3772 BUG_ON(addr0 & 0x3); /* Dword align */
3773 amdgpu_ring_write(ring, addr0);
3774 amdgpu_ring_write(ring, addr1);
3775 amdgpu_ring_write(ring, ref);
3776 amdgpu_ring_write(ring, mask);
3777 amdgpu_ring_write(ring, inv); /* poll interval */
3778 }
3779
gfx_v10_0_ring_test_ring(struct amdgpu_ring * ring)3780 static int gfx_v10_0_ring_test_ring(struct amdgpu_ring *ring)
3781 {
3782 struct amdgpu_device *adev = ring->adev;
3783 uint32_t scratch = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0);
3784 uint32_t tmp = 0;
3785 unsigned i;
3786 int r;
3787
3788 WREG32(scratch, 0xCAFEDEAD);
3789 r = amdgpu_ring_alloc(ring, 3);
3790 if (r) {
3791 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
3792 ring->idx, r);
3793 return r;
3794 }
3795
3796 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
3797 amdgpu_ring_write(ring, scratch -
3798 PACKET3_SET_UCONFIG_REG_START);
3799 amdgpu_ring_write(ring, 0xDEADBEEF);
3800 amdgpu_ring_commit(ring);
3801
3802 for (i = 0; i < adev->usec_timeout; i++) {
3803 tmp = RREG32(scratch);
3804 if (tmp == 0xDEADBEEF)
3805 break;
3806 if (amdgpu_emu_mode == 1)
3807 msleep(1);
3808 else
3809 udelay(1);
3810 }
3811
3812 if (i >= adev->usec_timeout)
3813 r = -ETIMEDOUT;
3814
3815 return r;
3816 }
3817
gfx_v10_0_ring_test_ib(struct amdgpu_ring * ring,long timeout)3818 static int gfx_v10_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
3819 {
3820 struct amdgpu_device *adev = ring->adev;
3821 struct amdgpu_ib ib;
3822 struct dma_fence *f = NULL;
3823 unsigned index;
3824 uint64_t gpu_addr;
3825 volatile uint32_t *cpu_ptr;
3826 long r;
3827
3828 memset(&ib, 0, sizeof(ib));
3829
3830 if (ring->is_mes_queue) {
3831 uint32_t padding, offset;
3832
3833 offset = amdgpu_mes_ctx_get_offs(ring, AMDGPU_MES_CTX_IB_OFFS);
3834 padding = amdgpu_mes_ctx_get_offs(ring,
3835 AMDGPU_MES_CTX_PADDING_OFFS);
3836
3837 ib.gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
3838 ib.ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);
3839
3840 gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, padding);
3841 cpu_ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, padding);
3842 *cpu_ptr = cpu_to_le32(0xCAFEDEAD);
3843 } else {
3844 r = amdgpu_device_wb_get(adev, &index);
3845 if (r)
3846 return r;
3847
3848 gpu_addr = adev->wb.gpu_addr + (index * 4);
3849 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD);
3850 cpu_ptr = &adev->wb.wb[index];
3851
3852 r = amdgpu_ib_get(adev, NULL, 20, AMDGPU_IB_POOL_DIRECT, &ib);
3853 if (r) {
3854 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
3855 goto err1;
3856 }
3857 }
3858
3859 ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3);
3860 ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM;
3861 ib.ptr[2] = lower_32_bits(gpu_addr);
3862 ib.ptr[3] = upper_32_bits(gpu_addr);
3863 ib.ptr[4] = 0xDEADBEEF;
3864 ib.length_dw = 5;
3865
3866 r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
3867 if (r)
3868 goto err2;
3869
3870 r = dma_fence_wait_timeout(f, false, timeout);
3871 if (r == 0) {
3872 r = -ETIMEDOUT;
3873 goto err2;
3874 } else if (r < 0) {
3875 goto err2;
3876 }
3877
3878 if (le32_to_cpu(*cpu_ptr) == 0xDEADBEEF)
3879 r = 0;
3880 else
3881 r = -EINVAL;
3882 err2:
3883 if (!ring->is_mes_queue)
3884 amdgpu_ib_free(adev, &ib, NULL);
3885 dma_fence_put(f);
3886 err1:
3887 if (!ring->is_mes_queue)
3888 amdgpu_device_wb_free(adev, index);
3889 return r;
3890 }
3891
gfx_v10_0_free_microcode(struct amdgpu_device * adev)3892 static void gfx_v10_0_free_microcode(struct amdgpu_device *adev)
3893 {
3894 release_firmware(adev->gfx.pfp_fw);
3895 adev->gfx.pfp_fw = NULL;
3896 release_firmware(adev->gfx.me_fw);
3897 adev->gfx.me_fw = NULL;
3898 release_firmware(adev->gfx.ce_fw);
3899 adev->gfx.ce_fw = NULL;
3900 release_firmware(adev->gfx.rlc_fw);
3901 adev->gfx.rlc_fw = NULL;
3902 release_firmware(adev->gfx.mec_fw);
3903 adev->gfx.mec_fw = NULL;
3904 release_firmware(adev->gfx.mec2_fw);
3905 adev->gfx.mec2_fw = NULL;
3906
3907 kfree(adev->gfx.rlc.register_list_format);
3908 }
3909
gfx_v10_0_check_fw_write_wait(struct amdgpu_device * adev)3910 static void gfx_v10_0_check_fw_write_wait(struct amdgpu_device *adev)
3911 {
3912 adev->gfx.cp_fw_write_wait = false;
3913
3914 switch (adev->ip_versions[GC_HWIP][0]) {
3915 case IP_VERSION(10, 1, 10):
3916 case IP_VERSION(10, 1, 2):
3917 case IP_VERSION(10, 1, 1):
3918 case IP_VERSION(10, 1, 3):
3919 case IP_VERSION(10, 1, 4):
3920 if ((adev->gfx.me_fw_version >= 0x00000046) &&
3921 (adev->gfx.me_feature_version >= 27) &&
3922 (adev->gfx.pfp_fw_version >= 0x00000068) &&
3923 (adev->gfx.pfp_feature_version >= 27) &&
3924 (adev->gfx.mec_fw_version >= 0x0000005b) &&
3925 (adev->gfx.mec_feature_version >= 27))
3926 adev->gfx.cp_fw_write_wait = true;
3927 break;
3928 case IP_VERSION(10, 3, 0):
3929 case IP_VERSION(10, 3, 2):
3930 case IP_VERSION(10, 3, 1):
3931 case IP_VERSION(10, 3, 4):
3932 case IP_VERSION(10, 3, 5):
3933 case IP_VERSION(10, 3, 6):
3934 case IP_VERSION(10, 3, 3):
3935 case IP_VERSION(10, 3, 7):
3936 adev->gfx.cp_fw_write_wait = true;
3937 break;
3938 default:
3939 break;
3940 }
3941
3942 if (!adev->gfx.cp_fw_write_wait)
3943 DRM_WARN_ONCE("CP firmware version too old, please update!");
3944 }
3945
gfx_v10_0_navi10_gfxoff_should_enable(struct amdgpu_device * adev)3946 static bool gfx_v10_0_navi10_gfxoff_should_enable(struct amdgpu_device *adev)
3947 {
3948 bool ret = false;
3949
3950 switch (adev->pdev->revision) {
3951 case 0xc2:
3952 case 0xc3:
3953 ret = true;
3954 break;
3955 default:
3956 ret = false;
3957 break;
3958 }
3959
3960 return ret ;
3961 }
3962
gfx_v10_0_check_gfxoff_flag(struct amdgpu_device * adev)3963 static void gfx_v10_0_check_gfxoff_flag(struct amdgpu_device *adev)
3964 {
3965 switch (adev->ip_versions[GC_HWIP][0]) {
3966 case IP_VERSION(10, 1, 10):
3967 if (!gfx_v10_0_navi10_gfxoff_should_enable(adev))
3968 adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
3969 break;
3970 default:
3971 break;
3972 }
3973 }
3974
gfx_v10_0_init_microcode(struct amdgpu_device * adev)3975 static int gfx_v10_0_init_microcode(struct amdgpu_device *adev)
3976 {
3977 const char *chip_name;
3978 char fw_name[40];
3979 char *wks = "";
3980 int err;
3981 const struct rlc_firmware_header_v2_0 *rlc_hdr;
3982 uint16_t version_major;
3983 uint16_t version_minor;
3984
3985 DRM_DEBUG("\n");
3986
3987 switch (adev->ip_versions[GC_HWIP][0]) {
3988 case IP_VERSION(10, 1, 10):
3989 chip_name = "navi10";
3990 break;
3991 case IP_VERSION(10, 1, 1):
3992 chip_name = "navi14";
3993 if (!(adev->pdev->device == 0x7340 &&
3994 adev->pdev->revision != 0x00))
3995 wks = "_wks";
3996 break;
3997 case IP_VERSION(10, 1, 2):
3998 chip_name = "navi12";
3999 break;
4000 case IP_VERSION(10, 3, 0):
4001 chip_name = "sienna_cichlid";
4002 break;
4003 case IP_VERSION(10, 3, 2):
4004 chip_name = "navy_flounder";
4005 break;
4006 case IP_VERSION(10, 3, 1):
4007 chip_name = "vangogh";
4008 break;
4009 case IP_VERSION(10, 3, 4):
4010 chip_name = "dimgrey_cavefish";
4011 break;
4012 case IP_VERSION(10, 3, 5):
4013 chip_name = "beige_goby";
4014 break;
4015 case IP_VERSION(10, 3, 3):
4016 chip_name = "yellow_carp";
4017 break;
4018 case IP_VERSION(10, 3, 6):
4019 chip_name = "gc_10_3_6";
4020 break;
4021 case IP_VERSION(10, 1, 3):
4022 case IP_VERSION(10, 1, 4):
4023 chip_name = "cyan_skillfish2";
4024 break;
4025 case IP_VERSION(10, 3, 7):
4026 chip_name = "gc_10_3_7";
4027 break;
4028 default:
4029 BUG();
4030 }
4031
4032 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp%s.bin", chip_name, wks);
4033 err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
4034 if (err)
4035 goto out;
4036 err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
4037 if (err)
4038 goto out;
4039 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_PFP);
4040
4041 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me%s.bin", chip_name, wks);
4042 err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
4043 if (err)
4044 goto out;
4045 err = amdgpu_ucode_validate(adev->gfx.me_fw);
4046 if (err)
4047 goto out;
4048 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_ME);
4049
4050 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce%s.bin", chip_name, wks);
4051 err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
4052 if (err)
4053 goto out;
4054 err = amdgpu_ucode_validate(adev->gfx.ce_fw);
4055 if (err)
4056 goto out;
4057 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_CE);
4058
4059 if (!amdgpu_sriov_vf(adev)) {
4060 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name);
4061 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
4062 if (err)
4063 goto out;
4064 /* don't check this. There are apparently firmwares in the wild with
4065 * incorrect size in the header
4066 */
4067 err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
4068 if (err)
4069 dev_dbg(adev->dev,
4070 "gfx10: amdgpu_ucode_validate() failed \"%s\"\n",
4071 fw_name);
4072 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
4073 version_major = le16_to_cpu(rlc_hdr->header.header_version_major);
4074 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor);
4075 err = amdgpu_gfx_rlc_init_microcode(adev, version_major, version_minor);
4076 if (err)
4077 goto out;
4078 }
4079
4080 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec%s.bin", chip_name, wks);
4081 err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
4082 if (err)
4083 goto out;
4084 err = amdgpu_ucode_validate(adev->gfx.mec_fw);
4085 if (err)
4086 goto out;
4087 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1);
4088 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1_JT);
4089
4090 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2%s.bin", chip_name, wks);
4091 err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
4092 if (!err) {
4093 err = amdgpu_ucode_validate(adev->gfx.mec2_fw);
4094 if (err)
4095 goto out;
4096 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC2);
4097 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC2_JT);
4098 } else {
4099 err = 0;
4100 adev->gfx.mec2_fw = NULL;
4101 }
4102
4103 gfx_v10_0_check_fw_write_wait(adev);
4104 out:
4105 if (err) {
4106 dev_err(adev->dev,
4107 "gfx10: Failed to init firmware \"%s\"\n",
4108 fw_name);
4109 release_firmware(adev->gfx.pfp_fw);
4110 adev->gfx.pfp_fw = NULL;
4111 release_firmware(adev->gfx.me_fw);
4112 adev->gfx.me_fw = NULL;
4113 release_firmware(adev->gfx.ce_fw);
4114 adev->gfx.ce_fw = NULL;
4115 release_firmware(adev->gfx.rlc_fw);
4116 adev->gfx.rlc_fw = NULL;
4117 release_firmware(adev->gfx.mec_fw);
4118 adev->gfx.mec_fw = NULL;
4119 release_firmware(adev->gfx.mec2_fw);
4120 adev->gfx.mec2_fw = NULL;
4121 }
4122
4123 gfx_v10_0_check_gfxoff_flag(adev);
4124
4125 return err;
4126 }
4127
gfx_v10_0_get_csb_size(struct amdgpu_device * adev)4128 static u32 gfx_v10_0_get_csb_size(struct amdgpu_device *adev)
4129 {
4130 u32 count = 0;
4131 const struct cs_section_def *sect = NULL;
4132 const struct cs_extent_def *ext = NULL;
4133
4134 /* begin clear state */
4135 count += 2;
4136 /* context control state */
4137 count += 3;
4138
4139 for (sect = gfx10_cs_data; sect->section != NULL; ++sect) {
4140 for (ext = sect->section; ext->extent != NULL; ++ext) {
4141 if (sect->id == SECT_CONTEXT)
4142 count += 2 + ext->reg_count;
4143 else
4144 return 0;
4145 }
4146 }
4147
4148 /* set PA_SC_TILE_STEERING_OVERRIDE */
4149 count += 3;
4150 /* end clear state */
4151 count += 2;
4152 /* clear state */
4153 count += 2;
4154
4155 return count;
4156 }
4157
gfx_v10_0_get_csb_buffer(struct amdgpu_device * adev,volatile u32 * buffer)4158 static void gfx_v10_0_get_csb_buffer(struct amdgpu_device *adev,
4159 volatile u32 *buffer)
4160 {
4161 u32 count = 0, i;
4162 const struct cs_section_def *sect = NULL;
4163 const struct cs_extent_def *ext = NULL;
4164 int ctx_reg_offset;
4165
4166 if (adev->gfx.rlc.cs_data == NULL)
4167 return;
4168 if (buffer == NULL)
4169 return;
4170
4171 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
4172 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
4173
4174 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
4175 buffer[count++] = cpu_to_le32(0x80000000);
4176 buffer[count++] = cpu_to_le32(0x80000000);
4177
4178 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
4179 for (ext = sect->section; ext->extent != NULL; ++ext) {
4180 if (sect->id == SECT_CONTEXT) {
4181 buffer[count++] =
4182 cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
4183 buffer[count++] = cpu_to_le32(ext->reg_index -
4184 PACKET3_SET_CONTEXT_REG_START);
4185 for (i = 0; i < ext->reg_count; i++)
4186 buffer[count++] = cpu_to_le32(ext->extent[i]);
4187 } else {
4188 return;
4189 }
4190 }
4191 }
4192
4193 ctx_reg_offset =
4194 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START;
4195 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1));
4196 buffer[count++] = cpu_to_le32(ctx_reg_offset);
4197 buffer[count++] = cpu_to_le32(adev->gfx.config.pa_sc_tile_steering_override);
4198
4199 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
4200 buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
4201
4202 buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
4203 buffer[count++] = cpu_to_le32(0);
4204 }
4205
gfx_v10_0_rlc_fini(struct amdgpu_device * adev)4206 static void gfx_v10_0_rlc_fini(struct amdgpu_device *adev)
4207 {
4208 /* clear state block */
4209 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj,
4210 &adev->gfx.rlc.clear_state_gpu_addr,
4211 (void **)&adev->gfx.rlc.cs_ptr);
4212
4213 /* jump table block */
4214 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
4215 &adev->gfx.rlc.cp_table_gpu_addr,
4216 (void **)&adev->gfx.rlc.cp_table_ptr);
4217 }
4218
gfx_v10_0_init_rlcg_reg_access_ctrl(struct amdgpu_device * adev)4219 static void gfx_v10_0_init_rlcg_reg_access_ctrl(struct amdgpu_device *adev)
4220 {
4221 struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl;
4222
4223 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl;
4224 reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0);
4225 reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG1);
4226 reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG2);
4227 reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG3);
4228 reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_CNTL);
4229 reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, 0, mmGRBM_GFX_INDEX);
4230 switch (adev->ip_versions[GC_HWIP][0]) {
4231 case IP_VERSION(10, 3, 0):
4232 reg_access_ctrl->spare_int =
4233 SOC15_REG_OFFSET(GC, 0, mmRLC_SPARE_INT_0_Sienna_Cichlid);
4234 break;
4235 default:
4236 reg_access_ctrl->spare_int =
4237 SOC15_REG_OFFSET(GC, 0, mmRLC_SPARE_INT);
4238 break;
4239 }
4240 adev->gfx.rlc.rlcg_reg_access_supported = true;
4241 }
4242
gfx_v10_0_rlc_init(struct amdgpu_device * adev)4243 static int gfx_v10_0_rlc_init(struct amdgpu_device *adev)
4244 {
4245 const struct cs_section_def *cs_data;
4246 int r;
4247
4248 adev->gfx.rlc.cs_data = gfx10_cs_data;
4249
4250 cs_data = adev->gfx.rlc.cs_data;
4251
4252 if (cs_data) {
4253 /* init clear state block */
4254 r = amdgpu_gfx_rlc_init_csb(adev);
4255 if (r)
4256 return r;
4257 }
4258
4259 /* init spm vmid with 0xf */
4260 if (adev->gfx.rlc.funcs->update_spm_vmid)
4261 adev->gfx.rlc.funcs->update_spm_vmid(adev, 0xf);
4262
4263
4264 return 0;
4265 }
4266
gfx_v10_0_mec_fini(struct amdgpu_device * adev)4267 static void gfx_v10_0_mec_fini(struct amdgpu_device *adev)
4268 {
4269 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL);
4270 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL);
4271 }
4272
gfx_v10_0_me_init(struct amdgpu_device * adev)4273 static int gfx_v10_0_me_init(struct amdgpu_device *adev)
4274 {
4275 int r;
4276
4277 bitmap_zero(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES);
4278
4279 amdgpu_gfx_graphics_queue_acquire(adev);
4280
4281 r = gfx_v10_0_init_microcode(adev);
4282 if (r)
4283 DRM_ERROR("Failed to load gfx firmware!\n");
4284
4285 return r;
4286 }
4287
gfx_v10_0_mec_init(struct amdgpu_device * adev)4288 static int gfx_v10_0_mec_init(struct amdgpu_device *adev)
4289 {
4290 int r;
4291 u32 *hpd;
4292 const __le32 *fw_data = NULL;
4293 unsigned fw_size;
4294 u32 *fw = NULL;
4295 size_t mec_hpd_size;
4296
4297 const struct gfx_firmware_header_v1_0 *mec_hdr = NULL;
4298
4299 bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
4300
4301 /* take ownership of the relevant compute queues */
4302 amdgpu_gfx_compute_queue_acquire(adev);
4303 mec_hpd_size = adev->gfx.num_compute_rings * GFX10_MEC_HPD_SIZE;
4304
4305 if (mec_hpd_size) {
4306 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE,
4307 AMDGPU_GEM_DOMAIN_GTT,
4308 &adev->gfx.mec.hpd_eop_obj,
4309 &adev->gfx.mec.hpd_eop_gpu_addr,
4310 (void **)&hpd);
4311 if (r) {
4312 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
4313 gfx_v10_0_mec_fini(adev);
4314 return r;
4315 }
4316
4317 memset(hpd, 0, mec_hpd_size);
4318
4319 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
4320 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
4321 }
4322
4323 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
4324 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
4325
4326 fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
4327 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
4328 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes);
4329
4330 r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes,
4331 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
4332 &adev->gfx.mec.mec_fw_obj,
4333 &adev->gfx.mec.mec_fw_gpu_addr,
4334 (void **)&fw);
4335 if (r) {
4336 dev_err(adev->dev, "(%d) failed to create mec fw bo\n", r);
4337 gfx_v10_0_mec_fini(adev);
4338 return r;
4339 }
4340
4341 memcpy(fw, fw_data, fw_size);
4342
4343 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj);
4344 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj);
4345 }
4346
4347 return 0;
4348 }
4349
wave_read_ind(struct amdgpu_device * adev,uint32_t wave,uint32_t address)4350 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address)
4351 {
4352 WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
4353 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
4354 (address << SQ_IND_INDEX__INDEX__SHIFT));
4355 return RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
4356 }
4357
wave_read_regs(struct amdgpu_device * adev,uint32_t wave,uint32_t thread,uint32_t regno,uint32_t num,uint32_t * out)4358 static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave,
4359 uint32_t thread, uint32_t regno,
4360 uint32_t num, uint32_t *out)
4361 {
4362 WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
4363 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
4364 (regno << SQ_IND_INDEX__INDEX__SHIFT) |
4365 (thread << SQ_IND_INDEX__WORKITEM_ID__SHIFT) |
4366 (SQ_IND_INDEX__AUTO_INCR_MASK));
4367 while (num--)
4368 *(out++) = RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
4369 }
4370
gfx_v10_0_read_wave_data(struct amdgpu_device * adev,uint32_t simd,uint32_t wave,uint32_t * dst,int * no_fields)4371 static void gfx_v10_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)
4372 {
4373 /* in gfx10 the SIMD_ID is specified as part of the INSTANCE
4374 * field when performing a select_se_sh so it should be
4375 * zero here */
4376 WARN_ON(simd != 0);
4377
4378 /* type 2 wave data */
4379 dst[(*no_fields)++] = 2;
4380 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS);
4381 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO);
4382 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI);
4383 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO);
4384 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI);
4385 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID1);
4386 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID2);
4387 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_INST_DW0);
4388 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_GPR_ALLOC);
4389 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_LDS_ALLOC);
4390 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_TRAPSTS);
4391 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS);
4392 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS2);
4393 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG1);
4394 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_M0);
4395 dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_MODE);
4396 }
4397
gfx_v10_0_read_wave_sgprs(struct amdgpu_device * adev,uint32_t simd,uint32_t wave,uint32_t start,uint32_t size,uint32_t * dst)4398 static void gfx_v10_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd,
4399 uint32_t wave, uint32_t start,
4400 uint32_t size, uint32_t *dst)
4401 {
4402 WARN_ON(simd != 0);
4403
4404 wave_read_regs(
4405 adev, wave, 0, start + SQIND_WAVE_SGPRS_OFFSET, size,
4406 dst);
4407 }
4408
gfx_v10_0_read_wave_vgprs(struct amdgpu_device * adev,uint32_t simd,uint32_t wave,uint32_t thread,uint32_t start,uint32_t size,uint32_t * dst)4409 static void gfx_v10_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t simd,
4410 uint32_t wave, uint32_t thread,
4411 uint32_t start, uint32_t size,
4412 uint32_t *dst)
4413 {
4414 wave_read_regs(
4415 adev, wave, thread,
4416 start + SQIND_WAVE_VGPRS_OFFSET, size, dst);
4417 }
4418
gfx_v10_0_select_me_pipe_q(struct amdgpu_device * adev,u32 me,u32 pipe,u32 q,u32 vm)4419 static void gfx_v10_0_select_me_pipe_q(struct amdgpu_device *adev,
4420 u32 me, u32 pipe, u32 q, u32 vm)
4421 {
4422 nv_grbm_select(adev, me, pipe, q, vm);
4423 }
4424
gfx_v10_0_update_perfmon_mgcg(struct amdgpu_device * adev,bool enable)4425 static void gfx_v10_0_update_perfmon_mgcg(struct amdgpu_device *adev,
4426 bool enable)
4427 {
4428 uint32_t data, def;
4429
4430 data = def = RREG32_SOC15(GC, 0, mmRLC_PERFMON_CLK_CNTL);
4431
4432 if (enable)
4433 data |= RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK;
4434 else
4435 data &= ~RLC_PERFMON_CLK_CNTL__PERFMON_CLOCK_STATE_MASK;
4436
4437 if (data != def)
4438 WREG32_SOC15(GC, 0, mmRLC_PERFMON_CLK_CNTL, data);
4439 }
4440
4441 static const struct amdgpu_gfx_funcs gfx_v10_0_gfx_funcs = {
4442 .get_gpu_clock_counter = &gfx_v10_0_get_gpu_clock_counter,
4443 .select_se_sh = &gfx_v10_0_select_se_sh,
4444 .read_wave_data = &gfx_v10_0_read_wave_data,
4445 .read_wave_sgprs = &gfx_v10_0_read_wave_sgprs,
4446 .read_wave_vgprs = &gfx_v10_0_read_wave_vgprs,
4447 .select_me_pipe_q = &gfx_v10_0_select_me_pipe_q,
4448 .init_spm_golden = &gfx_v10_0_init_spm_golden_registers,
4449 .update_perfmon_mgcg = &gfx_v10_0_update_perfmon_mgcg,
4450 };
4451
gfx_v10_0_gpu_early_init(struct amdgpu_device * adev)4452 static void gfx_v10_0_gpu_early_init(struct amdgpu_device *adev)
4453 {
4454 u32 gb_addr_config;
4455
4456 adev->gfx.funcs = &gfx_v10_0_gfx_funcs;
4457
4458 switch (adev->ip_versions[GC_HWIP][0]) {
4459 case IP_VERSION(10, 1, 10):
4460 case IP_VERSION(10, 1, 1):
4461 case IP_VERSION(10, 1, 2):
4462 adev->gfx.config.max_hw_contexts = 8;
4463 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4464 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4465 adev->gfx.config.sc_hiz_tile_fifo_size = 0;
4466 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
4467 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);
4468 break;
4469 case IP_VERSION(10, 3, 0):
4470 case IP_VERSION(10, 3, 2):
4471 case IP_VERSION(10, 3, 1):
4472 case IP_VERSION(10, 3, 4):
4473 case IP_VERSION(10, 3, 5):
4474 case IP_VERSION(10, 3, 6):
4475 case IP_VERSION(10, 3, 3):
4476 case IP_VERSION(10, 3, 7):
4477 adev->gfx.config.max_hw_contexts = 8;
4478 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4479 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4480 adev->gfx.config.sc_hiz_tile_fifo_size = 0;
4481 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
4482 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);
4483 adev->gfx.config.gb_addr_config_fields.num_pkrs =
4484 1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PKRS);
4485 break;
4486 case IP_VERSION(10, 1, 3):
4487 case IP_VERSION(10, 1, 4):
4488 adev->gfx.config.max_hw_contexts = 8;
4489 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4490 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4491 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
4492 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
4493 gb_addr_config = CYAN_SKILLFISH_GB_ADDR_CONFIG_GOLDEN;
4494 break;
4495 default:
4496 BUG();
4497 break;
4498 }
4499
4500 adev->gfx.config.gb_addr_config = gb_addr_config;
4501
4502 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 <<
4503 REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4504 GB_ADDR_CONFIG, NUM_PIPES);
4505
4506 adev->gfx.config.max_tile_pipes =
4507 adev->gfx.config.gb_addr_config_fields.num_pipes;
4508
4509 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 <<
4510 REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4511 GB_ADDR_CONFIG, MAX_COMPRESSED_FRAGS);
4512 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 <<
4513 REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4514 GB_ADDR_CONFIG, NUM_RB_PER_SE);
4515 adev->gfx.config.gb_addr_config_fields.num_se = 1 <<
4516 REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4517 GB_ADDR_CONFIG, NUM_SHADER_ENGINES);
4518 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 +
4519 REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4520 GB_ADDR_CONFIG, PIPE_INTERLEAVE_SIZE));
4521 }
4522
gfx_v10_0_gfx_ring_init(struct amdgpu_device * adev,int ring_id,int me,int pipe,int queue)4523 static int gfx_v10_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id,
4524 int me, int pipe, int queue)
4525 {
4526 struct amdgpu_ring *ring;
4527 unsigned int irq_type;
4528 unsigned int hw_prio;
4529
4530 ring = &adev->gfx.gfx_ring[ring_id];
4531
4532 ring->me = me;
4533 ring->pipe = pipe;
4534 ring->queue = queue;
4535
4536 ring->ring_obj = NULL;
4537 ring->use_doorbell = true;
4538
4539 if (!ring_id)
4540 ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1;
4541 else
4542 ring->doorbell_index = adev->doorbell_index.gfx_ring1 << 1;
4543 sprintf(ring->name, "gfx_%d.%d.%d", ring->me, ring->pipe, ring->queue);
4544
4545 irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe;
4546 hw_prio = amdgpu_gfx_is_high_priority_graphics_queue(adev, ring) ?
4547 AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL;
4548 return amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type,
4549 hw_prio, NULL);
4550 }
4551
gfx_v10_0_compute_ring_init(struct amdgpu_device * adev,int ring_id,int mec,int pipe,int queue)4552 static int gfx_v10_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
4553 int mec, int pipe, int queue)
4554 {
4555 unsigned irq_type;
4556 struct amdgpu_ring *ring;
4557 unsigned int hw_prio;
4558
4559 ring = &adev->gfx.compute_ring[ring_id];
4560
4561 /* mec0 is me1 */
4562 ring->me = mec + 1;
4563 ring->pipe = pipe;
4564 ring->queue = queue;
4565
4566 ring->ring_obj = NULL;
4567 ring->use_doorbell = true;
4568 ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1;
4569 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr
4570 + (ring_id * GFX10_MEC_HPD_SIZE);
4571 sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
4572
4573 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
4574 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)
4575 + ring->pipe;
4576 hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ?
4577 AMDGPU_RING_PRIO_2 : AMDGPU_RING_PRIO_DEFAULT;
4578 /* type-2 packets are deprecated on MEC, use type-3 instead */
4579 return amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type,
4580 hw_prio, NULL);
4581 }
4582
gfx_v10_0_sw_init(void * handle)4583 static int gfx_v10_0_sw_init(void *handle)
4584 {
4585 int i, j, k, r, ring_id = 0;
4586 struct amdgpu_kiq *kiq;
4587 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4588
4589 switch (adev->ip_versions[GC_HWIP][0]) {
4590 case IP_VERSION(10, 1, 10):
4591 case IP_VERSION(10, 1, 1):
4592 case IP_VERSION(10, 1, 2):
4593 case IP_VERSION(10, 1, 3):
4594 case IP_VERSION(10, 1, 4):
4595 adev->gfx.me.num_me = 1;
4596 adev->gfx.me.num_pipe_per_me = 1;
4597 adev->gfx.me.num_queue_per_pipe = 1;
4598 adev->gfx.mec.num_mec = 2;
4599 adev->gfx.mec.num_pipe_per_mec = 4;
4600 adev->gfx.mec.num_queue_per_pipe = 8;
4601 break;
4602 case IP_VERSION(10, 3, 0):
4603 case IP_VERSION(10, 3, 2):
4604 case IP_VERSION(10, 3, 1):
4605 case IP_VERSION(10, 3, 4):
4606 case IP_VERSION(10, 3, 5):
4607 case IP_VERSION(10, 3, 6):
4608 case IP_VERSION(10, 3, 3):
4609 case IP_VERSION(10, 3, 7):
4610 adev->gfx.me.num_me = 1;
4611 adev->gfx.me.num_pipe_per_me = 1;
4612 adev->gfx.me.num_queue_per_pipe = 1;
4613 adev->gfx.mec.num_mec = 2;
4614 adev->gfx.mec.num_pipe_per_mec = 4;
4615 adev->gfx.mec.num_queue_per_pipe = 4;
4616 break;
4617 default:
4618 adev->gfx.me.num_me = 1;
4619 adev->gfx.me.num_pipe_per_me = 1;
4620 adev->gfx.me.num_queue_per_pipe = 1;
4621 adev->gfx.mec.num_mec = 1;
4622 adev->gfx.mec.num_pipe_per_mec = 4;
4623 adev->gfx.mec.num_queue_per_pipe = 8;
4624 break;
4625 }
4626
4627 /* KIQ event */
4628 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP,
4629 GFX_10_1__SRCID__CP_IB2_INTERRUPT_PKT,
4630 &adev->gfx.kiq.irq);
4631 if (r)
4632 return r;
4633
4634 /* EOP Event */
4635 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP,
4636 GFX_10_1__SRCID__CP_EOP_INTERRUPT,
4637 &adev->gfx.eop_irq);
4638 if (r)
4639 return r;
4640
4641 /* Privileged reg */
4642 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_REG_FAULT,
4643 &adev->gfx.priv_reg_irq);
4644 if (r)
4645 return r;
4646
4647 /* Privileged inst */
4648 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_INSTR_FAULT,
4649 &adev->gfx.priv_inst_irq);
4650 if (r)
4651 return r;
4652
4653 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
4654
4655 r = gfx_v10_0_me_init(adev);
4656 if (r)
4657 return r;
4658
4659 if (adev->gfx.rlc.funcs) {
4660 if (adev->gfx.rlc.funcs->init) {
4661 r = adev->gfx.rlc.funcs->init(adev);
4662 if (r) {
4663 dev_err(adev->dev, "Failed to init rlc BOs!\n");
4664 return r;
4665 }
4666 }
4667 }
4668
4669 r = gfx_v10_0_mec_init(adev);
4670 if (r) {
4671 DRM_ERROR("Failed to init MEC BOs!\n");
4672 return r;
4673 }
4674
4675 /* set up the gfx ring */
4676 for (i = 0; i < adev->gfx.me.num_me; i++) {
4677 for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) {
4678 for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) {
4679 if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j))
4680 continue;
4681
4682 r = gfx_v10_0_gfx_ring_init(adev, ring_id,
4683 i, k, j);
4684 if (r)
4685 return r;
4686 ring_id++;
4687 }
4688 }
4689 }
4690
4691 ring_id = 0;
4692 /* set up the compute queues - allocate horizontally across pipes */
4693 for (i = 0; i < adev->gfx.mec.num_mec; ++i) {
4694 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {
4695 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
4696 if (!amdgpu_gfx_is_mec_queue_enabled(adev, i, k,
4697 j))
4698 continue;
4699
4700 r = gfx_v10_0_compute_ring_init(adev, ring_id,
4701 i, k, j);
4702 if (r)
4703 return r;
4704
4705 ring_id++;
4706 }
4707 }
4708 }
4709
4710 if (!adev->enable_mes_kiq) {
4711 r = amdgpu_gfx_kiq_init(adev, GFX10_MEC_HPD_SIZE);
4712 if (r) {
4713 DRM_ERROR("Failed to init KIQ BOs!\n");
4714 return r;
4715 }
4716
4717 kiq = &adev->gfx.kiq;
4718 r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq);
4719 if (r)
4720 return r;
4721 }
4722
4723 r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v10_compute_mqd));
4724 if (r)
4725 return r;
4726
4727 /* allocate visible FB for rlc auto-loading fw */
4728 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
4729 r = gfx_v10_0_rlc_backdoor_autoload_buffer_init(adev);
4730 if (r)
4731 return r;
4732 }
4733
4734 adev->gfx.ce_ram_size = F32_CE_PROGRAM_RAM_SIZE;
4735
4736 gfx_v10_0_gpu_early_init(adev);
4737
4738 return 0;
4739 }
4740
gfx_v10_0_pfp_fini(struct amdgpu_device * adev)4741 static void gfx_v10_0_pfp_fini(struct amdgpu_device *adev)
4742 {
4743 amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_obj,
4744 &adev->gfx.pfp.pfp_fw_gpu_addr,
4745 (void **)&adev->gfx.pfp.pfp_fw_ptr);
4746 }
4747
gfx_v10_0_ce_fini(struct amdgpu_device * adev)4748 static void gfx_v10_0_ce_fini(struct amdgpu_device *adev)
4749 {
4750 amdgpu_bo_free_kernel(&adev->gfx.ce.ce_fw_obj,
4751 &adev->gfx.ce.ce_fw_gpu_addr,
4752 (void **)&adev->gfx.ce.ce_fw_ptr);
4753 }
4754
gfx_v10_0_me_fini(struct amdgpu_device * adev)4755 static void gfx_v10_0_me_fini(struct amdgpu_device *adev)
4756 {
4757 amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_obj,
4758 &adev->gfx.me.me_fw_gpu_addr,
4759 (void **)&adev->gfx.me.me_fw_ptr);
4760 }
4761
gfx_v10_0_sw_fini(void * handle)4762 static int gfx_v10_0_sw_fini(void *handle)
4763 {
4764 int i;
4765 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4766
4767 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
4768 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
4769 for (i = 0; i < adev->gfx.num_compute_rings; i++)
4770 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
4771
4772 amdgpu_gfx_mqd_sw_fini(adev);
4773
4774 if (!adev->enable_mes_kiq) {
4775 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring);
4776 amdgpu_gfx_kiq_fini(adev);
4777 }
4778
4779 gfx_v10_0_pfp_fini(adev);
4780 gfx_v10_0_ce_fini(adev);
4781 gfx_v10_0_me_fini(adev);
4782 gfx_v10_0_rlc_fini(adev);
4783 gfx_v10_0_mec_fini(adev);
4784
4785 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO)
4786 gfx_v10_0_rlc_backdoor_autoload_buffer_fini(adev);
4787
4788 gfx_v10_0_free_microcode(adev);
4789
4790 return 0;
4791 }
4792
gfx_v10_0_select_se_sh(struct amdgpu_device * adev,u32 se_num,u32 sh_num,u32 instance)4793 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
4794 u32 sh_num, u32 instance)
4795 {
4796 u32 data;
4797
4798 if (instance == 0xffffffff)
4799 data = REG_SET_FIELD(0, GRBM_GFX_INDEX,
4800 INSTANCE_BROADCAST_WRITES, 1);
4801 else
4802 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX,
4803 instance);
4804
4805 if (se_num == 0xffffffff)
4806 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES,
4807 1);
4808 else
4809 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
4810
4811 if (sh_num == 0xffffffff)
4812 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES,
4813 1);
4814 else
4815 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num);
4816
4817 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data);
4818 }
4819
gfx_v10_0_get_rb_active_bitmap(struct amdgpu_device * adev)4820 static u32 gfx_v10_0_get_rb_active_bitmap(struct amdgpu_device *adev)
4821 {
4822 u32 data, mask;
4823
4824 data = RREG32_SOC15(GC, 0, mmCC_RB_BACKEND_DISABLE);
4825 data |= RREG32_SOC15(GC, 0, mmGC_USER_RB_BACKEND_DISABLE);
4826
4827 data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK;
4828 data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT;
4829
4830 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se /
4831 adev->gfx.config.max_sh_per_se);
4832
4833 return (~data) & mask;
4834 }
4835
gfx_v10_0_setup_rb(struct amdgpu_device * adev)4836 static void gfx_v10_0_setup_rb(struct amdgpu_device *adev)
4837 {
4838 int i, j;
4839 u32 data;
4840 u32 active_rbs = 0;
4841 u32 bitmap;
4842 u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
4843 adev->gfx.config.max_sh_per_se;
4844
4845 mutex_lock(&adev->grbm_idx_mutex);
4846 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
4847 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
4848 bitmap = i * adev->gfx.config.max_sh_per_se + j;
4849 if (((adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 0)) ||
4850 (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 3)) ||
4851 (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 6))) &&
4852 ((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1))
4853 continue;
4854 gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff);
4855 data = gfx_v10_0_get_rb_active_bitmap(adev);
4856 active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *
4857 rb_bitmap_width_per_sh);
4858 }
4859 }
4860 gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
4861 mutex_unlock(&adev->grbm_idx_mutex);
4862
4863 adev->gfx.config.backend_enable_mask = active_rbs;
4864 adev->gfx.config.num_rbs = hweight32(active_rbs);
4865 }
4866
gfx_v10_0_init_pa_sc_tile_steering_override(struct amdgpu_device * adev)4867 static u32 gfx_v10_0_init_pa_sc_tile_steering_override(struct amdgpu_device *adev)
4868 {
4869 uint32_t num_sc;
4870 uint32_t enabled_rb_per_sh;
4871 uint32_t active_rb_bitmap;
4872 uint32_t num_rb_per_sc;
4873 uint32_t num_packer_per_sc;
4874 uint32_t pa_sc_tile_steering_override;
4875
4876 /* for ASICs that integrates GFX v10.3
4877 * pa_sc_tile_steering_override should be set to 0 */
4878 if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 3, 0))
4879 return 0;
4880
4881 /* init num_sc */
4882 num_sc = adev->gfx.config.max_shader_engines * adev->gfx.config.max_sh_per_se *
4883 adev->gfx.config.num_sc_per_sh;
4884 /* init num_rb_per_sc */
4885 active_rb_bitmap = gfx_v10_0_get_rb_active_bitmap(adev);
4886 enabled_rb_per_sh = hweight32(active_rb_bitmap);
4887 num_rb_per_sc = enabled_rb_per_sh / adev->gfx.config.num_sc_per_sh;
4888 /* init num_packer_per_sc */
4889 num_packer_per_sc = adev->gfx.config.num_packer_per_sc;
4890
4891 pa_sc_tile_steering_override = 0;
4892 pa_sc_tile_steering_override |=
4893 (order_base_2(num_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_SC__SHIFT) &
4894 PA_SC_TILE_STEERING_OVERRIDE__NUM_SC_MASK;
4895 pa_sc_tile_steering_override |=
4896 (order_base_2(num_rb_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC__SHIFT) &
4897 PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC_MASK;
4898 pa_sc_tile_steering_override |=
4899 (order_base_2(num_packer_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC__SHIFT) &
4900 PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC_MASK;
4901
4902 return pa_sc_tile_steering_override;
4903 }
4904
4905 #define DEFAULT_SH_MEM_BASES (0x6000)
4906
gfx_v10_0_init_compute_vmid(struct amdgpu_device * adev)4907 static void gfx_v10_0_init_compute_vmid(struct amdgpu_device *adev)
4908 {
4909 int i;
4910 uint32_t sh_mem_bases;
4911
4912 /*
4913 * Configure apertures:
4914 * LDS: 0x60000000'00000000 - 0x60000001'00000000 (4GB)
4915 * Scratch: 0x60000001'00000000 - 0x60000002'00000000 (4GB)
4916 * GPUVM: 0x60010000'00000000 - 0x60020000'00000000 (1TB)
4917 */
4918 sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);
4919
4920 mutex_lock(&adev->srbm_mutex);
4921 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
4922 nv_grbm_select(adev, 0, 0, 0, i);
4923 /* CP and shaders */
4924 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);
4925 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases);
4926 }
4927 nv_grbm_select(adev, 0, 0, 0, 0);
4928 mutex_unlock(&adev->srbm_mutex);
4929
4930 /* Initialize all compute VMIDs to have no GDS, GWS, or OA
4931 access. These should be enabled by FW for target VMIDs. */
4932 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
4933 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * i, 0);
4934 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * i, 0);
4935 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, i, 0);
4936 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, i, 0);
4937 }
4938 }
4939
gfx_v10_0_init_gds_vmid(struct amdgpu_device * adev)4940 static void gfx_v10_0_init_gds_vmid(struct amdgpu_device *adev)
4941 {
4942 int vmid;
4943
4944 /*
4945 * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA
4946 * access. Compute VMIDs should be enabled by FW for target VMIDs,
4947 * the driver can enable them for graphics. VMID0 should maintain
4948 * access so that HWS firmware can save/restore entries.
4949 */
4950 for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) {
4951 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * vmid, 0);
4952 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * vmid, 0);
4953 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, vmid, 0);
4954 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, vmid, 0);
4955 }
4956 }
4957
4958
gfx_v10_0_tcp_harvest(struct amdgpu_device * adev)4959 static void gfx_v10_0_tcp_harvest(struct amdgpu_device *adev)
4960 {
4961 int i, j, k;
4962 int max_wgp_per_sh = adev->gfx.config.max_cu_per_sh >> 1;
4963 u32 tmp, wgp_active_bitmap = 0;
4964 u32 gcrd_targets_disable_tcp = 0;
4965 u32 utcl_invreq_disable = 0;
4966 /*
4967 * GCRD_TARGETS_DISABLE field contains
4968 * for Navi10/Navi12: GL1C=[18:15], SQC=[14:10], TCP=[9:0]
4969 * for Navi14: GL1C=[21:18], SQC=[17:12], TCP=[11:0]
4970 */
4971 u32 gcrd_targets_disable_mask = amdgpu_gfx_create_bitmask(
4972 2 * max_wgp_per_sh + /* TCP */
4973 max_wgp_per_sh + /* SQC */
4974 4); /* GL1C */
4975 /*
4976 * UTCL1_UTCL0_INVREQ_DISABLE field contains
4977 * for Navi10Navi12: SQG=[24], RMI=[23:20], SQC=[19:10], TCP=[9:0]
4978 * for Navi14: SQG=[28], RMI=[27:24], SQC=[23:12], TCP=[11:0]
4979 */
4980 u32 utcl_invreq_disable_mask = amdgpu_gfx_create_bitmask(
4981 2 * max_wgp_per_sh + /* TCP */
4982 2 * max_wgp_per_sh + /* SQC */
4983 4 + /* RMI */
4984 1); /* SQG */
4985
4986 mutex_lock(&adev->grbm_idx_mutex);
4987 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
4988 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
4989 gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff);
4990 wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev);
4991 /*
4992 * Set corresponding TCP bits for the inactive WGPs in
4993 * GCRD_SA_TARGETS_DISABLE
4994 */
4995 gcrd_targets_disable_tcp = 0;
4996 /* Set TCP & SQC bits in UTCL1_UTCL0_INVREQ_DISABLE */
4997 utcl_invreq_disable = 0;
4998
4999 for (k = 0; k < max_wgp_per_sh; k++) {
5000 if (!(wgp_active_bitmap & (1 << k))) {
5001 gcrd_targets_disable_tcp |= 3 << (2 * k);
5002 gcrd_targets_disable_tcp |= 1 << (k + (max_wgp_per_sh * 2));
5003 utcl_invreq_disable |= (3 << (2 * k)) |
5004 (3 << (2 * (max_wgp_per_sh + k)));
5005 }
5006 }
5007
5008 tmp = RREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE);
5009 /* only override TCP & SQC bits */
5010 tmp &= (0xffffffffU << (4 * max_wgp_per_sh));
5011 tmp |= (utcl_invreq_disable & utcl_invreq_disable_mask);
5012 WREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE, tmp);
5013
5014 tmp = RREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE);
5015 /* only override TCP & SQC bits */
5016 tmp &= (0xffffffffU << (3 * max_wgp_per_sh));
5017 tmp |= (gcrd_targets_disable_tcp & gcrd_targets_disable_mask);
5018 WREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE, tmp);
5019 }
5020 }
5021
5022 gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
5023 mutex_unlock(&adev->grbm_idx_mutex);
5024 }
5025
gfx_v10_0_get_tcc_info(struct amdgpu_device * adev)5026 static void gfx_v10_0_get_tcc_info(struct amdgpu_device *adev)
5027 {
5028 /* TCCs are global (not instanced). */
5029 uint32_t tcc_disable;
5030
5031 if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 3, 0)) {
5032 tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE_gc_10_3) |
5033 RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE_gc_10_3);
5034 } else {
5035 tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE) |
5036 RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE);
5037 }
5038
5039 adev->gfx.config.tcc_disabled_mask =
5040 REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, TCC_DISABLE) |
5041 (REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, HI_TCC_DISABLE) << 16);
5042 }
5043
gfx_v10_0_constants_init(struct amdgpu_device * adev)5044 static void gfx_v10_0_constants_init(struct amdgpu_device *adev)
5045 {
5046 u32 tmp;
5047 int i;
5048
5049 WREG32_FIELD15(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff);
5050
5051 gfx_v10_0_setup_rb(adev);
5052 gfx_v10_0_get_cu_info(adev, &adev->gfx.cu_info);
5053 gfx_v10_0_get_tcc_info(adev);
5054 adev->gfx.config.pa_sc_tile_steering_override =
5055 gfx_v10_0_init_pa_sc_tile_steering_override(adev);
5056
5057 /* XXX SH_MEM regs */
5058 /* where to put LDS, scratch, GPUVM in FSA64 space */
5059 mutex_lock(&adev->srbm_mutex);
5060 for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB_0].num_ids; i++) {
5061 nv_grbm_select(adev, 0, 0, 0, i);
5062 /* CP and shaders */
5063 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);
5064 if (i != 0) {
5065 tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE,
5066 (adev->gmc.private_aperture_start >> 48));
5067 tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE,
5068 (adev->gmc.shared_aperture_start >> 48));
5069 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, tmp);
5070 }
5071 }
5072 nv_grbm_select(adev, 0, 0, 0, 0);
5073
5074 mutex_unlock(&adev->srbm_mutex);
5075
5076 gfx_v10_0_init_compute_vmid(adev);
5077 gfx_v10_0_init_gds_vmid(adev);
5078
5079 }
5080
gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device * adev,bool enable)5081 static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
5082 bool enable)
5083 {
5084 u32 tmp;
5085
5086 if (amdgpu_sriov_vf(adev))
5087 return;
5088
5089 tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0);
5090
5091 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE,
5092 enable ? 1 : 0);
5093 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE,
5094 enable ? 1 : 0);
5095 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE,
5096 enable ? 1 : 0);
5097 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE,
5098 enable ? 1 : 0);
5099
5100 WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp);
5101 }
5102
gfx_v10_0_init_csb(struct amdgpu_device * adev)5103 static int gfx_v10_0_init_csb(struct amdgpu_device *adev)
5104 {
5105 adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr);
5106
5107 /* csib */
5108 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 2)) {
5109 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_HI,
5110 adev->gfx.rlc.clear_state_gpu_addr >> 32);
5111 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_LO,
5112 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
5113 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size);
5114 } else {
5115 WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_HI,
5116 adev->gfx.rlc.clear_state_gpu_addr >> 32);
5117 WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_LO,
5118 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
5119 WREG32_SOC15(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size);
5120 }
5121 return 0;
5122 }
5123
gfx_v10_0_rlc_stop(struct amdgpu_device * adev)5124 static void gfx_v10_0_rlc_stop(struct amdgpu_device *adev)
5125 {
5126 u32 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL);
5127
5128 tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0);
5129 WREG32_SOC15(GC, 0, mmRLC_CNTL, tmp);
5130 }
5131
gfx_v10_0_rlc_reset(struct amdgpu_device * adev)5132 static void gfx_v10_0_rlc_reset(struct amdgpu_device *adev)
5133 {
5134 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
5135 udelay(50);
5136 WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
5137 udelay(50);
5138 }
5139
gfx_v10_0_rlc_smu_handshake_cntl(struct amdgpu_device * adev,bool enable)5140 static void gfx_v10_0_rlc_smu_handshake_cntl(struct amdgpu_device *adev,
5141 bool enable)
5142 {
5143 uint32_t rlc_pg_cntl;
5144
5145 rlc_pg_cntl = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL);
5146
5147 if (!enable) {
5148 /* RLC_PG_CNTL[23] = 0 (default)
5149 * RLC will wait for handshake acks with SMU
5150 * GFXOFF will be enabled
5151 * RLC_PG_CNTL[23] = 1
5152 * RLC will not issue any message to SMU
5153 * hence no handshake between SMU & RLC
5154 * GFXOFF will be disabled
5155 */
5156 rlc_pg_cntl |= 0x800000;
5157 } else
5158 rlc_pg_cntl &= ~0x800000;
5159 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, rlc_pg_cntl);
5160 }
5161
gfx_v10_0_rlc_start(struct amdgpu_device * adev)5162 static void gfx_v10_0_rlc_start(struct amdgpu_device *adev)
5163 {
5164 /* TODO: enable rlc & smu handshake until smu
5165 * and gfxoff feature works as expected */
5166 if (!(amdgpu_pp_feature_mask & PP_GFXOFF_MASK))
5167 gfx_v10_0_rlc_smu_handshake_cntl(adev, false);
5168
5169 WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1);
5170 udelay(50);
5171 }
5172
gfx_v10_0_rlc_enable_srm(struct amdgpu_device * adev)5173 static void gfx_v10_0_rlc_enable_srm(struct amdgpu_device *adev)
5174 {
5175 uint32_t tmp;
5176
5177 /* enable Save Restore Machine */
5178 tmp = RREG32_SOC15(GC, 0, mmRLC_SRM_CNTL);
5179 tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK;
5180 tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK;
5181 WREG32_SOC15(GC, 0, mmRLC_SRM_CNTL, tmp);
5182 }
5183
gfx_v10_0_rlc_load_microcode(struct amdgpu_device * adev)5184 static int gfx_v10_0_rlc_load_microcode(struct amdgpu_device *adev)
5185 {
5186 const struct rlc_firmware_header_v2_0 *hdr;
5187 const __le32 *fw_data;
5188 unsigned i, fw_size;
5189
5190 if (!adev->gfx.rlc_fw)
5191 return -EINVAL;
5192
5193 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
5194 amdgpu_ucode_print_rlc_hdr(&hdr->header);
5195
5196 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
5197 le32_to_cpu(hdr->header.ucode_array_offset_bytes));
5198 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
5199
5200 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR,
5201 RLCG_UCODE_LOADING_START_ADDRESS);
5202
5203 for (i = 0; i < fw_size; i++)
5204 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_DATA,
5205 le32_to_cpup(fw_data++));
5206
5207 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);
5208
5209 return 0;
5210 }
5211
gfx_v10_0_rlc_resume(struct amdgpu_device * adev)5212 static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev)
5213 {
5214 int r;
5215
5216 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP &&
5217 adev->psp.autoload_supported) {
5218
5219 r = gfx_v10_0_wait_for_rlc_autoload_complete(adev);
5220 if (r)
5221 return r;
5222
5223 gfx_v10_0_init_csb(adev);
5224
5225 if (!amdgpu_sriov_vf(adev)) /* enable RLC SRM */
5226 gfx_v10_0_rlc_enable_srm(adev);
5227 } else {
5228 if (amdgpu_sriov_vf(adev)) {
5229 gfx_v10_0_init_csb(adev);
5230 return 0;
5231 }
5232
5233 adev->gfx.rlc.funcs->stop(adev);
5234
5235 /* disable CG */
5236 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0);
5237
5238 /* disable PG */
5239 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, 0);
5240
5241 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
5242 /* legacy rlc firmware loading */
5243 r = gfx_v10_0_rlc_load_microcode(adev);
5244 if (r)
5245 return r;
5246 } else if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
5247 /* rlc backdoor autoload firmware */
5248 r = gfx_v10_0_rlc_backdoor_autoload_enable(adev);
5249 if (r)
5250 return r;
5251 }
5252
5253 gfx_v10_0_init_csb(adev);
5254
5255 adev->gfx.rlc.funcs->start(adev);
5256
5257 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
5258 r = gfx_v10_0_wait_for_rlc_autoload_complete(adev);
5259 if (r)
5260 return r;
5261 }
5262 }
5263 return 0;
5264 }
5265
5266 static struct {
5267 FIRMWARE_ID id;
5268 unsigned int offset;
5269 unsigned int size;
5270 } rlc_autoload_info[FIRMWARE_ID_MAX];
5271
gfx_v10_0_parse_rlc_toc(struct amdgpu_device * adev)5272 static int gfx_v10_0_parse_rlc_toc(struct amdgpu_device *adev)
5273 {
5274 int ret;
5275 RLC_TABLE_OF_CONTENT *rlc_toc;
5276
5277 ret = amdgpu_bo_create_reserved(adev, adev->psp.toc.size_bytes, PAGE_SIZE,
5278 AMDGPU_GEM_DOMAIN_GTT,
5279 &adev->gfx.rlc.rlc_toc_bo,
5280 &adev->gfx.rlc.rlc_toc_gpu_addr,
5281 (void **)&adev->gfx.rlc.rlc_toc_buf);
5282 if (ret) {
5283 dev_err(adev->dev, "(%d) failed to create rlc toc bo\n", ret);
5284 return ret;
5285 }
5286
5287 /* Copy toc from psp sos fw to rlc toc buffer */
5288 memcpy(adev->gfx.rlc.rlc_toc_buf, adev->psp.toc.start_addr, adev->psp.toc.size_bytes);
5289
5290 rlc_toc = (RLC_TABLE_OF_CONTENT *)adev->gfx.rlc.rlc_toc_buf;
5291 while (rlc_toc && (rlc_toc->id > FIRMWARE_ID_INVALID) &&
5292 (rlc_toc->id < FIRMWARE_ID_MAX)) {
5293 if ((rlc_toc->id >= FIRMWARE_ID_CP_CE) &&
5294 (rlc_toc->id <= FIRMWARE_ID_CP_MES)) {
5295 /* Offset needs 4KB alignment */
5296 rlc_toc->offset = ALIGN(rlc_toc->offset * 4, PAGE_SIZE);
5297 }
5298
5299 rlc_autoload_info[rlc_toc->id].id = rlc_toc->id;
5300 rlc_autoload_info[rlc_toc->id].offset = rlc_toc->offset * 4;
5301 rlc_autoload_info[rlc_toc->id].size = rlc_toc->size * 4;
5302
5303 rlc_toc++;
5304 }
5305
5306 return 0;
5307 }
5308
gfx_v10_0_calc_toc_total_size(struct amdgpu_device * adev)5309 static uint32_t gfx_v10_0_calc_toc_total_size(struct amdgpu_device *adev)
5310 {
5311 uint32_t total_size = 0;
5312 FIRMWARE_ID id;
5313 int ret;
5314
5315 ret = gfx_v10_0_parse_rlc_toc(adev);
5316 if (ret) {
5317 dev_err(adev->dev, "failed to parse rlc toc\n");
5318 return 0;
5319 }
5320
5321 for (id = FIRMWARE_ID_RLC_G_UCODE; id < FIRMWARE_ID_MAX; id++)
5322 total_size += rlc_autoload_info[id].size;
5323
5324 /* In case the offset in rlc toc ucode is aligned */
5325 if (total_size < rlc_autoload_info[FIRMWARE_ID_MAX-1].offset)
5326 total_size = rlc_autoload_info[FIRMWARE_ID_MAX-1].offset +
5327 rlc_autoload_info[FIRMWARE_ID_MAX-1].size;
5328
5329 return total_size;
5330 }
5331
gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device * adev)5332 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev)
5333 {
5334 int r;
5335 uint32_t total_size;
5336
5337 total_size = gfx_v10_0_calc_toc_total_size(adev);
5338
5339 r = amdgpu_bo_create_reserved(adev, total_size, PAGE_SIZE,
5340 AMDGPU_GEM_DOMAIN_GTT,
5341 &adev->gfx.rlc.rlc_autoload_bo,
5342 &adev->gfx.rlc.rlc_autoload_gpu_addr,
5343 (void **)&adev->gfx.rlc.rlc_autoload_ptr);
5344 if (r) {
5345 dev_err(adev->dev, "(%d) failed to create fw autoload bo\n", r);
5346 return r;
5347 }
5348
5349 return 0;
5350 }
5351
gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device * adev)5352 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev)
5353 {
5354 amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_toc_bo,
5355 &adev->gfx.rlc.rlc_toc_gpu_addr,
5356 (void **)&adev->gfx.rlc.rlc_toc_buf);
5357 amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_autoload_bo,
5358 &adev->gfx.rlc.rlc_autoload_gpu_addr,
5359 (void **)&adev->gfx.rlc.rlc_autoload_ptr);
5360 }
5361
gfx_v10_0_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device * adev,FIRMWARE_ID id,const void * fw_data,uint32_t fw_size)5362 static void gfx_v10_0_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device *adev,
5363 FIRMWARE_ID id,
5364 const void *fw_data,
5365 uint32_t fw_size)
5366 {
5367 uint32_t toc_offset;
5368 uint32_t toc_fw_size;
5369 char *ptr = adev->gfx.rlc.rlc_autoload_ptr;
5370
5371 if (id <= FIRMWARE_ID_INVALID || id >= FIRMWARE_ID_MAX)
5372 return;
5373
5374 toc_offset = rlc_autoload_info[id].offset;
5375 toc_fw_size = rlc_autoload_info[id].size;
5376
5377 if (fw_size == 0)
5378 fw_size = toc_fw_size;
5379
5380 if (fw_size > toc_fw_size)
5381 fw_size = toc_fw_size;
5382
5383 memcpy(ptr + toc_offset, fw_data, fw_size);
5384
5385 if (fw_size < toc_fw_size)
5386 memset(ptr + toc_offset + fw_size, 0, toc_fw_size - fw_size);
5387 }
5388
gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device * adev)5389 static void gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device *adev)
5390 {
5391 void *data;
5392 uint32_t size;
5393
5394 data = adev->gfx.rlc.rlc_toc_buf;
5395 size = rlc_autoload_info[FIRMWARE_ID_RLC_TOC].size;
5396
5397 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5398 FIRMWARE_ID_RLC_TOC,
5399 data, size);
5400 }
5401
gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device * adev)5402 static void gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device *adev)
5403 {
5404 const __le32 *fw_data;
5405 uint32_t fw_size;
5406 const struct gfx_firmware_header_v1_0 *cp_hdr;
5407 const struct rlc_firmware_header_v2_0 *rlc_hdr;
5408
5409 /* pfp ucode */
5410 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5411 adev->gfx.pfp_fw->data;
5412 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
5413 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5414 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
5415 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5416 FIRMWARE_ID_CP_PFP,
5417 fw_data, fw_size);
5418
5419 /* ce ucode */
5420 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5421 adev->gfx.ce_fw->data;
5422 fw_data = (const __le32 *)(adev->gfx.ce_fw->data +
5423 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5424 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
5425 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5426 FIRMWARE_ID_CP_CE,
5427 fw_data, fw_size);
5428
5429 /* me ucode */
5430 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5431 adev->gfx.me_fw->data;
5432 fw_data = (const __le32 *)(adev->gfx.me_fw->data +
5433 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5434 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
5435 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5436 FIRMWARE_ID_CP_ME,
5437 fw_data, fw_size);
5438
5439 /* rlc ucode */
5440 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)
5441 adev->gfx.rlc_fw->data;
5442 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
5443 le32_to_cpu(rlc_hdr->header.ucode_array_offset_bytes));
5444 fw_size = le32_to_cpu(rlc_hdr->header.ucode_size_bytes);
5445 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5446 FIRMWARE_ID_RLC_G_UCODE,
5447 fw_data, fw_size);
5448
5449 /* mec1 ucode */
5450 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5451 adev->gfx.mec_fw->data;
5452 fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
5453 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5454 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes) -
5455 cp_hdr->jt_size * 4;
5456 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5457 FIRMWARE_ID_CP_MEC,
5458 fw_data, fw_size);
5459 /* mec2 ucode is not necessary if mec2 ucode is same as mec1 */
5460 }
5461
5462 /* Temporarily put sdma part here */
gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device * adev)5463 static void gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device *adev)
5464 {
5465 const __le32 *fw_data;
5466 uint32_t fw_size;
5467 const struct sdma_firmware_header_v1_0 *sdma_hdr;
5468 int i;
5469
5470 for (i = 0; i < adev->sdma.num_instances; i++) {
5471 sdma_hdr = (const struct sdma_firmware_header_v1_0 *)
5472 adev->sdma.instance[i].fw->data;
5473 fw_data = (const __le32 *) (adev->sdma.instance[i].fw->data +
5474 le32_to_cpu(sdma_hdr->header.ucode_array_offset_bytes));
5475 fw_size = le32_to_cpu(sdma_hdr->header.ucode_size_bytes);
5476
5477 if (i == 0) {
5478 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5479 FIRMWARE_ID_SDMA0_UCODE, fw_data, fw_size);
5480 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5481 FIRMWARE_ID_SDMA0_JT,
5482 (uint32_t *)fw_data +
5483 sdma_hdr->jt_offset,
5484 sdma_hdr->jt_size * 4);
5485 } else if (i == 1) {
5486 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5487 FIRMWARE_ID_SDMA1_UCODE, fw_data, fw_size);
5488 gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5489 FIRMWARE_ID_SDMA1_JT,
5490 (uint32_t *)fw_data +
5491 sdma_hdr->jt_offset,
5492 sdma_hdr->jt_size * 4);
5493 }
5494 }
5495 }
5496
gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device * adev)5497 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev)
5498 {
5499 uint32_t rlc_g_offset, rlc_g_size, tmp;
5500 uint64_t gpu_addr;
5501
5502 gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(adev);
5503 gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(adev);
5504 gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(adev);
5505
5506 rlc_g_offset = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].offset;
5507 rlc_g_size = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].size;
5508 gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset;
5509
5510 WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_HI, upper_32_bits(gpu_addr));
5511 WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_LO, lower_32_bits(gpu_addr));
5512 WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_SIZE, rlc_g_size);
5513
5514 tmp = RREG32_SOC15(GC, 0, mmRLC_HYP_RESET_VECTOR);
5515 if (!(tmp & (RLC_HYP_RESET_VECTOR__COLD_BOOT_EXIT_MASK |
5516 RLC_HYP_RESET_VECTOR__VDDGFX_EXIT_MASK))) {
5517 DRM_ERROR("Neither COLD_BOOT_EXIT nor VDDGFX_EXIT is set\n");
5518 return -EINVAL;
5519 }
5520
5521 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL);
5522 if (tmp & RLC_CNTL__RLC_ENABLE_F32_MASK) {
5523 DRM_ERROR("RLC ROM should halt itself\n");
5524 return -EINVAL;
5525 }
5526
5527 return 0;
5528 }
5529
gfx_v10_0_rlc_backdoor_autoload_config_me_cache(struct amdgpu_device * adev)5530 static int gfx_v10_0_rlc_backdoor_autoload_config_me_cache(struct amdgpu_device *adev)
5531 {
5532 uint32_t usec_timeout = 50000; /* wait for 50ms */
5533 uint32_t tmp;
5534 int i;
5535 uint64_t addr;
5536
5537 /* Trigger an invalidation of the L1 instruction caches */
5538 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
5539 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5540 WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp);
5541
5542 /* Wait for invalidation complete */
5543 for (i = 0; i < usec_timeout; i++) {
5544 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
5545 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
5546 INVALIDATE_CACHE_COMPLETE))
5547 break;
5548 udelay(1);
5549 }
5550
5551 if (i >= usec_timeout) {
5552 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5553 return -EINVAL;
5554 }
5555
5556 /* Program me ucode address into intruction cache address register */
5557 addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5558 rlc_autoload_info[FIRMWARE_ID_CP_ME].offset;
5559 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO,
5560 lower_32_bits(addr) & 0xFFFFF000);
5561 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI,
5562 upper_32_bits(addr));
5563
5564 return 0;
5565 }
5566
gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(struct amdgpu_device * adev)5567 static int gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(struct amdgpu_device *adev)
5568 {
5569 uint32_t usec_timeout = 50000; /* wait for 50ms */
5570 uint32_t tmp;
5571 int i;
5572 uint64_t addr;
5573
5574 /* Trigger an invalidation of the L1 instruction caches */
5575 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
5576 tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5577 WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp);
5578
5579 /* Wait for invalidation complete */
5580 for (i = 0; i < usec_timeout; i++) {
5581 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
5582 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL,
5583 INVALIDATE_CACHE_COMPLETE))
5584 break;
5585 udelay(1);
5586 }
5587
5588 if (i >= usec_timeout) {
5589 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5590 return -EINVAL;
5591 }
5592
5593 /* Program ce ucode address into intruction cache address register */
5594 addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5595 rlc_autoload_info[FIRMWARE_ID_CP_CE].offset;
5596 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO,
5597 lower_32_bits(addr) & 0xFFFFF000);
5598 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI,
5599 upper_32_bits(addr));
5600
5601 return 0;
5602 }
5603
gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(struct amdgpu_device * adev)5604 static int gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(struct amdgpu_device *adev)
5605 {
5606 uint32_t usec_timeout = 50000; /* wait for 50ms */
5607 uint32_t tmp;
5608 int i;
5609 uint64_t addr;
5610
5611 /* Trigger an invalidation of the L1 instruction caches */
5612 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5613 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5614 WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp);
5615
5616 /* Wait for invalidation complete */
5617 for (i = 0; i < usec_timeout; i++) {
5618 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5619 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
5620 INVALIDATE_CACHE_COMPLETE))
5621 break;
5622 udelay(1);
5623 }
5624
5625 if (i >= usec_timeout) {
5626 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5627 return -EINVAL;
5628 }
5629
5630 /* Program pfp ucode address into intruction cache address register */
5631 addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5632 rlc_autoload_info[FIRMWARE_ID_CP_PFP].offset;
5633 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO,
5634 lower_32_bits(addr) & 0xFFFFF000);
5635 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI,
5636 upper_32_bits(addr));
5637
5638 return 0;
5639 }
5640
gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(struct amdgpu_device * adev)5641 static int gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(struct amdgpu_device *adev)
5642 {
5643 uint32_t usec_timeout = 50000; /* wait for 50ms */
5644 uint32_t tmp;
5645 int i;
5646 uint64_t addr;
5647
5648 /* Trigger an invalidation of the L1 instruction caches */
5649 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
5650 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5651 WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp);
5652
5653 /* Wait for invalidation complete */
5654 for (i = 0; i < usec_timeout; i++) {
5655 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
5656 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL,
5657 INVALIDATE_CACHE_COMPLETE))
5658 break;
5659 udelay(1);
5660 }
5661
5662 if (i >= usec_timeout) {
5663 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5664 return -EINVAL;
5665 }
5666
5667 /* Program mec1 ucode address into intruction cache address register */
5668 addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5669 rlc_autoload_info[FIRMWARE_ID_CP_MEC].offset;
5670 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO,
5671 lower_32_bits(addr) & 0xFFFFF000);
5672 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI,
5673 upper_32_bits(addr));
5674
5675 return 0;
5676 }
5677
gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device * adev)5678 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev)
5679 {
5680 uint32_t cp_status;
5681 uint32_t bootload_status;
5682 int i, r;
5683
5684 for (i = 0; i < adev->usec_timeout; i++) {
5685 cp_status = RREG32_SOC15(GC, 0, mmCP_STAT);
5686 bootload_status = RREG32_SOC15(GC, 0, mmRLC_RLCS_BOOTLOAD_STATUS);
5687 if ((cp_status == 0) &&
5688 (REG_GET_FIELD(bootload_status,
5689 RLC_RLCS_BOOTLOAD_STATUS, BOOTLOAD_COMPLETE) == 1)) {
5690 break;
5691 }
5692 udelay(1);
5693 }
5694
5695 if (i >= adev->usec_timeout) {
5696 dev_err(adev->dev, "rlc autoload: gc ucode autoload timeout\n");
5697 return -ETIMEDOUT;
5698 }
5699
5700 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
5701 r = gfx_v10_0_rlc_backdoor_autoload_config_me_cache(adev);
5702 if (r)
5703 return r;
5704
5705 r = gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(adev);
5706 if (r)
5707 return r;
5708
5709 r = gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(adev);
5710 if (r)
5711 return r;
5712
5713 r = gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(adev);
5714 if (r)
5715 return r;
5716 }
5717
5718 return 0;
5719 }
5720
gfx_v10_0_cp_gfx_enable(struct amdgpu_device * adev,bool enable)5721 static int gfx_v10_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
5722 {
5723 int i;
5724 u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL);
5725
5726 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1);
5727 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1);
5728 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1);
5729
5730 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 2)) {
5731 WREG32_SOC15_RLC(GC, 0, mmCP_ME_CNTL, tmp);
5732 } else {
5733 WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp);
5734 }
5735
5736 if (adev->job_hang && !enable)
5737 return 0;
5738
5739 for (i = 0; i < adev->usec_timeout; i++) {
5740 if (RREG32_SOC15(GC, 0, mmCP_STAT) == 0)
5741 break;
5742 udelay(1);
5743 }
5744
5745 if (i >= adev->usec_timeout)
5746 DRM_ERROR("failed to %s cp gfx\n", enable ? "unhalt" : "halt");
5747
5748 return 0;
5749 }
5750
gfx_v10_0_cp_gfx_load_pfp_microcode(struct amdgpu_device * adev)5751 static int gfx_v10_0_cp_gfx_load_pfp_microcode(struct amdgpu_device *adev)
5752 {
5753 int r;
5754 const struct gfx_firmware_header_v1_0 *pfp_hdr;
5755 const __le32 *fw_data;
5756 unsigned i, fw_size;
5757 uint32_t tmp;
5758 uint32_t usec_timeout = 50000; /* wait for 50ms */
5759
5760 pfp_hdr = (const struct gfx_firmware_header_v1_0 *)
5761 adev->gfx.pfp_fw->data;
5762
5763 amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
5764
5765 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
5766 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
5767 fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes);
5768
5769 r = amdgpu_bo_create_reserved(adev, pfp_hdr->header.ucode_size_bytes,
5770 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
5771 &adev->gfx.pfp.pfp_fw_obj,
5772 &adev->gfx.pfp.pfp_fw_gpu_addr,
5773 (void **)&adev->gfx.pfp.pfp_fw_ptr);
5774 if (r) {
5775 dev_err(adev->dev, "(%d) failed to create pfp fw bo\n", r);
5776 gfx_v10_0_pfp_fini(adev);
5777 return r;
5778 }
5779
5780 memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_data, fw_size);
5781
5782 amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj);
5783 amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj);
5784
5785 /* Trigger an invalidation of the L1 instruction caches */
5786 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5787 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5788 WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp);
5789
5790 /* Wait for invalidation complete */
5791 for (i = 0; i < usec_timeout; i++) {
5792 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5793 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
5794 INVALIDATE_CACHE_COMPLETE))
5795 break;
5796 udelay(1);
5797 }
5798
5799 if (i >= usec_timeout) {
5800 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5801 return -EINVAL;
5802 }
5803
5804 if (amdgpu_emu_mode == 1)
5805 adev->hdp.funcs->flush_hdp(adev, NULL);
5806
5807 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL);
5808 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0);
5809 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0);
5810 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0);
5811 tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
5812 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL, tmp);
5813 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO,
5814 adev->gfx.pfp.pfp_fw_gpu_addr & 0xFFFFF000);
5815 WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI,
5816 upper_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr));
5817
5818 WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_ADDR, 0);
5819
5820 for (i = 0; i < pfp_hdr->jt_size; i++)
5821 WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_DATA,
5822 le32_to_cpup(fw_data + pfp_hdr->jt_offset + i));
5823
5824 WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version);
5825
5826 return 0;
5827 }
5828
gfx_v10_0_cp_gfx_load_ce_microcode(struct amdgpu_device * adev)5829 static int gfx_v10_0_cp_gfx_load_ce_microcode(struct amdgpu_device *adev)
5830 {
5831 int r;
5832 const struct gfx_firmware_header_v1_0 *ce_hdr;
5833 const __le32 *fw_data;
5834 unsigned i, fw_size;
5835 uint32_t tmp;
5836 uint32_t usec_timeout = 50000; /* wait for 50ms */
5837
5838 ce_hdr = (const struct gfx_firmware_header_v1_0 *)
5839 adev->gfx.ce_fw->data;
5840
5841 amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
5842
5843 fw_data = (const __le32 *)(adev->gfx.ce_fw->data +
5844 le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
5845 fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes);
5846
5847 r = amdgpu_bo_create_reserved(adev, ce_hdr->header.ucode_size_bytes,
5848 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
5849 &adev->gfx.ce.ce_fw_obj,
5850 &adev->gfx.ce.ce_fw_gpu_addr,
5851 (void **)&adev->gfx.ce.ce_fw_ptr);
5852 if (r) {
5853 dev_err(adev->dev, "(%d) failed to create ce fw bo\n", r);
5854 gfx_v10_0_ce_fini(adev);
5855 return r;
5856 }
5857
5858 memcpy(adev->gfx.ce.ce_fw_ptr, fw_data, fw_size);
5859
5860 amdgpu_bo_kunmap(adev->gfx.ce.ce_fw_obj);
5861 amdgpu_bo_unreserve(adev->gfx.ce.ce_fw_obj);
5862
5863 /* Trigger an invalidation of the L1 instruction caches */
5864 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
5865 tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5866 WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp);
5867
5868 /* Wait for invalidation complete */
5869 for (i = 0; i < usec_timeout; i++) {
5870 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
5871 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL,
5872 INVALIDATE_CACHE_COMPLETE))
5873 break;
5874 udelay(1);
5875 }
5876
5877 if (i >= usec_timeout) {
5878 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5879 return -EINVAL;
5880 }
5881
5882 if (amdgpu_emu_mode == 1)
5883 adev->hdp.funcs->flush_hdp(adev, NULL);
5884
5885 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_CNTL);
5886 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, VMID, 0);
5887 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, CACHE_POLICY, 0);
5888 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, EXE_DISABLE, 0);
5889 tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
5890 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO,
5891 adev->gfx.ce.ce_fw_gpu_addr & 0xFFFFF000);
5892 WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI,
5893 upper_32_bits(adev->gfx.ce.ce_fw_gpu_addr));
5894
5895 WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_ADDR, 0);
5896
5897 for (i = 0; i < ce_hdr->jt_size; i++)
5898 WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_DATA,
5899 le32_to_cpup(fw_data + ce_hdr->jt_offset + i));
5900
5901 WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_ADDR, adev->gfx.ce_fw_version);
5902
5903 return 0;
5904 }
5905
gfx_v10_0_cp_gfx_load_me_microcode(struct amdgpu_device * adev)5906 static int gfx_v10_0_cp_gfx_load_me_microcode(struct amdgpu_device *adev)
5907 {
5908 int r;
5909 const struct gfx_firmware_header_v1_0 *me_hdr;
5910 const __le32 *fw_data;
5911 unsigned i, fw_size;
5912 uint32_t tmp;
5913 uint32_t usec_timeout = 50000; /* wait for 50ms */
5914
5915 me_hdr = (const struct gfx_firmware_header_v1_0 *)
5916 adev->gfx.me_fw->data;
5917
5918 amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
5919
5920 fw_data = (const __le32 *)(adev->gfx.me_fw->data +
5921 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
5922 fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes);
5923
5924 r = amdgpu_bo_create_reserved(adev, me_hdr->header.ucode_size_bytes,
5925 PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
5926 &adev->gfx.me.me_fw_obj,
5927 &adev->gfx.me.me_fw_gpu_addr,
5928 (void **)&adev->gfx.me.me_fw_ptr);
5929 if (r) {
5930 dev_err(adev->dev, "(%d) failed to create me fw bo\n", r);
5931 gfx_v10_0_me_fini(adev);
5932 return r;
5933 }
5934
5935 memcpy(adev->gfx.me.me_fw_ptr, fw_data, fw_size);
5936
5937 amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj);
5938 amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj);
5939
5940 /* Trigger an invalidation of the L1 instruction caches */
5941 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
5942 tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5943 WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp);
5944
5945 /* Wait for invalidation complete */
5946 for (i = 0; i < usec_timeout; i++) {
5947 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
5948 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
5949 INVALIDATE_CACHE_COMPLETE))
5950 break;
5951 udelay(1);
5952 }
5953
5954 if (i >= usec_timeout) {
5955 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5956 return -EINVAL;
5957 }
5958
5959 if (amdgpu_emu_mode == 1)
5960 adev->hdp.funcs->flush_hdp(adev, NULL);
5961
5962 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_CNTL);
5963 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0);
5964 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0);
5965 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0);
5966 tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
5967 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO,
5968 adev->gfx.me.me_fw_gpu_addr & 0xFFFFF000);
5969 WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI,
5970 upper_32_bits(adev->gfx.me.me_fw_gpu_addr));
5971
5972 WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_ADDR, 0);
5973
5974 for (i = 0; i < me_hdr->jt_size; i++)
5975 WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_DATA,
5976 le32_to_cpup(fw_data + me_hdr->jt_offset + i));
5977
5978 WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_ADDR, adev->gfx.me_fw_version);
5979
5980 return 0;
5981 }
5982
gfx_v10_0_cp_gfx_load_microcode(struct amdgpu_device * adev)5983 static int gfx_v10_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
5984 {
5985 int r;
5986
5987 if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
5988 return -EINVAL;
5989
5990 gfx_v10_0_cp_gfx_enable(adev, false);
5991
5992 r = gfx_v10_0_cp_gfx_load_pfp_microcode(adev);
5993 if (r) {
5994 dev_err(adev->dev, "(%d) failed to load pfp fw\n", r);
5995 return r;
5996 }
5997
5998 r = gfx_v10_0_cp_gfx_load_ce_microcode(adev);
5999 if (r) {
6000 dev_err(adev->dev, "(%d) failed to load ce fw\n", r);
6001 return r;
6002 }
6003
6004 r = gfx_v10_0_cp_gfx_load_me_microcode(adev);
6005 if (r) {
6006 dev_err(adev->dev, "(%d) failed to load me fw\n", r);
6007 return r;
6008 }
6009
6010 return 0;
6011 }
6012
gfx_v10_0_cp_gfx_start(struct amdgpu_device * adev)6013 static int gfx_v10_0_cp_gfx_start(struct amdgpu_device *adev)
6014 {
6015 struct amdgpu_ring *ring;
6016 const struct cs_section_def *sect = NULL;
6017 const struct cs_extent_def *ext = NULL;
6018 int r, i;
6019 int ctx_reg_offset;
6020
6021 /* init the CP */
6022 WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT,
6023 adev->gfx.config.max_hw_contexts - 1);
6024 WREG32_SOC15(GC, 0, mmCP_DEVICE_ID, 1);
6025
6026 gfx_v10_0_cp_gfx_enable(adev, true);
6027
6028 ring = &adev->gfx.gfx_ring[0];
6029 r = amdgpu_ring_alloc(ring, gfx_v10_0_get_csb_size(adev) + 4);
6030 if (r) {
6031 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
6032 return r;
6033 }
6034
6035 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
6036 amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
6037
6038 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
6039 amdgpu_ring_write(ring, 0x80000000);
6040 amdgpu_ring_write(ring, 0x80000000);
6041
6042 for (sect = gfx10_cs_data; sect->section != NULL; ++sect) {
6043 for (ext = sect->section; ext->extent != NULL; ++ext) {
6044 if (sect->id == SECT_CONTEXT) {
6045 amdgpu_ring_write(ring,
6046 PACKET3(PACKET3_SET_CONTEXT_REG,
6047 ext->reg_count));
6048 amdgpu_ring_write(ring, ext->reg_index -
6049 PACKET3_SET_CONTEXT_REG_START);
6050 for (i = 0; i < ext->reg_count; i++)
6051 amdgpu_ring_write(ring, ext->extent[i]);
6052 }
6053 }
6054 }
6055
6056 ctx_reg_offset =
6057 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START;
6058 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
6059 amdgpu_ring_write(ring, ctx_reg_offset);
6060 amdgpu_ring_write(ring, adev->gfx.config.pa_sc_tile_steering_override);
6061
6062 amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
6063 amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
6064
6065 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
6066 amdgpu_ring_write(ring, 0);
6067
6068 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
6069 amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
6070 amdgpu_ring_write(ring, 0x8000);
6071 amdgpu_ring_write(ring, 0x8000);
6072
6073 amdgpu_ring_commit(ring);
6074
6075 /* submit cs packet to copy state 0 to next available state */
6076 if (adev->gfx.num_gfx_rings > 1) {
6077 /* maximum supported gfx ring is 2 */
6078 ring = &adev->gfx.gfx_ring[1];
6079 r = amdgpu_ring_alloc(ring, 2);
6080 if (r) {
6081 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
6082 return r;
6083 }
6084
6085 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
6086 amdgpu_ring_write(ring, 0);
6087
6088 amdgpu_ring_commit(ring);
6089 }
6090 return 0;
6091 }
6092
gfx_v10_0_cp_gfx_switch_pipe(struct amdgpu_device * adev,CP_PIPE_ID pipe)6093 static void gfx_v10_0_cp_gfx_switch_pipe(struct amdgpu_device *adev,
6094 CP_PIPE_ID pipe)
6095 {
6096 u32 tmp;
6097
6098 tmp = RREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL);
6099 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, pipe);
6100
6101 WREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL, tmp);
6102 }
6103
gfx_v10_0_cp_gfx_set_doorbell(struct amdgpu_device * adev,struct amdgpu_ring * ring)6104 static void gfx_v10_0_cp_gfx_set_doorbell(struct amdgpu_device *adev,
6105 struct amdgpu_ring *ring)
6106 {
6107 u32 tmp;
6108
6109 if (!amdgpu_async_gfx_ring) {
6110 tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);
6111 if (ring->use_doorbell) {
6112 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6113 DOORBELL_OFFSET, ring->doorbell_index);
6114 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6115 DOORBELL_EN, 1);
6116 } else {
6117 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6118 DOORBELL_EN, 0);
6119 }
6120 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp);
6121 }
6122 switch (adev->ip_versions[GC_HWIP][0]) {
6123 case IP_VERSION(10, 3, 0):
6124 case IP_VERSION(10, 3, 2):
6125 case IP_VERSION(10, 3, 1):
6126 case IP_VERSION(10, 3, 4):
6127 case IP_VERSION(10, 3, 5):
6128 case IP_VERSION(10, 3, 6):
6129 case IP_VERSION(10, 3, 3):
6130 case IP_VERSION(10, 3, 7):
6131 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
6132 DOORBELL_RANGE_LOWER_Sienna_Cichlid, ring->doorbell_index);
6133 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
6134
6135 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER,
6136 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_Sienna_Cichlid_MASK);
6137 break;
6138 default:
6139 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
6140 DOORBELL_RANGE_LOWER, ring->doorbell_index);
6141 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
6142
6143 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER,
6144 CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK);
6145 break;
6146 }
6147 }
6148
gfx_v10_0_cp_gfx_resume(struct amdgpu_device * adev)6149 static int gfx_v10_0_cp_gfx_resume(struct amdgpu_device *adev)
6150 {
6151 struct amdgpu_ring *ring;
6152 u32 tmp;
6153 u32 rb_bufsz;
6154 u64 rb_addr, rptr_addr, wptr_gpu_addr;
6155 u32 i;
6156
6157 /* Set the write pointer delay */
6158 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_DELAY, 0);
6159
6160 /* set the RB to use vmid 0 */
6161 WREG32_SOC15(GC, 0, mmCP_RB_VMID, 0);
6162
6163 /* Init gfx ring 0 for pipe 0 */
6164 mutex_lock(&adev->srbm_mutex);
6165 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0);
6166
6167 /* Set ring buffer size */
6168 ring = &adev->gfx.gfx_ring[0];
6169 rb_bufsz = order_base_2(ring->ring_size / 8);
6170 tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);
6171 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);
6172 #ifdef __BIG_ENDIAN
6173 tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1);
6174 #endif
6175 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
6176
6177 /* Initialize the ring buffer's write pointers */
6178 ring->wptr = 0;
6179 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
6180 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
6181
6182 /* set the wb address wether it's enabled or not */
6183 rptr_addr = ring->rptr_gpu_addr;
6184 WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
6185 WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &
6186 CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
6187
6188 wptr_gpu_addr = ring->wptr_gpu_addr;
6189 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO,
6190 lower_32_bits(wptr_gpu_addr));
6191 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI,
6192 upper_32_bits(wptr_gpu_addr));
6193
6194 mdelay(1);
6195 WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
6196
6197 rb_addr = ring->gpu_addr >> 8;
6198 WREG32_SOC15(GC, 0, mmCP_RB0_BASE, rb_addr);
6199 WREG32_SOC15(GC, 0, mmCP_RB0_BASE_HI, upper_32_bits(rb_addr));
6200
6201 WREG32_SOC15(GC, 0, mmCP_RB_ACTIVE, 1);
6202
6203 gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
6204 mutex_unlock(&adev->srbm_mutex);
6205
6206 /* Init gfx ring 1 for pipe 1 */
6207 if (adev->gfx.num_gfx_rings > 1) {
6208 mutex_lock(&adev->srbm_mutex);
6209 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID1);
6210 /* maximum supported gfx ring is 2 */
6211 ring = &adev->gfx.gfx_ring[1];
6212 rb_bufsz = order_base_2(ring->ring_size / 8);
6213 tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz);
6214 tmp = REG_SET_FIELD(tmp, CP_RB1_CNTL, RB_BLKSZ, rb_bufsz - 2);
6215 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp);
6216 /* Initialize the ring buffer's write pointers */
6217 ring->wptr = 0;
6218 WREG32_SOC15(GC, 0, mmCP_RB1_WPTR, lower_32_bits(ring->wptr));
6219 WREG32_SOC15(GC, 0, mmCP_RB1_WPTR_HI, upper_32_bits(ring->wptr));
6220 /* Set the wb address wether it's enabled or not */
6221 rptr_addr = ring->rptr_gpu_addr;
6222 WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr));
6223 WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &
6224 CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
6225 wptr_gpu_addr = ring->wptr_gpu_addr;
6226 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO,
6227 lower_32_bits(wptr_gpu_addr));
6228 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI,
6229 upper_32_bits(wptr_gpu_addr));
6230
6231 mdelay(1);
6232 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp);
6233
6234 rb_addr = ring->gpu_addr >> 8;
6235 WREG32_SOC15(GC, 0, mmCP_RB1_BASE, rb_addr);
6236 WREG32_SOC15(GC, 0, mmCP_RB1_BASE_HI, upper_32_bits(rb_addr));
6237 WREG32_SOC15(GC, 0, mmCP_RB1_ACTIVE, 1);
6238
6239 gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
6240 mutex_unlock(&adev->srbm_mutex);
6241 }
6242 /* Switch to pipe 0 */
6243 mutex_lock(&adev->srbm_mutex);
6244 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0);
6245 mutex_unlock(&adev->srbm_mutex);
6246
6247 /* start the ring */
6248 gfx_v10_0_cp_gfx_start(adev);
6249
6250 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
6251 ring = &adev->gfx.gfx_ring[i];
6252 ring->sched.ready = true;
6253 }
6254
6255 return 0;
6256 }
6257
gfx_v10_0_cp_compute_enable(struct amdgpu_device * adev,bool enable)6258 static void gfx_v10_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
6259 {
6260 if (enable) {
6261 switch (adev->ip_versions[GC_HWIP][0]) {
6262 case IP_VERSION(10, 3, 0):
6263 case IP_VERSION(10, 3, 2):
6264 case IP_VERSION(10, 3, 1):
6265 case IP_VERSION(10, 3, 4):
6266 case IP_VERSION(10, 3, 5):
6267 case IP_VERSION(10, 3, 6):
6268 case IP_VERSION(10, 3, 3):
6269 case IP_VERSION(10, 3, 7):
6270 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid, 0);
6271 break;
6272 default:
6273 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 0);
6274 break;
6275 }
6276 } else {
6277 switch (adev->ip_versions[GC_HWIP][0]) {
6278 case IP_VERSION(10, 3, 0):
6279 case IP_VERSION(10, 3, 2):
6280 case IP_VERSION(10, 3, 1):
6281 case IP_VERSION(10, 3, 4):
6282 case IP_VERSION(10, 3, 5):
6283 case IP_VERSION(10, 3, 6):
6284 case IP_VERSION(10, 3, 3):
6285 case IP_VERSION(10, 3, 7):
6286 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid,
6287 (CP_MEC_CNTL__MEC_ME1_HALT_MASK |
6288 CP_MEC_CNTL__MEC_ME2_HALT_MASK));
6289 break;
6290 default:
6291 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL,
6292 (CP_MEC_CNTL__MEC_ME1_HALT_MASK |
6293 CP_MEC_CNTL__MEC_ME2_HALT_MASK));
6294 break;
6295 }
6296 adev->gfx.kiq.ring.sched.ready = false;
6297 }
6298 udelay(50);
6299 }
6300
gfx_v10_0_cp_compute_load_microcode(struct amdgpu_device * adev)6301 static int gfx_v10_0_cp_compute_load_microcode(struct amdgpu_device *adev)
6302 {
6303 const struct gfx_firmware_header_v1_0 *mec_hdr;
6304 const __le32 *fw_data;
6305 unsigned i;
6306 u32 tmp;
6307 u32 usec_timeout = 50000; /* Wait for 50 ms */
6308
6309 if (!adev->gfx.mec_fw)
6310 return -EINVAL;
6311
6312 gfx_v10_0_cp_compute_enable(adev, false);
6313
6314 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
6315 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
6316
6317 fw_data = (const __le32 *)
6318 (adev->gfx.mec_fw->data +
6319 le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
6320
6321 /* Trigger an invalidation of the L1 instruction caches */
6322 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
6323 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);
6324 WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp);
6325
6326 /* Wait for invalidation complete */
6327 for (i = 0; i < usec_timeout; i++) {
6328 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
6329 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL,
6330 INVALIDATE_CACHE_COMPLETE))
6331 break;
6332 udelay(1);
6333 }
6334
6335 if (i >= usec_timeout) {
6336 dev_err(adev->dev, "failed to invalidate instruction cache\n");
6337 return -EINVAL;
6338 }
6339
6340 if (amdgpu_emu_mode == 1)
6341 adev->hdp.funcs->flush_hdp(adev, NULL);
6342
6343 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL);
6344 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);
6345 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0);
6346 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
6347 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL, tmp);
6348
6349 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, adev->gfx.mec.mec_fw_gpu_addr &
6350 0xFFFFF000);
6351 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI,
6352 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr));
6353
6354 /* MEC1 */
6355 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, 0);
6356
6357 for (i = 0; i < mec_hdr->jt_size; i++)
6358 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_DATA,
6359 le32_to_cpup(fw_data + mec_hdr->jt_offset + i));
6360
6361 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version);
6362
6363 /*
6364 * TODO: Loading MEC2 firmware is only necessary if MEC2 should run
6365 * different microcode than MEC1.
6366 */
6367
6368 return 0;
6369 }
6370
gfx_v10_0_kiq_setting(struct amdgpu_ring * ring)6371 static void gfx_v10_0_kiq_setting(struct amdgpu_ring *ring)
6372 {
6373 uint32_t tmp;
6374 struct amdgpu_device *adev = ring->adev;
6375
6376 /* tell RLC which is KIQ queue */
6377 switch (adev->ip_versions[GC_HWIP][0]) {
6378 case IP_VERSION(10, 3, 0):
6379 case IP_VERSION(10, 3, 2):
6380 case IP_VERSION(10, 3, 1):
6381 case IP_VERSION(10, 3, 4):
6382 case IP_VERSION(10, 3, 5):
6383 case IP_VERSION(10, 3, 6):
6384 case IP_VERSION(10, 3, 3):
6385 case IP_VERSION(10, 3, 7):
6386 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid);
6387 tmp &= 0xffffff00;
6388 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
6389 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp);
6390 tmp |= 0x80;
6391 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp);
6392 break;
6393 default:
6394 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);
6395 tmp &= 0xffffff00;
6396 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
6397 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
6398 tmp |= 0x80;
6399 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
6400 break;
6401 }
6402 }
6403
gfx_v10_0_gfx_mqd_set_priority(struct amdgpu_device * adev,struct v10_gfx_mqd * mqd,struct amdgpu_mqd_prop * prop)6404 static void gfx_v10_0_gfx_mqd_set_priority(struct amdgpu_device *adev,
6405 struct v10_gfx_mqd *mqd,
6406 struct amdgpu_mqd_prop *prop)
6407 {
6408 bool priority = 0;
6409 u32 tmp;
6410
6411 /* set up default queue priority level
6412 * 0x0 = low priority, 0x1 = high priority
6413 */
6414 if (prop->hqd_pipe_priority == AMDGPU_GFX_PIPE_PRIO_HIGH)
6415 priority = 1;
6416
6417 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY);
6418 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, priority);
6419 mqd->cp_gfx_hqd_queue_priority = tmp;
6420 }
6421
gfx_v10_0_gfx_mqd_init(struct amdgpu_device * adev,void * m,struct amdgpu_mqd_prop * prop)6422 static int gfx_v10_0_gfx_mqd_init(struct amdgpu_device *adev, void *m,
6423 struct amdgpu_mqd_prop *prop)
6424 {
6425 struct v10_gfx_mqd *mqd = m;
6426 uint64_t hqd_gpu_addr, wb_gpu_addr;
6427 uint32_t tmp;
6428 uint32_t rb_bufsz;
6429
6430 /* set up gfx hqd wptr */
6431 mqd->cp_gfx_hqd_wptr = 0;
6432 mqd->cp_gfx_hqd_wptr_hi = 0;
6433
6434 /* set the pointer to the MQD */
6435 mqd->cp_mqd_base_addr = prop->mqd_gpu_addr & 0xfffffffc;
6436 mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr);
6437
6438 /* set up mqd control */
6439 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL);
6440 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0);
6441 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1);
6442 tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0);
6443 mqd->cp_gfx_mqd_control = tmp;
6444
6445 /* set up gfx_hqd_vimd with 0x0 to indicate the ring buffer's vmid */
6446 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID);
6447 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0);
6448 mqd->cp_gfx_hqd_vmid = 0;
6449
6450 /* set up gfx queue priority */
6451 gfx_v10_0_gfx_mqd_set_priority(adev, mqd, prop);
6452
6453 /* set up time quantum */
6454 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM);
6455 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1);
6456 mqd->cp_gfx_hqd_quantum = tmp;
6457
6458 /* set up gfx hqd base. this is similar as CP_RB_BASE */
6459 hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8;
6460 mqd->cp_gfx_hqd_base = hqd_gpu_addr;
6461 mqd->cp_gfx_hqd_base_hi = upper_32_bits(hqd_gpu_addr);
6462
6463 /* set up hqd_rptr_addr/_hi, similar as CP_RB_RPTR */
6464 wb_gpu_addr = prop->rptr_gpu_addr;
6465 mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc;
6466 mqd->cp_gfx_hqd_rptr_addr_hi =
6467 upper_32_bits(wb_gpu_addr) & 0xffff;
6468
6469 /* set up rb_wptr_poll addr */
6470 wb_gpu_addr = prop->wptr_gpu_addr;
6471 mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
6472 mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
6473
6474 /* set up the gfx_hqd_control, similar as CP_RB0_CNTL */
6475 rb_bufsz = order_base_2(prop->queue_size / 4) - 1;
6476 tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL);
6477 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz);
6478 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2);
6479 #ifdef __BIG_ENDIAN
6480 tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, BUF_SWAP, 1);
6481 #endif
6482 mqd->cp_gfx_hqd_cntl = tmp;
6483
6484 /* set up cp_doorbell_control */
6485 tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);
6486 if (prop->use_doorbell) {
6487 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6488 DOORBELL_OFFSET, prop->doorbell_index);
6489 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6490 DOORBELL_EN, 1);
6491 } else
6492 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6493 DOORBELL_EN, 0);
6494 mqd->cp_rb_doorbell_control = tmp;
6495
6496 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
6497 mqd->cp_gfx_hqd_rptr = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR);
6498
6499 /* active the queue */
6500 mqd->cp_gfx_hqd_active = 1;
6501
6502 return 0;
6503 }
6504
6505 #ifdef BRING_UP_DEBUG
gfx_v10_0_gfx_queue_init_register(struct amdgpu_ring * ring)6506 static int gfx_v10_0_gfx_queue_init_register(struct amdgpu_ring *ring)
6507 {
6508 struct amdgpu_device *adev = ring->adev;
6509 struct v10_gfx_mqd *mqd = ring->mqd_ptr;
6510
6511 /* set mmCP_GFX_HQD_WPTR/_HI to 0 */
6512 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_WPTR, mqd->cp_gfx_hqd_wptr);
6513 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_WPTR_HI, mqd->cp_gfx_hqd_wptr_hi);
6514
6515 /* set GFX_MQD_BASE */
6516 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr);
6517 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi);
6518
6519 /* set GFX_MQD_CONTROL */
6520 WREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL, mqd->cp_gfx_mqd_control);
6521
6522 /* set GFX_HQD_VMID to 0 */
6523 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID, mqd->cp_gfx_hqd_vmid);
6524
6525 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY,
6526 mqd->cp_gfx_hqd_queue_priority);
6527 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM, mqd->cp_gfx_hqd_quantum);
6528
6529 /* set GFX_HQD_BASE, similar as CP_RB_BASE */
6530 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_BASE, mqd->cp_gfx_hqd_base);
6531 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_BASE_HI, mqd->cp_gfx_hqd_base_hi);
6532
6533 /* set GFX_HQD_RPTR_ADDR, similar as CP_RB_RPTR */
6534 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR_ADDR, mqd->cp_gfx_hqd_rptr_addr);
6535 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR_ADDR_HI, mqd->cp_gfx_hqd_rptr_addr_hi);
6536
6537 /* set GFX_HQD_CNTL, similar as CP_RB_CNTL */
6538 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL, mqd->cp_gfx_hqd_cntl);
6539
6540 /* set RB_WPTR_POLL_ADDR */
6541 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, mqd->cp_rb_wptr_poll_addr_lo);
6542 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, mqd->cp_rb_wptr_poll_addr_hi);
6543
6544 /* set RB_DOORBELL_CONTROL */
6545 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, mqd->cp_rb_doorbell_control);
6546
6547 /* active the queue */
6548 WREG32_SOC15(GC, 0, mmCP_GFX_HQD_ACTIVE, mqd->cp_gfx_hqd_active);
6549
6550 return 0;
6551 }
6552 #endif
6553
gfx_v10_0_gfx_init_queue(struct amdgpu_ring * ring)6554 static int gfx_v10_0_gfx_init_queue(struct amdgpu_ring *ring)
6555 {
6556 struct amdgpu_device *adev = ring->adev;
6557 struct v10_gfx_mqd *mqd = ring->mqd_ptr;
6558 int mqd_idx = ring - &adev->gfx.gfx_ring[0];
6559
6560 if (!amdgpu_in_reset(adev) && !adev->in_suspend) {
6561 memset((void *)mqd, 0, sizeof(*mqd));
6562 mutex_lock(&adev->srbm_mutex);
6563 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6564 amdgpu_ring_init_mqd(ring);
6565
6566 /*
6567 * if there are 2 gfx rings, set the lower doorbell
6568 * range of the first ring, otherwise the range of
6569 * the second ring will override the first ring
6570 */
6571 if (ring->doorbell_index == adev->doorbell_index.gfx_ring0 << 1)
6572 gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
6573
6574 #ifdef BRING_UP_DEBUG
6575 gfx_v10_0_gfx_queue_init_register(ring);
6576 #endif
6577 nv_grbm_select(adev, 0, 0, 0, 0);
6578 mutex_unlock(&adev->srbm_mutex);
6579 if (adev->gfx.me.mqd_backup[mqd_idx])
6580 memcpy(adev->gfx.me.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
6581 } else if (amdgpu_in_reset(adev)) {
6582 /* reset mqd with the backup copy */
6583 if (adev->gfx.me.mqd_backup[mqd_idx])
6584 memcpy(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd));
6585 /* reset the ring */
6586 ring->wptr = 0;
6587 *ring->wptr_cpu_addr = 0;
6588 amdgpu_ring_clear_ring(ring);
6589 #ifdef BRING_UP_DEBUG
6590 mutex_lock(&adev->srbm_mutex);
6591 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6592 gfx_v10_0_gfx_queue_init_register(ring);
6593 nv_grbm_select(adev, 0, 0, 0, 0);
6594 mutex_unlock(&adev->srbm_mutex);
6595 #endif
6596 } else {
6597 amdgpu_ring_clear_ring(ring);
6598 }
6599
6600 return 0;
6601 }
6602
6603 #ifndef BRING_UP_DEBUG
gfx_v10_0_kiq_enable_kgq(struct amdgpu_device * adev)6604 static int gfx_v10_0_kiq_enable_kgq(struct amdgpu_device *adev)
6605 {
6606 struct amdgpu_kiq *kiq = &adev->gfx.kiq;
6607 struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring;
6608 int r, i;
6609
6610 if (!kiq->pmf || !kiq->pmf->kiq_map_queues)
6611 return -EINVAL;
6612
6613 r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size *
6614 adev->gfx.num_gfx_rings);
6615 if (r) {
6616 DRM_ERROR("Failed to lock KIQ (%d).\n", r);
6617 return r;
6618 }
6619
6620 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
6621 kiq->pmf->kiq_map_queues(kiq_ring, &adev->gfx.gfx_ring[i]);
6622
6623 return amdgpu_ring_test_helper(kiq_ring);
6624 }
6625 #endif
6626
gfx_v10_0_cp_async_gfx_ring_resume(struct amdgpu_device * adev)6627 static int gfx_v10_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev)
6628 {
6629 int r, i;
6630 struct amdgpu_ring *ring;
6631
6632 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
6633 ring = &adev->gfx.gfx_ring[i];
6634
6635 r = amdgpu_bo_reserve(ring->mqd_obj, false);
6636 if (unlikely(r != 0))
6637 goto done;
6638
6639 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
6640 if (!r) {
6641 r = gfx_v10_0_gfx_init_queue(ring);
6642 amdgpu_bo_kunmap(ring->mqd_obj);
6643 ring->mqd_ptr = NULL;
6644 }
6645 amdgpu_bo_unreserve(ring->mqd_obj);
6646 if (r)
6647 goto done;
6648 }
6649 #ifndef BRING_UP_DEBUG
6650 r = gfx_v10_0_kiq_enable_kgq(adev);
6651 if (r)
6652 goto done;
6653 #endif
6654 r = gfx_v10_0_cp_gfx_start(adev);
6655 if (r)
6656 goto done;
6657
6658 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
6659 ring = &adev->gfx.gfx_ring[i];
6660 ring->sched.ready = true;
6661 }
6662 done:
6663 return r;
6664 }
6665
gfx_v10_0_compute_mqd_init(struct amdgpu_device * adev,void * m,struct amdgpu_mqd_prop * prop)6666 static int gfx_v10_0_compute_mqd_init(struct amdgpu_device *adev, void *m,
6667 struct amdgpu_mqd_prop *prop)
6668 {
6669 struct v10_compute_mqd *mqd = m;
6670 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr;
6671 uint32_t tmp;
6672
6673 mqd->header = 0xC0310800;
6674 mqd->compute_pipelinestat_enable = 0x00000001;
6675 mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
6676 mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
6677 mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
6678 mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
6679 mqd->compute_misc_reserved = 0x00000003;
6680
6681 eop_base_addr = prop->eop_gpu_addr >> 8;
6682 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr;
6683 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);
6684
6685 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
6686 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL);
6687 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
6688 (order_base_2(GFX10_MEC_HPD_SIZE / 4) - 1));
6689
6690 mqd->cp_hqd_eop_control = tmp;
6691
6692 /* enable doorbell? */
6693 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
6694
6695 if (prop->use_doorbell) {
6696 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6697 DOORBELL_OFFSET, prop->doorbell_index);
6698 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6699 DOORBELL_EN, 1);
6700 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6701 DOORBELL_SOURCE, 0);
6702 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6703 DOORBELL_HIT, 0);
6704 } else {
6705 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6706 DOORBELL_EN, 0);
6707 }
6708
6709 mqd->cp_hqd_pq_doorbell_control = tmp;
6710
6711 /* disable the queue if it's active */
6712 mqd->cp_hqd_dequeue_request = 0;
6713 mqd->cp_hqd_pq_rptr = 0;
6714 mqd->cp_hqd_pq_wptr_lo = 0;
6715 mqd->cp_hqd_pq_wptr_hi = 0;
6716
6717 /* set the pointer to the MQD */
6718 mqd->cp_mqd_base_addr_lo = prop->mqd_gpu_addr & 0xfffffffc;
6719 mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr);
6720
6721 /* set MQD vmid to 0 */
6722 tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL);
6723 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
6724 mqd->cp_mqd_control = tmp;
6725
6726 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
6727 hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8;
6728 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;
6729 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
6730
6731 /* set up the HQD, this is similar to CP_RB0_CNTL */
6732 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL);
6733 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
6734 (order_base_2(prop->queue_size / 4) - 1));
6735 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
6736 (order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1));
6737 #ifdef __BIG_ENDIAN
6738 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
6739 #endif
6740 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);
6741 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0);
6742 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
6743 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
6744 mqd->cp_hqd_pq_control = tmp;
6745
6746 /* set the wb address whether it's enabled or not */
6747 wb_gpu_addr = prop->rptr_gpu_addr;
6748 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
6749 mqd->cp_hqd_pq_rptr_report_addr_hi =
6750 upper_32_bits(wb_gpu_addr) & 0xffff;
6751
6752 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
6753 wb_gpu_addr = prop->wptr_gpu_addr;
6754 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
6755 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
6756
6757 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
6758 mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR);
6759
6760 /* set the vmid for the queue */
6761 mqd->cp_hqd_vmid = 0;
6762
6763 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE);
6764 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);
6765 mqd->cp_hqd_persistent_state = tmp;
6766
6767 /* set MIN_IB_AVAIL_SIZE */
6768 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL);
6769 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3);
6770 mqd->cp_hqd_ib_control = tmp;
6771
6772 /* set static priority for a compute queue/ring */
6773 mqd->cp_hqd_pipe_priority = prop->hqd_pipe_priority;
6774 mqd->cp_hqd_queue_priority = prop->hqd_queue_priority;
6775
6776 mqd->cp_hqd_active = prop->hqd_active;
6777
6778 return 0;
6779 }
6780
gfx_v10_0_kiq_init_register(struct amdgpu_ring * ring)6781 static int gfx_v10_0_kiq_init_register(struct amdgpu_ring *ring)
6782 {
6783 struct amdgpu_device *adev = ring->adev;
6784 struct v10_compute_mqd *mqd = ring->mqd_ptr;
6785 int j;
6786
6787 /* inactivate the queue */
6788 if (amdgpu_sriov_vf(adev))
6789 WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, 0);
6790
6791 /* disable wptr polling */
6792 WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0);
6793
6794 /* disable the queue if it's active */
6795 if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) {
6796 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1);
6797 for (j = 0; j < adev->usec_timeout; j++) {
6798 if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1))
6799 break;
6800 udelay(1);
6801 }
6802 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST,
6803 mqd->cp_hqd_dequeue_request);
6804 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR,
6805 mqd->cp_hqd_pq_rptr);
6806 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
6807 mqd->cp_hqd_pq_wptr_lo);
6808 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
6809 mqd->cp_hqd_pq_wptr_hi);
6810 }
6811
6812 /* disable doorbells */
6813 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 0);
6814
6815 /* write the EOP addr */
6816 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR,
6817 mqd->cp_hqd_eop_base_addr_lo);
6818 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI,
6819 mqd->cp_hqd_eop_base_addr_hi);
6820
6821 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
6822 WREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL,
6823 mqd->cp_hqd_eop_control);
6824
6825 /* set the pointer to the MQD */
6826 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR,
6827 mqd->cp_mqd_base_addr_lo);
6828 WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI,
6829 mqd->cp_mqd_base_addr_hi);
6830
6831 /* set MQD vmid to 0 */
6832 WREG32_SOC15(GC, 0, mmCP_MQD_CONTROL,
6833 mqd->cp_mqd_control);
6834
6835 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
6836 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE,
6837 mqd->cp_hqd_pq_base_lo);
6838 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI,
6839 mqd->cp_hqd_pq_base_hi);
6840
6841 /* set up the HQD, this is similar to CP_RB0_CNTL */
6842 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL,
6843 mqd->cp_hqd_pq_control);
6844
6845 /* set the wb address whether it's enabled or not */
6846 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR,
6847 mqd->cp_hqd_pq_rptr_report_addr_lo);
6848 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
6849 mqd->cp_hqd_pq_rptr_report_addr_hi);
6850
6851 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
6852 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR,
6853 mqd->cp_hqd_pq_wptr_poll_addr_lo);
6854 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,
6855 mqd->cp_hqd_pq_wptr_poll_addr_hi);
6856
6857 /* enable the doorbell if requested */
6858 if (ring->use_doorbell) {
6859 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER,
6860 (adev->doorbell_index.kiq * 2) << 2);
6861 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER,
6862 (adev->doorbell_index.userqueue_end * 2) << 2);
6863 }
6864
6865 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
6866 mqd->cp_hqd_pq_doorbell_control);
6867
6868 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
6869 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
6870 mqd->cp_hqd_pq_wptr_lo);
6871 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
6872 mqd->cp_hqd_pq_wptr_hi);
6873
6874 /* set the vmid for the queue */
6875 WREG32_SOC15(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid);
6876
6877 WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE,
6878 mqd->cp_hqd_persistent_state);
6879
6880 /* activate the queue */
6881 WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE,
6882 mqd->cp_hqd_active);
6883
6884 if (ring->use_doorbell)
6885 WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1);
6886
6887 return 0;
6888 }
6889
gfx_v10_0_kiq_init_queue(struct amdgpu_ring * ring)6890 static int gfx_v10_0_kiq_init_queue(struct amdgpu_ring *ring)
6891 {
6892 struct amdgpu_device *adev = ring->adev;
6893 struct v10_compute_mqd *mqd = ring->mqd_ptr;
6894 int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS;
6895
6896 gfx_v10_0_kiq_setting(ring);
6897
6898 if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */
6899 /* reset MQD to a clean status */
6900 if (adev->gfx.mec.mqd_backup[mqd_idx])
6901 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd));
6902
6903 /* reset ring buffer */
6904 ring->wptr = 0;
6905 amdgpu_ring_clear_ring(ring);
6906
6907 mutex_lock(&adev->srbm_mutex);
6908 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6909 gfx_v10_0_kiq_init_register(ring);
6910 nv_grbm_select(adev, 0, 0, 0, 0);
6911 mutex_unlock(&adev->srbm_mutex);
6912 } else {
6913 memset((void *)mqd, 0, sizeof(*mqd));
6914 mutex_lock(&adev->srbm_mutex);
6915 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6916 amdgpu_ring_init_mqd(ring);
6917 gfx_v10_0_kiq_init_register(ring);
6918 nv_grbm_select(adev, 0, 0, 0, 0);
6919 mutex_unlock(&adev->srbm_mutex);
6920
6921 if (adev->gfx.mec.mqd_backup[mqd_idx])
6922 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
6923 }
6924
6925 return 0;
6926 }
6927
gfx_v10_0_kcq_init_queue(struct amdgpu_ring * ring)6928 static int gfx_v10_0_kcq_init_queue(struct amdgpu_ring *ring)
6929 {
6930 struct amdgpu_device *adev = ring->adev;
6931 struct v10_compute_mqd *mqd = ring->mqd_ptr;
6932 int mqd_idx = ring - &adev->gfx.compute_ring[0];
6933
6934 if (!amdgpu_in_reset(adev) && !adev->in_suspend) {
6935 memset((void *)mqd, 0, sizeof(*mqd));
6936 mutex_lock(&adev->srbm_mutex);
6937 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6938 amdgpu_ring_init_mqd(ring);
6939 nv_grbm_select(adev, 0, 0, 0, 0);
6940 mutex_unlock(&adev->srbm_mutex);
6941
6942 if (adev->gfx.mec.mqd_backup[mqd_idx])
6943 memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
6944 } else if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */
6945 /* reset MQD to a clean status */
6946 if (adev->gfx.mec.mqd_backup[mqd_idx])
6947 memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd));
6948
6949 /* reset ring buffer */
6950 ring->wptr = 0;
6951 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 0);
6952 amdgpu_ring_clear_ring(ring);
6953 } else {
6954 amdgpu_ring_clear_ring(ring);
6955 }
6956
6957 return 0;
6958 }
6959
gfx_v10_0_kiq_resume(struct amdgpu_device * adev)6960 static int gfx_v10_0_kiq_resume(struct amdgpu_device *adev)
6961 {
6962 struct amdgpu_ring *ring;
6963 int r;
6964
6965 ring = &adev->gfx.kiq.ring;
6966
6967 r = amdgpu_bo_reserve(ring->mqd_obj, false);
6968 if (unlikely(r != 0))
6969 return r;
6970
6971 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
6972 if (unlikely(r != 0))
6973 return r;
6974
6975 gfx_v10_0_kiq_init_queue(ring);
6976 amdgpu_bo_kunmap(ring->mqd_obj);
6977 ring->mqd_ptr = NULL;
6978 amdgpu_bo_unreserve(ring->mqd_obj);
6979 ring->sched.ready = true;
6980 return 0;
6981 }
6982
gfx_v10_0_kcq_resume(struct amdgpu_device * adev)6983 static int gfx_v10_0_kcq_resume(struct amdgpu_device *adev)
6984 {
6985 struct amdgpu_ring *ring = NULL;
6986 int r = 0, i;
6987
6988 gfx_v10_0_cp_compute_enable(adev, true);
6989
6990 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
6991 ring = &adev->gfx.compute_ring[i];
6992
6993 r = amdgpu_bo_reserve(ring->mqd_obj, false);
6994 if (unlikely(r != 0))
6995 goto done;
6996 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
6997 if (!r) {
6998 r = gfx_v10_0_kcq_init_queue(ring);
6999 amdgpu_bo_kunmap(ring->mqd_obj);
7000 ring->mqd_ptr = NULL;
7001 }
7002 amdgpu_bo_unreserve(ring->mqd_obj);
7003 if (r)
7004 goto done;
7005 }
7006
7007 r = amdgpu_gfx_enable_kcq(adev);
7008 done:
7009 return r;
7010 }
7011
gfx_v10_0_cp_resume(struct amdgpu_device * adev)7012 static int gfx_v10_0_cp_resume(struct amdgpu_device *adev)
7013 {
7014 int r, i;
7015 struct amdgpu_ring *ring;
7016
7017 if (!(adev->flags & AMD_IS_APU))
7018 gfx_v10_0_enable_gui_idle_interrupt(adev, false);
7019
7020 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
7021 /* legacy firmware loading */
7022 r = gfx_v10_0_cp_gfx_load_microcode(adev);
7023 if (r)
7024 return r;
7025
7026 r = gfx_v10_0_cp_compute_load_microcode(adev);
7027 if (r)
7028 return r;
7029 }
7030
7031 if (adev->enable_mes_kiq && adev->mes.kiq_hw_init)
7032 r = amdgpu_mes_kiq_hw_init(adev);
7033 else
7034 r = gfx_v10_0_kiq_resume(adev);
7035 if (r)
7036 return r;
7037
7038 r = gfx_v10_0_kcq_resume(adev);
7039 if (r)
7040 return r;
7041
7042 if (!amdgpu_async_gfx_ring) {
7043 r = gfx_v10_0_cp_gfx_resume(adev);
7044 if (r)
7045 return r;
7046 } else {
7047 r = gfx_v10_0_cp_async_gfx_ring_resume(adev);
7048 if (r)
7049 return r;
7050 }
7051
7052 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
7053 ring = &adev->gfx.gfx_ring[i];
7054 r = amdgpu_ring_test_helper(ring);
7055 if (r)
7056 return r;
7057 }
7058
7059 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
7060 ring = &adev->gfx.compute_ring[i];
7061 r = amdgpu_ring_test_helper(ring);
7062 if (r)
7063 return r;
7064 }
7065
7066 return 0;
7067 }
7068
gfx_v10_0_cp_enable(struct amdgpu_device * adev,bool enable)7069 static void gfx_v10_0_cp_enable(struct amdgpu_device *adev, bool enable)
7070 {
7071 gfx_v10_0_cp_gfx_enable(adev, enable);
7072 gfx_v10_0_cp_compute_enable(adev, enable);
7073 }
7074
gfx_v10_0_check_grbm_cam_remapping(struct amdgpu_device * adev)7075 static bool gfx_v10_0_check_grbm_cam_remapping(struct amdgpu_device *adev)
7076 {
7077 uint32_t data, pattern = 0xDEADBEEF;
7078
7079 /* check if mmVGT_ESGS_RING_SIZE_UMD
7080 * has been remapped to mmVGT_ESGS_RING_SIZE */
7081 switch (adev->ip_versions[GC_HWIP][0]) {
7082 case IP_VERSION(10, 3, 0):
7083 case IP_VERSION(10, 3, 2):
7084 case IP_VERSION(10, 3, 4):
7085 case IP_VERSION(10, 3, 5):
7086 data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid);
7087 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, 0);
7088 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern);
7089
7090 if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) == pattern) {
7091 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD , data);
7092 return true;
7093 } else {
7094 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, data);
7095 return false;
7096 }
7097 break;
7098 case IP_VERSION(10, 3, 1):
7099 case IP_VERSION(10, 3, 3):
7100 case IP_VERSION(10, 3, 6):
7101 case IP_VERSION(10, 3, 7):
7102 return true;
7103 default:
7104 data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE);
7105 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, 0);
7106 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern);
7107
7108 if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE) == pattern) {
7109 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, data);
7110 return true;
7111 } else {
7112 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, data);
7113 return false;
7114 }
7115 break;
7116 }
7117 }
7118
gfx_v10_0_setup_grbm_cam_remapping(struct amdgpu_device * adev)7119 static void gfx_v10_0_setup_grbm_cam_remapping(struct amdgpu_device *adev)
7120 {
7121 uint32_t data;
7122
7123 if (amdgpu_sriov_vf(adev))
7124 return;
7125
7126 /* initialize cam_index to 0
7127 * index will auto-inc after each data writting */
7128 WREG32_SOC15(GC, 0, mmGRBM_CAM_INDEX, 0);
7129
7130 switch (adev->ip_versions[GC_HWIP][0]) {
7131 case IP_VERSION(10, 3, 0):
7132 case IP_VERSION(10, 3, 2):
7133 case IP_VERSION(10, 3, 1):
7134 case IP_VERSION(10, 3, 4):
7135 case IP_VERSION(10, 3, 5):
7136 case IP_VERSION(10, 3, 6):
7137 case IP_VERSION(10, 3, 3):
7138 case IP_VERSION(10, 3, 7):
7139 /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */
7140 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) <<
7141 GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7142 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_Sienna_Cichlid) <<
7143 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7144 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7145 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7146
7147 /* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */
7148 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) <<
7149 GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7150 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_Sienna_Cichlid) <<
7151 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7152 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7153 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7154
7155 /* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */
7156 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) <<
7157 GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7158 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid) <<
7159 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7160 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7161 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7162
7163 /* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */
7164 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) <<
7165 GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7166 (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid) <<
7167 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7168 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7169 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7170
7171 /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */
7172 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) <<
7173 GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7174 (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) <<
7175 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7176 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7177 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7178
7179 /* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */
7180 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) <<
7181 GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7182 (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_Sienna_Cichlid) <<
7183 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7184 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7185 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7186
7187 /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */
7188 data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) <<
7189 GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7190 (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_Sienna_Cichlid) <<
7191 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7192 break;
7193 default:
7194 /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */
7195 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) <<
7196 GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7197 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE) <<
7198 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7199 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7200 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7201
7202 /* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */
7203 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) <<
7204 GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7205 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE) <<
7206 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7207 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7208 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7209
7210 /* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */
7211 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) <<
7212 GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7213 (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI) <<
7214 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7215 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7216 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7217
7218 /* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */
7219 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) <<
7220 GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7221 (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM) <<
7222 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7223 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7224 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7225
7226 /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */
7227 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) <<
7228 GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7229 (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE) <<
7230 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7231 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7232 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7233
7234 /* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */
7235 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) <<
7236 GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7237 (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE) <<
7238 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7239 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7240 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7241
7242 /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */
7243 data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) <<
7244 GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
7245 (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL) <<
7246 GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
7247 break;
7248 }
7249
7250 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
7251 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
7252 }
7253
gfx_v10_0_disable_gpa_mode(struct amdgpu_device * adev)7254 static void gfx_v10_0_disable_gpa_mode(struct amdgpu_device *adev)
7255 {
7256 uint32_t data;
7257 data = RREG32_SOC15(GC, 0, mmCPC_PSP_DEBUG);
7258 data |= CPC_PSP_DEBUG__GPA_OVERRIDE_MASK;
7259 WREG32_SOC15(GC, 0, mmCPC_PSP_DEBUG, data);
7260
7261 data = RREG32_SOC15(GC, 0, mmCPG_PSP_DEBUG);
7262 data |= CPG_PSP_DEBUG__GPA_OVERRIDE_MASK;
7263 WREG32_SOC15(GC, 0, mmCPG_PSP_DEBUG, data);
7264 }
7265
gfx_v10_0_hw_init(void * handle)7266 static int gfx_v10_0_hw_init(void *handle)
7267 {
7268 int r;
7269 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7270
7271 if (!amdgpu_emu_mode)
7272 gfx_v10_0_init_golden_registers(adev);
7273
7274 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
7275 /**
7276 * For gfx 10, rlc firmware loading relies on smu firmware is
7277 * loaded firstly, so in direct type, it has to load smc ucode
7278 * here before rlc.
7279 */
7280 if (!(adev->flags & AMD_IS_APU)) {
7281 r = amdgpu_pm_load_smu_firmware(adev, NULL);
7282 if (r)
7283 return r;
7284 }
7285 gfx_v10_0_disable_gpa_mode(adev);
7286 }
7287
7288 /* if GRBM CAM not remapped, set up the remapping */
7289 if (!gfx_v10_0_check_grbm_cam_remapping(adev))
7290 gfx_v10_0_setup_grbm_cam_remapping(adev);
7291
7292 gfx_v10_0_constants_init(adev);
7293
7294 r = gfx_v10_0_rlc_resume(adev);
7295 if (r)
7296 return r;
7297
7298 /*
7299 * init golden registers and rlc resume may override some registers,
7300 * reconfig them here
7301 */
7302 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 10) ||
7303 adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 1) ||
7304 adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 2))
7305 gfx_v10_0_tcp_harvest(adev);
7306
7307 r = gfx_v10_0_cp_resume(adev);
7308 if (r)
7309 return r;
7310
7311 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 0))
7312 gfx_v10_3_program_pbb_mode(adev);
7313
7314 if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 3, 0))
7315 gfx_v10_3_set_power_brake_sequence(adev);
7316
7317 return r;
7318 }
7319
7320 #ifndef BRING_UP_DEBUG
gfx_v10_0_kiq_disable_kgq(struct amdgpu_device * adev)7321 static int gfx_v10_0_kiq_disable_kgq(struct amdgpu_device *adev)
7322 {
7323 struct amdgpu_kiq *kiq = &adev->gfx.kiq;
7324 struct amdgpu_ring *kiq_ring = &kiq->ring;
7325 int i;
7326
7327 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
7328 return -EINVAL;
7329
7330 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size *
7331 adev->gfx.num_gfx_rings))
7332 return -ENOMEM;
7333
7334 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
7335 kiq->pmf->kiq_unmap_queues(kiq_ring, &adev->gfx.gfx_ring[i],
7336 PREEMPT_QUEUES, 0, 0);
7337 if (!adev->job_hang)
7338 return amdgpu_ring_test_helper(kiq_ring);
7339 else
7340 return 0;
7341 }
7342 #endif
7343
gfx_v10_0_hw_fini(void * handle)7344 static int gfx_v10_0_hw_fini(void *handle)
7345 {
7346 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7347 int r;
7348 uint32_t tmp;
7349
7350 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
7351 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
7352
7353 if (!adev->no_hw_access) {
7354 #ifndef BRING_UP_DEBUG
7355 if (amdgpu_async_gfx_ring) {
7356 r = gfx_v10_0_kiq_disable_kgq(adev);
7357 if (r)
7358 DRM_ERROR("KGQ disable failed\n");
7359 }
7360 #endif
7361 if (amdgpu_gfx_disable_kcq(adev))
7362 DRM_ERROR("KCQ disable failed\n");
7363 }
7364
7365 if (amdgpu_sriov_vf(adev)) {
7366 gfx_v10_0_cp_gfx_enable(adev, false);
7367 /* Program KIQ position of RLC_CP_SCHEDULERS during destroy */
7368 if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(10, 3, 0)) {
7369 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid);
7370 tmp &= 0xffffff00;
7371 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp);
7372 } else {
7373 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);
7374 tmp &= 0xffffff00;
7375 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
7376 }
7377
7378 return 0;
7379 }
7380 gfx_v10_0_cp_enable(adev, false);
7381 gfx_v10_0_enable_gui_idle_interrupt(adev, false);
7382
7383 return 0;
7384 }
7385
gfx_v10_0_suspend(void * handle)7386 static int gfx_v10_0_suspend(void *handle)
7387 {
7388 return gfx_v10_0_hw_fini(handle);
7389 }
7390
gfx_v10_0_resume(void * handle)7391 static int gfx_v10_0_resume(void *handle)
7392 {
7393 return gfx_v10_0_hw_init(handle);
7394 }
7395
gfx_v10_0_is_idle(void * handle)7396 static bool gfx_v10_0_is_idle(void *handle)
7397 {
7398 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7399
7400 if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS),
7401 GRBM_STATUS, GUI_ACTIVE))
7402 return false;
7403 else
7404 return true;
7405 }
7406
gfx_v10_0_wait_for_idle(void * handle)7407 static int gfx_v10_0_wait_for_idle(void *handle)
7408 {
7409 unsigned i;
7410 u32 tmp;
7411 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7412
7413 for (i = 0; i < adev->usec_timeout; i++) {
7414 /* read MC_STATUS */
7415 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS) &
7416 GRBM_STATUS__GUI_ACTIVE_MASK;
7417
7418 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE))
7419 return 0;
7420 udelay(1);
7421 }
7422 return -ETIMEDOUT;
7423 }
7424
gfx_v10_0_soft_reset(void * handle)7425 static int gfx_v10_0_soft_reset(void *handle)
7426 {
7427 u32 grbm_soft_reset = 0;
7428 u32 tmp;
7429 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7430
7431 /* GRBM_STATUS */
7432 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS);
7433 if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
7434 GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
7435 GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__DB_BUSY_MASK |
7436 GRBM_STATUS__CB_BUSY_MASK | GRBM_STATUS__GDS_BUSY_MASK |
7437 GRBM_STATUS__SPI_BUSY_MASK | GRBM_STATUS__GE_BUSY_NO_DMA_MASK)) {
7438 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7439 GRBM_SOFT_RESET, SOFT_RESET_CP,
7440 1);
7441 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7442 GRBM_SOFT_RESET, SOFT_RESET_GFX,
7443 1);
7444 }
7445
7446 if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) {
7447 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7448 GRBM_SOFT_RESET, SOFT_RESET_CP,
7449 1);
7450 }
7451
7452 /* GRBM_STATUS2 */
7453 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2);
7454 switch (adev->ip_versions[GC_HWIP][0]) {
7455 case IP_VERSION(10, 3, 0):
7456 case IP_VERSION(10, 3, 2):
7457 case IP_VERSION(10, 3, 1):
7458 case IP_VERSION(10, 3, 4):
7459 case IP_VERSION(10, 3, 5):
7460 case IP_VERSION(10, 3, 6):
7461 case IP_VERSION(10, 3, 3):
7462 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY_Sienna_Cichlid))
7463 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7464 GRBM_SOFT_RESET,
7465 SOFT_RESET_RLC,
7466 1);
7467 break;
7468 default:
7469 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY))
7470 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7471 GRBM_SOFT_RESET,
7472 SOFT_RESET_RLC,
7473 1);
7474 break;
7475 }
7476
7477 if (grbm_soft_reset) {
7478 /* stop the rlc */
7479 gfx_v10_0_rlc_stop(adev);
7480
7481 /* Disable GFX parsing/prefetching */
7482 gfx_v10_0_cp_gfx_enable(adev, false);
7483
7484 /* Disable MEC parsing/prefetching */
7485 gfx_v10_0_cp_compute_enable(adev, false);
7486
7487 if (grbm_soft_reset) {
7488 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
7489 tmp |= grbm_soft_reset;
7490 dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
7491 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
7492 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
7493
7494 udelay(50);
7495
7496 tmp &= ~grbm_soft_reset;
7497 WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
7498 tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
7499 }
7500
7501 /* Wait a little for things to settle down */
7502 udelay(50);
7503 }
7504 return 0;
7505 }
7506
gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device * adev)7507 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev)
7508 {
7509 uint64_t clock, clock_lo, clock_hi, hi_check;
7510
7511 switch (adev->ip_versions[GC_HWIP][0]) {
7512 case IP_VERSION(10, 3, 1):
7513 case IP_VERSION(10, 3, 3):
7514 case IP_VERSION(10, 3, 7):
7515 preempt_disable();
7516 clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Vangogh);
7517 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Vangogh);
7518 hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_Vangogh);
7519 /* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over
7520 * roughly every 42 seconds.
7521 */
7522 if (hi_check != clock_hi) {
7523 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_Vangogh);
7524 clock_hi = hi_check;
7525 }
7526 preempt_enable();
7527 clock = clock_lo | (clock_hi << 32ULL);
7528 break;
7529 case IP_VERSION(10, 3, 6):
7530 preempt_disable();
7531 clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6);
7532 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6);
7533 hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER_GC_10_3_6);
7534 /* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over
7535 * roughly every 42 seconds.
7536 */
7537 if (hi_check != clock_hi) {
7538 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER_GC_10_3_6);
7539 clock_hi = hi_check;
7540 }
7541 preempt_enable();
7542 clock = clock_lo | (clock_hi << 32ULL);
7543 break;
7544 default:
7545 preempt_disable();
7546 clock_hi = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER);
7547 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER);
7548 hi_check = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER);
7549 /* The SMUIO TSC clock frequency is 100MHz, which sets 32-bit carry over
7550 * roughly every 42 seconds.
7551 */
7552 if (hi_check != clock_hi) {
7553 clock_lo = RREG32_SOC15_NO_KIQ(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER);
7554 clock_hi = hi_check;
7555 }
7556 preempt_enable();
7557 clock = clock_lo | (clock_hi << 32ULL);
7558 break;
7559 }
7560 return clock;
7561 }
7562
gfx_v10_0_ring_emit_gds_switch(struct amdgpu_ring * ring,uint32_t vmid,uint32_t gds_base,uint32_t gds_size,uint32_t gws_base,uint32_t gws_size,uint32_t oa_base,uint32_t oa_size)7563 static void gfx_v10_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
7564 uint32_t vmid,
7565 uint32_t gds_base, uint32_t gds_size,
7566 uint32_t gws_base, uint32_t gws_size,
7567 uint32_t oa_base, uint32_t oa_size)
7568 {
7569 struct amdgpu_device *adev = ring->adev;
7570
7571 /* GDS Base */
7572 gfx_v10_0_write_data_to_reg(ring, 0, false,
7573 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE) + 2 * vmid,
7574 gds_base);
7575
7576 /* GDS Size */
7577 gfx_v10_0_write_data_to_reg(ring, 0, false,
7578 SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE) + 2 * vmid,
7579 gds_size);
7580
7581 /* GWS */
7582 gfx_v10_0_write_data_to_reg(ring, 0, false,
7583 SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0) + vmid,
7584 gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
7585
7586 /* OA */
7587 gfx_v10_0_write_data_to_reg(ring, 0, false,
7588 SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0) + vmid,
7589 (1 << (oa_size + oa_base)) - (1 << oa_base));
7590 }
7591
gfx_v10_0_early_init(void * handle)7592 static int gfx_v10_0_early_init(void *handle)
7593 {
7594 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7595
7596 switch (adev->ip_versions[GC_HWIP][0]) {
7597 case IP_VERSION(10, 1, 10):
7598 case IP_VERSION(10, 1, 1):
7599 case IP_VERSION(10, 1, 2):
7600 case IP_VERSION(10, 1, 3):
7601 case IP_VERSION(10, 1, 4):
7602 adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_NV1X;
7603 break;
7604 case IP_VERSION(10, 3, 0):
7605 case IP_VERSION(10, 3, 2):
7606 case IP_VERSION(10, 3, 1):
7607 case IP_VERSION(10, 3, 4):
7608 case IP_VERSION(10, 3, 5):
7609 case IP_VERSION(10, 3, 6):
7610 case IP_VERSION(10, 3, 3):
7611 case IP_VERSION(10, 3, 7):
7612 adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_Sienna_Cichlid;
7613 break;
7614 default:
7615 break;
7616 }
7617
7618 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev),
7619 AMDGPU_MAX_COMPUTE_RINGS);
7620
7621 gfx_v10_0_set_kiq_pm4_funcs(adev);
7622 gfx_v10_0_set_ring_funcs(adev);
7623 gfx_v10_0_set_irq_funcs(adev);
7624 gfx_v10_0_set_gds_init(adev);
7625 gfx_v10_0_set_rlc_funcs(adev);
7626 gfx_v10_0_set_mqd_funcs(adev);
7627
7628 /* init rlcg reg access ctrl */
7629 gfx_v10_0_init_rlcg_reg_access_ctrl(adev);
7630
7631 return 0;
7632 }
7633
gfx_v10_0_late_init(void * handle)7634 static int gfx_v10_0_late_init(void *handle)
7635 {
7636 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7637 int r;
7638
7639 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
7640 if (r)
7641 return r;
7642
7643 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
7644 if (r)
7645 return r;
7646
7647 return 0;
7648 }
7649
gfx_v10_0_is_rlc_enabled(struct amdgpu_device * adev)7650 static bool gfx_v10_0_is_rlc_enabled(struct amdgpu_device *adev)
7651 {
7652 uint32_t rlc_cntl;
7653
7654 /* if RLC is not enabled, do nothing */
7655 rlc_cntl = RREG32_SOC15(GC, 0, mmRLC_CNTL);
7656 return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false;
7657 }
7658
gfx_v10_0_set_safe_mode(struct amdgpu_device * adev)7659 static void gfx_v10_0_set_safe_mode(struct amdgpu_device *adev)
7660 {
7661 uint32_t data;
7662 unsigned i;
7663
7664 data = RLC_SAFE_MODE__CMD_MASK;
7665 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT);
7666
7667 switch (adev->ip_versions[GC_HWIP][0]) {
7668 case IP_VERSION(10, 3, 0):
7669 case IP_VERSION(10, 3, 2):
7670 case IP_VERSION(10, 3, 1):
7671 case IP_VERSION(10, 3, 4):
7672 case IP_VERSION(10, 3, 5):
7673 case IP_VERSION(10, 3, 6):
7674 case IP_VERSION(10, 3, 3):
7675 case IP_VERSION(10, 3, 7):
7676 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data);
7677
7678 /* wait for RLC_SAFE_MODE */
7679 for (i = 0; i < adev->usec_timeout; i++) {
7680 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid),
7681 RLC_SAFE_MODE, CMD))
7682 break;
7683 udelay(1);
7684 }
7685 break;
7686 default:
7687 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
7688
7689 /* wait for RLC_SAFE_MODE */
7690 for (i = 0; i < adev->usec_timeout; i++) {
7691 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE),
7692 RLC_SAFE_MODE, CMD))
7693 break;
7694 udelay(1);
7695 }
7696 break;
7697 }
7698 }
7699
gfx_v10_0_unset_safe_mode(struct amdgpu_device * adev)7700 static void gfx_v10_0_unset_safe_mode(struct amdgpu_device *adev)
7701 {
7702 uint32_t data;
7703
7704 data = RLC_SAFE_MODE__CMD_MASK;
7705 switch (adev->ip_versions[GC_HWIP][0]) {
7706 case IP_VERSION(10, 3, 0):
7707 case IP_VERSION(10, 3, 2):
7708 case IP_VERSION(10, 3, 1):
7709 case IP_VERSION(10, 3, 4):
7710 case IP_VERSION(10, 3, 5):
7711 case IP_VERSION(10, 3, 6):
7712 case IP_VERSION(10, 3, 3):
7713 case IP_VERSION(10, 3, 7):
7714 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data);
7715 break;
7716 default:
7717 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
7718 break;
7719 }
7720 }
7721
gfx_v10_0_update_medium_grain_clock_gating(struct amdgpu_device * adev,bool enable)7722 static void gfx_v10_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
7723 bool enable)
7724 {
7725 uint32_t data, def;
7726
7727 if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_MGLS)))
7728 return;
7729
7730 /* It is disabled by HW by default */
7731 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
7732 /* 0 - Disable some blocks' MGCG */
7733 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000);
7734 WREG32_SOC15(GC, 0, mmCGTT_WD_CLK_CTRL, 0xff000000);
7735 WREG32_SOC15(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xff000000);
7736 WREG32_SOC15(GC, 0, mmCGTT_IA_CLK_CTRL, 0xff000000);
7737
7738 /* 1 - RLC_CGTT_MGCG_OVERRIDE */
7739 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7740 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
7741 RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
7742 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
7743 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK |
7744 RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK |
7745 RLC_CGTT_MGCG_OVERRIDE__ENABLE_CGTS_LEGACY_MASK);
7746
7747 if (def != data)
7748 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7749
7750 /* MGLS is a global flag to control all MGLS in GFX */
7751 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
7752 /* 2 - RLC memory Light sleep */
7753 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) {
7754 def = data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
7755 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
7756 if (def != data)
7757 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
7758 }
7759 /* 3 - CP memory Light sleep */
7760 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
7761 def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
7762 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
7763 if (def != data)
7764 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
7765 }
7766 }
7767 } else if (!enable || !(adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
7768 /* 1 - MGCG_OVERRIDE */
7769 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7770 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
7771 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
7772 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
7773 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK |
7774 RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK |
7775 RLC_CGTT_MGCG_OVERRIDE__ENABLE_CGTS_LEGACY_MASK);
7776 if (def != data)
7777 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7778
7779 /* 2 - disable MGLS in CP */
7780 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
7781 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {
7782 data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
7783 WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
7784 }
7785
7786 /* 3 - disable MGLS in RLC */
7787 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
7788 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) {
7789 data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
7790 WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
7791 }
7792
7793 }
7794 }
7795
gfx_v10_0_update_3d_clock_gating(struct amdgpu_device * adev,bool enable)7796 static void gfx_v10_0_update_3d_clock_gating(struct amdgpu_device *adev,
7797 bool enable)
7798 {
7799 uint32_t data, def;
7800
7801 if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_3D_CGCG | AMD_CG_SUPPORT_GFX_3D_CGLS)))
7802 return;
7803
7804 /* Enable 3D CGCG/CGLS */
7805 if (enable) {
7806 /* write cmd to clear cgcg/cgls ov */
7807 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7808
7809 /* unset CGCG override */
7810 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)
7811 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK;
7812
7813 /* update CGCG and CGLS override bits */
7814 if (def != data)
7815 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7816
7817 /* enable 3Dcgcg FSM(0x0000363f) */
7818 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
7819 data = 0;
7820
7821 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)
7822 data = (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
7823 RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;
7824
7825 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS)
7826 data |= (0x000F << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
7827 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK;
7828
7829 if (def != data)
7830 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
7831
7832 /* set IDLE_POLL_COUNT(0x00900100) */
7833 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
7834 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
7835 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
7836 if (def != data)
7837 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
7838 } else {
7839 /* Disable CGCG/CGLS */
7840 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
7841
7842 /* disable cgcg, cgls should be disabled */
7843 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)
7844 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;
7845
7846 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS)
7847 data &= ~RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK;
7848
7849 /* disable cgcg and cgls in FSM */
7850 if (def != data)
7851 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
7852 }
7853 }
7854
gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device * adev,bool enable)7855 static void gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev,
7856 bool enable)
7857 {
7858 uint32_t def, data;
7859
7860 if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_CGLS)))
7861 return;
7862
7863 if (enable) {
7864 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7865
7866 /* unset CGCG override */
7867 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)
7868 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK;
7869
7870 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
7871 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
7872
7873 /* update CGCG and CGLS override bits */
7874 if (def != data)
7875 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7876
7877 /* enable cgcg FSM(0x0000363F) */
7878 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
7879 data = 0;
7880
7881 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)
7882 data = (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
7883 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
7884
7885 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
7886 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
7887 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
7888
7889 if (def != data)
7890 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
7891
7892 /* set IDLE_POLL_COUNT(0x00900100) */
7893 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
7894 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
7895 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
7896 if (def != data)
7897 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
7898 } else {
7899 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
7900
7901 /* reset CGCG/CGLS bits */
7902 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)
7903 data &= ~RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
7904
7905 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
7906 data &= ~RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
7907
7908 /* disable cgcg and cgls in FSM */
7909 if (def != data)
7910 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
7911 }
7912 }
7913
gfx_v10_0_update_fine_grain_clock_gating(struct amdgpu_device * adev,bool enable)7914 static void gfx_v10_0_update_fine_grain_clock_gating(struct amdgpu_device *adev,
7915 bool enable)
7916 {
7917 uint32_t def, data;
7918
7919 if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_FGCG))
7920 return;
7921
7922 if (enable) {
7923 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7924 /* unset FGCG override */
7925 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK;
7926 /* update FGCG override bits */
7927 if (def != data)
7928 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7929
7930 def = data = RREG32_SOC15(GC, 0, mmRLC_CLK_CNTL);
7931 /* unset RLC SRAM CLK GATER override */
7932 data &= ~RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK;
7933 /* update RLC SRAM CLK GATER override bits */
7934 if (def != data)
7935 WREG32_SOC15(GC, 0, mmRLC_CLK_CNTL, data);
7936 } else {
7937 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7938 /* reset FGCG bits */
7939 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK;
7940 /* disable FGCG*/
7941 if (def != data)
7942 WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7943
7944 def = data = RREG32_SOC15(GC, 0, mmRLC_CLK_CNTL);
7945 /* reset RLC SRAM CLK GATER bits */
7946 data |= RLC_CLK_CNTL__RLC_SRAM_CLK_GATER_OVERRIDE_MASK;
7947 /* disable RLC SRAM CLK*/
7948 if (def != data)
7949 WREG32_SOC15(GC, 0, mmRLC_CLK_CNTL, data);
7950 }
7951 }
7952
gfx_v10_0_apply_medium_grain_clock_gating_workaround(struct amdgpu_device * adev)7953 static void gfx_v10_0_apply_medium_grain_clock_gating_workaround(struct amdgpu_device *adev)
7954 {
7955 uint32_t reg_data = 0;
7956 uint32_t reg_idx = 0;
7957 uint32_t i;
7958
7959 const uint32_t tcp_ctrl_regs[] = {
7960 mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG,
7961 mmCGTS_SA0_WGP00_CU1_TCP_CTRL_REG,
7962 mmCGTS_SA0_WGP01_CU0_TCP_CTRL_REG,
7963 mmCGTS_SA0_WGP01_CU1_TCP_CTRL_REG,
7964 mmCGTS_SA0_WGP02_CU0_TCP_CTRL_REG,
7965 mmCGTS_SA0_WGP02_CU1_TCP_CTRL_REG,
7966 mmCGTS_SA0_WGP10_CU0_TCP_CTRL_REG,
7967 mmCGTS_SA0_WGP10_CU1_TCP_CTRL_REG,
7968 mmCGTS_SA0_WGP11_CU0_TCP_CTRL_REG,
7969 mmCGTS_SA0_WGP11_CU1_TCP_CTRL_REG,
7970 mmCGTS_SA0_WGP12_CU0_TCP_CTRL_REG,
7971 mmCGTS_SA0_WGP12_CU1_TCP_CTRL_REG,
7972 mmCGTS_SA1_WGP00_CU0_TCP_CTRL_REG,
7973 mmCGTS_SA1_WGP00_CU1_TCP_CTRL_REG,
7974 mmCGTS_SA1_WGP01_CU0_TCP_CTRL_REG,
7975 mmCGTS_SA1_WGP01_CU1_TCP_CTRL_REG,
7976 mmCGTS_SA1_WGP02_CU0_TCP_CTRL_REG,
7977 mmCGTS_SA1_WGP02_CU1_TCP_CTRL_REG,
7978 mmCGTS_SA1_WGP10_CU0_TCP_CTRL_REG,
7979 mmCGTS_SA1_WGP10_CU1_TCP_CTRL_REG,
7980 mmCGTS_SA1_WGP11_CU0_TCP_CTRL_REG,
7981 mmCGTS_SA1_WGP11_CU1_TCP_CTRL_REG,
7982 mmCGTS_SA1_WGP12_CU0_TCP_CTRL_REG,
7983 mmCGTS_SA1_WGP12_CU1_TCP_CTRL_REG
7984 };
7985
7986 const uint32_t tcp_ctrl_regs_nv12[] = {
7987 mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG,
7988 mmCGTS_SA0_WGP00_CU1_TCP_CTRL_REG,
7989 mmCGTS_SA0_WGP01_CU0_TCP_CTRL_REG,
7990 mmCGTS_SA0_WGP01_CU1_TCP_CTRL_REG,
7991 mmCGTS_SA0_WGP02_CU0_TCP_CTRL_REG,
7992 mmCGTS_SA0_WGP02_CU1_TCP_CTRL_REG,
7993 mmCGTS_SA0_WGP10_CU0_TCP_CTRL_REG,
7994 mmCGTS_SA0_WGP10_CU1_TCP_CTRL_REG,
7995 mmCGTS_SA0_WGP11_CU0_TCP_CTRL_REG,
7996 mmCGTS_SA0_WGP11_CU1_TCP_CTRL_REG,
7997 mmCGTS_SA1_WGP00_CU0_TCP_CTRL_REG,
7998 mmCGTS_SA1_WGP00_CU1_TCP_CTRL_REG,
7999 mmCGTS_SA1_WGP01_CU0_TCP_CTRL_REG,
8000 mmCGTS_SA1_WGP01_CU1_TCP_CTRL_REG,
8001 mmCGTS_SA1_WGP02_CU0_TCP_CTRL_REG,
8002 mmCGTS_SA1_WGP02_CU1_TCP_CTRL_REG,
8003 mmCGTS_SA1_WGP10_CU0_TCP_CTRL_REG,
8004 mmCGTS_SA1_WGP10_CU1_TCP_CTRL_REG,
8005 mmCGTS_SA1_WGP11_CU0_TCP_CTRL_REG,
8006 mmCGTS_SA1_WGP11_CU1_TCP_CTRL_REG,
8007 };
8008
8009 const uint32_t sm_ctlr_regs[] = {
8010 mmCGTS_SA0_QUAD0_SM_CTRL_REG,
8011 mmCGTS_SA0_QUAD1_SM_CTRL_REG,
8012 mmCGTS_SA1_QUAD0_SM_CTRL_REG,
8013 mmCGTS_SA1_QUAD1_SM_CTRL_REG
8014 };
8015
8016 if (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 2)) {
8017 for (i = 0; i < ARRAY_SIZE(tcp_ctrl_regs_nv12); i++) {
8018 reg_idx = adev->reg_offset[GC_HWIP][0][mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG_BASE_IDX] +
8019 tcp_ctrl_regs_nv12[i];
8020 reg_data = RREG32(reg_idx);
8021 reg_data |= CGTS_SA0_WGP00_CU0_TCP_CTRL_REG__TCPI_LS_OVERRIDE_MASK;
8022 WREG32(reg_idx, reg_data);
8023 }
8024 } else {
8025 for (i = 0; i < ARRAY_SIZE(tcp_ctrl_regs); i++) {
8026 reg_idx = adev->reg_offset[GC_HWIP][0][mmCGTS_SA0_WGP00_CU0_TCP_CTRL_REG_BASE_IDX] +
8027 tcp_ctrl_regs[i];
8028 reg_data = RREG32(reg_idx);
8029 reg_data |= CGTS_SA0_WGP00_CU0_TCP_CTRL_REG__TCPI_LS_OVERRIDE_MASK;
8030 WREG32(reg_idx, reg_data);
8031 }
8032 }
8033
8034 for (i = 0; i < ARRAY_SIZE(sm_ctlr_regs); i++) {
8035 reg_idx = adev->reg_offset[GC_HWIP][0][mmCGTS_SA0_QUAD0_SM_CTRL_REG_BASE_IDX] +
8036 sm_ctlr_regs[i];
8037 reg_data = RREG32(reg_idx);
8038 reg_data &= ~CGTS_SA0_QUAD0_SM_CTRL_REG__SM_MODE_MASK;
8039 reg_data |= 2 << CGTS_SA0_QUAD0_SM_CTRL_REG__SM_MODE__SHIFT;
8040 WREG32(reg_idx, reg_data);
8041 }
8042 }
8043
gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device * adev,bool enable)8044 static int gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device *adev,
8045 bool enable)
8046 {
8047 amdgpu_gfx_rlc_enter_safe_mode(adev);
8048
8049 if (enable) {
8050 /* enable FGCG firstly*/
8051 gfx_v10_0_update_fine_grain_clock_gating(adev, enable);
8052 /* CGCG/CGLS should be enabled after MGCG/MGLS
8053 * === MGCG + MGLS ===
8054 */
8055 gfx_v10_0_update_medium_grain_clock_gating(adev, enable);
8056 /* === CGCG /CGLS for GFX 3D Only === */
8057 gfx_v10_0_update_3d_clock_gating(adev, enable);
8058 /* === CGCG + CGLS === */
8059 gfx_v10_0_update_coarse_grain_clock_gating(adev, enable);
8060
8061 if ((adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 10)) ||
8062 (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 1)) ||
8063 (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 1, 2)))
8064 gfx_v10_0_apply_medium_grain_clock_gating_workaround(adev);
8065 } else {
8066 /* CGCG/CGLS should be disabled before MGCG/MGLS
8067 * === CGCG + CGLS ===
8068 */
8069 gfx_v10_0_update_coarse_grain_clock_gating(adev, enable);
8070 /* === CGCG /CGLS for GFX 3D Only === */
8071 gfx_v10_0_update_3d_clock_gating(adev, enable);
8072 /* === MGCG + MGLS === */
8073 gfx_v10_0_update_medium_grain_clock_gating(adev, enable);
8074 /* disable fgcg at last*/
8075 gfx_v10_0_update_fine_grain_clock_gating(adev, enable);
8076 }
8077
8078 if (adev->cg_flags &
8079 (AMD_CG_SUPPORT_GFX_MGCG |
8080 AMD_CG_SUPPORT_GFX_CGLS |
8081 AMD_CG_SUPPORT_GFX_CGCG |
8082 AMD_CG_SUPPORT_GFX_3D_CGCG |
8083 AMD_CG_SUPPORT_GFX_3D_CGLS))
8084 gfx_v10_0_enable_gui_idle_interrupt(adev, enable);
8085
8086 amdgpu_gfx_rlc_exit_safe_mode(adev);
8087
8088 return 0;
8089 }
8090
gfx_v10_0_update_spm_vmid(struct amdgpu_device * adev,unsigned vmid)8091 static void gfx_v10_0_update_spm_vmid(struct amdgpu_device *adev, unsigned vmid)
8092 {
8093 u32 reg, data;
8094
8095 amdgpu_gfx_off_ctrl(adev, false);
8096
8097 /* not for *_SOC15 */
8098 reg = SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_MC_CNTL);
8099 if (amdgpu_sriov_is_pp_one_vf(adev))
8100 data = RREG32_NO_KIQ(reg);
8101 else
8102 data = RREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL);
8103
8104 data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK;
8105 data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT;
8106
8107 if (amdgpu_sriov_is_pp_one_vf(adev))
8108 WREG32_SOC15_NO_KIQ(GC, 0, mmRLC_SPM_MC_CNTL, data);
8109 else
8110 WREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL, data);
8111
8112 amdgpu_gfx_off_ctrl(adev, true);
8113 }
8114
gfx_v10_0_check_rlcg_range(struct amdgpu_device * adev,uint32_t offset,struct soc15_reg_rlcg * entries,int arr_size)8115 static bool gfx_v10_0_check_rlcg_range(struct amdgpu_device *adev,
8116 uint32_t offset,
8117 struct soc15_reg_rlcg *entries, int arr_size)
8118 {
8119 int i;
8120 uint32_t reg;
8121
8122 if (!entries)
8123 return false;
8124
8125 for (i = 0; i < arr_size; i++) {
8126 const struct soc15_reg_rlcg *entry;
8127
8128 entry = &entries[i];
8129 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg;
8130 if (offset == reg)
8131 return true;
8132 }
8133
8134 return false;
8135 }
8136
gfx_v10_0_is_rlcg_access_range(struct amdgpu_device * adev,u32 offset)8137 static bool gfx_v10_0_is_rlcg_access_range(struct amdgpu_device *adev, u32 offset)
8138 {
8139 return gfx_v10_0_check_rlcg_range(adev, offset, NULL, 0);
8140 }
8141
gfx_v10_cntl_power_gating(struct amdgpu_device * adev,bool enable)8142 static void gfx_v10_cntl_power_gating(struct amdgpu_device *adev, bool enable)
8143 {
8144 u32 data = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL);
8145
8146 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG))
8147 data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
8148 else
8149 data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
8150
8151 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, data);
8152
8153 /*
8154 * CGPG enablement required and the register to program the hysteresis value
8155 * RLC_PG_DELAY_3.CGCG_ACTIVE_BEFORE_CGPG to the desired CGPG hysteresis value
8156 * in refclk count. Note that RLC FW is modified to take 16 bits from
8157 * RLC_PG_DELAY_3[15:0] as the hysteresis instead of just 8 bits.
8158 *
8159 * The recommendation from RLC team is setting RLC_PG_DELAY_3 to 200us as part)
8160 * of CGPG enablement starting point.
8161 * Power/performance team will optimize it and might give a new value later.
8162 */
8163 if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) {
8164 switch (adev->ip_versions[GC_HWIP][0]) {
8165 case IP_VERSION(10, 3, 1):
8166 case IP_VERSION(10, 3, 3):
8167 case IP_VERSION(10, 3, 6):
8168 case IP_VERSION(10, 3, 7):
8169 data = 0x4E20 & RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK_Vangogh;
8170 WREG32_SOC15(GC, 0, mmRLC_PG_DELAY_3, data);
8171 break;
8172 default:
8173 break;
8174 }
8175 }
8176 }
8177
gfx_v10_cntl_pg(struct amdgpu_device * adev,bool enable)8178 static void gfx_v10_cntl_pg(struct amdgpu_device *adev, bool enable)
8179 {
8180 amdgpu_gfx_rlc_enter_safe_mode(adev);
8181
8182 gfx_v10_cntl_power_gating(adev, enable);
8183
8184 amdgpu_gfx_rlc_exit_safe_mode(adev);
8185 }
8186
8187 static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs = {
8188 .is_rlc_enabled = gfx_v10_0_is_rlc_enabled,
8189 .set_safe_mode = gfx_v10_0_set_safe_mode,
8190 .unset_safe_mode = gfx_v10_0_unset_safe_mode,
8191 .init = gfx_v10_0_rlc_init,
8192 .get_csb_size = gfx_v10_0_get_csb_size,
8193 .get_csb_buffer = gfx_v10_0_get_csb_buffer,
8194 .resume = gfx_v10_0_rlc_resume,
8195 .stop = gfx_v10_0_rlc_stop,
8196 .reset = gfx_v10_0_rlc_reset,
8197 .start = gfx_v10_0_rlc_start,
8198 .update_spm_vmid = gfx_v10_0_update_spm_vmid,
8199 };
8200
8201 static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs_sriov = {
8202 .is_rlc_enabled = gfx_v10_0_is_rlc_enabled,
8203 .set_safe_mode = gfx_v10_0_set_safe_mode,
8204 .unset_safe_mode = gfx_v10_0_unset_safe_mode,
8205 .init = gfx_v10_0_rlc_init,
8206 .get_csb_size = gfx_v10_0_get_csb_size,
8207 .get_csb_buffer = gfx_v10_0_get_csb_buffer,
8208 .resume = gfx_v10_0_rlc_resume,
8209 .stop = gfx_v10_0_rlc_stop,
8210 .reset = gfx_v10_0_rlc_reset,
8211 .start = gfx_v10_0_rlc_start,
8212 .update_spm_vmid = gfx_v10_0_update_spm_vmid,
8213 .is_rlcg_access_range = gfx_v10_0_is_rlcg_access_range,
8214 };
8215
gfx_v10_0_set_powergating_state(void * handle,enum amd_powergating_state state)8216 static int gfx_v10_0_set_powergating_state(void *handle,
8217 enum amd_powergating_state state)
8218 {
8219 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
8220 bool enable = (state == AMD_PG_STATE_GATE);
8221
8222 if (amdgpu_sriov_vf(adev))
8223 return 0;
8224
8225 switch (adev->ip_versions[GC_HWIP][0]) {
8226 case IP_VERSION(10, 1, 10):
8227 case IP_VERSION(10, 1, 1):
8228 case IP_VERSION(10, 1, 2):
8229 case IP_VERSION(10, 3, 0):
8230 case IP_VERSION(10, 3, 2):
8231 case IP_VERSION(10, 3, 4):
8232 case IP_VERSION(10, 3, 5):
8233 amdgpu_gfx_off_ctrl(adev, enable);
8234 break;
8235 case IP_VERSION(10, 3, 1):
8236 case IP_VERSION(10, 3, 3):
8237 case IP_VERSION(10, 3, 6):
8238 case IP_VERSION(10, 3, 7):
8239 gfx_v10_cntl_pg(adev, enable);
8240 amdgpu_gfx_off_ctrl(adev, enable);
8241 break;
8242 default:
8243 break;
8244 }
8245 return 0;
8246 }
8247
gfx_v10_0_set_clockgating_state(void * handle,enum amd_clockgating_state state)8248 static int gfx_v10_0_set_clockgating_state(void *handle,
8249 enum amd_clockgating_state state)
8250 {
8251 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
8252
8253 if (amdgpu_sriov_vf(adev))
8254 return 0;
8255
8256 switch (adev->ip_versions[GC_HWIP][0]) {
8257 case IP_VERSION(10, 1, 10):
8258 case IP_VERSION(10, 1, 1):
8259 case IP_VERSION(10, 1, 2):
8260 case IP_VERSION(10, 3, 0):
8261 case IP_VERSION(10, 3, 2):
8262 case IP_VERSION(10, 3, 1):
8263 case IP_VERSION(10, 3, 4):
8264 case IP_VERSION(10, 3, 5):
8265 case IP_VERSION(10, 3, 6):
8266 case IP_VERSION(10, 3, 3):
8267 case IP_VERSION(10, 3, 7):
8268 gfx_v10_0_update_gfx_clock_gating(adev,
8269 state == AMD_CG_STATE_GATE);
8270 break;
8271 default:
8272 break;
8273 }
8274 return 0;
8275 }
8276
gfx_v10_0_get_clockgating_state(void * handle,u64 * flags)8277 static void gfx_v10_0_get_clockgating_state(void *handle, u64 *flags)
8278 {
8279 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
8280 int data;
8281
8282 /* AMD_CG_SUPPORT_GFX_FGCG */
8283 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE));
8284 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK))
8285 *flags |= AMD_CG_SUPPORT_GFX_FGCG;
8286
8287 /* AMD_CG_SUPPORT_GFX_MGCG */
8288 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE));
8289 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK))
8290 *flags |= AMD_CG_SUPPORT_GFX_MGCG;
8291
8292 /* AMD_CG_SUPPORT_GFX_CGCG */
8293 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL));
8294 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK)
8295 *flags |= AMD_CG_SUPPORT_GFX_CGCG;
8296
8297 /* AMD_CG_SUPPORT_GFX_CGLS */
8298 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK)
8299 *flags |= AMD_CG_SUPPORT_GFX_CGLS;
8300
8301 /* AMD_CG_SUPPORT_GFX_RLC_LS */
8302 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_MEM_SLP_CNTL));
8303 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK)
8304 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS;
8305
8306 /* AMD_CG_SUPPORT_GFX_CP_LS */
8307 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmCP_MEM_SLP_CNTL));
8308 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK)
8309 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS;
8310
8311 /* AMD_CG_SUPPORT_GFX_3D_CGCG */
8312 data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D));
8313 if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK)
8314 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG;
8315
8316 /* AMD_CG_SUPPORT_GFX_3D_CGLS */
8317 if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK)
8318 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS;
8319 }
8320
gfx_v10_0_ring_get_rptr_gfx(struct amdgpu_ring * ring)8321 static u64 gfx_v10_0_ring_get_rptr_gfx(struct amdgpu_ring *ring)
8322 {
8323 /* gfx10 is 32bit rptr*/
8324 return *(uint32_t *)ring->rptr_cpu_addr;
8325 }
8326
gfx_v10_0_ring_get_wptr_gfx(struct amdgpu_ring * ring)8327 static u64 gfx_v10_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
8328 {
8329 struct amdgpu_device *adev = ring->adev;
8330 u64 wptr;
8331
8332 /* XXX check if swapping is necessary on BE */
8333 if (ring->use_doorbell) {
8334 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr);
8335 } else {
8336 wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR);
8337 wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32;
8338 }
8339
8340 return wptr;
8341 }
8342
gfx_v10_0_ring_set_wptr_gfx(struct amdgpu_ring * ring)8343 static void gfx_v10_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
8344 {
8345 struct amdgpu_device *adev = ring->adev;
8346 uint32_t *wptr_saved;
8347 uint32_t *is_queue_unmap;
8348 uint64_t aggregated_db_index;
8349 uint32_t mqd_size = adev->mqds[AMDGPU_HW_IP_GFX].mqd_size;
8350 uint64_t wptr_tmp;
8351
8352 if (ring->is_mes_queue) {
8353 wptr_saved = (uint32_t *)(ring->mqd_ptr + mqd_size);
8354 is_queue_unmap = (uint32_t *)(ring->mqd_ptr + mqd_size +
8355 sizeof(uint32_t));
8356 aggregated_db_index =
8357 amdgpu_mes_get_aggregated_doorbell_index(adev,
8358 AMDGPU_MES_PRIORITY_LEVEL_NORMAL);
8359
8360 wptr_tmp = ring->wptr & ring->buf_mask;
8361 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, wptr_tmp);
8362 *wptr_saved = wptr_tmp;
8363 /* assume doorbell always being used by mes mapped queue */
8364 if (*is_queue_unmap) {
8365 WDOORBELL64(aggregated_db_index, wptr_tmp);
8366 WDOORBELL64(ring->doorbell_index, wptr_tmp);
8367 } else {
8368 WDOORBELL64(ring->doorbell_index, wptr_tmp);
8369
8370 if (*is_queue_unmap)
8371 WDOORBELL64(aggregated_db_index, wptr_tmp);
8372 }
8373 } else {
8374 if (ring->use_doorbell) {
8375 /* XXX check if swapping is necessary on BE */
8376 atomic64_set((atomic64_t *)ring->wptr_cpu_addr,
8377 ring->wptr);
8378 WDOORBELL64(ring->doorbell_index, ring->wptr);
8379 } else {
8380 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR,
8381 lower_32_bits(ring->wptr));
8382 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI,
8383 upper_32_bits(ring->wptr));
8384 }
8385 }
8386 }
8387
gfx_v10_0_ring_get_rptr_compute(struct amdgpu_ring * ring)8388 static u64 gfx_v10_0_ring_get_rptr_compute(struct amdgpu_ring *ring)
8389 {
8390 /* gfx10 hardware is 32bit rptr */
8391 return *(uint32_t *)ring->rptr_cpu_addr;
8392 }
8393
gfx_v10_0_ring_get_wptr_compute(struct amdgpu_ring * ring)8394 static u64 gfx_v10_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
8395 {
8396 u64 wptr;
8397
8398 /* XXX check if swapping is necessary on BE */
8399 if (ring->use_doorbell)
8400 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr);
8401 else
8402 BUG();
8403 return wptr;
8404 }
8405
gfx_v10_0_ring_set_wptr_compute(struct amdgpu_ring * ring)8406 static void gfx_v10_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
8407 {
8408 struct amdgpu_device *adev = ring->adev;
8409 uint32_t *wptr_saved;
8410 uint32_t *is_queue_unmap;
8411 uint64_t aggregated_db_index;
8412 uint32_t mqd_size = adev->mqds[AMDGPU_HW_IP_COMPUTE].mqd_size;
8413 uint64_t wptr_tmp;
8414
8415 if (ring->is_mes_queue) {
8416 wptr_saved = (uint32_t *)(ring->mqd_ptr + mqd_size);
8417 is_queue_unmap = (uint32_t *)(ring->mqd_ptr + mqd_size +
8418 sizeof(uint32_t));
8419 aggregated_db_index =
8420 amdgpu_mes_get_aggregated_doorbell_index(adev,
8421 AMDGPU_MES_PRIORITY_LEVEL_NORMAL);
8422
8423 wptr_tmp = ring->wptr & ring->buf_mask;
8424 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, wptr_tmp);
8425 *wptr_saved = wptr_tmp;
8426 /* assume doorbell always used by mes mapped queue */
8427 if (*is_queue_unmap) {
8428 WDOORBELL64(aggregated_db_index, wptr_tmp);
8429 WDOORBELL64(ring->doorbell_index, wptr_tmp);
8430 } else {
8431 WDOORBELL64(ring->doorbell_index, wptr_tmp);
8432
8433 if (*is_queue_unmap)
8434 WDOORBELL64(aggregated_db_index, wptr_tmp);
8435 }
8436 } else {
8437 /* XXX check if swapping is necessary on BE */
8438 if (ring->use_doorbell) {
8439 atomic64_set((atomic64_t *)ring->wptr_cpu_addr,
8440 ring->wptr);
8441 WDOORBELL64(ring->doorbell_index, ring->wptr);
8442 } else {
8443 BUG(); /* only DOORBELL method supported on gfx10 now */
8444 }
8445 }
8446 }
8447
gfx_v10_0_ring_emit_hdp_flush(struct amdgpu_ring * ring)8448 static void gfx_v10_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
8449 {
8450 struct amdgpu_device *adev = ring->adev;
8451 u32 ref_and_mask, reg_mem_engine;
8452 const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
8453
8454 if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
8455 switch (ring->me) {
8456 case 1:
8457 ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe;
8458 break;
8459 case 2:
8460 ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe;
8461 break;
8462 default:
8463 return;
8464 }
8465 reg_mem_engine = 0;
8466 } else {
8467 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0;
8468 reg_mem_engine = 1; /* pfp */
8469 }
8470
8471 gfx_v10_0_wait_reg_mem(ring, reg_mem_engine, 0, 1,
8472 adev->nbio.funcs->get_hdp_flush_req_offset(adev),
8473 adev->nbio.funcs->get_hdp_flush_done_offset(adev),
8474 ref_and_mask, ref_and_mask, 0x20);
8475 }
8476
gfx_v10_0_ring_emit_ib_gfx(struct amdgpu_ring * ring,struct amdgpu_job * job,struct amdgpu_ib * ib,uint32_t flags)8477 static void gfx_v10_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
8478 struct amdgpu_job *job,
8479 struct amdgpu_ib *ib,
8480 uint32_t flags)
8481 {
8482 unsigned vmid = AMDGPU_JOB_GET_VMID(job);
8483 u32 header, control = 0;
8484
8485 if (ib->flags & AMDGPU_IB_FLAG_CE)
8486 header = PACKET3(PACKET3_INDIRECT_BUFFER_CNST, 2);
8487 else
8488 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
8489
8490 control |= ib->length_dw | (vmid << 24);
8491
8492 if ((amdgpu_sriov_vf(ring->adev) || amdgpu_mcbp) && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) {
8493 control |= INDIRECT_BUFFER_PRE_ENB(1);
8494
8495 if (flags & AMDGPU_IB_PREEMPTED)
8496 control |= INDIRECT_BUFFER_PRE_RESUME(1);
8497
8498 if (!(ib->flags & AMDGPU_IB_FLAG_CE) && vmid)
8499 gfx_v10_0_ring_emit_de_meta(ring,
8500 (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false);
8501 }
8502
8503 if (ring->is_mes_queue)
8504 /* inherit vmid from mqd */
8505 control |= 0x400000;
8506
8507 amdgpu_ring_write(ring, header);
8508 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
8509 amdgpu_ring_write(ring,
8510 #ifdef __BIG_ENDIAN
8511 (2 << 0) |
8512 #endif
8513 lower_32_bits(ib->gpu_addr));
8514 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
8515 amdgpu_ring_write(ring, control);
8516 }
8517
gfx_v10_0_ring_emit_ib_compute(struct amdgpu_ring * ring,struct amdgpu_job * job,struct amdgpu_ib * ib,uint32_t flags)8518 static void gfx_v10_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
8519 struct amdgpu_job *job,
8520 struct amdgpu_ib *ib,
8521 uint32_t flags)
8522 {
8523 unsigned vmid = AMDGPU_JOB_GET_VMID(job);
8524 u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24);
8525
8526 if (ring->is_mes_queue)
8527 /* inherit vmid from mqd */
8528 control |= 0x40000000;
8529
8530 /* Currently, there is a high possibility to get wave ID mismatch
8531 * between ME and GDS, leading to a hw deadlock, because ME generates
8532 * different wave IDs than the GDS expects. This situation happens
8533 * randomly when at least 5 compute pipes use GDS ordered append.
8534 * The wave IDs generated by ME are also wrong after suspend/resume.
8535 * Those are probably bugs somewhere else in the kernel driver.
8536 *
8537 * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and
8538 * GDS to 0 for this ring (me/pipe).
8539 */
8540 if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) {
8541 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
8542 amdgpu_ring_write(ring, mmGDS_COMPUTE_MAX_WAVE_ID);
8543 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id);
8544 }
8545
8546 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
8547 BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
8548 amdgpu_ring_write(ring,
8549 #ifdef __BIG_ENDIAN
8550 (2 << 0) |
8551 #endif
8552 lower_32_bits(ib->gpu_addr));
8553 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
8554 amdgpu_ring_write(ring, control);
8555 }
8556
gfx_v10_0_ring_emit_fence(struct amdgpu_ring * ring,u64 addr,u64 seq,unsigned flags)8557 static void gfx_v10_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
8558 u64 seq, unsigned flags)
8559 {
8560 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
8561 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
8562
8563 /* RELEASE_MEM - flush caches, send int */
8564 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6));
8565 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ |
8566 PACKET3_RELEASE_MEM_GCR_GL2_WB |
8567 PACKET3_RELEASE_MEM_GCR_GLM_INV | /* must be set with GLM_WB */
8568 PACKET3_RELEASE_MEM_GCR_GLM_WB |
8569 PACKET3_RELEASE_MEM_CACHE_POLICY(3) |
8570 PACKET3_RELEASE_MEM_EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
8571 PACKET3_RELEASE_MEM_EVENT_INDEX(5)));
8572 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_DATA_SEL(write64bit ? 2 : 1) |
8573 PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0)));
8574
8575 /*
8576 * the address should be Qword aligned if 64bit write, Dword
8577 * aligned if only send 32bit data low (discard data high)
8578 */
8579 if (write64bit)
8580 BUG_ON(addr & 0x7);
8581 else
8582 BUG_ON(addr & 0x3);
8583 amdgpu_ring_write(ring, lower_32_bits(addr));
8584 amdgpu_ring_write(ring, upper_32_bits(addr));
8585 amdgpu_ring_write(ring, lower_32_bits(seq));
8586 amdgpu_ring_write(ring, upper_32_bits(seq));
8587 amdgpu_ring_write(ring, ring->is_mes_queue ?
8588 (ring->hw_queue_id | AMDGPU_FENCE_MES_QUEUE_FLAG) : 0);
8589 }
8590
gfx_v10_0_ring_emit_pipeline_sync(struct amdgpu_ring * ring)8591 static void gfx_v10_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
8592 {
8593 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
8594 uint32_t seq = ring->fence_drv.sync_seq;
8595 uint64_t addr = ring->fence_drv.gpu_addr;
8596
8597 gfx_v10_0_wait_reg_mem(ring, usepfp, 1, 0, lower_32_bits(addr),
8598 upper_32_bits(addr), seq, 0xffffffff, 4);
8599 }
8600
gfx_v10_0_ring_invalidate_tlbs(struct amdgpu_ring * ring,uint16_t pasid,uint32_t flush_type,bool all_hub,uint8_t dst_sel)8601 static void gfx_v10_0_ring_invalidate_tlbs(struct amdgpu_ring *ring,
8602 uint16_t pasid, uint32_t flush_type,
8603 bool all_hub, uint8_t dst_sel)
8604 {
8605 amdgpu_ring_write(ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0));
8606 amdgpu_ring_write(ring,
8607 PACKET3_INVALIDATE_TLBS_DST_SEL(dst_sel) |
8608 PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) |
8609 PACKET3_INVALIDATE_TLBS_PASID(pasid) |
8610 PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type));
8611 }
8612
gfx_v10_0_ring_emit_vm_flush(struct amdgpu_ring * ring,unsigned vmid,uint64_t pd_addr)8613 static void gfx_v10_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
8614 unsigned vmid, uint64_t pd_addr)
8615 {
8616 if (ring->is_mes_queue)
8617 gfx_v10_0_ring_invalidate_tlbs(ring, 0, 0, false, 0);
8618 else
8619 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
8620
8621 /* compute doesn't have PFP */
8622 if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) {
8623 /* sync PFP to ME, otherwise we might get invalid PFP reads */
8624 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
8625 amdgpu_ring_write(ring, 0x0);
8626 }
8627 }
8628
gfx_v10_0_ring_emit_fence_kiq(struct amdgpu_ring * ring,u64 addr,u64 seq,unsigned int flags)8629 static void gfx_v10_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr,
8630 u64 seq, unsigned int flags)
8631 {
8632 struct amdgpu_device *adev = ring->adev;
8633
8634 /* we only allocate 32bit for each seq wb address */
8635 BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
8636
8637 /* write fence seq to the "addr" */
8638 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
8639 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
8640 WRITE_DATA_DST_SEL(5) | WR_CONFIRM));
8641 amdgpu_ring_write(ring, lower_32_bits(addr));
8642 amdgpu_ring_write(ring, upper_32_bits(addr));
8643 amdgpu_ring_write(ring, lower_32_bits(seq));
8644
8645 if (flags & AMDGPU_FENCE_FLAG_INT) {
8646 /* set register to trigger INT */
8647 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
8648 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
8649 WRITE_DATA_DST_SEL(0) | WR_CONFIRM));
8650 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmCPC_INT_STATUS));
8651 amdgpu_ring_write(ring, 0);
8652 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */
8653 }
8654 }
8655
gfx_v10_0_ring_emit_sb(struct amdgpu_ring * ring)8656 static void gfx_v10_0_ring_emit_sb(struct amdgpu_ring *ring)
8657 {
8658 amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
8659 amdgpu_ring_write(ring, 0);
8660 }
8661
gfx_v10_0_ring_emit_cntxcntl(struct amdgpu_ring * ring,uint32_t flags)8662 static void gfx_v10_0_ring_emit_cntxcntl(struct amdgpu_ring *ring,
8663 uint32_t flags)
8664 {
8665 uint32_t dw2 = 0;
8666
8667 if (amdgpu_mcbp || amdgpu_sriov_vf(ring->adev))
8668 gfx_v10_0_ring_emit_ce_meta(ring,
8669 (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false);
8670
8671 dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */
8672 if (flags & AMDGPU_HAVE_CTX_SWITCH) {
8673 /* set load_global_config & load_global_uconfig */
8674 dw2 |= 0x8001;
8675 /* set load_cs_sh_regs */
8676 dw2 |= 0x01000000;
8677 /* set load_per_context_state & load_gfx_sh_regs for GFX */
8678 dw2 |= 0x10002;
8679
8680 /* set load_ce_ram if preamble presented */
8681 if (AMDGPU_PREAMBLE_IB_PRESENT & flags)
8682 dw2 |= 0x10000000;
8683 } else {
8684 /* still load_ce_ram if this is the first time preamble presented
8685 * although there is no context switch happens.
8686 */
8687 if (AMDGPU_PREAMBLE_IB_PRESENT_FIRST & flags)
8688 dw2 |= 0x10000000;
8689 }
8690
8691 amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
8692 amdgpu_ring_write(ring, dw2);
8693 amdgpu_ring_write(ring, 0);
8694 }
8695
gfx_v10_0_ring_emit_init_cond_exec(struct amdgpu_ring * ring)8696 static unsigned gfx_v10_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring)
8697 {
8698 unsigned ret;
8699
8700 amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3));
8701 amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
8702 amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
8703 amdgpu_ring_write(ring, 0); /* discard following DWs if *cond_exec_gpu_addr==0 */
8704 ret = ring->wptr & ring->buf_mask;
8705 amdgpu_ring_write(ring, 0x55aa55aa); /* patch dummy value later */
8706
8707 return ret;
8708 }
8709
gfx_v10_0_ring_emit_patch_cond_exec(struct amdgpu_ring * ring,unsigned offset)8710 static void gfx_v10_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigned offset)
8711 {
8712 unsigned cur;
8713 BUG_ON(offset > ring->buf_mask);
8714 BUG_ON(ring->ring[offset] != 0x55aa55aa);
8715
8716 cur = (ring->wptr - 1) & ring->buf_mask;
8717 if (likely(cur > offset))
8718 ring->ring[offset] = cur - offset;
8719 else
8720 ring->ring[offset] = (ring->buf_mask + 1) - offset + cur;
8721 }
8722
gfx_v10_0_ring_preempt_ib(struct amdgpu_ring * ring)8723 static int gfx_v10_0_ring_preempt_ib(struct amdgpu_ring *ring)
8724 {
8725 int i, r = 0;
8726 struct amdgpu_device *adev = ring->adev;
8727 struct amdgpu_kiq *kiq = &adev->gfx.kiq;
8728 struct amdgpu_ring *kiq_ring = &kiq->ring;
8729 unsigned long flags;
8730
8731 if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
8732 return -EINVAL;
8733
8734 spin_lock_irqsave(&kiq->ring_lock, flags);
8735
8736 if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) {
8737 spin_unlock_irqrestore(&kiq->ring_lock, flags);
8738 return -ENOMEM;
8739 }
8740
8741 /* assert preemption condition */
8742 amdgpu_ring_set_preempt_cond_exec(ring, false);
8743
8744 /* assert IB preemption, emit the trailing fence */
8745 kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP,
8746 ring->trail_fence_gpu_addr,
8747 ++ring->trail_seq);
8748 amdgpu_ring_commit(kiq_ring);
8749
8750 spin_unlock_irqrestore(&kiq->ring_lock, flags);
8751
8752 /* poll the trailing fence */
8753 for (i = 0; i < adev->usec_timeout; i++) {
8754 if (ring->trail_seq ==
8755 le32_to_cpu(*(ring->trail_fence_cpu_addr)))
8756 break;
8757 udelay(1);
8758 }
8759
8760 if (i >= adev->usec_timeout) {
8761 r = -EINVAL;
8762 DRM_ERROR("ring %d failed to preempt ib\n", ring->idx);
8763 }
8764
8765 /* deassert preemption condition */
8766 amdgpu_ring_set_preempt_cond_exec(ring, true);
8767 return r;
8768 }
8769
gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring * ring,bool resume)8770 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume)
8771 {
8772 struct amdgpu_device *adev = ring->adev;
8773 struct v10_ce_ib_state ce_payload = {0};
8774 uint64_t offset, ce_payload_gpu_addr;
8775 void *ce_payload_cpu_addr;
8776 int cnt;
8777
8778 cnt = (sizeof(ce_payload) >> 2) + 4 - 2;
8779
8780 if (ring->is_mes_queue) {
8781 offset = offsetof(struct amdgpu_mes_ctx_meta_data,
8782 gfx[0].gfx_meta_data) +
8783 offsetof(struct v10_gfx_meta_data, ce_payload);
8784 ce_payload_gpu_addr =
8785 amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
8786 ce_payload_cpu_addr =
8787 amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);
8788 } else {
8789 offset = offsetof(struct v10_gfx_meta_data, ce_payload);
8790 ce_payload_gpu_addr = amdgpu_csa_vaddr(ring->adev) + offset;
8791 ce_payload_cpu_addr = adev->virt.csa_cpu_addr + offset;
8792 }
8793
8794 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
8795 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) |
8796 WRITE_DATA_DST_SEL(8) |
8797 WR_CONFIRM) |
8798 WRITE_DATA_CACHE_POLICY(0));
8799 amdgpu_ring_write(ring, lower_32_bits(ce_payload_gpu_addr));
8800 amdgpu_ring_write(ring, upper_32_bits(ce_payload_gpu_addr));
8801
8802 if (resume)
8803 amdgpu_ring_write_multiple(ring, ce_payload_cpu_addr,
8804 sizeof(ce_payload) >> 2);
8805 else
8806 amdgpu_ring_write_multiple(ring, (void *)&ce_payload,
8807 sizeof(ce_payload) >> 2);
8808 }
8809
gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring * ring,bool resume)8810 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume)
8811 {
8812 struct amdgpu_device *adev = ring->adev;
8813 struct v10_de_ib_state de_payload = {0};
8814 uint64_t offset, gds_addr, de_payload_gpu_addr;
8815 void *de_payload_cpu_addr;
8816 int cnt;
8817
8818 if (ring->is_mes_queue) {
8819 offset = offsetof(struct amdgpu_mes_ctx_meta_data,
8820 gfx[0].gfx_meta_data) +
8821 offsetof(struct v10_gfx_meta_data, de_payload);
8822 de_payload_gpu_addr =
8823 amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
8824 de_payload_cpu_addr =
8825 amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);
8826
8827 offset = offsetof(struct amdgpu_mes_ctx_meta_data,
8828 gfx[0].gds_backup) +
8829 offsetof(struct v10_gfx_meta_data, de_payload);
8830 gds_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
8831 } else {
8832 offset = offsetof(struct v10_gfx_meta_data, de_payload);
8833 de_payload_gpu_addr = amdgpu_csa_vaddr(ring->adev) + offset;
8834 de_payload_cpu_addr = adev->virt.csa_cpu_addr + offset;
8835
8836 gds_addr = ALIGN(amdgpu_csa_vaddr(ring->adev) +
8837 AMDGPU_CSA_SIZE - adev->gds.gds_size,
8838 PAGE_SIZE);
8839 }
8840
8841 de_payload.gds_backup_addrlo = lower_32_bits(gds_addr);
8842 de_payload.gds_backup_addrhi = upper_32_bits(gds_addr);
8843
8844 cnt = (sizeof(de_payload) >> 2) + 4 - 2;
8845 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
8846 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
8847 WRITE_DATA_DST_SEL(8) |
8848 WR_CONFIRM) |
8849 WRITE_DATA_CACHE_POLICY(0));
8850 amdgpu_ring_write(ring, lower_32_bits(de_payload_gpu_addr));
8851 amdgpu_ring_write(ring, upper_32_bits(de_payload_gpu_addr));
8852
8853 if (resume)
8854 amdgpu_ring_write_multiple(ring, de_payload_cpu_addr,
8855 sizeof(de_payload) >> 2);
8856 else
8857 amdgpu_ring_write_multiple(ring, (void *)&de_payload,
8858 sizeof(de_payload) >> 2);
8859 }
8860
gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring * ring,bool start,bool secure)8861 static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start,
8862 bool secure)
8863 {
8864 uint32_t v = secure ? FRAME_TMZ : 0;
8865
8866 amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0));
8867 amdgpu_ring_write(ring, v | FRAME_CMD(start ? 0 : 1));
8868 }
8869
gfx_v10_0_ring_emit_rreg(struct amdgpu_ring * ring,uint32_t reg,uint32_t reg_val_offs)8870 static void gfx_v10_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg,
8871 uint32_t reg_val_offs)
8872 {
8873 struct amdgpu_device *adev = ring->adev;
8874
8875 amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4));
8876 amdgpu_ring_write(ring, 0 | /* src: register*/
8877 (5 << 8) | /* dst: memory */
8878 (1 << 20)); /* write confirm */
8879 amdgpu_ring_write(ring, reg);
8880 amdgpu_ring_write(ring, 0);
8881 amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr +
8882 reg_val_offs * 4));
8883 amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr +
8884 reg_val_offs * 4));
8885 }
8886
gfx_v10_0_ring_emit_wreg(struct amdgpu_ring * ring,uint32_t reg,uint32_t val)8887 static void gfx_v10_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
8888 uint32_t val)
8889 {
8890 uint32_t cmd = 0;
8891
8892 switch (ring->funcs->type) {
8893 case AMDGPU_RING_TYPE_GFX:
8894 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM;
8895 break;
8896 case AMDGPU_RING_TYPE_KIQ:
8897 cmd = (1 << 16); /* no inc addr */
8898 break;
8899 default:
8900 cmd = WR_CONFIRM;
8901 break;
8902 }
8903 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
8904 amdgpu_ring_write(ring, cmd);
8905 amdgpu_ring_write(ring, reg);
8906 amdgpu_ring_write(ring, 0);
8907 amdgpu_ring_write(ring, val);
8908 }
8909
gfx_v10_0_ring_emit_reg_wait(struct amdgpu_ring * ring,uint32_t reg,uint32_t val,uint32_t mask)8910 static void gfx_v10_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
8911 uint32_t val, uint32_t mask)
8912 {
8913 gfx_v10_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20);
8914 }
8915
gfx_v10_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring * ring,uint32_t reg0,uint32_t reg1,uint32_t ref,uint32_t mask)8916 static void gfx_v10_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
8917 uint32_t reg0, uint32_t reg1,
8918 uint32_t ref, uint32_t mask)
8919 {
8920 int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
8921 struct amdgpu_device *adev = ring->adev;
8922 bool fw_version_ok = false;
8923
8924 fw_version_ok = adev->gfx.cp_fw_write_wait;
8925
8926 if (fw_version_ok)
8927 gfx_v10_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1,
8928 ref, mask, 0x20);
8929 else
8930 amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1,
8931 ref, mask);
8932 }
8933
gfx_v10_0_ring_soft_recovery(struct amdgpu_ring * ring,unsigned vmid)8934 static void gfx_v10_0_ring_soft_recovery(struct amdgpu_ring *ring,
8935 unsigned vmid)
8936 {
8937 struct amdgpu_device *adev = ring->adev;
8938 uint32_t value = 0;
8939
8940 value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03);
8941 value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01);
8942 value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1);
8943 value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid);
8944 WREG32_SOC15(GC, 0, mmSQ_CMD, value);
8945 }
8946
8947 static void
gfx_v10_0_set_gfx_eop_interrupt_state(struct amdgpu_device * adev,uint32_t me,uint32_t pipe,enum amdgpu_interrupt_state state)8948 gfx_v10_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
8949 uint32_t me, uint32_t pipe,
8950 enum amdgpu_interrupt_state state)
8951 {
8952 uint32_t cp_int_cntl, cp_int_cntl_reg;
8953
8954 if (!me) {
8955 switch (pipe) {
8956 case 0:
8957 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0);
8958 break;
8959 case 1:
8960 cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING1);
8961 break;
8962 default:
8963 DRM_DEBUG("invalid pipe %d\n", pipe);
8964 return;
8965 }
8966 } else {
8967 DRM_DEBUG("invalid me %d\n", me);
8968 return;
8969 }
8970
8971 switch (state) {
8972 case AMDGPU_IRQ_STATE_DISABLE:
8973 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
8974 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
8975 TIME_STAMP_INT_ENABLE, 0);
8976 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
8977 break;
8978 case AMDGPU_IRQ_STATE_ENABLE:
8979 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
8980 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
8981 TIME_STAMP_INT_ENABLE, 1);
8982 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
8983 break;
8984 default:
8985 break;
8986 }
8987 }
8988
gfx_v10_0_set_compute_eop_interrupt_state(struct amdgpu_device * adev,int me,int pipe,enum amdgpu_interrupt_state state)8989 static void gfx_v10_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
8990 int me, int pipe,
8991 enum amdgpu_interrupt_state state)
8992 {
8993 u32 mec_int_cntl, mec_int_cntl_reg;
8994
8995 /*
8996 * amdgpu controls only the first MEC. That's why this function only
8997 * handles the setting of interrupts for this specific MEC. All other
8998 * pipes' interrupts are set by amdkfd.
8999 */
9000
9001 if (me == 1) {
9002 switch (pipe) {
9003 case 0:
9004 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
9005 break;
9006 case 1:
9007 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL);
9008 break;
9009 case 2:
9010 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL);
9011 break;
9012 case 3:
9013 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL);
9014 break;
9015 default:
9016 DRM_DEBUG("invalid pipe %d\n", pipe);
9017 return;
9018 }
9019 } else {
9020 DRM_DEBUG("invalid me %d\n", me);
9021 return;
9022 }
9023
9024 switch (state) {
9025 case AMDGPU_IRQ_STATE_DISABLE:
9026 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg);
9027 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
9028 TIME_STAMP_INT_ENABLE, 0);
9029 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl);
9030 break;
9031 case AMDGPU_IRQ_STATE_ENABLE:
9032 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg);
9033 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
9034 TIME_STAMP_INT_ENABLE, 1);
9035 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl);
9036 break;
9037 default:
9038 break;
9039 }
9040 }
9041
gfx_v10_0_set_eop_interrupt_state(struct amdgpu_device * adev,struct amdgpu_irq_src * src,unsigned type,enum amdgpu_interrupt_state state)9042 static int gfx_v10_0_set_eop_interrupt_state(struct amdgpu_device *adev,
9043 struct amdgpu_irq_src *src,
9044 unsigned type,
9045 enum amdgpu_interrupt_state state)
9046 {
9047 switch (type) {
9048 case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP:
9049 gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 0, state);
9050 break;
9051 case AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP:
9052 gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 1, state);
9053 break;
9054 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
9055 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 0, state);
9056 break;
9057 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
9058 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 1, state);
9059 break;
9060 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
9061 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 2, state);
9062 break;
9063 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
9064 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 3, state);
9065 break;
9066 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP:
9067 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 0, state);
9068 break;
9069 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP:
9070 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 1, state);
9071 break;
9072 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP:
9073 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 2, state);
9074 break;
9075 case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP:
9076 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 3, state);
9077 break;
9078 default:
9079 break;
9080 }
9081 return 0;
9082 }
9083
gfx_v10_0_eop_irq(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)9084 static int gfx_v10_0_eop_irq(struct amdgpu_device *adev,
9085 struct amdgpu_irq_src *source,
9086 struct amdgpu_iv_entry *entry)
9087 {
9088 int i;
9089 u8 me_id, pipe_id, queue_id;
9090 struct amdgpu_ring *ring;
9091 uint32_t mes_queue_id = entry->src_data[0];
9092
9093 DRM_DEBUG("IH: CP EOP\n");
9094
9095 if (adev->enable_mes && (mes_queue_id & AMDGPU_FENCE_MES_QUEUE_FLAG)) {
9096 struct amdgpu_mes_queue *queue;
9097
9098 mes_queue_id &= AMDGPU_FENCE_MES_QUEUE_ID_MASK;
9099
9100 spin_lock(&adev->mes.queue_id_lock);
9101 queue = idr_find(&adev->mes.queue_id_idr, mes_queue_id);
9102 if (queue) {
9103 DRM_DEBUG("process mes queue id = %d\n", mes_queue_id);
9104 amdgpu_fence_process(queue->ring);
9105 }
9106 spin_unlock(&adev->mes.queue_id_lock);
9107 } else {
9108 me_id = (entry->ring_id & 0x0c) >> 2;
9109 pipe_id = (entry->ring_id & 0x03) >> 0;
9110 queue_id = (entry->ring_id & 0x70) >> 4;
9111
9112 switch (me_id) {
9113 case 0:
9114 if (pipe_id == 0)
9115 amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
9116 else
9117 amdgpu_fence_process(&adev->gfx.gfx_ring[1]);
9118 break;
9119 case 1:
9120 case 2:
9121 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
9122 ring = &adev->gfx.compute_ring[i];
9123 /* Per-queue interrupt is supported for MEC starting from VI.
9124 * The interrupt can only be enabled/disabled per pipe instead
9125 * of per queue.
9126 */
9127 if ((ring->me == me_id) &&
9128 (ring->pipe == pipe_id) &&
9129 (ring->queue == queue_id))
9130 amdgpu_fence_process(ring);
9131 }
9132 break;
9133 }
9134 }
9135
9136 return 0;
9137 }
9138
gfx_v10_0_set_priv_reg_fault_state(struct amdgpu_device * adev,struct amdgpu_irq_src * source,unsigned type,enum amdgpu_interrupt_state state)9139 static int gfx_v10_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
9140 struct amdgpu_irq_src *source,
9141 unsigned type,
9142 enum amdgpu_interrupt_state state)
9143 {
9144 switch (state) {
9145 case AMDGPU_IRQ_STATE_DISABLE:
9146 case AMDGPU_IRQ_STATE_ENABLE:
9147 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
9148 PRIV_REG_INT_ENABLE,
9149 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
9150 break;
9151 default:
9152 break;
9153 }
9154
9155 return 0;
9156 }
9157
gfx_v10_0_set_priv_inst_fault_state(struct amdgpu_device * adev,struct amdgpu_irq_src * source,unsigned type,enum amdgpu_interrupt_state state)9158 static int gfx_v10_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
9159 struct amdgpu_irq_src *source,
9160 unsigned type,
9161 enum amdgpu_interrupt_state state)
9162 {
9163 switch (state) {
9164 case AMDGPU_IRQ_STATE_DISABLE:
9165 case AMDGPU_IRQ_STATE_ENABLE:
9166 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
9167 PRIV_INSTR_INT_ENABLE,
9168 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
9169 break;
9170 default:
9171 break;
9172 }
9173
9174 return 0;
9175 }
9176
gfx_v10_0_handle_priv_fault(struct amdgpu_device * adev,struct amdgpu_iv_entry * entry)9177 static void gfx_v10_0_handle_priv_fault(struct amdgpu_device *adev,
9178 struct amdgpu_iv_entry *entry)
9179 {
9180 u8 me_id, pipe_id, queue_id;
9181 struct amdgpu_ring *ring;
9182 int i;
9183
9184 me_id = (entry->ring_id & 0x0c) >> 2;
9185 pipe_id = (entry->ring_id & 0x03) >> 0;
9186 queue_id = (entry->ring_id & 0x70) >> 4;
9187
9188 switch (me_id) {
9189 case 0:
9190 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
9191 ring = &adev->gfx.gfx_ring[i];
9192 /* we only enabled 1 gfx queue per pipe for now */
9193 if (ring->me == me_id && ring->pipe == pipe_id)
9194 drm_sched_fault(&ring->sched);
9195 }
9196 break;
9197 case 1:
9198 case 2:
9199 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
9200 ring = &adev->gfx.compute_ring[i];
9201 if (ring->me == me_id && ring->pipe == pipe_id &&
9202 ring->queue == queue_id)
9203 drm_sched_fault(&ring->sched);
9204 }
9205 break;
9206 default:
9207 BUG();
9208 }
9209 }
9210
gfx_v10_0_priv_reg_irq(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)9211 static int gfx_v10_0_priv_reg_irq(struct amdgpu_device *adev,
9212 struct amdgpu_irq_src *source,
9213 struct amdgpu_iv_entry *entry)
9214 {
9215 DRM_ERROR("Illegal register access in command stream\n");
9216 gfx_v10_0_handle_priv_fault(adev, entry);
9217 return 0;
9218 }
9219
gfx_v10_0_priv_inst_irq(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)9220 static int gfx_v10_0_priv_inst_irq(struct amdgpu_device *adev,
9221 struct amdgpu_irq_src *source,
9222 struct amdgpu_iv_entry *entry)
9223 {
9224 DRM_ERROR("Illegal instruction in command stream\n");
9225 gfx_v10_0_handle_priv_fault(adev, entry);
9226 return 0;
9227 }
9228
gfx_v10_0_kiq_set_interrupt_state(struct amdgpu_device * adev,struct amdgpu_irq_src * src,unsigned int type,enum amdgpu_interrupt_state state)9229 static int gfx_v10_0_kiq_set_interrupt_state(struct amdgpu_device *adev,
9230 struct amdgpu_irq_src *src,
9231 unsigned int type,
9232 enum amdgpu_interrupt_state state)
9233 {
9234 uint32_t tmp, target;
9235 struct amdgpu_ring *ring = &(adev->gfx.kiq.ring);
9236
9237 if (ring->me == 1)
9238 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
9239 else
9240 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME2_PIPE0_INT_CNTL);
9241 target += ring->pipe;
9242
9243 switch (type) {
9244 case AMDGPU_CP_KIQ_IRQ_DRIVER0:
9245 if (state == AMDGPU_IRQ_STATE_DISABLE) {
9246 tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
9247 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
9248 GENERIC2_INT_ENABLE, 0);
9249 WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
9250
9251 tmp = RREG32_SOC15_IP(GC, target);
9252 tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
9253 GENERIC2_INT_ENABLE, 0);
9254 WREG32_SOC15_IP(GC, target, tmp);
9255 } else {
9256 tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
9257 tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
9258 GENERIC2_INT_ENABLE, 1);
9259 WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
9260
9261 tmp = RREG32_SOC15_IP(GC, target);
9262 tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
9263 GENERIC2_INT_ENABLE, 1);
9264 WREG32_SOC15_IP(GC, target, tmp);
9265 }
9266 break;
9267 default:
9268 BUG(); /* kiq only support GENERIC2_INT now */
9269 break;
9270 }
9271 return 0;
9272 }
9273
gfx_v10_0_kiq_irq(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)9274 static int gfx_v10_0_kiq_irq(struct amdgpu_device *adev,
9275 struct amdgpu_irq_src *source,
9276 struct amdgpu_iv_entry *entry)
9277 {
9278 u8 me_id, pipe_id, queue_id;
9279 struct amdgpu_ring *ring = &(adev->gfx.kiq.ring);
9280
9281 me_id = (entry->ring_id & 0x0c) >> 2;
9282 pipe_id = (entry->ring_id & 0x03) >> 0;
9283 queue_id = (entry->ring_id & 0x70) >> 4;
9284 DRM_DEBUG("IH: CPC GENERIC2_INT, me:%d, pipe:%d, queue:%d\n",
9285 me_id, pipe_id, queue_id);
9286
9287 amdgpu_fence_process(ring);
9288 return 0;
9289 }
9290
gfx_v10_0_emit_mem_sync(struct amdgpu_ring * ring)9291 static void gfx_v10_0_emit_mem_sync(struct amdgpu_ring *ring)
9292 {
9293 const unsigned int gcr_cntl =
9294 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(1) |
9295 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(1) |
9296 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_INV(1) |
9297 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_WB(1) |
9298 PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_INV(1) |
9299 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(1) |
9300 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(1) |
9301 PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(1);
9302
9303 /* ACQUIRE_MEM - make one or more surfaces valid for use by the subsequent operations */
9304 amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 6));
9305 amdgpu_ring_write(ring, 0); /* CP_COHER_CNTL */
9306 amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */
9307 amdgpu_ring_write(ring, 0xffffff); /* CP_COHER_SIZE_HI */
9308 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */
9309 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE_HI */
9310 amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */
9311 amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */
9312 }
9313
9314 static const struct amd_ip_funcs gfx_v10_0_ip_funcs = {
9315 .name = "gfx_v10_0",
9316 .early_init = gfx_v10_0_early_init,
9317 .late_init = gfx_v10_0_late_init,
9318 .sw_init = gfx_v10_0_sw_init,
9319 .sw_fini = gfx_v10_0_sw_fini,
9320 .hw_init = gfx_v10_0_hw_init,
9321 .hw_fini = gfx_v10_0_hw_fini,
9322 .suspend = gfx_v10_0_suspend,
9323 .resume = gfx_v10_0_resume,
9324 .is_idle = gfx_v10_0_is_idle,
9325 .wait_for_idle = gfx_v10_0_wait_for_idle,
9326 .soft_reset = gfx_v10_0_soft_reset,
9327 .set_clockgating_state = gfx_v10_0_set_clockgating_state,
9328 .set_powergating_state = gfx_v10_0_set_powergating_state,
9329 .get_clockgating_state = gfx_v10_0_get_clockgating_state,
9330 };
9331
9332 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = {
9333 .type = AMDGPU_RING_TYPE_GFX,
9334 .align_mask = 0xff,
9335 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
9336 .support_64bit_ptrs = true,
9337 .secure_submission_supported = true,
9338 .vmhub = AMDGPU_GFXHUB_0,
9339 .get_rptr = gfx_v10_0_ring_get_rptr_gfx,
9340 .get_wptr = gfx_v10_0_ring_get_wptr_gfx,
9341 .set_wptr = gfx_v10_0_ring_set_wptr_gfx,
9342 .emit_frame_size = /* totally 242 maximum if 16 IBs */
9343 5 + /* COND_EXEC */
9344 7 + /* PIPELINE_SYNC */
9345 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
9346 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
9347 2 + /* VM_FLUSH */
9348 8 + /* FENCE for VM_FLUSH */
9349 20 + /* GDS switch */
9350 4 + /* double SWITCH_BUFFER,
9351 * the first COND_EXEC jump to the place
9352 * just prior to this double SWITCH_BUFFER
9353 */
9354 5 + /* COND_EXEC */
9355 7 + /* HDP_flush */
9356 4 + /* VGT_flush */
9357 14 + /* CE_META */
9358 31 + /* DE_META */
9359 3 + /* CNTX_CTRL */
9360 5 + /* HDP_INVL */
9361 8 + 8 + /* FENCE x2 */
9362 2 + /* SWITCH_BUFFER */
9363 8, /* gfx_v10_0_emit_mem_sync */
9364 .emit_ib_size = 4, /* gfx_v10_0_ring_emit_ib_gfx */
9365 .emit_ib = gfx_v10_0_ring_emit_ib_gfx,
9366 .emit_fence = gfx_v10_0_ring_emit_fence,
9367 .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync,
9368 .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush,
9369 .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch,
9370 .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush,
9371 .test_ring = gfx_v10_0_ring_test_ring,
9372 .test_ib = gfx_v10_0_ring_test_ib,
9373 .insert_nop = amdgpu_ring_insert_nop,
9374 .pad_ib = amdgpu_ring_generic_pad_ib,
9375 .emit_switch_buffer = gfx_v10_0_ring_emit_sb,
9376 .emit_cntxcntl = gfx_v10_0_ring_emit_cntxcntl,
9377 .init_cond_exec = gfx_v10_0_ring_emit_init_cond_exec,
9378 .patch_cond_exec = gfx_v10_0_ring_emit_patch_cond_exec,
9379 .preempt_ib = gfx_v10_0_ring_preempt_ib,
9380 .emit_frame_cntl = gfx_v10_0_ring_emit_frame_cntl,
9381 .emit_wreg = gfx_v10_0_ring_emit_wreg,
9382 .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
9383 .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
9384 .soft_recovery = gfx_v10_0_ring_soft_recovery,
9385 .emit_mem_sync = gfx_v10_0_emit_mem_sync,
9386 };
9387
9388 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_compute = {
9389 .type = AMDGPU_RING_TYPE_COMPUTE,
9390 .align_mask = 0xff,
9391 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
9392 .support_64bit_ptrs = true,
9393 .vmhub = AMDGPU_GFXHUB_0,
9394 .get_rptr = gfx_v10_0_ring_get_rptr_compute,
9395 .get_wptr = gfx_v10_0_ring_get_wptr_compute,
9396 .set_wptr = gfx_v10_0_ring_set_wptr_compute,
9397 .emit_frame_size =
9398 20 + /* gfx_v10_0_ring_emit_gds_switch */
9399 7 + /* gfx_v10_0_ring_emit_hdp_flush */
9400 5 + /* hdp invalidate */
9401 7 + /* gfx_v10_0_ring_emit_pipeline_sync */
9402 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
9403 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
9404 2 + /* gfx_v10_0_ring_emit_vm_flush */
9405 8 + 8 + 8 + /* gfx_v10_0_ring_emit_fence x3 for user fence, vm fence */
9406 8, /* gfx_v10_0_emit_mem_sync */
9407 .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */
9408 .emit_ib = gfx_v10_0_ring_emit_ib_compute,
9409 .emit_fence = gfx_v10_0_ring_emit_fence,
9410 .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync,
9411 .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush,
9412 .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch,
9413 .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush,
9414 .test_ring = gfx_v10_0_ring_test_ring,
9415 .test_ib = gfx_v10_0_ring_test_ib,
9416 .insert_nop = amdgpu_ring_insert_nop,
9417 .pad_ib = amdgpu_ring_generic_pad_ib,
9418 .emit_wreg = gfx_v10_0_ring_emit_wreg,
9419 .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
9420 .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
9421 .emit_mem_sync = gfx_v10_0_emit_mem_sync,
9422 };
9423
9424 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_kiq = {
9425 .type = AMDGPU_RING_TYPE_KIQ,
9426 .align_mask = 0xff,
9427 .nop = PACKET3(PACKET3_NOP, 0x3FFF),
9428 .support_64bit_ptrs = true,
9429 .vmhub = AMDGPU_GFXHUB_0,
9430 .get_rptr = gfx_v10_0_ring_get_rptr_compute,
9431 .get_wptr = gfx_v10_0_ring_get_wptr_compute,
9432 .set_wptr = gfx_v10_0_ring_set_wptr_compute,
9433 .emit_frame_size =
9434 20 + /* gfx_v10_0_ring_emit_gds_switch */
9435 7 + /* gfx_v10_0_ring_emit_hdp_flush */
9436 5 + /*hdp invalidate */
9437 7 + /* gfx_v10_0_ring_emit_pipeline_sync */
9438 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
9439 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
9440 2 + /* gfx_v10_0_ring_emit_vm_flush */
9441 8 + 8 + 8, /* gfx_v10_0_ring_emit_fence_kiq x3 for user fence, vm fence */
9442 .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */
9443 .emit_ib = gfx_v10_0_ring_emit_ib_compute,
9444 .emit_fence = gfx_v10_0_ring_emit_fence_kiq,
9445 .test_ring = gfx_v10_0_ring_test_ring,
9446 .test_ib = gfx_v10_0_ring_test_ib,
9447 .insert_nop = amdgpu_ring_insert_nop,
9448 .pad_ib = amdgpu_ring_generic_pad_ib,
9449 .emit_rreg = gfx_v10_0_ring_emit_rreg,
9450 .emit_wreg = gfx_v10_0_ring_emit_wreg,
9451 .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
9452 .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
9453 };
9454
gfx_v10_0_set_ring_funcs(struct amdgpu_device * adev)9455 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev)
9456 {
9457 int i;
9458
9459 adev->gfx.kiq.ring.funcs = &gfx_v10_0_ring_funcs_kiq;
9460
9461 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
9462 adev->gfx.gfx_ring[i].funcs = &gfx_v10_0_ring_funcs_gfx;
9463
9464 for (i = 0; i < adev->gfx.num_compute_rings; i++)
9465 adev->gfx.compute_ring[i].funcs = &gfx_v10_0_ring_funcs_compute;
9466 }
9467
9468 static const struct amdgpu_irq_src_funcs gfx_v10_0_eop_irq_funcs = {
9469 .set = gfx_v10_0_set_eop_interrupt_state,
9470 .process = gfx_v10_0_eop_irq,
9471 };
9472
9473 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_reg_irq_funcs = {
9474 .set = gfx_v10_0_set_priv_reg_fault_state,
9475 .process = gfx_v10_0_priv_reg_irq,
9476 };
9477
9478 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_inst_irq_funcs = {
9479 .set = gfx_v10_0_set_priv_inst_fault_state,
9480 .process = gfx_v10_0_priv_inst_irq,
9481 };
9482
9483 static const struct amdgpu_irq_src_funcs gfx_v10_0_kiq_irq_funcs = {
9484 .set = gfx_v10_0_kiq_set_interrupt_state,
9485 .process = gfx_v10_0_kiq_irq,
9486 };
9487
gfx_v10_0_set_irq_funcs(struct amdgpu_device * adev)9488 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev)
9489 {
9490 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
9491 adev->gfx.eop_irq.funcs = &gfx_v10_0_eop_irq_funcs;
9492
9493 adev->gfx.kiq.irq.num_types = AMDGPU_CP_KIQ_IRQ_LAST;
9494 adev->gfx.kiq.irq.funcs = &gfx_v10_0_kiq_irq_funcs;
9495
9496 adev->gfx.priv_reg_irq.num_types = 1;
9497 adev->gfx.priv_reg_irq.funcs = &gfx_v10_0_priv_reg_irq_funcs;
9498
9499 adev->gfx.priv_inst_irq.num_types = 1;
9500 adev->gfx.priv_inst_irq.funcs = &gfx_v10_0_priv_inst_irq_funcs;
9501 }
9502
gfx_v10_0_set_rlc_funcs(struct amdgpu_device * adev)9503 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev)
9504 {
9505 switch (adev->ip_versions[GC_HWIP][0]) {
9506 case IP_VERSION(10, 1, 10):
9507 case IP_VERSION(10, 1, 1):
9508 case IP_VERSION(10, 1, 3):
9509 case IP_VERSION(10, 1, 4):
9510 case IP_VERSION(10, 3, 2):
9511 case IP_VERSION(10, 3, 1):
9512 case IP_VERSION(10, 3, 4):
9513 case IP_VERSION(10, 3, 5):
9514 case IP_VERSION(10, 3, 6):
9515 case IP_VERSION(10, 3, 3):
9516 case IP_VERSION(10, 3, 7):
9517 adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs;
9518 break;
9519 case IP_VERSION(10, 1, 2):
9520 case IP_VERSION(10, 3, 0):
9521 adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs_sriov;
9522 break;
9523 default:
9524 break;
9525 }
9526 }
9527
gfx_v10_0_set_gds_init(struct amdgpu_device * adev)9528 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev)
9529 {
9530 unsigned total_cu = adev->gfx.config.max_cu_per_sh *
9531 adev->gfx.config.max_sh_per_se *
9532 adev->gfx.config.max_shader_engines;
9533
9534 adev->gds.gds_size = 0x10000;
9535 adev->gds.gds_compute_max_wave_id = total_cu * 32 - 1;
9536 adev->gds.gws_size = 64;
9537 adev->gds.oa_size = 16;
9538 }
9539
gfx_v10_0_set_mqd_funcs(struct amdgpu_device * adev)9540 static void gfx_v10_0_set_mqd_funcs(struct amdgpu_device *adev)
9541 {
9542 /* set gfx eng mqd */
9543 adev->mqds[AMDGPU_HW_IP_GFX].mqd_size =
9544 sizeof(struct v10_gfx_mqd);
9545 adev->mqds[AMDGPU_HW_IP_GFX].init_mqd =
9546 gfx_v10_0_gfx_mqd_init;
9547 /* set compute eng mqd */
9548 adev->mqds[AMDGPU_HW_IP_COMPUTE].mqd_size =
9549 sizeof(struct v10_compute_mqd);
9550 adev->mqds[AMDGPU_HW_IP_COMPUTE].init_mqd =
9551 gfx_v10_0_compute_mqd_init;
9552 }
9553
gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device * adev,u32 bitmap)9554 static void gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device *adev,
9555 u32 bitmap)
9556 {
9557 u32 data;
9558
9559 if (!bitmap)
9560 return;
9561
9562 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;
9563 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;
9564
9565 WREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG, data);
9566 }
9567
gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device * adev)9568 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev)
9569 {
9570 u32 disabled_mask =
9571 ~amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh >> 1);
9572 u32 efuse_setting = 0;
9573 u32 vbios_setting = 0;
9574
9575 efuse_setting = RREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG);
9576 efuse_setting &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;
9577 efuse_setting >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;
9578
9579 vbios_setting = RREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG);
9580 vbios_setting &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;
9581 vbios_setting >>= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;
9582
9583 disabled_mask |= efuse_setting | vbios_setting;
9584
9585 return (~disabled_mask);
9586 }
9587
gfx_v10_0_get_cu_active_bitmap_per_sh(struct amdgpu_device * adev)9588 static u32 gfx_v10_0_get_cu_active_bitmap_per_sh(struct amdgpu_device *adev)
9589 {
9590 u32 wgp_idx, wgp_active_bitmap;
9591 u32 cu_bitmap_per_wgp, cu_active_bitmap;
9592
9593 wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev);
9594 cu_active_bitmap = 0;
9595
9596 for (wgp_idx = 0; wgp_idx < 16; wgp_idx++) {
9597 /* if there is one WGP enabled, it means 2 CUs will be enabled */
9598 cu_bitmap_per_wgp = 3 << (2 * wgp_idx);
9599 if (wgp_active_bitmap & (1 << wgp_idx))
9600 cu_active_bitmap |= cu_bitmap_per_wgp;
9601 }
9602
9603 return cu_active_bitmap;
9604 }
9605
gfx_v10_0_get_cu_info(struct amdgpu_device * adev,struct amdgpu_cu_info * cu_info)9606 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev,
9607 struct amdgpu_cu_info *cu_info)
9608 {
9609 int i, j, k, counter, active_cu_number = 0;
9610 u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
9611 unsigned disable_masks[4 * 2];
9612
9613 if (!adev || !cu_info)
9614 return -EINVAL;
9615
9616 amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2);
9617
9618 mutex_lock(&adev->grbm_idx_mutex);
9619 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
9620 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
9621 bitmap = i * adev->gfx.config.max_sh_per_se + j;
9622 if (((adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 0)) ||
9623 (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 3)) ||
9624 (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 6)) ||
9625 (adev->ip_versions[GC_HWIP][0] == IP_VERSION(10, 3, 7))) &&
9626 ((gfx_v10_3_get_disabled_sa(adev) >> bitmap) & 1))
9627 continue;
9628 mask = 1;
9629 ao_bitmap = 0;
9630 counter = 0;
9631 gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff);
9632 if (i < 4 && j < 2)
9633 gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(
9634 adev, disable_masks[i * 2 + j]);
9635 bitmap = gfx_v10_0_get_cu_active_bitmap_per_sh(adev);
9636 cu_info->bitmap[i][j] = bitmap;
9637
9638 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) {
9639 if (bitmap & mask) {
9640 if (counter < adev->gfx.config.max_cu_per_sh)
9641 ao_bitmap |= mask;
9642 counter++;
9643 }
9644 mask <<= 1;
9645 }
9646 active_cu_number += counter;
9647 if (i < 2 && j < 2)
9648 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
9649 cu_info->ao_cu_bitmap[i][j] = ao_bitmap;
9650 }
9651 }
9652 gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
9653 mutex_unlock(&adev->grbm_idx_mutex);
9654
9655 cu_info->number = active_cu_number;
9656 cu_info->ao_cu_mask = ao_cu_mask;
9657 cu_info->simd_per_cu = NUM_SIMD_PER_CU;
9658
9659 return 0;
9660 }
9661
gfx_v10_3_get_disabled_sa(struct amdgpu_device * adev)9662 static u32 gfx_v10_3_get_disabled_sa(struct amdgpu_device *adev)
9663 {
9664 uint32_t efuse_setting, vbios_setting, disabled_sa, max_sa_mask;
9665
9666 efuse_setting = RREG32_SOC15(GC, 0, mmCC_GC_SA_UNIT_DISABLE);
9667 efuse_setting &= CC_GC_SA_UNIT_DISABLE__SA_DISABLE_MASK;
9668 efuse_setting >>= CC_GC_SA_UNIT_DISABLE__SA_DISABLE__SHIFT;
9669
9670 vbios_setting = RREG32_SOC15(GC, 0, mmGC_USER_SA_UNIT_DISABLE);
9671 vbios_setting &= GC_USER_SA_UNIT_DISABLE__SA_DISABLE_MASK;
9672 vbios_setting >>= GC_USER_SA_UNIT_DISABLE__SA_DISABLE__SHIFT;
9673
9674 max_sa_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_sh_per_se *
9675 adev->gfx.config.max_shader_engines);
9676 disabled_sa = efuse_setting | vbios_setting;
9677 disabled_sa &= max_sa_mask;
9678
9679 return disabled_sa;
9680 }
9681
gfx_v10_3_program_pbb_mode(struct amdgpu_device * adev)9682 static void gfx_v10_3_program_pbb_mode(struct amdgpu_device *adev)
9683 {
9684 uint32_t max_sa_per_se, max_sa_per_se_mask, max_shader_engines;
9685 uint32_t disabled_sa_mask, se_index, disabled_sa_per_se;
9686
9687 disabled_sa_mask = gfx_v10_3_get_disabled_sa(adev);
9688
9689 max_sa_per_se = adev->gfx.config.max_sh_per_se;
9690 max_sa_per_se_mask = (1 << max_sa_per_se) - 1;
9691 max_shader_engines = adev->gfx.config.max_shader_engines;
9692
9693 for (se_index = 0; max_shader_engines > se_index; se_index++) {
9694 disabled_sa_per_se = disabled_sa_mask >> (se_index * max_sa_per_se);
9695 disabled_sa_per_se &= max_sa_per_se_mask;
9696 if (disabled_sa_per_se == max_sa_per_se_mask) {
9697 WREG32_FIELD15(GC, 0, PA_SC_ENHANCE_3, FORCE_PBB_WORKLOAD_MODE_TO_ZERO, 1);
9698 break;
9699 }
9700 }
9701 }
9702
gfx_v10_3_set_power_brake_sequence(struct amdgpu_device * adev)9703 static void gfx_v10_3_set_power_brake_sequence(struct amdgpu_device *adev)
9704 {
9705 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX,
9706 (0x1 << GRBM_GFX_INDEX__SA_BROADCAST_WRITES__SHIFT) |
9707 (0x1 << GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES__SHIFT) |
9708 (0x1 << GRBM_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT));
9709
9710 WREG32_SOC15(GC, 0, mmGC_CAC_IND_INDEX, ixPWRBRK_STALL_PATTERN_CTRL);
9711 WREG32_SOC15(GC, 0, mmGC_CAC_IND_DATA,
9712 (0x1 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_STEP_INTERVAL__SHIFT) |
9713 (0x12 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_BEGIN_STEP__SHIFT) |
9714 (0x13 << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_END_STEP__SHIFT) |
9715 (0xf << PWRBRK_STALL_PATTERN_CTRL__PWRBRK_THROTTLE_PATTERN_BIT_NUMS__SHIFT));
9716
9717 WREG32_SOC15(GC, 0, mmGC_THROTTLE_CTRL_Sienna_Cichlid,
9718 (0x1 << GC_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT) |
9719 (0x1 << GC_THROTTLE_CTRL__PATTERN_MODE__SHIFT) |
9720 (0x5 << GC_THROTTLE_CTRL__RELEASE_STEP_INTERVAL__SHIFT));
9721
9722 WREG32_SOC15(GC, 0, mmDIDT_IND_INDEX, ixDIDT_SQ_THROTTLE_CTRL);
9723
9724 WREG32_SOC15(GC, 0, mmDIDT_IND_DATA,
9725 (0x1 << DIDT_SQ_THROTTLE_CTRL__PWRBRK_STALL_EN__SHIFT));
9726 }
9727
9728 const struct amdgpu_ip_block_version gfx_v10_0_ip_block =
9729 {
9730 .type = AMD_IP_BLOCK_TYPE_GFX,
9731 .major = 10,
9732 .minor = 0,
9733 .rev = 0,
9734 .funcs = &gfx_v10_0_ip_funcs,
9735 };
9736