1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/* Copyright (c) 2020 SiFive, Inc */
3
4/dts-v1/;
5
6#include <dt-bindings/clock/sifive-fu740-prci.h>
7
8/ {
9	#address-cells = <2>;
10	#size-cells = <2>;
11	compatible = "sifive,fu740-c000", "sifive,fu740";
12
13	aliases {
14		serial0 = &uart0;
15		serial1 = &uart1;
16		ethernet0 = &eth0;
17	};
18
19	chosen {
20	};
21
22	cpus {
23		#address-cells = <1>;
24		#size-cells = <0>;
25		cpu0: cpu@0 {
26			compatible = "sifive,bullet0", "riscv";
27			device_type = "cpu";
28			i-cache-block-size = <64>;
29			i-cache-sets = <128>;
30			i-cache-size = <16384>;
31			next-level-cache = <&ccache>;
32			reg = <0x0>;
33			riscv,isa = "rv64imac";
34			status = "disabled";
35			cpu0_intc: interrupt-controller {
36				#interrupt-cells = <1>;
37				compatible = "riscv,cpu-intc";
38				interrupt-controller;
39			};
40		};
41		cpu1: cpu@1 {
42			compatible = "sifive,bullet0", "riscv";
43			d-cache-block-size = <64>;
44			d-cache-sets = <64>;
45			d-cache-size = <32768>;
46			d-tlb-sets = <1>;
47			d-tlb-size = <40>;
48			device_type = "cpu";
49			i-cache-block-size = <64>;
50			i-cache-sets = <128>;
51			i-cache-size = <32768>;
52			i-tlb-sets = <1>;
53			i-tlb-size = <40>;
54			mmu-type = "riscv,sv39";
55			next-level-cache = <&ccache>;
56			reg = <0x1>;
57			riscv,isa = "rv64imafdc";
58			tlb-split;
59			cpu1_intc: interrupt-controller {
60				#interrupt-cells = <1>;
61				compatible = "riscv,cpu-intc";
62				interrupt-controller;
63			};
64		};
65		cpu2: cpu@2 {
66			compatible = "sifive,bullet0", "riscv";
67			d-cache-block-size = <64>;
68			d-cache-sets = <64>;
69			d-cache-size = <32768>;
70			d-tlb-sets = <1>;
71			d-tlb-size = <40>;
72			device_type = "cpu";
73			i-cache-block-size = <64>;
74			i-cache-sets = <128>;
75			i-cache-size = <32768>;
76			i-tlb-sets = <1>;
77			i-tlb-size = <40>;
78			mmu-type = "riscv,sv39";
79			next-level-cache = <&ccache>;
80			reg = <0x2>;
81			riscv,isa = "rv64imafdc";
82			tlb-split;
83			cpu2_intc: interrupt-controller {
84				#interrupt-cells = <1>;
85				compatible = "riscv,cpu-intc";
86				interrupt-controller;
87			};
88		};
89		cpu3: cpu@3 {
90			compatible = "sifive,bullet0", "riscv";
91			d-cache-block-size = <64>;
92			d-cache-sets = <64>;
93			d-cache-size = <32768>;
94			d-tlb-sets = <1>;
95			d-tlb-size = <40>;
96			device_type = "cpu";
97			i-cache-block-size = <64>;
98			i-cache-sets = <128>;
99			i-cache-size = <32768>;
100			i-tlb-sets = <1>;
101			i-tlb-size = <40>;
102			mmu-type = "riscv,sv39";
103			next-level-cache = <&ccache>;
104			reg = <0x3>;
105			riscv,isa = "rv64imafdc";
106			tlb-split;
107			cpu3_intc: interrupt-controller {
108				#interrupt-cells = <1>;
109				compatible = "riscv,cpu-intc";
110				interrupt-controller;
111			};
112		};
113		cpu4: cpu@4 {
114			compatible = "sifive,bullet0", "riscv";
115			d-cache-block-size = <64>;
116			d-cache-sets = <64>;
117			d-cache-size = <32768>;
118			d-tlb-sets = <1>;
119			d-tlb-size = <40>;
120			device_type = "cpu";
121			i-cache-block-size = <64>;
122			i-cache-sets = <128>;
123			i-cache-size = <32768>;
124			i-tlb-sets = <1>;
125			i-tlb-size = <40>;
126			mmu-type = "riscv,sv39";
127			next-level-cache = <&ccache>;
128			reg = <0x4>;
129			riscv,isa = "rv64imafdc";
130			tlb-split;
131			cpu4_intc: interrupt-controller {
132				#interrupt-cells = <1>;
133				compatible = "riscv,cpu-intc";
134				interrupt-controller;
135			};
136		};
137
138		cpu-map {
139			cluster0 {
140				core0 {
141					cpu = <&cpu0>;
142				};
143
144				core1 {
145					cpu = <&cpu1>;
146				};
147
148				core2 {
149					cpu = <&cpu2>;
150				};
151
152				core3 {
153					cpu = <&cpu3>;
154				};
155
156				core4 {
157					cpu = <&cpu4>;
158				};
159			};
160		};
161	};
162	soc {
163		#address-cells = <2>;
164		#size-cells = <2>;
165		compatible = "simple-bus";
166		ranges;
167		plic0: interrupt-controller@c000000 {
168			#interrupt-cells = <1>;
169			#address-cells = <0>;
170			compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
171			reg = <0x0 0xc000000 0x0 0x4000000>;
172			riscv,ndev = <69>;
173			interrupt-controller;
174			interrupts-extended =
175				<&cpu0_intc 0xffffffff>,
176				<&cpu1_intc 0xffffffff>, <&cpu1_intc 9>,
177				<&cpu2_intc 0xffffffff>, <&cpu2_intc 9>,
178				<&cpu3_intc 0xffffffff>, <&cpu3_intc 9>,
179				<&cpu4_intc 0xffffffff>, <&cpu4_intc 9>;
180		};
181		prci: clock-controller@10000000 {
182			compatible = "sifive,fu740-c000-prci";
183			reg = <0x0 0x10000000 0x0 0x1000>;
184			clocks = <&hfclk>, <&rtcclk>;
185			#clock-cells = <1>;
186			#reset-cells = <1>;
187		};
188		uart0: serial@10010000 {
189			compatible = "sifive,fu740-c000-uart", "sifive,uart0";
190			reg = <0x0 0x10010000 0x0 0x1000>;
191			interrupt-parent = <&plic0>;
192			interrupts = <39>;
193			clocks = <&prci FU740_PRCI_CLK_PCLK>;
194			status = "disabled";
195		};
196		uart1: serial@10011000 {
197			compatible = "sifive,fu740-c000-uart", "sifive,uart0";
198			reg = <0x0 0x10011000 0x0 0x1000>;
199			interrupt-parent = <&plic0>;
200			interrupts = <40>;
201			clocks = <&prci FU740_PRCI_CLK_PCLK>;
202			status = "disabled";
203		};
204		i2c0: i2c@10030000 {
205			compatible = "sifive,fu740-c000-i2c", "sifive,i2c0";
206			reg = <0x0 0x10030000 0x0 0x1000>;
207			interrupt-parent = <&plic0>;
208			interrupts = <52>;
209			clocks = <&prci FU740_PRCI_CLK_PCLK>;
210			reg-shift = <2>;
211			reg-io-width = <1>;
212			#address-cells = <1>;
213			#size-cells = <0>;
214			status = "disabled";
215		};
216		i2c1: i2c@10031000 {
217			compatible = "sifive,fu740-c000-i2c", "sifive,i2c0";
218			reg = <0x0 0x10031000 0x0 0x1000>;
219			interrupt-parent = <&plic0>;
220			interrupts = <53>;
221			clocks = <&prci FU740_PRCI_CLK_PCLK>;
222			reg-shift = <2>;
223			reg-io-width = <1>;
224			#address-cells = <1>;
225			#size-cells = <0>;
226			status = "disabled";
227		};
228		qspi0: spi@10040000 {
229			compatible = "sifive,fu740-c000-spi", "sifive,spi0";
230			reg = <0x0 0x10040000 0x0 0x1000>,
231			      <0x0 0x20000000 0x0 0x10000000>;
232			interrupt-parent = <&plic0>;
233			interrupts = <41>;
234			clocks = <&prci FU740_PRCI_CLK_PCLK>;
235			#address-cells = <1>;
236			#size-cells = <0>;
237			status = "disabled";
238		};
239		qspi1: spi@10041000 {
240			compatible = "sifive,fu740-c000-spi", "sifive,spi0";
241			reg = <0x0 0x10041000 0x0 0x1000>,
242			      <0x0 0x30000000 0x0 0x10000000>;
243			interrupt-parent = <&plic0>;
244			interrupts = <42>;
245			clocks = <&prci FU740_PRCI_CLK_PCLK>;
246			#address-cells = <1>;
247			#size-cells = <0>;
248			status = "disabled";
249		};
250		spi0: spi@10050000 {
251			compatible = "sifive,fu740-c000-spi", "sifive,spi0";
252			reg = <0x0 0x10050000 0x0 0x1000>;
253			interrupt-parent = <&plic0>;
254			interrupts = <43>;
255			clocks = <&prci FU740_PRCI_CLK_PCLK>;
256			#address-cells = <1>;
257			#size-cells = <0>;
258			status = "disabled";
259		};
260		eth0: ethernet@10090000 {
261			compatible = "sifive,fu540-c000-gem";
262			interrupt-parent = <&plic0>;
263			interrupts = <55>;
264			reg = <0x0 0x10090000 0x0 0x2000>,
265			      <0x0 0x100a0000 0x0 0x1000>;
266			local-mac-address = [00 00 00 00 00 00];
267			clock-names = "pclk", "hclk";
268			clocks = <&prci FU740_PRCI_CLK_GEMGXLPLL>,
269				 <&prci FU740_PRCI_CLK_GEMGXLPLL>;
270			#address-cells = <1>;
271			#size-cells = <0>;
272			status = "disabled";
273		};
274		pwm0: pwm@10020000 {
275			compatible = "sifive,fu740-c000-pwm", "sifive,pwm0";
276			reg = <0x0 0x10020000 0x0 0x1000>;
277			interrupt-parent = <&plic0>;
278			interrupts = <44>, <45>, <46>, <47>;
279			clocks = <&prci FU740_PRCI_CLK_PCLK>;
280			#pwm-cells = <3>;
281			status = "disabled";
282		};
283		pwm1: pwm@10021000 {
284			compatible = "sifive,fu740-c000-pwm", "sifive,pwm0";
285			reg = <0x0 0x10021000 0x0 0x1000>;
286			interrupt-parent = <&plic0>;
287			interrupts = <48>, <49>, <50>, <51>;
288			clocks = <&prci FU740_PRCI_CLK_PCLK>;
289			#pwm-cells = <3>;
290			status = "disabled";
291		};
292		ccache: cache-controller@2010000 {
293			compatible = "sifive,fu740-c000-ccache", "cache";
294			cache-block-size = <64>;
295			cache-level = <2>;
296			cache-sets = <2048>;
297			cache-size = <2097152>;
298			cache-unified;
299			interrupt-parent = <&plic0>;
300			interrupts = <19>, <21>, <22>, <20>;
301			reg = <0x0 0x2010000 0x0 0x1000>;
302		};
303		gpio: gpio@10060000 {
304			compatible = "sifive,fu740-c000-gpio", "sifive,gpio0";
305			interrupt-parent = <&plic0>;
306			interrupts = <23>, <24>, <25>, <26>, <27>, <28>, <29>,
307				     <30>, <31>, <32>, <33>, <34>, <35>, <36>,
308				     <37>, <38>;
309			reg = <0x0 0x10060000 0x0 0x1000>;
310			gpio-controller;
311			#gpio-cells = <2>;
312			interrupt-controller;
313			#interrupt-cells = <2>;
314			clocks = <&prci FU740_PRCI_CLK_PCLK>;
315			status = "disabled";
316		};
317		pcie@e00000000 {
318			compatible = "sifive,fu740-pcie";
319			#address-cells = <3>;
320			#size-cells = <2>;
321			#interrupt-cells = <1>;
322			reg = <0xe 0x00000000 0x0 0x80000000>,
323			      <0xd 0xf0000000 0x0 0x10000000>,
324			      <0x0 0x100d0000 0x0 0x1000>;
325			reg-names = "dbi", "config", "mgmt";
326			device_type = "pci";
327			dma-coherent;
328			bus-range = <0x0 0xff>;
329			ranges = <0x81000000  0x0 0x60080000  0x0 0x60080000 0x0 0x10000>,      /* I/O */
330				 <0x82000000  0x0 0x60090000  0x0 0x60090000 0x0 0xff70000>,    /* mem */
331				 <0x82000000  0x0 0x70000000  0x0 0x70000000 0x0 0x10000000>,    /* mem */
332				 <0xc3000000 0x20 0x00000000 0x20 0x00000000 0x20 0x00000000>;  /* mem prefetchable */
333			num-lanes = <0x8>;
334			interrupts = <56>, <57>, <58>, <59>, <60>, <61>, <62>, <63>, <64>;
335			interrupt-names = "msi", "inta", "intb", "intc", "intd";
336			interrupt-parent = <&plic0>;
337			interrupt-map-mask = <0x0 0x0 0x0 0x7>;
338			interrupt-map = <0x0 0x0 0x0 0x1 &plic0 57>,
339					<0x0 0x0 0x0 0x2 &plic0 58>,
340					<0x0 0x0 0x0 0x3 &plic0 59>,
341					<0x0 0x0 0x0 0x4 &plic0 60>;
342			clock-names = "pcie_aux";
343			clocks = <&prci FU740_PRCI_CLK_PCIE_AUX>;
344			pwren-gpios = <&gpio 5 0>;
345			reset-gpios = <&gpio 8 0>;
346			resets = <&prci 4>;
347			status = "okay";
348		};
349	};
350};
351