1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3  * MPC5200 General Purpose Timer device driver
4  *
5  * Copyright (c) 2009 Secret Lab Technologies Ltd.
6  * Copyright (c) 2008 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
7  *
8  * This file is a driver for the General Purpose Timer (gpt) devices
9  * found on the MPC5200 SoC.  Each timer has an IO pin which can be used
10  * for GPIO or can be used to raise interrupts.  The timer function can
11  * be used independently from the IO pin, or it can be used to control
12  * output signals or measure input signals.
13  *
14  * This driver supports the GPIO and IRQ controller functions of the GPT
15  * device.  Timer functions are not yet supported.
16  *
17  * The timer gpt0 can be used as watchdog (wdt).  If the wdt mode is used,
18  * this prevents the use of any gpt0 gpt function (i.e. they will fail with
19  * -EBUSY).  Thus, the safety wdt function always has precedence over the gpt
20  * function.  If the kernel has been compiled with CONFIG_WATCHDOG_NOWAYOUT,
21  * this means that gpt0 is locked in wdt mode until the next reboot - this
22  * may be a requirement in safety applications.
23  *
24  * To use the GPIO function, the following two properties must be added
25  * to the device tree node for the gpt device (typically in the .dts file
26  * for the board):
27  * 	gpio-controller;
28  * 	#gpio-cells = < 2 >;
29  * This driver will register the GPIO pin if it finds the gpio-controller
30  * property in the device tree.
31  *
32  * To use the IRQ controller function, the following two properties must
33  * be added to the device tree node for the gpt device:
34  * 	interrupt-controller;
35  * 	#interrupt-cells = < 1 >;
36  * The IRQ controller binding only uses one cell to specify the interrupt,
37  * and the IRQ flags are encoded in the cell.  A cell is not used to encode
38  * the IRQ number because the GPT only has a single IRQ source.  For flags,
39  * a value of '1' means rising edge sensitive and '2' means falling edge.
40  *
41  * The GPIO and the IRQ controller functions can be used at the same time,
42  * but in this use case the IO line will only work as an input.  Trying to
43  * use it as a GPIO output will not work.
44  *
45  * When using the GPIO line as an output, it can either be driven as normal
46  * IO, or it can be an Open Collector (OC) output.  At the moment it is the
47  * responsibility of either the bootloader or the platform setup code to set
48  * the output mode.  This driver does not change the output mode setting.
49  */
50 
51 #include <linux/device.h>
52 #include <linux/irq.h>
53 #include <linux/interrupt.h>
54 #include <linux/io.h>
55 #include <linux/list.h>
56 #include <linux/mutex.h>
57 #include <linux/of.h>
58 #include <linux/of_address.h>
59 #include <linux/of_irq.h>
60 #include <linux/of_platform.h>
61 #include <linux/of_gpio.h>
62 #include <linux/kernel.h>
63 #include <linux/property.h>
64 #include <linux/slab.h>
65 #include <linux/fs.h>
66 #include <linux/watchdog.h>
67 #include <linux/miscdevice.h>
68 #include <linux/uaccess.h>
69 #include <linux/module.h>
70 #include <asm/div64.h>
71 #include <asm/mpc52xx.h>
72 
73 MODULE_DESCRIPTION("Freescale MPC52xx gpt driver");
74 MODULE_AUTHOR("Sascha Hauer, Grant Likely, Albrecht Dreß");
75 MODULE_LICENSE("GPL");
76 
77 /**
78  * struct mpc52xx_gpt - Private data structure for MPC52xx GPT driver
79  * @dev: pointer to device structure
80  * @regs: virtual address of GPT registers
81  * @lock: spinlock to coordinate between different functions.
82  * @gc: gpio_chip instance structure; used when GPIO is enabled
83  * @irqhost: Pointer to irq_domain instance; used when IRQ mode is supported
84  * @wdt_mode: only relevant for gpt0: bit 0 (MPC52xx_GPT_CAN_WDT) indicates
85  *   if the gpt may be used as wdt, bit 1 (MPC52xx_GPT_IS_WDT) indicates
86  *   if the timer is actively used as wdt which blocks gpt functions
87  */
88 struct mpc52xx_gpt_priv {
89 	struct list_head list;		/* List of all GPT devices */
90 	struct device *dev;
91 	struct mpc52xx_gpt __iomem *regs;
92 	raw_spinlock_t lock;
93 	struct irq_domain *irqhost;
94 	u32 ipb_freq;
95 	u8 wdt_mode;
96 
97 #if defined(CONFIG_GPIOLIB)
98 	struct gpio_chip gc;
99 #endif
100 };
101 
102 LIST_HEAD(mpc52xx_gpt_list);
103 DEFINE_MUTEX(mpc52xx_gpt_list_mutex);
104 
105 #define MPC52xx_GPT_MODE_MS_MASK	(0x07)
106 #define MPC52xx_GPT_MODE_MS_IC		(0x01)
107 #define MPC52xx_GPT_MODE_MS_OC		(0x02)
108 #define MPC52xx_GPT_MODE_MS_PWM		(0x03)
109 #define MPC52xx_GPT_MODE_MS_GPIO	(0x04)
110 
111 #define MPC52xx_GPT_MODE_GPIO_MASK	(0x30)
112 #define MPC52xx_GPT_MODE_GPIO_OUT_LOW	(0x20)
113 #define MPC52xx_GPT_MODE_GPIO_OUT_HIGH	(0x30)
114 
115 #define MPC52xx_GPT_MODE_COUNTER_ENABLE	(0x1000)
116 #define MPC52xx_GPT_MODE_CONTINUOUS	(0x0400)
117 #define MPC52xx_GPT_MODE_OPEN_DRAIN	(0x0200)
118 #define MPC52xx_GPT_MODE_IRQ_EN		(0x0100)
119 #define MPC52xx_GPT_MODE_WDT_EN		(0x8000)
120 
121 #define MPC52xx_GPT_MODE_ICT_MASK	(0x030000)
122 #define MPC52xx_GPT_MODE_ICT_RISING	(0x010000)
123 #define MPC52xx_GPT_MODE_ICT_FALLING	(0x020000)
124 #define MPC52xx_GPT_MODE_ICT_TOGGLE	(0x030000)
125 
126 #define MPC52xx_GPT_MODE_WDT_PING	(0xa5)
127 
128 #define MPC52xx_GPT_STATUS_IRQMASK	(0x000f)
129 
130 #define MPC52xx_GPT_CAN_WDT		(1 << 0)
131 #define MPC52xx_GPT_IS_WDT		(1 << 1)
132 
133 
134 /* ---------------------------------------------------------------------
135  * Cascaded interrupt controller hooks
136  */
137 
mpc52xx_gpt_irq_unmask(struct irq_data * d)138 static void mpc52xx_gpt_irq_unmask(struct irq_data *d)
139 {
140 	struct mpc52xx_gpt_priv *gpt = irq_data_get_irq_chip_data(d);
141 	unsigned long flags;
142 
143 	raw_spin_lock_irqsave(&gpt->lock, flags);
144 	setbits32(&gpt->regs->mode, MPC52xx_GPT_MODE_IRQ_EN);
145 	raw_spin_unlock_irqrestore(&gpt->lock, flags);
146 }
147 
mpc52xx_gpt_irq_mask(struct irq_data * d)148 static void mpc52xx_gpt_irq_mask(struct irq_data *d)
149 {
150 	struct mpc52xx_gpt_priv *gpt = irq_data_get_irq_chip_data(d);
151 	unsigned long flags;
152 
153 	raw_spin_lock_irqsave(&gpt->lock, flags);
154 	clrbits32(&gpt->regs->mode, MPC52xx_GPT_MODE_IRQ_EN);
155 	raw_spin_unlock_irqrestore(&gpt->lock, flags);
156 }
157 
mpc52xx_gpt_irq_ack(struct irq_data * d)158 static void mpc52xx_gpt_irq_ack(struct irq_data *d)
159 {
160 	struct mpc52xx_gpt_priv *gpt = irq_data_get_irq_chip_data(d);
161 
162 	out_be32(&gpt->regs->status, MPC52xx_GPT_STATUS_IRQMASK);
163 }
164 
mpc52xx_gpt_irq_set_type(struct irq_data * d,unsigned int flow_type)165 static int mpc52xx_gpt_irq_set_type(struct irq_data *d, unsigned int flow_type)
166 {
167 	struct mpc52xx_gpt_priv *gpt = irq_data_get_irq_chip_data(d);
168 	unsigned long flags;
169 	u32 reg;
170 
171 	dev_dbg(gpt->dev, "%s: virq=%i type=%x\n", __func__, d->irq, flow_type);
172 
173 	raw_spin_lock_irqsave(&gpt->lock, flags);
174 	reg = in_be32(&gpt->regs->mode) & ~MPC52xx_GPT_MODE_ICT_MASK;
175 	if (flow_type & IRQF_TRIGGER_RISING)
176 		reg |= MPC52xx_GPT_MODE_ICT_RISING;
177 	if (flow_type & IRQF_TRIGGER_FALLING)
178 		reg |= MPC52xx_GPT_MODE_ICT_FALLING;
179 	out_be32(&gpt->regs->mode, reg);
180 	raw_spin_unlock_irqrestore(&gpt->lock, flags);
181 
182 	return 0;
183 }
184 
185 static struct irq_chip mpc52xx_gpt_irq_chip = {
186 	.name = "MPC52xx GPT",
187 	.irq_unmask = mpc52xx_gpt_irq_unmask,
188 	.irq_mask = mpc52xx_gpt_irq_mask,
189 	.irq_ack = mpc52xx_gpt_irq_ack,
190 	.irq_set_type = mpc52xx_gpt_irq_set_type,
191 };
192 
mpc52xx_gpt_irq_cascade(struct irq_desc * desc)193 static void mpc52xx_gpt_irq_cascade(struct irq_desc *desc)
194 {
195 	struct mpc52xx_gpt_priv *gpt = irq_desc_get_handler_data(desc);
196 	u32 status;
197 
198 	status = in_be32(&gpt->regs->status) & MPC52xx_GPT_STATUS_IRQMASK;
199 	if (status)
200 		generic_handle_domain_irq(gpt->irqhost, 0);
201 }
202 
mpc52xx_gpt_irq_map(struct irq_domain * h,unsigned int virq,irq_hw_number_t hw)203 static int mpc52xx_gpt_irq_map(struct irq_domain *h, unsigned int virq,
204 			       irq_hw_number_t hw)
205 {
206 	struct mpc52xx_gpt_priv *gpt = h->host_data;
207 
208 	dev_dbg(gpt->dev, "%s: h=%p, virq=%i\n", __func__, h, virq);
209 	irq_set_chip_data(virq, gpt);
210 	irq_set_chip_and_handler(virq, &mpc52xx_gpt_irq_chip, handle_edge_irq);
211 
212 	return 0;
213 }
214 
mpc52xx_gpt_irq_xlate(struct irq_domain * h,struct device_node * ct,const u32 * intspec,unsigned int intsize,irq_hw_number_t * out_hwirq,unsigned int * out_flags)215 static int mpc52xx_gpt_irq_xlate(struct irq_domain *h, struct device_node *ct,
216 				 const u32 *intspec, unsigned int intsize,
217 				 irq_hw_number_t *out_hwirq,
218 				 unsigned int *out_flags)
219 {
220 	struct mpc52xx_gpt_priv *gpt = h->host_data;
221 
222 	dev_dbg(gpt->dev, "%s: flags=%i\n", __func__, intspec[0]);
223 
224 	if ((intsize < 1) || (intspec[0] > 3)) {
225 		dev_err(gpt->dev, "bad irq specifier in %pOF\n", ct);
226 		return -EINVAL;
227 	}
228 
229 	*out_hwirq = 0; /* The GPT only has 1 IRQ line */
230 	*out_flags = intspec[0];
231 
232 	return 0;
233 }
234 
235 static const struct irq_domain_ops mpc52xx_gpt_irq_ops = {
236 	.map = mpc52xx_gpt_irq_map,
237 	.xlate = mpc52xx_gpt_irq_xlate,
238 };
239 
240 static void
mpc52xx_gpt_irq_setup(struct mpc52xx_gpt_priv * gpt,struct device_node * node)241 mpc52xx_gpt_irq_setup(struct mpc52xx_gpt_priv *gpt, struct device_node *node)
242 {
243 	int cascade_virq;
244 	unsigned long flags;
245 	u32 mode;
246 
247 	cascade_virq = irq_of_parse_and_map(node, 0);
248 	if (!cascade_virq)
249 		return;
250 
251 	gpt->irqhost = irq_domain_add_linear(node, 1, &mpc52xx_gpt_irq_ops, gpt);
252 	if (!gpt->irqhost) {
253 		dev_err(gpt->dev, "irq_domain_add_linear() failed\n");
254 		return;
255 	}
256 
257 	irq_set_handler_data(cascade_virq, gpt);
258 	irq_set_chained_handler(cascade_virq, mpc52xx_gpt_irq_cascade);
259 
260 	/* If the GPT is currently disabled, then change it to be in Input
261 	 * Capture mode.  If the mode is non-zero, then the pin could be
262 	 * already in use for something. */
263 	raw_spin_lock_irqsave(&gpt->lock, flags);
264 	mode = in_be32(&gpt->regs->mode);
265 	if ((mode & MPC52xx_GPT_MODE_MS_MASK) == 0)
266 		out_be32(&gpt->regs->mode, mode | MPC52xx_GPT_MODE_MS_IC);
267 	raw_spin_unlock_irqrestore(&gpt->lock, flags);
268 
269 	dev_dbg(gpt->dev, "%s() complete. virq=%i\n", __func__, cascade_virq);
270 }
271 
272 
273 /* ---------------------------------------------------------------------
274  * GPIOLIB hooks
275  */
276 #if defined(CONFIG_GPIOLIB)
mpc52xx_gpt_gpio_get(struct gpio_chip * gc,unsigned int gpio)277 static int mpc52xx_gpt_gpio_get(struct gpio_chip *gc, unsigned int gpio)
278 {
279 	struct mpc52xx_gpt_priv *gpt = gpiochip_get_data(gc);
280 
281 	return (in_be32(&gpt->regs->status) >> 8) & 1;
282 }
283 
284 static void
mpc52xx_gpt_gpio_set(struct gpio_chip * gc,unsigned int gpio,int v)285 mpc52xx_gpt_gpio_set(struct gpio_chip *gc, unsigned int gpio, int v)
286 {
287 	struct mpc52xx_gpt_priv *gpt = gpiochip_get_data(gc);
288 	unsigned long flags;
289 	u32 r;
290 
291 	dev_dbg(gpt->dev, "%s: gpio:%d v:%d\n", __func__, gpio, v);
292 	r = v ? MPC52xx_GPT_MODE_GPIO_OUT_HIGH : MPC52xx_GPT_MODE_GPIO_OUT_LOW;
293 
294 	raw_spin_lock_irqsave(&gpt->lock, flags);
295 	clrsetbits_be32(&gpt->regs->mode, MPC52xx_GPT_MODE_GPIO_MASK, r);
296 	raw_spin_unlock_irqrestore(&gpt->lock, flags);
297 }
298 
mpc52xx_gpt_gpio_dir_in(struct gpio_chip * gc,unsigned int gpio)299 static int mpc52xx_gpt_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
300 {
301 	struct mpc52xx_gpt_priv *gpt = gpiochip_get_data(gc);
302 	unsigned long flags;
303 
304 	dev_dbg(gpt->dev, "%s: gpio:%d\n", __func__, gpio);
305 
306 	raw_spin_lock_irqsave(&gpt->lock, flags);
307 	clrbits32(&gpt->regs->mode, MPC52xx_GPT_MODE_GPIO_MASK);
308 	raw_spin_unlock_irqrestore(&gpt->lock, flags);
309 
310 	return 0;
311 }
312 
313 static int
mpc52xx_gpt_gpio_dir_out(struct gpio_chip * gc,unsigned int gpio,int val)314 mpc52xx_gpt_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
315 {
316 	mpc52xx_gpt_gpio_set(gc, gpio, val);
317 	return 0;
318 }
319 
mpc52xx_gpt_gpio_setup(struct mpc52xx_gpt_priv * gpt)320 static void mpc52xx_gpt_gpio_setup(struct mpc52xx_gpt_priv *gpt)
321 {
322 	int rc;
323 
324 	/* Only setup GPIO if the device claims the GPT is a GPIO controller */
325 	if (!device_property_present(gpt->dev, "gpio-controller"))
326 		return;
327 
328 	gpt->gc.label = kasprintf(GFP_KERNEL, "%pfw", dev_fwnode(gpt->dev));
329 	if (!gpt->gc.label) {
330 		dev_err(gpt->dev, "out of memory\n");
331 		return;
332 	}
333 
334 	gpt->gc.ngpio = 1;
335 	gpt->gc.direction_input  = mpc52xx_gpt_gpio_dir_in;
336 	gpt->gc.direction_output = mpc52xx_gpt_gpio_dir_out;
337 	gpt->gc.get = mpc52xx_gpt_gpio_get;
338 	gpt->gc.set = mpc52xx_gpt_gpio_set;
339 	gpt->gc.base = -1;
340 	gpt->gc.parent = gpt->dev;
341 
342 	/* Setup external pin in GPIO mode */
343 	clrsetbits_be32(&gpt->regs->mode, MPC52xx_GPT_MODE_MS_MASK,
344 			MPC52xx_GPT_MODE_MS_GPIO);
345 
346 	rc = gpiochip_add_data(&gpt->gc, gpt);
347 	if (rc)
348 		dev_err(gpt->dev, "gpiochip_add_data() failed; rc=%i\n", rc);
349 
350 	dev_dbg(gpt->dev, "%s() complete.\n", __func__);
351 }
352 #else /* defined(CONFIG_GPIOLIB) */
mpc52xx_gpt_gpio_setup(struct mpc52xx_gpt_priv * gpt)353 static void mpc52xx_gpt_gpio_setup(struct mpc52xx_gpt_priv *gpt) { }
354 #endif /* defined(CONFIG_GPIOLIB) */
355 
356 /***********************************************************************
357  * Timer API
358  */
359 
360 /**
361  * mpc52xx_gpt_from_irq - Return the GPT device associated with an IRQ number
362  * @irq: irq of timer.
363  */
mpc52xx_gpt_from_irq(int irq)364 struct mpc52xx_gpt_priv *mpc52xx_gpt_from_irq(int irq)
365 {
366 	struct mpc52xx_gpt_priv *gpt;
367 	struct list_head *pos;
368 
369 	/* Iterate over the list of timers looking for a matching device */
370 	mutex_lock(&mpc52xx_gpt_list_mutex);
371 	list_for_each(pos, &mpc52xx_gpt_list) {
372 		gpt = container_of(pos, struct mpc52xx_gpt_priv, list);
373 		if (gpt->irqhost && irq == irq_linear_revmap(gpt->irqhost, 0)) {
374 			mutex_unlock(&mpc52xx_gpt_list_mutex);
375 			return gpt;
376 		}
377 	}
378 	mutex_unlock(&mpc52xx_gpt_list_mutex);
379 
380 	return NULL;
381 }
382 EXPORT_SYMBOL(mpc52xx_gpt_from_irq);
383 
mpc52xx_gpt_do_start(struct mpc52xx_gpt_priv * gpt,u64 period,int continuous,int as_wdt)384 static int mpc52xx_gpt_do_start(struct mpc52xx_gpt_priv *gpt, u64 period,
385 				int continuous, int as_wdt)
386 {
387 	u32 clear, set;
388 	u64 clocks;
389 	u32 prescale;
390 	unsigned long flags;
391 
392 	clear = MPC52xx_GPT_MODE_MS_MASK | MPC52xx_GPT_MODE_CONTINUOUS;
393 	set = MPC52xx_GPT_MODE_MS_GPIO | MPC52xx_GPT_MODE_COUNTER_ENABLE;
394 	if (as_wdt) {
395 		clear |= MPC52xx_GPT_MODE_IRQ_EN;
396 		set |= MPC52xx_GPT_MODE_WDT_EN;
397 	} else if (continuous)
398 		set |= MPC52xx_GPT_MODE_CONTINUOUS;
399 
400 	/* Determine the number of clocks in the requested period.  64 bit
401 	 * arithmetic is done here to preserve the precision until the value
402 	 * is scaled back down into the u32 range.  Period is in 'ns', bus
403 	 * frequency is in Hz. */
404 	clocks = period * (u64)gpt->ipb_freq;
405 	do_div(clocks, 1000000000); /* Scale it down to ns range */
406 
407 	/* This device cannot handle a clock count greater than 32 bits */
408 	if (clocks > 0xffffffff)
409 		return -EINVAL;
410 
411 	/* Calculate the prescaler and count values from the clocks value.
412 	 * 'clocks' is the number of clock ticks in the period.  The timer
413 	 * has 16 bit precision and a 16 bit prescaler.  Prescaler is
414 	 * calculated by integer dividing the clocks by 0x10000 (shifting
415 	 * down 16 bits) to obtain the smallest possible divisor for clocks
416 	 * to get a 16 bit count value.
417 	 *
418 	 * Note: the prescale register is '1' based, not '0' based.  ie. a
419 	 * value of '1' means divide the clock by one.  0xffff divides the
420 	 * clock by 0xffff.  '0x0000' does not divide by zero, but wraps
421 	 * around and divides by 0x10000.  That is why prescale must be
422 	 * a u32 variable, not a u16, for this calculation. */
423 	prescale = (clocks >> 16) + 1;
424 	do_div(clocks, prescale);
425 	if (clocks > 0xffff) {
426 		pr_err("calculation error; prescale:%x clocks:%llx\n",
427 		       prescale, clocks);
428 		return -EINVAL;
429 	}
430 
431 	/* Set and enable the timer, reject an attempt to use a wdt as gpt */
432 	raw_spin_lock_irqsave(&gpt->lock, flags);
433 	if (as_wdt)
434 		gpt->wdt_mode |= MPC52xx_GPT_IS_WDT;
435 	else if ((gpt->wdt_mode & MPC52xx_GPT_IS_WDT) != 0) {
436 		raw_spin_unlock_irqrestore(&gpt->lock, flags);
437 		return -EBUSY;
438 	}
439 	out_be32(&gpt->regs->count, prescale << 16 | clocks);
440 	clrsetbits_be32(&gpt->regs->mode, clear, set);
441 	raw_spin_unlock_irqrestore(&gpt->lock, flags);
442 
443 	return 0;
444 }
445 
446 /**
447  * mpc52xx_gpt_start_timer - Set and enable the GPT timer
448  * @gpt: Pointer to gpt private data structure
449  * @period: period of timer in ns; max. ~130s @ 33MHz IPB clock
450  * @continuous: set to 1 to make timer continuous free running
451  *
452  * An interrupt will be generated every time the timer fires
453  */
mpc52xx_gpt_start_timer(struct mpc52xx_gpt_priv * gpt,u64 period,int continuous)454 int mpc52xx_gpt_start_timer(struct mpc52xx_gpt_priv *gpt, u64 period,
455                             int continuous)
456 {
457 	return mpc52xx_gpt_do_start(gpt, period, continuous, 0);
458 }
459 EXPORT_SYMBOL(mpc52xx_gpt_start_timer);
460 
461 /**
462  * mpc52xx_gpt_stop_timer - Stop a gpt
463  * @gpt: Pointer to gpt private data structure
464  *
465  * Returns an error if attempting to stop a wdt
466  */
mpc52xx_gpt_stop_timer(struct mpc52xx_gpt_priv * gpt)467 int mpc52xx_gpt_stop_timer(struct mpc52xx_gpt_priv *gpt)
468 {
469 	unsigned long flags;
470 
471 	/* reject the operation if the timer is used as watchdog (gpt 0 only) */
472 	raw_spin_lock_irqsave(&gpt->lock, flags);
473 	if ((gpt->wdt_mode & MPC52xx_GPT_IS_WDT) != 0) {
474 		raw_spin_unlock_irqrestore(&gpt->lock, flags);
475 		return -EBUSY;
476 	}
477 
478 	clrbits32(&gpt->regs->mode, MPC52xx_GPT_MODE_COUNTER_ENABLE);
479 	raw_spin_unlock_irqrestore(&gpt->lock, flags);
480 	return 0;
481 }
482 EXPORT_SYMBOL(mpc52xx_gpt_stop_timer);
483 
484 /**
485  * mpc52xx_gpt_timer_period - Read the timer period
486  * @gpt: Pointer to gpt private data structure
487  *
488  * Returns the timer period in ns
489  */
mpc52xx_gpt_timer_period(struct mpc52xx_gpt_priv * gpt)490 u64 mpc52xx_gpt_timer_period(struct mpc52xx_gpt_priv *gpt)
491 {
492 	u64 period;
493 	u64 prescale;
494 	unsigned long flags;
495 
496 	raw_spin_lock_irqsave(&gpt->lock, flags);
497 	period = in_be32(&gpt->regs->count);
498 	raw_spin_unlock_irqrestore(&gpt->lock, flags);
499 
500 	prescale = period >> 16;
501 	period &= 0xffff;
502 	if (prescale == 0)
503 		prescale = 0x10000;
504 	period = period * prescale * 1000000000ULL;
505 	do_div(period, gpt->ipb_freq);
506 	return period;
507 }
508 EXPORT_SYMBOL(mpc52xx_gpt_timer_period);
509 
510 #if defined(CONFIG_MPC5200_WDT)
511 /***********************************************************************
512  * Watchdog API for gpt0
513  */
514 
515 #define WDT_IDENTITY	    "mpc52xx watchdog on GPT0"
516 
517 /* wdt_is_active stores whether or not the /dev/watchdog device is opened */
518 static unsigned long wdt_is_active;
519 
520 /* wdt-capable gpt */
521 static struct mpc52xx_gpt_priv *mpc52xx_gpt_wdt;
522 
523 /* low-level wdt functions */
mpc52xx_gpt_wdt_ping(struct mpc52xx_gpt_priv * gpt_wdt)524 static inline void mpc52xx_gpt_wdt_ping(struct mpc52xx_gpt_priv *gpt_wdt)
525 {
526 	unsigned long flags;
527 
528 	raw_spin_lock_irqsave(&gpt_wdt->lock, flags);
529 	out_8((u8 *) &gpt_wdt->regs->mode, MPC52xx_GPT_MODE_WDT_PING);
530 	raw_spin_unlock_irqrestore(&gpt_wdt->lock, flags);
531 }
532 
533 /* wdt misc device api */
mpc52xx_wdt_write(struct file * file,const char __user * data,size_t len,loff_t * ppos)534 static ssize_t mpc52xx_wdt_write(struct file *file, const char __user *data,
535 				 size_t len, loff_t *ppos)
536 {
537 	struct mpc52xx_gpt_priv *gpt_wdt = file->private_data;
538 	mpc52xx_gpt_wdt_ping(gpt_wdt);
539 	return 0;
540 }
541 
542 static const struct watchdog_info mpc5200_wdt_info = {
543 	.options	= WDIOF_SETTIMEOUT | WDIOF_KEEPALIVEPING,
544 	.identity	= WDT_IDENTITY,
545 };
546 
mpc52xx_wdt_ioctl(struct file * file,unsigned int cmd,unsigned long arg)547 static long mpc52xx_wdt_ioctl(struct file *file, unsigned int cmd,
548 			      unsigned long arg)
549 {
550 	struct mpc52xx_gpt_priv *gpt_wdt = file->private_data;
551 	int __user *data = (int __user *)arg;
552 	int timeout;
553 	u64 real_timeout;
554 	int ret = 0;
555 
556 	switch (cmd) {
557 	case WDIOC_GETSUPPORT:
558 		ret = copy_to_user(data, &mpc5200_wdt_info,
559 				   sizeof(mpc5200_wdt_info));
560 		if (ret)
561 			ret = -EFAULT;
562 		break;
563 
564 	case WDIOC_GETSTATUS:
565 	case WDIOC_GETBOOTSTATUS:
566 		ret = put_user(0, data);
567 		break;
568 
569 	case WDIOC_KEEPALIVE:
570 		mpc52xx_gpt_wdt_ping(gpt_wdt);
571 		break;
572 
573 	case WDIOC_SETTIMEOUT:
574 		ret = get_user(timeout, data);
575 		if (ret)
576 			break;
577 		real_timeout = (u64) timeout * 1000000000ULL;
578 		ret = mpc52xx_gpt_do_start(gpt_wdt, real_timeout, 0, 1);
579 		if (ret)
580 			break;
581 		/* fall through and return the timeout */
582 		fallthrough;
583 
584 	case WDIOC_GETTIMEOUT:
585 		/* we need to round here as to avoid e.g. the following
586 		 * situation:
587 		 * - timeout requested is 1 second;
588 		 * - real timeout @33MHz is 999997090ns
589 		 * - the int divide by 10^9 will return 0.
590 		 */
591 		real_timeout =
592 			mpc52xx_gpt_timer_period(gpt_wdt) + 500000000ULL;
593 		do_div(real_timeout, 1000000000ULL);
594 		timeout = (int) real_timeout;
595 		ret = put_user(timeout, data);
596 		break;
597 
598 	default:
599 		ret = -ENOTTY;
600 	}
601 	return ret;
602 }
603 
mpc52xx_wdt_open(struct inode * inode,struct file * file)604 static int mpc52xx_wdt_open(struct inode *inode, struct file *file)
605 {
606 	int ret;
607 
608 	/* sanity check */
609 	if (!mpc52xx_gpt_wdt)
610 		return -ENODEV;
611 
612 	/* /dev/watchdog can only be opened once */
613 	if (test_and_set_bit(0, &wdt_is_active))
614 		return -EBUSY;
615 
616 	/* Set and activate the watchdog with 30 seconds timeout */
617 	ret = mpc52xx_gpt_do_start(mpc52xx_gpt_wdt, 30ULL * 1000000000ULL,
618 				   0, 1);
619 	if (ret) {
620 		clear_bit(0, &wdt_is_active);
621 		return ret;
622 	}
623 
624 	file->private_data = mpc52xx_gpt_wdt;
625 	return stream_open(inode, file);
626 }
627 
mpc52xx_wdt_release(struct inode * inode,struct file * file)628 static int mpc52xx_wdt_release(struct inode *inode, struct file *file)
629 {
630 	/* note: releasing the wdt in NOWAYOUT-mode does not stop it */
631 #if !defined(CONFIG_WATCHDOG_NOWAYOUT)
632 	struct mpc52xx_gpt_priv *gpt_wdt = file->private_data;
633 	unsigned long flags;
634 
635 	raw_spin_lock_irqsave(&gpt_wdt->lock, flags);
636 	clrbits32(&gpt_wdt->regs->mode,
637 		  MPC52xx_GPT_MODE_COUNTER_ENABLE | MPC52xx_GPT_MODE_WDT_EN);
638 	gpt_wdt->wdt_mode &= ~MPC52xx_GPT_IS_WDT;
639 	raw_spin_unlock_irqrestore(&gpt_wdt->lock, flags);
640 #endif
641 	clear_bit(0, &wdt_is_active);
642 	return 0;
643 }
644 
645 
646 static const struct file_operations mpc52xx_wdt_fops = {
647 	.owner		= THIS_MODULE,
648 	.llseek		= no_llseek,
649 	.write		= mpc52xx_wdt_write,
650 	.unlocked_ioctl = mpc52xx_wdt_ioctl,
651 	.compat_ioctl	= compat_ptr_ioctl,
652 	.open		= mpc52xx_wdt_open,
653 	.release	= mpc52xx_wdt_release,
654 };
655 
656 static struct miscdevice mpc52xx_wdt_miscdev = {
657 	.minor		= WATCHDOG_MINOR,
658 	.name		= "watchdog",
659 	.fops		= &mpc52xx_wdt_fops,
660 };
661 
mpc52xx_gpt_wdt_init(void)662 static int mpc52xx_gpt_wdt_init(void)
663 {
664 	int err;
665 
666 	/* try to register the watchdog misc device */
667 	err = misc_register(&mpc52xx_wdt_miscdev);
668 	if (err)
669 		pr_err("%s: cannot register watchdog device\n", WDT_IDENTITY);
670 	else
671 		pr_info("%s: watchdog device registered\n", WDT_IDENTITY);
672 	return err;
673 }
674 
mpc52xx_gpt_wdt_setup(struct mpc52xx_gpt_priv * gpt,const u32 * period)675 static int mpc52xx_gpt_wdt_setup(struct mpc52xx_gpt_priv *gpt,
676 				 const u32 *period)
677 {
678 	u64 real_timeout;
679 
680 	/* remember the gpt for the wdt operation */
681 	mpc52xx_gpt_wdt = gpt;
682 
683 	/* configure the wdt if the device tree contained a timeout */
684 	if (!period || *period == 0)
685 		return 0;
686 
687 	real_timeout = (u64) *period * 1000000000ULL;
688 	if (mpc52xx_gpt_do_start(gpt, real_timeout, 0, 1))
689 		dev_warn(gpt->dev, "starting as wdt failed\n");
690 	else
691 		dev_info(gpt->dev, "watchdog set to %us timeout\n", *period);
692 	return 0;
693 }
694 
695 #else
696 
mpc52xx_gpt_wdt_init(void)697 static int mpc52xx_gpt_wdt_init(void)
698 {
699 	return 0;
700 }
701 
mpc52xx_gpt_wdt_setup(struct mpc52xx_gpt_priv * gpt,const u32 * period)702 static inline int mpc52xx_gpt_wdt_setup(struct mpc52xx_gpt_priv *gpt,
703 					const u32 *period)
704 {
705 	return 0;
706 }
707 
708 #endif	/*  CONFIG_MPC5200_WDT	*/
709 
710 /* ---------------------------------------------------------------------
711  * of_platform bus binding code
712  */
mpc52xx_gpt_probe(struct platform_device * ofdev)713 static int mpc52xx_gpt_probe(struct platform_device *ofdev)
714 {
715 	struct mpc52xx_gpt_priv *gpt;
716 
717 	gpt = devm_kzalloc(&ofdev->dev, sizeof *gpt, GFP_KERNEL);
718 	if (!gpt)
719 		return -ENOMEM;
720 
721 	raw_spin_lock_init(&gpt->lock);
722 	gpt->dev = &ofdev->dev;
723 	gpt->ipb_freq = mpc5xxx_get_bus_frequency(&ofdev->dev);
724 	gpt->regs = of_iomap(ofdev->dev.of_node, 0);
725 	if (!gpt->regs)
726 		return -ENOMEM;
727 
728 	dev_set_drvdata(&ofdev->dev, gpt);
729 
730 	mpc52xx_gpt_gpio_setup(gpt);
731 	mpc52xx_gpt_irq_setup(gpt, ofdev->dev.of_node);
732 
733 	mutex_lock(&mpc52xx_gpt_list_mutex);
734 	list_add(&gpt->list, &mpc52xx_gpt_list);
735 	mutex_unlock(&mpc52xx_gpt_list_mutex);
736 
737 	/* check if this device could be a watchdog */
738 	if (of_get_property(ofdev->dev.of_node, "fsl,has-wdt", NULL) ||
739 	    of_get_property(ofdev->dev.of_node, "has-wdt", NULL)) {
740 		const u32 *on_boot_wdt;
741 
742 		gpt->wdt_mode = MPC52xx_GPT_CAN_WDT;
743 		on_boot_wdt = of_get_property(ofdev->dev.of_node,
744 					      "fsl,wdt-on-boot", NULL);
745 		if (on_boot_wdt) {
746 			dev_info(gpt->dev, "used as watchdog\n");
747 			gpt->wdt_mode |= MPC52xx_GPT_IS_WDT;
748 		} else
749 			dev_info(gpt->dev, "can function as watchdog\n");
750 		mpc52xx_gpt_wdt_setup(gpt, on_boot_wdt);
751 	}
752 
753 	return 0;
754 }
755 
756 static const struct of_device_id mpc52xx_gpt_match[] = {
757 	{ .compatible = "fsl,mpc5200-gpt", },
758 
759 	/* Depreciated compatible values; don't use for new dts files */
760 	{ .compatible = "fsl,mpc5200-gpt-gpio", },
761 	{ .compatible = "mpc5200-gpt", },
762 	{}
763 };
764 
765 static struct platform_driver mpc52xx_gpt_driver = {
766 	.driver = {
767 		.name = "mpc52xx-gpt",
768 		.suppress_bind_attrs = true,
769 		.of_match_table = mpc52xx_gpt_match,
770 	},
771 	.probe = mpc52xx_gpt_probe,
772 };
773 
mpc52xx_gpt_init(void)774 static int __init mpc52xx_gpt_init(void)
775 {
776 	return platform_driver_register(&mpc52xx_gpt_driver);
777 }
778 
779 /* Make sure GPIOs and IRQs get set up before anyone tries to use them */
780 subsys_initcall(mpc52xx_gpt_init);
781 device_initcall(mpc52xx_gpt_wdt_init);
782