1 // SPDX-License-Identifier: GPL-2.0-only
2 #include <linux/device.h>
3 #include <linux/cpu.h>
4 #include <linux/smp.h>
5 #include <linux/percpu.h>
6 #include <linux/init.h>
7 #include <linux/sched.h>
8 #include <linux/export.h>
9 #include <linux/nodemask.h>
10 #include <linux/cpumask.h>
11 #include <linux/notifier.h>
12 #include <linux/of.h>
13 
14 #include <asm/current.h>
15 #include <asm/processor.h>
16 #include <asm/cputable.h>
17 #include <asm/hvcall.h>
18 #include <asm/machdep.h>
19 #include <asm/smp.h>
20 #include <asm/pmc.h>
21 #include <asm/firmware.h>
22 #include <asm/idle.h>
23 #include <asm/svm.h>
24 
25 #include "cacheinfo.h"
26 #include "setup.h"
27 
28 #ifdef CONFIG_PPC64
29 #include <asm/paca.h>
30 #include <asm/lppaca.h>
31 #endif
32 
33 static DEFINE_PER_CPU(struct cpu, cpu_devices);
34 
35 #ifdef CONFIG_PPC64
36 
37 /*
38  * Snooze delay has not been hooked up since 3fa8cad82b94 ("powerpc/pseries/cpuidle:
39  * smt-snooze-delay cleanup.") and has been broken even longer. As was foretold in
40  * 2014:
41  *
42  *  "ppc64_util currently utilises it. Once we fix ppc64_util, propose to clean
43  *  up the kernel code."
44  *
45  * powerpc-utils stopped using it as of 1.3.8. At some point in the future this
46  * code should be removed.
47  */
48 
store_smt_snooze_delay(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)49 static ssize_t store_smt_snooze_delay(struct device *dev,
50 				      struct device_attribute *attr,
51 				      const char *buf,
52 				      size_t count)
53 {
54 	pr_warn_once("%s (%d) stored to unsupported smt_snooze_delay, which has no effect.\n",
55 		     current->comm, current->pid);
56 	return count;
57 }
58 
show_smt_snooze_delay(struct device * dev,struct device_attribute * attr,char * buf)59 static ssize_t show_smt_snooze_delay(struct device *dev,
60 				     struct device_attribute *attr,
61 				     char *buf)
62 {
63 	pr_warn_once("%s (%d) read from unsupported smt_snooze_delay\n",
64 		     current->comm, current->pid);
65 	return sprintf(buf, "100\n");
66 }
67 
68 static DEVICE_ATTR(smt_snooze_delay, 0644, show_smt_snooze_delay,
69 		   store_smt_snooze_delay);
70 
setup_smt_snooze_delay(char * str)71 static int __init setup_smt_snooze_delay(char *str)
72 {
73 	if (!cpu_has_feature(CPU_FTR_SMT))
74 		return 1;
75 
76 	pr_warn("smt-snooze-delay command line option has no effect\n");
77 	return 1;
78 }
79 __setup("smt-snooze-delay=", setup_smt_snooze_delay);
80 
81 #endif /* CONFIG_PPC64 */
82 
83 #define __SYSFS_SPRSETUP_READ_WRITE(NAME, ADDRESS, EXTRA) \
84 static void read_##NAME(void *val) \
85 { \
86 	*(unsigned long *)val = mfspr(ADDRESS);	\
87 } \
88 static void write_##NAME(void *val) \
89 { \
90 	EXTRA; \
91 	mtspr(ADDRESS, *(unsigned long *)val);	\
92 }
93 
94 #define __SYSFS_SPRSETUP_SHOW_STORE(NAME) \
95 static ssize_t show_##NAME(struct device *dev, \
96 			struct device_attribute *attr, \
97 			char *buf) \
98 { \
99 	struct cpu *cpu = container_of(dev, struct cpu, dev); \
100 	unsigned long val; \
101 	smp_call_function_single(cpu->dev.id, read_##NAME, &val, 1);	\
102 	return sprintf(buf, "%lx\n", val); \
103 } \
104 static ssize_t __used \
105 	store_##NAME(struct device *dev, struct device_attribute *attr, \
106 			const char *buf, size_t count) \
107 { \
108 	struct cpu *cpu = container_of(dev, struct cpu, dev); \
109 	unsigned long val; \
110 	int ret = sscanf(buf, "%lx", &val); \
111 	if (ret != 1) \
112 		return -EINVAL; \
113 	smp_call_function_single(cpu->dev.id, write_##NAME, &val, 1); \
114 	return count; \
115 }
116 
117 #define SYSFS_PMCSETUP(NAME, ADDRESS) \
118 	__SYSFS_SPRSETUP_READ_WRITE(NAME, ADDRESS, ppc_enable_pmcs()) \
119 	__SYSFS_SPRSETUP_SHOW_STORE(NAME)
120 #define SYSFS_SPRSETUP(NAME, ADDRESS) \
121 	__SYSFS_SPRSETUP_READ_WRITE(NAME, ADDRESS, ) \
122 	__SYSFS_SPRSETUP_SHOW_STORE(NAME)
123 
124 #define SYSFS_SPRSETUP_SHOW_STORE(NAME) \
125 	__SYSFS_SPRSETUP_SHOW_STORE(NAME)
126 
127 #ifdef CONFIG_PPC64
128 
129 /*
130  * This is the system wide DSCR register default value. Any
131  * change to this default value through the sysfs interface
132  * will update all per cpu DSCR default values across the
133  * system stored in their respective PACA structures.
134  */
135 static unsigned long dscr_default;
136 
137 /**
138  * read_dscr() - Fetch the cpu specific DSCR default
139  * @val:	Returned cpu specific DSCR default value
140  *
141  * This function returns the per cpu DSCR default value
142  * for any cpu which is contained in it's PACA structure.
143  */
read_dscr(void * val)144 static void read_dscr(void *val)
145 {
146 	*(unsigned long *)val = get_paca()->dscr_default;
147 }
148 
149 
150 /**
151  * write_dscr() - Update the cpu specific DSCR default
152  * @val:	New cpu specific DSCR default value to update
153  *
154  * This function updates the per cpu DSCR default value
155  * for any cpu which is contained in it's PACA structure.
156  */
write_dscr(void * val)157 static void write_dscr(void *val)
158 {
159 	get_paca()->dscr_default = *(unsigned long *)val;
160 	if (!current->thread.dscr_inherit) {
161 		current->thread.dscr = *(unsigned long *)val;
162 		mtspr(SPRN_DSCR, *(unsigned long *)val);
163 	}
164 }
165 
166 SYSFS_SPRSETUP_SHOW_STORE(dscr);
167 static DEVICE_ATTR(dscr, 0600, show_dscr, store_dscr);
168 
add_write_permission_dev_attr(struct device_attribute * attr)169 static void add_write_permission_dev_attr(struct device_attribute *attr)
170 {
171 	attr->attr.mode |= 0200;
172 }
173 
174 /**
175  * show_dscr_default() - Fetch the system wide DSCR default
176  * @dev:	Device structure
177  * @attr:	Device attribute structure
178  * @buf:	Interface buffer
179  *
180  * This function returns the system wide DSCR default value.
181  */
show_dscr_default(struct device * dev,struct device_attribute * attr,char * buf)182 static ssize_t show_dscr_default(struct device *dev,
183 		struct device_attribute *attr, char *buf)
184 {
185 	return sprintf(buf, "%lx\n", dscr_default);
186 }
187 
188 /**
189  * store_dscr_default() - Update the system wide DSCR default
190  * @dev:	Device structure
191  * @attr:	Device attribute structure
192  * @buf:	Interface buffer
193  * @count:	Size of the update
194  *
195  * This function updates the system wide DSCR default value.
196  */
store_dscr_default(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)197 static ssize_t __used store_dscr_default(struct device *dev,
198 		struct device_attribute *attr, const char *buf,
199 		size_t count)
200 {
201 	unsigned long val;
202 	int ret = 0;
203 
204 	ret = sscanf(buf, "%lx", &val);
205 	if (ret != 1)
206 		return -EINVAL;
207 	dscr_default = val;
208 
209 	on_each_cpu(write_dscr, &val, 1);
210 
211 	return count;
212 }
213 
214 static DEVICE_ATTR(dscr_default, 0600,
215 		show_dscr_default, store_dscr_default);
216 
sysfs_create_dscr_default(void)217 static void __init sysfs_create_dscr_default(void)
218 {
219 	if (cpu_has_feature(CPU_FTR_DSCR)) {
220 		int cpu;
221 
222 		dscr_default = spr_default_dscr;
223 		for_each_possible_cpu(cpu)
224 			paca_ptrs[cpu]->dscr_default = dscr_default;
225 
226 		device_create_file(cpu_subsys.dev_root, &dev_attr_dscr_default);
227 	}
228 }
229 #endif /* CONFIG_PPC64 */
230 
231 #ifdef CONFIG_PPC_E500
232 #define MAX_BIT				63
233 
234 static u64 pw20_wt;
235 static u64 altivec_idle_wt;
236 
get_idle_ticks_bit(u64 ns)237 static unsigned int get_idle_ticks_bit(u64 ns)
238 {
239 	u64 cycle;
240 
241 	if (ns >= 10000)
242 		cycle = div_u64(ns + 500, 1000) * tb_ticks_per_usec;
243 	else
244 		cycle = div_u64(ns * tb_ticks_per_usec, 1000);
245 
246 	if (!cycle)
247 		return 0;
248 
249 	return ilog2(cycle);
250 }
251 
do_show_pwrmgtcr0(void * val)252 static void do_show_pwrmgtcr0(void *val)
253 {
254 	u32 *value = val;
255 
256 	*value = mfspr(SPRN_PWRMGTCR0);
257 }
258 
show_pw20_state(struct device * dev,struct device_attribute * attr,char * buf)259 static ssize_t show_pw20_state(struct device *dev,
260 				struct device_attribute *attr, char *buf)
261 {
262 	u32 value;
263 	unsigned int cpu = dev->id;
264 
265 	smp_call_function_single(cpu, do_show_pwrmgtcr0, &value, 1);
266 
267 	value &= PWRMGTCR0_PW20_WAIT;
268 
269 	return sprintf(buf, "%u\n", value ? 1 : 0);
270 }
271 
do_store_pw20_state(void * val)272 static void do_store_pw20_state(void *val)
273 {
274 	u32 *value = val;
275 	u32 pw20_state;
276 
277 	pw20_state = mfspr(SPRN_PWRMGTCR0);
278 
279 	if (*value)
280 		pw20_state |= PWRMGTCR0_PW20_WAIT;
281 	else
282 		pw20_state &= ~PWRMGTCR0_PW20_WAIT;
283 
284 	mtspr(SPRN_PWRMGTCR0, pw20_state);
285 }
286 
store_pw20_state(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)287 static ssize_t store_pw20_state(struct device *dev,
288 				struct device_attribute *attr,
289 				const char *buf, size_t count)
290 {
291 	u32 value;
292 	unsigned int cpu = dev->id;
293 
294 	if (kstrtou32(buf, 0, &value))
295 		return -EINVAL;
296 
297 	if (value > 1)
298 		return -EINVAL;
299 
300 	smp_call_function_single(cpu, do_store_pw20_state, &value, 1);
301 
302 	return count;
303 }
304 
show_pw20_wait_time(struct device * dev,struct device_attribute * attr,char * buf)305 static ssize_t show_pw20_wait_time(struct device *dev,
306 				struct device_attribute *attr, char *buf)
307 {
308 	u32 value;
309 	u64 tb_cycle = 1;
310 	u64 time;
311 
312 	unsigned int cpu = dev->id;
313 
314 	if (!pw20_wt) {
315 		smp_call_function_single(cpu, do_show_pwrmgtcr0, &value, 1);
316 		value = (value & PWRMGTCR0_PW20_ENT) >>
317 					PWRMGTCR0_PW20_ENT_SHIFT;
318 
319 		tb_cycle = (tb_cycle << (MAX_BIT - value + 1));
320 		/* convert ms to ns */
321 		if (tb_ticks_per_usec > 1000) {
322 			time = div_u64(tb_cycle, tb_ticks_per_usec / 1000);
323 		} else {
324 			u32 rem_us;
325 
326 			time = div_u64_rem(tb_cycle, tb_ticks_per_usec,
327 						&rem_us);
328 			time = time * 1000 + rem_us * 1000 / tb_ticks_per_usec;
329 		}
330 	} else {
331 		time = pw20_wt;
332 	}
333 
334 	return sprintf(buf, "%llu\n", time > 0 ? time : 0);
335 }
336 
set_pw20_wait_entry_bit(void * val)337 static void set_pw20_wait_entry_bit(void *val)
338 {
339 	u32 *value = val;
340 	u32 pw20_idle;
341 
342 	pw20_idle = mfspr(SPRN_PWRMGTCR0);
343 
344 	/* Set Automatic PW20 Core Idle Count */
345 	/* clear count */
346 	pw20_idle &= ~PWRMGTCR0_PW20_ENT;
347 
348 	/* set count */
349 	pw20_idle |= ((MAX_BIT - *value) << PWRMGTCR0_PW20_ENT_SHIFT);
350 
351 	mtspr(SPRN_PWRMGTCR0, pw20_idle);
352 }
353 
store_pw20_wait_time(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)354 static ssize_t store_pw20_wait_time(struct device *dev,
355 				struct device_attribute *attr,
356 				const char *buf, size_t count)
357 {
358 	u32 entry_bit;
359 	u64 value;
360 
361 	unsigned int cpu = dev->id;
362 
363 	if (kstrtou64(buf, 0, &value))
364 		return -EINVAL;
365 
366 	if (!value)
367 		return -EINVAL;
368 
369 	entry_bit = get_idle_ticks_bit(value);
370 	if (entry_bit > MAX_BIT)
371 		return -EINVAL;
372 
373 	pw20_wt = value;
374 
375 	smp_call_function_single(cpu, set_pw20_wait_entry_bit,
376 				&entry_bit, 1);
377 
378 	return count;
379 }
380 
show_altivec_idle(struct device * dev,struct device_attribute * attr,char * buf)381 static ssize_t show_altivec_idle(struct device *dev,
382 				struct device_attribute *attr, char *buf)
383 {
384 	u32 value;
385 	unsigned int cpu = dev->id;
386 
387 	smp_call_function_single(cpu, do_show_pwrmgtcr0, &value, 1);
388 
389 	value &= PWRMGTCR0_AV_IDLE_PD_EN;
390 
391 	return sprintf(buf, "%u\n", value ? 1 : 0);
392 }
393 
do_store_altivec_idle(void * val)394 static void do_store_altivec_idle(void *val)
395 {
396 	u32 *value = val;
397 	u32 altivec_idle;
398 
399 	altivec_idle = mfspr(SPRN_PWRMGTCR0);
400 
401 	if (*value)
402 		altivec_idle |= PWRMGTCR0_AV_IDLE_PD_EN;
403 	else
404 		altivec_idle &= ~PWRMGTCR0_AV_IDLE_PD_EN;
405 
406 	mtspr(SPRN_PWRMGTCR0, altivec_idle);
407 }
408 
store_altivec_idle(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)409 static ssize_t store_altivec_idle(struct device *dev,
410 				struct device_attribute *attr,
411 				const char *buf, size_t count)
412 {
413 	u32 value;
414 	unsigned int cpu = dev->id;
415 
416 	if (kstrtou32(buf, 0, &value))
417 		return -EINVAL;
418 
419 	if (value > 1)
420 		return -EINVAL;
421 
422 	smp_call_function_single(cpu, do_store_altivec_idle, &value, 1);
423 
424 	return count;
425 }
426 
show_altivec_idle_wait_time(struct device * dev,struct device_attribute * attr,char * buf)427 static ssize_t show_altivec_idle_wait_time(struct device *dev,
428 				struct device_attribute *attr, char *buf)
429 {
430 	u32 value;
431 	u64 tb_cycle = 1;
432 	u64 time;
433 
434 	unsigned int cpu = dev->id;
435 
436 	if (!altivec_idle_wt) {
437 		smp_call_function_single(cpu, do_show_pwrmgtcr0, &value, 1);
438 		value = (value & PWRMGTCR0_AV_IDLE_CNT) >>
439 					PWRMGTCR0_AV_IDLE_CNT_SHIFT;
440 
441 		tb_cycle = (tb_cycle << (MAX_BIT - value + 1));
442 		/* convert ms to ns */
443 		if (tb_ticks_per_usec > 1000) {
444 			time = div_u64(tb_cycle, tb_ticks_per_usec / 1000);
445 		} else {
446 			u32 rem_us;
447 
448 			time = div_u64_rem(tb_cycle, tb_ticks_per_usec,
449 						&rem_us);
450 			time = time * 1000 + rem_us * 1000 / tb_ticks_per_usec;
451 		}
452 	} else {
453 		time = altivec_idle_wt;
454 	}
455 
456 	return sprintf(buf, "%llu\n", time > 0 ? time : 0);
457 }
458 
set_altivec_idle_wait_entry_bit(void * val)459 static void set_altivec_idle_wait_entry_bit(void *val)
460 {
461 	u32 *value = val;
462 	u32 altivec_idle;
463 
464 	altivec_idle = mfspr(SPRN_PWRMGTCR0);
465 
466 	/* Set Automatic AltiVec Idle Count */
467 	/* clear count */
468 	altivec_idle &= ~PWRMGTCR0_AV_IDLE_CNT;
469 
470 	/* set count */
471 	altivec_idle |= ((MAX_BIT - *value) << PWRMGTCR0_AV_IDLE_CNT_SHIFT);
472 
473 	mtspr(SPRN_PWRMGTCR0, altivec_idle);
474 }
475 
store_altivec_idle_wait_time(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)476 static ssize_t store_altivec_idle_wait_time(struct device *dev,
477 				struct device_attribute *attr,
478 				const char *buf, size_t count)
479 {
480 	u32 entry_bit;
481 	u64 value;
482 
483 	unsigned int cpu = dev->id;
484 
485 	if (kstrtou64(buf, 0, &value))
486 		return -EINVAL;
487 
488 	if (!value)
489 		return -EINVAL;
490 
491 	entry_bit = get_idle_ticks_bit(value);
492 	if (entry_bit > MAX_BIT)
493 		return -EINVAL;
494 
495 	altivec_idle_wt = value;
496 
497 	smp_call_function_single(cpu, set_altivec_idle_wait_entry_bit,
498 				&entry_bit, 1);
499 
500 	return count;
501 }
502 
503 /*
504  * Enable/Disable interface:
505  * 0, disable. 1, enable.
506  */
507 static DEVICE_ATTR(pw20_state, 0600, show_pw20_state, store_pw20_state);
508 static DEVICE_ATTR(altivec_idle, 0600, show_altivec_idle, store_altivec_idle);
509 
510 /*
511  * Set wait time interface:(Nanosecond)
512  * Example: Base on TBfreq is 41MHZ.
513  * 1~48(ns): TB[63]
514  * 49~97(ns): TB[62]
515  * 98~195(ns): TB[61]
516  * 196~390(ns): TB[60]
517  * 391~780(ns): TB[59]
518  * 781~1560(ns): TB[58]
519  * ...
520  */
521 static DEVICE_ATTR(pw20_wait_time, 0600,
522 			show_pw20_wait_time,
523 			store_pw20_wait_time);
524 static DEVICE_ATTR(altivec_idle_wait_time, 0600,
525 			show_altivec_idle_wait_time,
526 			store_altivec_idle_wait_time);
527 #endif
528 
529 /*
530  * Enabling PMCs will slow partition context switch times so we only do
531  * it the first time we write to the PMCs.
532  */
533 
534 static DEFINE_PER_CPU(char, pmcs_enabled);
535 
ppc_enable_pmcs(void)536 void ppc_enable_pmcs(void)
537 {
538 	ppc_set_pmu_inuse(1);
539 
540 	/* Only need to enable them once */
541 	if (__this_cpu_read(pmcs_enabled))
542 		return;
543 
544 	__this_cpu_write(pmcs_enabled, 1);
545 
546 	if (ppc_md.enable_pmcs)
547 		ppc_md.enable_pmcs();
548 }
549 EXPORT_SYMBOL(ppc_enable_pmcs);
550 
551 
552 
553 /* Let's define all possible registers, we'll only hook up the ones
554  * that are implemented on the current processor
555  */
556 
557 #ifdef CONFIG_PMU_SYSFS
558 #if defined(CONFIG_PPC64) || defined(CONFIG_PPC_BOOK3S_32)
559 #define HAS_PPC_PMC_CLASSIC	1
560 #define HAS_PPC_PMC_IBM		1
561 #endif
562 
563 #ifdef CONFIG_PPC64
564 #define HAS_PPC_PMC_PA6T	1
565 #define HAS_PPC_PMC56          1
566 #endif
567 
568 #ifdef CONFIG_PPC_BOOK3S_32
569 #define HAS_PPC_PMC_G4		1
570 #endif
571 #endif /* CONFIG_PMU_SYSFS */
572 
573 #if defined(CONFIG_PPC64) && defined(CONFIG_DEBUG_MISC)
574 #define HAS_PPC_PA6T
575 #endif
576 /*
577  * SPRs which are not related to PMU.
578  */
579 #ifdef CONFIG_PPC64
580 SYSFS_SPRSETUP(purr, SPRN_PURR);
581 SYSFS_SPRSETUP(spurr, SPRN_SPURR);
582 SYSFS_SPRSETUP(pir, SPRN_PIR);
583 SYSFS_SPRSETUP(tscr, SPRN_TSCR);
584 
585 /*
586   Lets only enable read for phyp resources and
587   enable write when needed with a separate function.
588   Lets be conservative and default to pseries.
589 */
590 static DEVICE_ATTR(spurr, 0400, show_spurr, NULL);
591 static DEVICE_ATTR(purr, 0400, show_purr, store_purr);
592 static DEVICE_ATTR(pir, 0400, show_pir, NULL);
593 static DEVICE_ATTR(tscr, 0600, show_tscr, store_tscr);
594 #endif /* CONFIG_PPC64 */
595 
596 #ifdef HAS_PPC_PMC_CLASSIC
597 SYSFS_PMCSETUP(mmcr0, SPRN_MMCR0);
598 SYSFS_PMCSETUP(mmcr1, SPRN_MMCR1);
599 SYSFS_PMCSETUP(pmc1, SPRN_PMC1);
600 SYSFS_PMCSETUP(pmc2, SPRN_PMC2);
601 SYSFS_PMCSETUP(pmc3, SPRN_PMC3);
602 SYSFS_PMCSETUP(pmc4, SPRN_PMC4);
603 SYSFS_PMCSETUP(pmc5, SPRN_PMC5);
604 SYSFS_PMCSETUP(pmc6, SPRN_PMC6);
605 #endif
606 
607 #ifdef HAS_PPC_PMC_G4
608 SYSFS_PMCSETUP(mmcr2, SPRN_MMCR2);
609 #endif
610 
611 #ifdef HAS_PPC_PMC56
612 SYSFS_PMCSETUP(pmc7, SPRN_PMC7);
613 SYSFS_PMCSETUP(pmc8, SPRN_PMC8);
614 
615 SYSFS_PMCSETUP(mmcra, SPRN_MMCRA);
616 SYSFS_PMCSETUP(mmcr3, SPRN_MMCR3);
617 
618 static DEVICE_ATTR(mmcra, 0600, show_mmcra, store_mmcra);
619 static DEVICE_ATTR(mmcr3, 0600, show_mmcr3, store_mmcr3);
620 #endif /* HAS_PPC_PMC56 */
621 
622 
623 
624 
625 #ifdef HAS_PPC_PMC_PA6T
626 SYSFS_PMCSETUP(pa6t_pmc0, SPRN_PA6T_PMC0);
627 SYSFS_PMCSETUP(pa6t_pmc1, SPRN_PA6T_PMC1);
628 SYSFS_PMCSETUP(pa6t_pmc2, SPRN_PA6T_PMC2);
629 SYSFS_PMCSETUP(pa6t_pmc3, SPRN_PA6T_PMC3);
630 SYSFS_PMCSETUP(pa6t_pmc4, SPRN_PA6T_PMC4);
631 SYSFS_PMCSETUP(pa6t_pmc5, SPRN_PA6T_PMC5);
632 #endif
633 
634 #ifdef HAS_PPC_PA6T
635 SYSFS_SPRSETUP(hid0, SPRN_HID0);
636 SYSFS_SPRSETUP(hid1, SPRN_HID1);
637 SYSFS_SPRSETUP(hid4, SPRN_HID4);
638 SYSFS_SPRSETUP(hid5, SPRN_HID5);
639 SYSFS_SPRSETUP(ima0, SPRN_PA6T_IMA0);
640 SYSFS_SPRSETUP(ima1, SPRN_PA6T_IMA1);
641 SYSFS_SPRSETUP(ima2, SPRN_PA6T_IMA2);
642 SYSFS_SPRSETUP(ima3, SPRN_PA6T_IMA3);
643 SYSFS_SPRSETUP(ima4, SPRN_PA6T_IMA4);
644 SYSFS_SPRSETUP(ima5, SPRN_PA6T_IMA5);
645 SYSFS_SPRSETUP(ima6, SPRN_PA6T_IMA6);
646 SYSFS_SPRSETUP(ima7, SPRN_PA6T_IMA7);
647 SYSFS_SPRSETUP(ima8, SPRN_PA6T_IMA8);
648 SYSFS_SPRSETUP(ima9, SPRN_PA6T_IMA9);
649 SYSFS_SPRSETUP(imaat, SPRN_PA6T_IMAAT);
650 SYSFS_SPRSETUP(btcr, SPRN_PA6T_BTCR);
651 SYSFS_SPRSETUP(pccr, SPRN_PA6T_PCCR);
652 SYSFS_SPRSETUP(rpccr, SPRN_PA6T_RPCCR);
653 SYSFS_SPRSETUP(der, SPRN_PA6T_DER);
654 SYSFS_SPRSETUP(mer, SPRN_PA6T_MER);
655 SYSFS_SPRSETUP(ber, SPRN_PA6T_BER);
656 SYSFS_SPRSETUP(ier, SPRN_PA6T_IER);
657 SYSFS_SPRSETUP(sier, SPRN_PA6T_SIER);
658 SYSFS_SPRSETUP(siar, SPRN_PA6T_SIAR);
659 SYSFS_SPRSETUP(tsr0, SPRN_PA6T_TSR0);
660 SYSFS_SPRSETUP(tsr1, SPRN_PA6T_TSR1);
661 SYSFS_SPRSETUP(tsr2, SPRN_PA6T_TSR2);
662 SYSFS_SPRSETUP(tsr3, SPRN_PA6T_TSR3);
663 #endif /* HAS_PPC_PA6T */
664 
665 #ifdef HAS_PPC_PMC_IBM
666 static struct device_attribute ibm_common_attrs[] = {
667 	__ATTR(mmcr0, 0600, show_mmcr0, store_mmcr0),
668 	__ATTR(mmcr1, 0600, show_mmcr1, store_mmcr1),
669 };
670 #endif /* HAS_PPC_PMC_IBM */
671 
672 #ifdef HAS_PPC_PMC_G4
673 static struct device_attribute g4_common_attrs[] = {
674 	__ATTR(mmcr0, 0600, show_mmcr0, store_mmcr0),
675 	__ATTR(mmcr1, 0600, show_mmcr1, store_mmcr1),
676 	__ATTR(mmcr2, 0600, show_mmcr2, store_mmcr2),
677 };
678 #endif /* HAS_PPC_PMC_G4 */
679 
680 #ifdef HAS_PPC_PMC_CLASSIC
681 static struct device_attribute classic_pmc_attrs[] = {
682 	__ATTR(pmc1, 0600, show_pmc1, store_pmc1),
683 	__ATTR(pmc2, 0600, show_pmc2, store_pmc2),
684 	__ATTR(pmc3, 0600, show_pmc3, store_pmc3),
685 	__ATTR(pmc4, 0600, show_pmc4, store_pmc4),
686 	__ATTR(pmc5, 0600, show_pmc5, store_pmc5),
687 	__ATTR(pmc6, 0600, show_pmc6, store_pmc6),
688 #ifdef HAS_PPC_PMC56
689 	__ATTR(pmc7, 0600, show_pmc7, store_pmc7),
690 	__ATTR(pmc8, 0600, show_pmc8, store_pmc8),
691 #endif
692 };
693 #endif
694 
695 #if defined(HAS_PPC_PMC_PA6T) || defined(HAS_PPC_PA6T)
696 static struct device_attribute pa6t_attrs[] = {
697 #ifdef HAS_PPC_PMC_PA6T
698 	__ATTR(mmcr0, 0600, show_mmcr0, store_mmcr0),
699 	__ATTR(mmcr1, 0600, show_mmcr1, store_mmcr1),
700 	__ATTR(pmc0, 0600, show_pa6t_pmc0, store_pa6t_pmc0),
701 	__ATTR(pmc1, 0600, show_pa6t_pmc1, store_pa6t_pmc1),
702 	__ATTR(pmc2, 0600, show_pa6t_pmc2, store_pa6t_pmc2),
703 	__ATTR(pmc3, 0600, show_pa6t_pmc3, store_pa6t_pmc3),
704 	__ATTR(pmc4, 0600, show_pa6t_pmc4, store_pa6t_pmc4),
705 	__ATTR(pmc5, 0600, show_pa6t_pmc5, store_pa6t_pmc5),
706 #endif
707 #ifdef HAS_PPC_PA6T
708 	__ATTR(hid0, 0600, show_hid0, store_hid0),
709 	__ATTR(hid1, 0600, show_hid1, store_hid1),
710 	__ATTR(hid4, 0600, show_hid4, store_hid4),
711 	__ATTR(hid5, 0600, show_hid5, store_hid5),
712 	__ATTR(ima0, 0600, show_ima0, store_ima0),
713 	__ATTR(ima1, 0600, show_ima1, store_ima1),
714 	__ATTR(ima2, 0600, show_ima2, store_ima2),
715 	__ATTR(ima3, 0600, show_ima3, store_ima3),
716 	__ATTR(ima4, 0600, show_ima4, store_ima4),
717 	__ATTR(ima5, 0600, show_ima5, store_ima5),
718 	__ATTR(ima6, 0600, show_ima6, store_ima6),
719 	__ATTR(ima7, 0600, show_ima7, store_ima7),
720 	__ATTR(ima8, 0600, show_ima8, store_ima8),
721 	__ATTR(ima9, 0600, show_ima9, store_ima9),
722 	__ATTR(imaat, 0600, show_imaat, store_imaat),
723 	__ATTR(btcr, 0600, show_btcr, store_btcr),
724 	__ATTR(pccr, 0600, show_pccr, store_pccr),
725 	__ATTR(rpccr, 0600, show_rpccr, store_rpccr),
726 	__ATTR(der, 0600, show_der, store_der),
727 	__ATTR(mer, 0600, show_mer, store_mer),
728 	__ATTR(ber, 0600, show_ber, store_ber),
729 	__ATTR(ier, 0600, show_ier, store_ier),
730 	__ATTR(sier, 0600, show_sier, store_sier),
731 	__ATTR(siar, 0600, show_siar, store_siar),
732 	__ATTR(tsr0, 0600, show_tsr0, store_tsr0),
733 	__ATTR(tsr1, 0600, show_tsr1, store_tsr1),
734 	__ATTR(tsr2, 0600, show_tsr2, store_tsr2),
735 	__ATTR(tsr3, 0600, show_tsr3, store_tsr3),
736 #endif /* HAS_PPC_PA6T */
737 };
738 #endif
739 
740 #ifdef CONFIG_PPC_SVM
show_svm(struct device * dev,struct device_attribute * attr,char * buf)741 static ssize_t show_svm(struct device *dev, struct device_attribute *attr, char *buf)
742 {
743 	return sprintf(buf, "%u\n", is_secure_guest());
744 }
745 static DEVICE_ATTR(svm, 0444, show_svm, NULL);
746 
create_svm_file(void)747 static void __init create_svm_file(void)
748 {
749 	device_create_file(cpu_subsys.dev_root, &dev_attr_svm);
750 }
751 #else
create_svm_file(void)752 static void __init create_svm_file(void)
753 {
754 }
755 #endif /* CONFIG_PPC_SVM */
756 
757 #ifdef CONFIG_PPC_PSERIES
read_idle_purr(void * val)758 static void read_idle_purr(void *val)
759 {
760 	u64 *ret = val;
761 
762 	*ret = read_this_idle_purr();
763 }
764 
idle_purr_show(struct device * dev,struct device_attribute * attr,char * buf)765 static ssize_t idle_purr_show(struct device *dev,
766 			      struct device_attribute *attr, char *buf)
767 {
768 	struct cpu *cpu = container_of(dev, struct cpu, dev);
769 	u64 val;
770 
771 	smp_call_function_single(cpu->dev.id, read_idle_purr, &val, 1);
772 	return sprintf(buf, "%llx\n", val);
773 }
774 static DEVICE_ATTR(idle_purr, 0400, idle_purr_show, NULL);
775 
create_idle_purr_file(struct device * s)776 static void create_idle_purr_file(struct device *s)
777 {
778 	if (firmware_has_feature(FW_FEATURE_LPAR))
779 		device_create_file(s, &dev_attr_idle_purr);
780 }
781 
remove_idle_purr_file(struct device * s)782 static void remove_idle_purr_file(struct device *s)
783 {
784 	if (firmware_has_feature(FW_FEATURE_LPAR))
785 		device_remove_file(s, &dev_attr_idle_purr);
786 }
787 
read_idle_spurr(void * val)788 static void read_idle_spurr(void *val)
789 {
790 	u64 *ret = val;
791 
792 	*ret = read_this_idle_spurr();
793 }
794 
idle_spurr_show(struct device * dev,struct device_attribute * attr,char * buf)795 static ssize_t idle_spurr_show(struct device *dev,
796 			       struct device_attribute *attr, char *buf)
797 {
798 	struct cpu *cpu = container_of(dev, struct cpu, dev);
799 	u64 val;
800 
801 	smp_call_function_single(cpu->dev.id, read_idle_spurr, &val, 1);
802 	return sprintf(buf, "%llx\n", val);
803 }
804 static DEVICE_ATTR(idle_spurr, 0400, idle_spurr_show, NULL);
805 
create_idle_spurr_file(struct device * s)806 static void create_idle_spurr_file(struct device *s)
807 {
808 	if (firmware_has_feature(FW_FEATURE_LPAR))
809 		device_create_file(s, &dev_attr_idle_spurr);
810 }
811 
remove_idle_spurr_file(struct device * s)812 static void remove_idle_spurr_file(struct device *s)
813 {
814 	if (firmware_has_feature(FW_FEATURE_LPAR))
815 		device_remove_file(s, &dev_attr_idle_spurr);
816 }
817 
818 #else /* CONFIG_PPC_PSERIES */
819 #define create_idle_purr_file(s)
820 #define remove_idle_purr_file(s)
821 #define create_idle_spurr_file(s)
822 #define remove_idle_spurr_file(s)
823 #endif /* CONFIG_PPC_PSERIES */
824 
register_cpu_online(unsigned int cpu)825 static int register_cpu_online(unsigned int cpu)
826 {
827 	struct cpu *c = &per_cpu(cpu_devices, cpu);
828 	struct device *s = &c->dev;
829 	struct device_attribute *attrs, *pmc_attrs;
830 	int i, nattrs;
831 
832 	/* For cpus present at boot a reference was already grabbed in register_cpu() */
833 	if (!s->of_node)
834 		s->of_node = of_get_cpu_node(cpu, NULL);
835 
836 #ifdef CONFIG_PPC64
837 	if (cpu_has_feature(CPU_FTR_SMT))
838 		device_create_file(s, &dev_attr_smt_snooze_delay);
839 #endif
840 
841 	/* PMC stuff */
842 	switch (cur_cpu_spec->pmc_type) {
843 #ifdef HAS_PPC_PMC_IBM
844 	case PPC_PMC_IBM:
845 		attrs = ibm_common_attrs;
846 		nattrs = ARRAY_SIZE(ibm_common_attrs);
847 		pmc_attrs = classic_pmc_attrs;
848 		break;
849 #endif /* HAS_PPC_PMC_IBM */
850 #ifdef HAS_PPC_PMC_G4
851 	case PPC_PMC_G4:
852 		attrs = g4_common_attrs;
853 		nattrs = ARRAY_SIZE(g4_common_attrs);
854 		pmc_attrs = classic_pmc_attrs;
855 		break;
856 #endif /* HAS_PPC_PMC_G4 */
857 #if defined(HAS_PPC_PMC_PA6T) || defined(HAS_PPC_PA6T)
858 	case PPC_PMC_PA6T:
859 		/* PA Semi starts counting at PMC0 */
860 		attrs = pa6t_attrs;
861 		nattrs = ARRAY_SIZE(pa6t_attrs);
862 		pmc_attrs = NULL;
863 		break;
864 #endif
865 	default:
866 		attrs = NULL;
867 		nattrs = 0;
868 		pmc_attrs = NULL;
869 	}
870 
871 	for (i = 0; i < nattrs; i++)
872 		device_create_file(s, &attrs[i]);
873 
874 	if (pmc_attrs)
875 		for (i = 0; i < cur_cpu_spec->num_pmcs; i++)
876 			device_create_file(s, &pmc_attrs[i]);
877 
878 #ifdef CONFIG_PPC64
879 #ifdef	CONFIG_PMU_SYSFS
880 	if (cpu_has_feature(CPU_FTR_MMCRA))
881 		device_create_file(s, &dev_attr_mmcra);
882 
883 	if (cpu_has_feature(CPU_FTR_ARCH_31))
884 		device_create_file(s, &dev_attr_mmcr3);
885 #endif /* CONFIG_PMU_SYSFS */
886 
887 	if (cpu_has_feature(CPU_FTR_PURR)) {
888 		if (!firmware_has_feature(FW_FEATURE_LPAR))
889 			add_write_permission_dev_attr(&dev_attr_purr);
890 		device_create_file(s, &dev_attr_purr);
891 		create_idle_purr_file(s);
892 	}
893 
894 	if (cpu_has_feature(CPU_FTR_SPURR)) {
895 		device_create_file(s, &dev_attr_spurr);
896 		create_idle_spurr_file(s);
897 	}
898 
899 	if (cpu_has_feature(CPU_FTR_DSCR))
900 		device_create_file(s, &dev_attr_dscr);
901 
902 	if (cpu_has_feature(CPU_FTR_PPCAS_ARCH_V2))
903 		device_create_file(s, &dev_attr_pir);
904 
905 	if (cpu_has_feature(CPU_FTR_ARCH_206) &&
906 		!firmware_has_feature(FW_FEATURE_LPAR))
907 		device_create_file(s, &dev_attr_tscr);
908 #endif /* CONFIG_PPC64 */
909 
910 #ifdef CONFIG_PPC_E500
911 	if (PVR_VER(cur_cpu_spec->pvr_value) == PVR_VER_E6500) {
912 		device_create_file(s, &dev_attr_pw20_state);
913 		device_create_file(s, &dev_attr_pw20_wait_time);
914 
915 		device_create_file(s, &dev_attr_altivec_idle);
916 		device_create_file(s, &dev_attr_altivec_idle_wait_time);
917 	}
918 #endif
919 	cacheinfo_cpu_online(cpu);
920 	return 0;
921 }
922 
923 #ifdef CONFIG_HOTPLUG_CPU
unregister_cpu_online(unsigned int cpu)924 static int unregister_cpu_online(unsigned int cpu)
925 {
926 	struct cpu *c = &per_cpu(cpu_devices, cpu);
927 	struct device *s = &c->dev;
928 	struct device_attribute *attrs, *pmc_attrs;
929 	int i, nattrs;
930 
931 	if (WARN_RATELIMIT(!c->hotpluggable, "cpu %d can't be offlined\n", cpu))
932 		return -EBUSY;
933 
934 #ifdef CONFIG_PPC64
935 	if (cpu_has_feature(CPU_FTR_SMT))
936 		device_remove_file(s, &dev_attr_smt_snooze_delay);
937 #endif
938 
939 	/* PMC stuff */
940 	switch (cur_cpu_spec->pmc_type) {
941 #ifdef HAS_PPC_PMC_IBM
942 	case PPC_PMC_IBM:
943 		attrs = ibm_common_attrs;
944 		nattrs = ARRAY_SIZE(ibm_common_attrs);
945 		pmc_attrs = classic_pmc_attrs;
946 		break;
947 #endif /* HAS_PPC_PMC_IBM */
948 #ifdef HAS_PPC_PMC_G4
949 	case PPC_PMC_G4:
950 		attrs = g4_common_attrs;
951 		nattrs = ARRAY_SIZE(g4_common_attrs);
952 		pmc_attrs = classic_pmc_attrs;
953 		break;
954 #endif /* HAS_PPC_PMC_G4 */
955 #if defined(HAS_PPC_PMC_PA6T) || defined(HAS_PPC_PA6T)
956 	case PPC_PMC_PA6T:
957 		/* PA Semi starts counting at PMC0 */
958 		attrs = pa6t_attrs;
959 		nattrs = ARRAY_SIZE(pa6t_attrs);
960 		pmc_attrs = NULL;
961 		break;
962 #endif
963 	default:
964 		attrs = NULL;
965 		nattrs = 0;
966 		pmc_attrs = NULL;
967 	}
968 
969 	for (i = 0; i < nattrs; i++)
970 		device_remove_file(s, &attrs[i]);
971 
972 	if (pmc_attrs)
973 		for (i = 0; i < cur_cpu_spec->num_pmcs; i++)
974 			device_remove_file(s, &pmc_attrs[i]);
975 
976 #ifdef CONFIG_PPC64
977 #ifdef CONFIG_PMU_SYSFS
978 	if (cpu_has_feature(CPU_FTR_MMCRA))
979 		device_remove_file(s, &dev_attr_mmcra);
980 
981 	if (cpu_has_feature(CPU_FTR_ARCH_31))
982 		device_remove_file(s, &dev_attr_mmcr3);
983 #endif /* CONFIG_PMU_SYSFS */
984 
985 	if (cpu_has_feature(CPU_FTR_PURR)) {
986 		device_remove_file(s, &dev_attr_purr);
987 		remove_idle_purr_file(s);
988 	}
989 
990 	if (cpu_has_feature(CPU_FTR_SPURR)) {
991 		device_remove_file(s, &dev_attr_spurr);
992 		remove_idle_spurr_file(s);
993 	}
994 
995 	if (cpu_has_feature(CPU_FTR_DSCR))
996 		device_remove_file(s, &dev_attr_dscr);
997 
998 	if (cpu_has_feature(CPU_FTR_PPCAS_ARCH_V2))
999 		device_remove_file(s, &dev_attr_pir);
1000 
1001 	if (cpu_has_feature(CPU_FTR_ARCH_206) &&
1002 		!firmware_has_feature(FW_FEATURE_LPAR))
1003 		device_remove_file(s, &dev_attr_tscr);
1004 #endif /* CONFIG_PPC64 */
1005 
1006 #ifdef CONFIG_PPC_E500
1007 	if (PVR_VER(cur_cpu_spec->pvr_value) == PVR_VER_E6500) {
1008 		device_remove_file(s, &dev_attr_pw20_state);
1009 		device_remove_file(s, &dev_attr_pw20_wait_time);
1010 
1011 		device_remove_file(s, &dev_attr_altivec_idle);
1012 		device_remove_file(s, &dev_attr_altivec_idle_wait_time);
1013 	}
1014 #endif
1015 	cacheinfo_cpu_offline(cpu);
1016 	of_node_put(s->of_node);
1017 	s->of_node = NULL;
1018 	return 0;
1019 }
1020 #else /* !CONFIG_HOTPLUG_CPU */
1021 #define unregister_cpu_online NULL
1022 #endif
1023 
1024 #ifdef CONFIG_ARCH_CPU_PROBE_RELEASE
arch_cpu_probe(const char * buf,size_t count)1025 ssize_t arch_cpu_probe(const char *buf, size_t count)
1026 {
1027 	if (ppc_md.cpu_probe)
1028 		return ppc_md.cpu_probe(buf, count);
1029 
1030 	return -EINVAL;
1031 }
1032 
arch_cpu_release(const char * buf,size_t count)1033 ssize_t arch_cpu_release(const char *buf, size_t count)
1034 {
1035 	if (ppc_md.cpu_release)
1036 		return ppc_md.cpu_release(buf, count);
1037 
1038 	return -EINVAL;
1039 }
1040 #endif /* CONFIG_ARCH_CPU_PROBE_RELEASE */
1041 
1042 static DEFINE_MUTEX(cpu_mutex);
1043 
cpu_add_dev_attr(struct device_attribute * attr)1044 int cpu_add_dev_attr(struct device_attribute *attr)
1045 {
1046 	int cpu;
1047 
1048 	mutex_lock(&cpu_mutex);
1049 
1050 	for_each_possible_cpu(cpu) {
1051 		device_create_file(get_cpu_device(cpu), attr);
1052 	}
1053 
1054 	mutex_unlock(&cpu_mutex);
1055 	return 0;
1056 }
1057 EXPORT_SYMBOL_GPL(cpu_add_dev_attr);
1058 
cpu_add_dev_attr_group(struct attribute_group * attrs)1059 int cpu_add_dev_attr_group(struct attribute_group *attrs)
1060 {
1061 	int cpu;
1062 	struct device *dev;
1063 	int ret;
1064 
1065 	mutex_lock(&cpu_mutex);
1066 
1067 	for_each_possible_cpu(cpu) {
1068 		dev = get_cpu_device(cpu);
1069 		ret = sysfs_create_group(&dev->kobj, attrs);
1070 		WARN_ON(ret != 0);
1071 	}
1072 
1073 	mutex_unlock(&cpu_mutex);
1074 	return 0;
1075 }
1076 EXPORT_SYMBOL_GPL(cpu_add_dev_attr_group);
1077 
1078 
cpu_remove_dev_attr(struct device_attribute * attr)1079 void cpu_remove_dev_attr(struct device_attribute *attr)
1080 {
1081 	int cpu;
1082 
1083 	mutex_lock(&cpu_mutex);
1084 
1085 	for_each_possible_cpu(cpu) {
1086 		device_remove_file(get_cpu_device(cpu), attr);
1087 	}
1088 
1089 	mutex_unlock(&cpu_mutex);
1090 }
1091 EXPORT_SYMBOL_GPL(cpu_remove_dev_attr);
1092 
cpu_remove_dev_attr_group(struct attribute_group * attrs)1093 void cpu_remove_dev_attr_group(struct attribute_group *attrs)
1094 {
1095 	int cpu;
1096 	struct device *dev;
1097 
1098 	mutex_lock(&cpu_mutex);
1099 
1100 	for_each_possible_cpu(cpu) {
1101 		dev = get_cpu_device(cpu);
1102 		sysfs_remove_group(&dev->kobj, attrs);
1103 	}
1104 
1105 	mutex_unlock(&cpu_mutex);
1106 }
1107 EXPORT_SYMBOL_GPL(cpu_remove_dev_attr_group);
1108 
1109 
1110 /* NUMA stuff */
1111 
1112 #ifdef CONFIG_NUMA
sysfs_add_device_to_node(struct device * dev,int nid)1113 int sysfs_add_device_to_node(struct device *dev, int nid)
1114 {
1115 	struct node *node = node_devices[nid];
1116 	return sysfs_create_link(&node->dev.kobj, &dev->kobj,
1117 			kobject_name(&dev->kobj));
1118 }
1119 EXPORT_SYMBOL_GPL(sysfs_add_device_to_node);
1120 
sysfs_remove_device_from_node(struct device * dev,int nid)1121 void sysfs_remove_device_from_node(struct device *dev, int nid)
1122 {
1123 	struct node *node = node_devices[nid];
1124 	sysfs_remove_link(&node->dev.kobj, kobject_name(&dev->kobj));
1125 }
1126 EXPORT_SYMBOL_GPL(sysfs_remove_device_from_node);
1127 #endif
1128 
1129 /* Only valid if CPU is present. */
show_physical_id(struct device * dev,struct device_attribute * attr,char * buf)1130 static ssize_t show_physical_id(struct device *dev,
1131 				struct device_attribute *attr, char *buf)
1132 {
1133 	struct cpu *cpu = container_of(dev, struct cpu, dev);
1134 
1135 	return sprintf(buf, "%d\n", get_hard_smp_processor_id(cpu->dev.id));
1136 }
1137 static DEVICE_ATTR(physical_id, 0444, show_physical_id, NULL);
1138 
topology_init(void)1139 static int __init topology_init(void)
1140 {
1141 	int cpu, r;
1142 
1143 	for_each_possible_cpu(cpu) {
1144 		struct cpu *c = &per_cpu(cpu_devices, cpu);
1145 
1146 #ifdef CONFIG_HOTPLUG_CPU
1147 		/*
1148 		 * For now, we just see if the system supports making
1149 		 * the RTAS calls for CPU hotplug.  But, there may be a
1150 		 * more comprehensive way to do this for an individual
1151 		 * CPU.  For instance, the boot cpu might never be valid
1152 		 * for hotplugging.
1153 		 */
1154 		if (smp_ops && smp_ops->cpu_offline_self)
1155 			c->hotpluggable = 1;
1156 #endif
1157 
1158 		if (cpu_online(cpu) || c->hotpluggable) {
1159 			register_cpu(c, cpu);
1160 
1161 			device_create_file(&c->dev, &dev_attr_physical_id);
1162 		}
1163 	}
1164 	r = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "powerpc/topology:online",
1165 			      register_cpu_online, unregister_cpu_online);
1166 	WARN_ON(r < 0);
1167 #ifdef CONFIG_PPC64
1168 	sysfs_create_dscr_default();
1169 #endif /* CONFIG_PPC64 */
1170 
1171 	create_svm_file();
1172 
1173 	return 0;
1174 }
1175 subsys_initcall(topology_init);
1176