1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3  * cpu.h: Values of the PRID register used to match up
4  *	  various LoongArch CPU types.
5  *
6  * Copyright (C) 2020-2022 Loongson Technology Corporation Limited
7  */
8 #ifndef _ASM_CPU_H
9 #define _ASM_CPU_H
10 
11 /*
12  * As described in LoongArch specs from Loongson Technology, the PRID register
13  * (CPUCFG.00) has the following layout:
14  *
15  * +---------------+----------------+------------+--------------------+
16  * | Reserved      | Company ID     | Series ID  |  Product ID        |
17  * +---------------+----------------+------------+--------------------+
18  *  31		 24 23		  16 15	       12 11		     0
19  */
20 
21 /*
22  * Assigned Company values for bits 23:16 of the PRID register.
23  */
24 
25 #define PRID_COMP_MASK		0xff0000
26 
27 #define PRID_COMP_LOONGSON	0x140000
28 
29 /*
30  * Assigned Series ID values for bits 15:12 of the PRID register. In order
31  * to detect a certain CPU type exactly eventually additional registers may
32  * need to be examined.
33  */
34 
35 #define PRID_SERIES_MASK	0xf000
36 
37 #define PRID_SERIES_LA132	0x8000  /* Loongson 32bit */
38 #define PRID_SERIES_LA264	0xa000  /* Loongson 64bit, 2-issue */
39 #define PRID_SERIES_LA364	0xb000  /* Loongson 64bit,3-issue */
40 #define PRID_SERIES_LA464	0xc000  /* Loongson 64bit, 4-issue */
41 #define PRID_SERIES_LA664	0xd000  /* Loongson 64bit, 6-issue */
42 
43 /*
44  * Particular Product ID values for bits 11:0 of the PRID register.
45  */
46 
47 #define PRID_PRODUCT_MASK	0x0fff
48 
49 #if !defined(__ASSEMBLY__)
50 
51 enum cpu_type_enum {
52 	CPU_UNKNOWN,
53 	CPU_LOONGSON32,
54 	CPU_LOONGSON64,
55 	CPU_LAST
56 };
57 
58 #endif /* !__ASSEMBLY */
59 
60 /*
61  * ISA Level encodings
62  *
63  */
64 
65 #define LOONGARCH_CPU_ISA_LA32R 0x00000001
66 #define LOONGARCH_CPU_ISA_LA32S 0x00000002
67 #define LOONGARCH_CPU_ISA_LA64  0x00000004
68 
69 #define LOONGARCH_CPU_ISA_32BIT (LOONGARCH_CPU_ISA_LA32R | LOONGARCH_CPU_ISA_LA32S)
70 #define LOONGARCH_CPU_ISA_64BIT LOONGARCH_CPU_ISA_LA64
71 
72 /*
73  * CPU Option encodings
74  */
75 #define CPU_FEATURE_CPUCFG		0	/* CPU has CPUCFG */
76 #define CPU_FEATURE_LAM			1	/* CPU has Atomic instructions */
77 #define CPU_FEATURE_UAL			2	/* CPU supports unaligned access */
78 #define CPU_FEATURE_FPU			3	/* CPU has FPU */
79 #define CPU_FEATURE_LSX			4	/* CPU has LSX (128-bit SIMD) */
80 #define CPU_FEATURE_LASX		5	/* CPU has LASX (256-bit SIMD) */
81 #define CPU_FEATURE_COMPLEX		6	/* CPU has Complex instructions */
82 #define CPU_FEATURE_CRYPTO		7	/* CPU has Crypto instructions */
83 #define CPU_FEATURE_LVZ			8	/* CPU has Virtualization extension */
84 #define CPU_FEATURE_LBT_X86		9	/* CPU has X86 Binary Translation */
85 #define CPU_FEATURE_LBT_ARM		10	/* CPU has ARM Binary Translation */
86 #define CPU_FEATURE_LBT_MIPS		11	/* CPU has MIPS Binary Translation */
87 #define CPU_FEATURE_TLB			12	/* CPU has TLB */
88 #define CPU_FEATURE_CSR			13	/* CPU has CSR */
89 #define CPU_FEATURE_WATCH		14	/* CPU has watchpoint registers */
90 #define CPU_FEATURE_VINT		15	/* CPU has vectored interrupts */
91 #define CPU_FEATURE_CSRIPI		16	/* CPU has CSR-IPI */
92 #define CPU_FEATURE_EXTIOI		17	/* CPU has EXT-IOI */
93 #define CPU_FEATURE_PREFETCH		18	/* CPU has prefetch instructions */
94 #define CPU_FEATURE_PMP			19	/* CPU has perfermance counter */
95 #define CPU_FEATURE_SCALEFREQ		20	/* CPU supports cpufreq scaling */
96 #define CPU_FEATURE_FLATMODE		21	/* CPU has flat mode */
97 #define CPU_FEATURE_EIODECODE		22	/* CPU has EXTIOI interrupt pin decode mode */
98 #define CPU_FEATURE_GUESTID		23	/* CPU has GuestID feature */
99 #define CPU_FEATURE_HYPERVISOR		24	/* CPU has hypervisor (running in VM) */
100 
101 #define LOONGARCH_CPU_CPUCFG		BIT_ULL(CPU_FEATURE_CPUCFG)
102 #define LOONGARCH_CPU_LAM		BIT_ULL(CPU_FEATURE_LAM)
103 #define LOONGARCH_CPU_UAL		BIT_ULL(CPU_FEATURE_UAL)
104 #define LOONGARCH_CPU_FPU		BIT_ULL(CPU_FEATURE_FPU)
105 #define LOONGARCH_CPU_LSX		BIT_ULL(CPU_FEATURE_LSX)
106 #define LOONGARCH_CPU_LASX		BIT_ULL(CPU_FEATURE_LASX)
107 #define LOONGARCH_CPU_COMPLEX		BIT_ULL(CPU_FEATURE_COMPLEX)
108 #define LOONGARCH_CPU_CRYPTO		BIT_ULL(CPU_FEATURE_CRYPTO)
109 #define LOONGARCH_CPU_LVZ		BIT_ULL(CPU_FEATURE_LVZ)
110 #define LOONGARCH_CPU_LBT_X86		BIT_ULL(CPU_FEATURE_LBT_X86)
111 #define LOONGARCH_CPU_LBT_ARM		BIT_ULL(CPU_FEATURE_LBT_ARM)
112 #define LOONGARCH_CPU_LBT_MIPS		BIT_ULL(CPU_FEATURE_LBT_MIPS)
113 #define LOONGARCH_CPU_TLB		BIT_ULL(CPU_FEATURE_TLB)
114 #define LOONGARCH_CPU_CSR		BIT_ULL(CPU_FEATURE_CSR)
115 #define LOONGARCH_CPU_WATCH		BIT_ULL(CPU_FEATURE_WATCH)
116 #define LOONGARCH_CPU_VINT		BIT_ULL(CPU_FEATURE_VINT)
117 #define LOONGARCH_CPU_CSRIPI		BIT_ULL(CPU_FEATURE_CSRIPI)
118 #define LOONGARCH_CPU_EXTIOI		BIT_ULL(CPU_FEATURE_EXTIOI)
119 #define LOONGARCH_CPU_PREFETCH		BIT_ULL(CPU_FEATURE_PREFETCH)
120 #define LOONGARCH_CPU_PMP		BIT_ULL(CPU_FEATURE_PMP)
121 #define LOONGARCH_CPU_SCALEFREQ		BIT_ULL(CPU_FEATURE_SCALEFREQ)
122 #define LOONGARCH_CPU_FLATMODE		BIT_ULL(CPU_FEATURE_FLATMODE)
123 #define LOONGARCH_CPU_EIODECODE		BIT_ULL(CPU_FEATURE_EIODECODE)
124 #define LOONGARCH_CPU_GUESTID		BIT_ULL(CPU_FEATURE_GUESTID)
125 #define LOONGARCH_CPU_HYPERVISOR	BIT_ULL(CPU_FEATURE_HYPERVISOR)
126 
127 #endif /* _ASM_CPU_H */
128