1 /*
2 * Copyright 2011 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 */
23
24 #ifndef DRM_FOURCC_H
25 #define DRM_FOURCC_H
26
27 #include "drm.h"
28
29 #if defined(__cplusplus)
30 extern "C" {
31 #endif
32
33 /**
34 * DOC: overview
35 *
36 * In the DRM subsystem, framebuffer pixel formats are described using the
37 * fourcc codes defined in `include/uapi/drm/drm_fourcc.h`. In addition to the
38 * fourcc code, a Format Modifier may optionally be provided, in order to
39 * further describe the buffer's format - for example tiling or compression.
40 *
41 * Format Modifiers
42 * ----------------
43 *
44 * Format modifiers are used in conjunction with a fourcc code, forming a
45 * unique fourcc:modifier pair. This format:modifier pair must fully define the
46 * format and data layout of the buffer, and should be the only way to describe
47 * that particular buffer.
48 *
49 * Having multiple fourcc:modifier pairs which describe the same layout should
50 * be avoided, as such aliases run the risk of different drivers exposing
51 * different names for the same data format, forcing userspace to understand
52 * that they are aliases.
53 *
54 * Format modifiers may change any property of the buffer, including the number
55 * of planes and/or the required allocation size. Format modifiers are
56 * vendor-namespaced, and as such the relationship between a fourcc code and a
57 * modifier is specific to the modifer being used. For example, some modifiers
58 * may preserve meaning - such as number of planes - from the fourcc code,
59 * whereas others may not.
60 *
61 * Modifiers must uniquely encode buffer layout. In other words, a buffer must
62 * match only a single modifier. A modifier must not be a subset of layouts of
63 * another modifier. For instance, it's incorrect to encode pitch alignment in
64 * a modifier: a buffer may match a 64-pixel aligned modifier and a 32-pixel
65 * aligned modifier. That said, modifiers can have implicit minimal
66 * requirements.
67 *
68 * For modifiers where the combination of fourcc code and modifier can alias,
69 * a canonical pair needs to be defined and used by all drivers. Preferred
70 * combinations are also encouraged where all combinations might lead to
71 * confusion and unnecessarily reduced interoperability. An example for the
72 * latter is AFBC, where the ABGR layouts are preferred over ARGB layouts.
73 *
74 * There are two kinds of modifier users:
75 *
76 * - Kernel and user-space drivers: for drivers it's important that modifiers
77 * don't alias, otherwise two drivers might support the same format but use
78 * different aliases, preventing them from sharing buffers in an efficient
79 * format.
80 * - Higher-level programs interfacing with KMS/GBM/EGL/Vulkan/etc: these users
81 * see modifiers as opaque tokens they can check for equality and intersect.
82 * These users musn't need to know to reason about the modifier value
83 * (i.e. they are not expected to extract information out of the modifier).
84 *
85 * Vendors should document their modifier usage in as much detail as
86 * possible, to ensure maximum compatibility across devices, drivers and
87 * applications.
88 *
89 * The authoritative list of format modifier codes is found in
90 * `include/uapi/drm/drm_fourcc.h`
91 */
92
93 #define fourcc_code(a, b, c, d) ((__u32)(a) | ((__u32)(b) << 8) | \
94 ((__u32)(c) << 16) | ((__u32)(d) << 24))
95
96 #define DRM_FORMAT_BIG_ENDIAN (1U<<31) /* format is big endian instead of little endian */
97
98 /* Reserve 0 for the invalid format specifier */
99 #define DRM_FORMAT_INVALID 0
100
101 /* color index */
102 #define DRM_FORMAT_C8 fourcc_code('C', '8', ' ', ' ') /* [7:0] C */
103
104 /* 8 bpp Red */
105 #define DRM_FORMAT_R8 fourcc_code('R', '8', ' ', ' ') /* [7:0] R */
106
107 /* 10 bpp Red */
108 #define DRM_FORMAT_R10 fourcc_code('R', '1', '0', ' ') /* [15:0] x:R 6:10 little endian */
109
110 /* 12 bpp Red */
111 #define DRM_FORMAT_R12 fourcc_code('R', '1', '2', ' ') /* [15:0] x:R 4:12 little endian */
112
113 /* 16 bpp Red */
114 #define DRM_FORMAT_R16 fourcc_code('R', '1', '6', ' ') /* [15:0] R little endian */
115
116 /* 16 bpp RG */
117 #define DRM_FORMAT_RG88 fourcc_code('R', 'G', '8', '8') /* [15:0] R:G 8:8 little endian */
118 #define DRM_FORMAT_GR88 fourcc_code('G', 'R', '8', '8') /* [15:0] G:R 8:8 little endian */
119
120 /* 32 bpp RG */
121 #define DRM_FORMAT_RG1616 fourcc_code('R', 'G', '3', '2') /* [31:0] R:G 16:16 little endian */
122 #define DRM_FORMAT_GR1616 fourcc_code('G', 'R', '3', '2') /* [31:0] G:R 16:16 little endian */
123
124 /* 8 bpp RGB */
125 #define DRM_FORMAT_RGB332 fourcc_code('R', 'G', 'B', '8') /* [7:0] R:G:B 3:3:2 */
126 #define DRM_FORMAT_BGR233 fourcc_code('B', 'G', 'R', '8') /* [7:0] B:G:R 2:3:3 */
127
128 /* 16 bpp RGB */
129 #define DRM_FORMAT_XRGB4444 fourcc_code('X', 'R', '1', '2') /* [15:0] x:R:G:B 4:4:4:4 little endian */
130 #define DRM_FORMAT_XBGR4444 fourcc_code('X', 'B', '1', '2') /* [15:0] x:B:G:R 4:4:4:4 little endian */
131 #define DRM_FORMAT_RGBX4444 fourcc_code('R', 'X', '1', '2') /* [15:0] R:G:B:x 4:4:4:4 little endian */
132 #define DRM_FORMAT_BGRX4444 fourcc_code('B', 'X', '1', '2') /* [15:0] B:G:R:x 4:4:4:4 little endian */
133
134 #define DRM_FORMAT_ARGB4444 fourcc_code('A', 'R', '1', '2') /* [15:0] A:R:G:B 4:4:4:4 little endian */
135 #define DRM_FORMAT_ABGR4444 fourcc_code('A', 'B', '1', '2') /* [15:0] A:B:G:R 4:4:4:4 little endian */
136 #define DRM_FORMAT_RGBA4444 fourcc_code('R', 'A', '1', '2') /* [15:0] R:G:B:A 4:4:4:4 little endian */
137 #define DRM_FORMAT_BGRA4444 fourcc_code('B', 'A', '1', '2') /* [15:0] B:G:R:A 4:4:4:4 little endian */
138
139 #define DRM_FORMAT_XRGB1555 fourcc_code('X', 'R', '1', '5') /* [15:0] x:R:G:B 1:5:5:5 little endian */
140 #define DRM_FORMAT_XBGR1555 fourcc_code('X', 'B', '1', '5') /* [15:0] x:B:G:R 1:5:5:5 little endian */
141 #define DRM_FORMAT_RGBX5551 fourcc_code('R', 'X', '1', '5') /* [15:0] R:G:B:x 5:5:5:1 little endian */
142 #define DRM_FORMAT_BGRX5551 fourcc_code('B', 'X', '1', '5') /* [15:0] B:G:R:x 5:5:5:1 little endian */
143
144 #define DRM_FORMAT_ARGB1555 fourcc_code('A', 'R', '1', '5') /* [15:0] A:R:G:B 1:5:5:5 little endian */
145 #define DRM_FORMAT_ABGR1555 fourcc_code('A', 'B', '1', '5') /* [15:0] A:B:G:R 1:5:5:5 little endian */
146 #define DRM_FORMAT_RGBA5551 fourcc_code('R', 'A', '1', '5') /* [15:0] R:G:B:A 5:5:5:1 little endian */
147 #define DRM_FORMAT_BGRA5551 fourcc_code('B', 'A', '1', '5') /* [15:0] B:G:R:A 5:5:5:1 little endian */
148
149 #define DRM_FORMAT_RGB565 fourcc_code('R', 'G', '1', '6') /* [15:0] R:G:B 5:6:5 little endian */
150 #define DRM_FORMAT_BGR565 fourcc_code('B', 'G', '1', '6') /* [15:0] B:G:R 5:6:5 little endian */
151
152 /* 24 bpp RGB */
153 #define DRM_FORMAT_RGB888 fourcc_code('R', 'G', '2', '4') /* [23:0] R:G:B little endian */
154 #define DRM_FORMAT_BGR888 fourcc_code('B', 'G', '2', '4') /* [23:0] B:G:R little endian */
155
156 /* 32 bpp RGB */
157 #define DRM_FORMAT_XRGB8888 fourcc_code('X', 'R', '2', '4') /* [31:0] x:R:G:B 8:8:8:8 little endian */
158 #define DRM_FORMAT_XBGR8888 fourcc_code('X', 'B', '2', '4') /* [31:0] x:B:G:R 8:8:8:8 little endian */
159 #define DRM_FORMAT_RGBX8888 fourcc_code('R', 'X', '2', '4') /* [31:0] R:G:B:x 8:8:8:8 little endian */
160 #define DRM_FORMAT_BGRX8888 fourcc_code('B', 'X', '2', '4') /* [31:0] B:G:R:x 8:8:8:8 little endian */
161
162 #define DRM_FORMAT_ARGB8888 fourcc_code('A', 'R', '2', '4') /* [31:0] A:R:G:B 8:8:8:8 little endian */
163 #define DRM_FORMAT_ABGR8888 fourcc_code('A', 'B', '2', '4') /* [31:0] A:B:G:R 8:8:8:8 little endian */
164 #define DRM_FORMAT_RGBA8888 fourcc_code('R', 'A', '2', '4') /* [31:0] R:G:B:A 8:8:8:8 little endian */
165 #define DRM_FORMAT_BGRA8888 fourcc_code('B', 'A', '2', '4') /* [31:0] B:G:R:A 8:8:8:8 little endian */
166
167 #define DRM_FORMAT_XRGB2101010 fourcc_code('X', 'R', '3', '0') /* [31:0] x:R:G:B 2:10:10:10 little endian */
168 #define DRM_FORMAT_XBGR2101010 fourcc_code('X', 'B', '3', '0') /* [31:0] x:B:G:R 2:10:10:10 little endian */
169 #define DRM_FORMAT_RGBX1010102 fourcc_code('R', 'X', '3', '0') /* [31:0] R:G:B:x 10:10:10:2 little endian */
170 #define DRM_FORMAT_BGRX1010102 fourcc_code('B', 'X', '3', '0') /* [31:0] B:G:R:x 10:10:10:2 little endian */
171
172 #define DRM_FORMAT_ARGB2101010 fourcc_code('A', 'R', '3', '0') /* [31:0] A:R:G:B 2:10:10:10 little endian */
173 #define DRM_FORMAT_ABGR2101010 fourcc_code('A', 'B', '3', '0') /* [31:0] A:B:G:R 2:10:10:10 little endian */
174 #define DRM_FORMAT_RGBA1010102 fourcc_code('R', 'A', '3', '0') /* [31:0] R:G:B:A 10:10:10:2 little endian */
175 #define DRM_FORMAT_BGRA1010102 fourcc_code('B', 'A', '3', '0') /* [31:0] B:G:R:A 10:10:10:2 little endian */
176
177 /* 64 bpp RGB */
178 #define DRM_FORMAT_XRGB16161616 fourcc_code('X', 'R', '4', '8') /* [63:0] x:R:G:B 16:16:16:16 little endian */
179 #define DRM_FORMAT_XBGR16161616 fourcc_code('X', 'B', '4', '8') /* [63:0] x:B:G:R 16:16:16:16 little endian */
180
181 #define DRM_FORMAT_ARGB16161616 fourcc_code('A', 'R', '4', '8') /* [63:0] A:R:G:B 16:16:16:16 little endian */
182 #define DRM_FORMAT_ABGR16161616 fourcc_code('A', 'B', '4', '8') /* [63:0] A:B:G:R 16:16:16:16 little endian */
183
184 /*
185 * Floating point 64bpp RGB
186 * IEEE 754-2008 binary16 half-precision float
187 * [15:0] sign:exponent:mantissa 1:5:10
188 */
189 #define DRM_FORMAT_XRGB16161616F fourcc_code('X', 'R', '4', 'H') /* [63:0] x:R:G:B 16:16:16:16 little endian */
190 #define DRM_FORMAT_XBGR16161616F fourcc_code('X', 'B', '4', 'H') /* [63:0] x:B:G:R 16:16:16:16 little endian */
191
192 #define DRM_FORMAT_ARGB16161616F fourcc_code('A', 'R', '4', 'H') /* [63:0] A:R:G:B 16:16:16:16 little endian */
193 #define DRM_FORMAT_ABGR16161616F fourcc_code('A', 'B', '4', 'H') /* [63:0] A:B:G:R 16:16:16:16 little endian */
194
195 /*
196 * RGBA format with 10-bit components packed in 64-bit per pixel, with 6 bits
197 * of unused padding per component:
198 */
199 #define DRM_FORMAT_AXBXGXRX106106106106 fourcc_code('A', 'B', '1', '0') /* [63:0] A:x:B:x:G:x:R:x 10:6:10:6:10:6:10:6 little endian */
200
201 /* packed YCbCr */
202 #define DRM_FORMAT_YUYV fourcc_code('Y', 'U', 'Y', 'V') /* [31:0] Cr0:Y1:Cb0:Y0 8:8:8:8 little endian */
203 #define DRM_FORMAT_YVYU fourcc_code('Y', 'V', 'Y', 'U') /* [31:0] Cb0:Y1:Cr0:Y0 8:8:8:8 little endian */
204 #define DRM_FORMAT_UYVY fourcc_code('U', 'Y', 'V', 'Y') /* [31:0] Y1:Cr0:Y0:Cb0 8:8:8:8 little endian */
205 #define DRM_FORMAT_VYUY fourcc_code('V', 'Y', 'U', 'Y') /* [31:0] Y1:Cb0:Y0:Cr0 8:8:8:8 little endian */
206
207 #define DRM_FORMAT_AYUV fourcc_code('A', 'Y', 'U', 'V') /* [31:0] A:Y:Cb:Cr 8:8:8:8 little endian */
208 #define DRM_FORMAT_XYUV8888 fourcc_code('X', 'Y', 'U', 'V') /* [31:0] X:Y:Cb:Cr 8:8:8:8 little endian */
209 #define DRM_FORMAT_VUY888 fourcc_code('V', 'U', '2', '4') /* [23:0] Cr:Cb:Y 8:8:8 little endian */
210 #define DRM_FORMAT_VUY101010 fourcc_code('V', 'U', '3', '0') /* Y followed by U then V, 10:10:10. Non-linear modifier only */
211
212 /*
213 * packed Y2xx indicate for each component, xx valid data occupy msb
214 * 16-xx padding occupy lsb
215 */
216 #define DRM_FORMAT_Y210 fourcc_code('Y', '2', '1', '0') /* [63:0] Cr0:0:Y1:0:Cb0:0:Y0:0 10:6:10:6:10:6:10:6 little endian per 2 Y pixels */
217 #define DRM_FORMAT_Y212 fourcc_code('Y', '2', '1', '2') /* [63:0] Cr0:0:Y1:0:Cb0:0:Y0:0 12:4:12:4:12:4:12:4 little endian per 2 Y pixels */
218 #define DRM_FORMAT_Y216 fourcc_code('Y', '2', '1', '6') /* [63:0] Cr0:Y1:Cb0:Y0 16:16:16:16 little endian per 2 Y pixels */
219
220 /*
221 * packed Y4xx indicate for each component, xx valid data occupy msb
222 * 16-xx padding occupy lsb except Y410
223 */
224 #define DRM_FORMAT_Y410 fourcc_code('Y', '4', '1', '0') /* [31:0] A:Cr:Y:Cb 2:10:10:10 little endian */
225 #define DRM_FORMAT_Y412 fourcc_code('Y', '4', '1', '2') /* [63:0] A:0:Cr:0:Y:0:Cb:0 12:4:12:4:12:4:12:4 little endian */
226 #define DRM_FORMAT_Y416 fourcc_code('Y', '4', '1', '6') /* [63:0] A:Cr:Y:Cb 16:16:16:16 little endian */
227
228 #define DRM_FORMAT_XVYU2101010 fourcc_code('X', 'V', '3', '0') /* [31:0] X:Cr:Y:Cb 2:10:10:10 little endian */
229 #define DRM_FORMAT_XVYU12_16161616 fourcc_code('X', 'V', '3', '6') /* [63:0] X:0:Cr:0:Y:0:Cb:0 12:4:12:4:12:4:12:4 little endian */
230 #define DRM_FORMAT_XVYU16161616 fourcc_code('X', 'V', '4', '8') /* [63:0] X:Cr:Y:Cb 16:16:16:16 little endian */
231
232 /*
233 * packed YCbCr420 2x2 tiled formats
234 * first 64 bits will contain Y,Cb,Cr components for a 2x2 tile
235 */
236 /* [63:0] A3:A2:Y3:0:Cr0:0:Y2:0:A1:A0:Y1:0:Cb0:0:Y0:0 1:1:8:2:8:2:8:2:1:1:8:2:8:2:8:2 little endian */
237 #define DRM_FORMAT_Y0L0 fourcc_code('Y', '0', 'L', '0')
238 /* [63:0] X3:X2:Y3:0:Cr0:0:Y2:0:X1:X0:Y1:0:Cb0:0:Y0:0 1:1:8:2:8:2:8:2:1:1:8:2:8:2:8:2 little endian */
239 #define DRM_FORMAT_X0L0 fourcc_code('X', '0', 'L', '0')
240
241 /* [63:0] A3:A2:Y3:Cr0:Y2:A1:A0:Y1:Cb0:Y0 1:1:10:10:10:1:1:10:10:10 little endian */
242 #define DRM_FORMAT_Y0L2 fourcc_code('Y', '0', 'L', '2')
243 /* [63:0] X3:X2:Y3:Cr0:Y2:X1:X0:Y1:Cb0:Y0 1:1:10:10:10:1:1:10:10:10 little endian */
244 #define DRM_FORMAT_X0L2 fourcc_code('X', '0', 'L', '2')
245
246 /*
247 * 1-plane YUV 4:2:0
248 * In these formats, the component ordering is specified (Y, followed by U
249 * then V), but the exact Linear layout is undefined.
250 * These formats can only be used with a non-Linear modifier.
251 */
252 #define DRM_FORMAT_YUV420_8BIT fourcc_code('Y', 'U', '0', '8')
253 #define DRM_FORMAT_YUV420_10BIT fourcc_code('Y', 'U', '1', '0')
254
255 /*
256 * 2 plane RGB + A
257 * index 0 = RGB plane, same format as the corresponding non _A8 format has
258 * index 1 = A plane, [7:0] A
259 */
260 #define DRM_FORMAT_XRGB8888_A8 fourcc_code('X', 'R', 'A', '8')
261 #define DRM_FORMAT_XBGR8888_A8 fourcc_code('X', 'B', 'A', '8')
262 #define DRM_FORMAT_RGBX8888_A8 fourcc_code('R', 'X', 'A', '8')
263 #define DRM_FORMAT_BGRX8888_A8 fourcc_code('B', 'X', 'A', '8')
264 #define DRM_FORMAT_RGB888_A8 fourcc_code('R', '8', 'A', '8')
265 #define DRM_FORMAT_BGR888_A8 fourcc_code('B', '8', 'A', '8')
266 #define DRM_FORMAT_RGB565_A8 fourcc_code('R', '5', 'A', '8')
267 #define DRM_FORMAT_BGR565_A8 fourcc_code('B', '5', 'A', '8')
268
269 /*
270 * 2 plane YCbCr
271 * index 0 = Y plane, [7:0] Y
272 * index 1 = Cr:Cb plane, [15:0] Cr:Cb little endian
273 * or
274 * index 1 = Cb:Cr plane, [15:0] Cb:Cr little endian
275 */
276 #define DRM_FORMAT_NV12 fourcc_code('N', 'V', '1', '2') /* 2x2 subsampled Cr:Cb plane */
277 #define DRM_FORMAT_NV21 fourcc_code('N', 'V', '2', '1') /* 2x2 subsampled Cb:Cr plane */
278 #define DRM_FORMAT_NV16 fourcc_code('N', 'V', '1', '6') /* 2x1 subsampled Cr:Cb plane */
279 #define DRM_FORMAT_NV61 fourcc_code('N', 'V', '6', '1') /* 2x1 subsampled Cb:Cr plane */
280 #define DRM_FORMAT_NV24 fourcc_code('N', 'V', '2', '4') /* non-subsampled Cr:Cb plane */
281 #define DRM_FORMAT_NV42 fourcc_code('N', 'V', '4', '2') /* non-subsampled Cb:Cr plane */
282 /*
283 * 2 plane YCbCr
284 * index 0 = Y plane, [39:0] Y3:Y2:Y1:Y0 little endian
285 * index 1 = Cr:Cb plane, [39:0] Cr1:Cb1:Cr0:Cb0 little endian
286 */
287 #define DRM_FORMAT_NV15 fourcc_code('N', 'V', '1', '5') /* 2x2 subsampled Cr:Cb plane */
288
289 /*
290 * 2 plane YCbCr MSB aligned
291 * index 0 = Y plane, [15:0] Y:x [10:6] little endian
292 * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [10:6:10:6] little endian
293 */
294 #define DRM_FORMAT_P210 fourcc_code('P', '2', '1', '0') /* 2x1 subsampled Cr:Cb plane, 10 bit per channel */
295
296 /*
297 * 2 plane YCbCr MSB aligned
298 * index 0 = Y plane, [15:0] Y:x [10:6] little endian
299 * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [10:6:10:6] little endian
300 */
301 #define DRM_FORMAT_P010 fourcc_code('P', '0', '1', '0') /* 2x2 subsampled Cr:Cb plane 10 bits per channel */
302
303 /*
304 * 2 plane YCbCr MSB aligned
305 * index 0 = Y plane, [15:0] Y:x [12:4] little endian
306 * index 1 = Cr:Cb plane, [31:0] Cr:x:Cb:x [12:4:12:4] little endian
307 */
308 #define DRM_FORMAT_P012 fourcc_code('P', '0', '1', '2') /* 2x2 subsampled Cr:Cb plane 12 bits per channel */
309
310 /*
311 * 2 plane YCbCr MSB aligned
312 * index 0 = Y plane, [15:0] Y little endian
313 * index 1 = Cr:Cb plane, [31:0] Cr:Cb [16:16] little endian
314 */
315 #define DRM_FORMAT_P016 fourcc_code('P', '0', '1', '6') /* 2x2 subsampled Cr:Cb plane 16 bits per channel */
316
317 /* 2 plane YCbCr420.
318 * 3 10 bit components and 2 padding bits packed into 4 bytes.
319 * index 0 = Y plane, [31:0] x:Y2:Y1:Y0 2:10:10:10 little endian
320 * index 1 = Cr:Cb plane, [63:0] x:Cr2:Cb2:Cr1:x:Cb1:Cr0:Cb0 [2:10:10:10:2:10:10:10] little endian
321 */
322 #define DRM_FORMAT_P030 fourcc_code('P', '0', '3', '0') /* 2x2 subsampled Cr:Cb plane 10 bits per channel packed */
323
324 /* 3 plane non-subsampled (444) YCbCr
325 * 16 bits per component, but only 10 bits are used and 6 bits are padded
326 * index 0: Y plane, [15:0] Y:x [10:6] little endian
327 * index 1: Cb plane, [15:0] Cb:x [10:6] little endian
328 * index 2: Cr plane, [15:0] Cr:x [10:6] little endian
329 */
330 #define DRM_FORMAT_Q410 fourcc_code('Q', '4', '1', '0')
331
332 /* 3 plane non-subsampled (444) YCrCb
333 * 16 bits per component, but only 10 bits are used and 6 bits are padded
334 * index 0: Y plane, [15:0] Y:x [10:6] little endian
335 * index 1: Cr plane, [15:0] Cr:x [10:6] little endian
336 * index 2: Cb plane, [15:0] Cb:x [10:6] little endian
337 */
338 #define DRM_FORMAT_Q401 fourcc_code('Q', '4', '0', '1')
339
340 /*
341 * 3 plane YCbCr
342 * index 0: Y plane, [7:0] Y
343 * index 1: Cb plane, [7:0] Cb
344 * index 2: Cr plane, [7:0] Cr
345 * or
346 * index 1: Cr plane, [7:0] Cr
347 * index 2: Cb plane, [7:0] Cb
348 */
349 #define DRM_FORMAT_YUV410 fourcc_code('Y', 'U', 'V', '9') /* 4x4 subsampled Cb (1) and Cr (2) planes */
350 #define DRM_FORMAT_YVU410 fourcc_code('Y', 'V', 'U', '9') /* 4x4 subsampled Cr (1) and Cb (2) planes */
351 #define DRM_FORMAT_YUV411 fourcc_code('Y', 'U', '1', '1') /* 4x1 subsampled Cb (1) and Cr (2) planes */
352 #define DRM_FORMAT_YVU411 fourcc_code('Y', 'V', '1', '1') /* 4x1 subsampled Cr (1) and Cb (2) planes */
353 #define DRM_FORMAT_YUV420 fourcc_code('Y', 'U', '1', '2') /* 2x2 subsampled Cb (1) and Cr (2) planes */
354 #define DRM_FORMAT_YVU420 fourcc_code('Y', 'V', '1', '2') /* 2x2 subsampled Cr (1) and Cb (2) planes */
355 #define DRM_FORMAT_YUV422 fourcc_code('Y', 'U', '1', '6') /* 2x1 subsampled Cb (1) and Cr (2) planes */
356 #define DRM_FORMAT_YVU422 fourcc_code('Y', 'V', '1', '6') /* 2x1 subsampled Cr (1) and Cb (2) planes */
357 #define DRM_FORMAT_YUV444 fourcc_code('Y', 'U', '2', '4') /* non-subsampled Cb (1) and Cr (2) planes */
358 #define DRM_FORMAT_YVU444 fourcc_code('Y', 'V', '2', '4') /* non-subsampled Cr (1) and Cb (2) planes */
359
360
361 /*
362 * Format Modifiers:
363 *
364 * Format modifiers describe, typically, a re-ordering or modification
365 * of the data in a plane of an FB. This can be used to express tiled/
366 * swizzled formats, or compression, or a combination of the two.
367 *
368 * The upper 8 bits of the format modifier are a vendor-id as assigned
369 * below. The lower 56 bits are assigned as vendor sees fit.
370 */
371
372 /* Vendor Ids: */
373 #define DRM_FORMAT_MOD_VENDOR_NONE 0
374 #define DRM_FORMAT_MOD_VENDOR_INTEL 0x01
375 #define DRM_FORMAT_MOD_VENDOR_AMD 0x02
376 #define DRM_FORMAT_MOD_VENDOR_NVIDIA 0x03
377 #define DRM_FORMAT_MOD_VENDOR_SAMSUNG 0x04
378 #define DRM_FORMAT_MOD_VENDOR_QCOM 0x05
379 #define DRM_FORMAT_MOD_VENDOR_VIVANTE 0x06
380 #define DRM_FORMAT_MOD_VENDOR_BROADCOM 0x07
381 #define DRM_FORMAT_MOD_VENDOR_ARM 0x08
382 #define DRM_FORMAT_MOD_VENDOR_ALLWINNER 0x09
383 #define DRM_FORMAT_MOD_VENDOR_AMLOGIC 0x0a
384
385 /* add more to the end as needed */
386
387 #define DRM_FORMAT_RESERVED ((1ULL << 56) - 1)
388
389 #define fourcc_mod_get_vendor(modifier) \
390 (((modifier) >> 56) & 0xff)
391
392 #define fourcc_mod_is_vendor(modifier, vendor) \
393 (fourcc_mod_get_vendor(modifier) == DRM_FORMAT_MOD_VENDOR_## vendor)
394
395 #define fourcc_mod_code(vendor, val) \
396 ((((__u64)DRM_FORMAT_MOD_VENDOR_## vendor) << 56) | ((val) & 0x00ffffffffffffffULL))
397
398 /*
399 * Format Modifier tokens:
400 *
401 * When adding a new token please document the layout with a code comment,
402 * similar to the fourcc codes above. drm_fourcc.h is considered the
403 * authoritative source for all of these.
404 *
405 * Generic modifier names:
406 *
407 * DRM_FORMAT_MOD_GENERIC_* definitions are used to provide vendor-neutral names
408 * for layouts which are common across multiple vendors. To preserve
409 * compatibility, in cases where a vendor-specific definition already exists and
410 * a generic name for it is desired, the common name is a purely symbolic alias
411 * and must use the same numerical value as the original definition.
412 *
413 * Note that generic names should only be used for modifiers which describe
414 * generic layouts (such as pixel re-ordering), which may have
415 * independently-developed support across multiple vendors.
416 *
417 * In future cases where a generic layout is identified before merging with a
418 * vendor-specific modifier, a new 'GENERIC' vendor or modifier using vendor
419 * 'NONE' could be considered. This should only be for obvious, exceptional
420 * cases to avoid polluting the 'GENERIC' namespace with modifiers which only
421 * apply to a single vendor.
422 *
423 * Generic names should not be used for cases where multiple hardware vendors
424 * have implementations of the same standardised compression scheme (such as
425 * AFBC). In those cases, all implementations should use the same format
426 * modifier(s), reflecting the vendor of the standard.
427 */
428
429 #define DRM_FORMAT_MOD_GENERIC_16_16_TILE DRM_FORMAT_MOD_SAMSUNG_16_16_TILE
430
431 /*
432 * Invalid Modifier
433 *
434 * This modifier can be used as a sentinel to terminate the format modifiers
435 * list, or to initialize a variable with an invalid modifier. It might also be
436 * used to report an error back to userspace for certain APIs.
437 */
438 #define DRM_FORMAT_MOD_INVALID fourcc_mod_code(NONE, DRM_FORMAT_RESERVED)
439
440 /*
441 * Linear Layout
442 *
443 * Just plain linear layout. Note that this is different from no specifying any
444 * modifier (e.g. not setting DRM_MODE_FB_MODIFIERS in the DRM_ADDFB2 ioctl),
445 * which tells the driver to also take driver-internal information into account
446 * and so might actually result in a tiled framebuffer.
447 */
448 #define DRM_FORMAT_MOD_LINEAR fourcc_mod_code(NONE, 0)
449
450 /*
451 * Deprecated: use DRM_FORMAT_MOD_LINEAR instead
452 *
453 * The "none" format modifier doesn't actually mean that the modifier is
454 * implicit, instead it means that the layout is linear. Whether modifiers are
455 * used is out-of-band information carried in an API-specific way (e.g. in a
456 * flag for drm_mode_fb_cmd2).
457 */
458 #define DRM_FORMAT_MOD_NONE 0
459
460 /* Intel framebuffer modifiers */
461
462 /*
463 * Intel X-tiling layout
464 *
465 * This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb)
466 * in row-major layout. Within the tile bytes are laid out row-major, with
467 * a platform-dependent stride. On top of that the memory can apply
468 * platform-depending swizzling of some higher address bits into bit6.
469 *
470 * Note that this layout is only accurate on intel gen 8+ or valleyview chipsets.
471 * On earlier platforms the is highly platforms specific and not useful for
472 * cross-driver sharing. It exists since on a given platform it does uniquely
473 * identify the layout in a simple way for i915-specific userspace, which
474 * facilitated conversion of userspace to modifiers. Additionally the exact
475 * format on some really old platforms is not known.
476 */
477 #define I915_FORMAT_MOD_X_TILED fourcc_mod_code(INTEL, 1)
478
479 /*
480 * Intel Y-tiling layout
481 *
482 * This is a tiled layout using 4Kb tiles (except on gen2 where the tiles 2Kb)
483 * in row-major layout. Within the tile bytes are laid out in OWORD (16 bytes)
484 * chunks column-major, with a platform-dependent height. On top of that the
485 * memory can apply platform-depending swizzling of some higher address bits
486 * into bit6.
487 *
488 * Note that this layout is only accurate on intel gen 8+ or valleyview chipsets.
489 * On earlier platforms the is highly platforms specific and not useful for
490 * cross-driver sharing. It exists since on a given platform it does uniquely
491 * identify the layout in a simple way for i915-specific userspace, which
492 * facilitated conversion of userspace to modifiers. Additionally the exact
493 * format on some really old platforms is not known.
494 */
495 #define I915_FORMAT_MOD_Y_TILED fourcc_mod_code(INTEL, 2)
496
497 /*
498 * Intel Yf-tiling layout
499 *
500 * This is a tiled layout using 4Kb tiles in row-major layout.
501 * Within the tile pixels are laid out in 16 256 byte units / sub-tiles which
502 * are arranged in four groups (two wide, two high) with column-major layout.
503 * Each group therefore consits out of four 256 byte units, which are also laid
504 * out as 2x2 column-major.
505 * 256 byte units are made out of four 64 byte blocks of pixels, producing
506 * either a square block or a 2:1 unit.
507 * 64 byte blocks of pixels contain four pixel rows of 16 bytes, where the width
508 * in pixel depends on the pixel depth.
509 */
510 #define I915_FORMAT_MOD_Yf_TILED fourcc_mod_code(INTEL, 3)
511
512 /*
513 * Intel color control surface (CCS) for render compression
514 *
515 * The framebuffer format must be one of the 8:8:8:8 RGB formats.
516 * The main surface will be plane index 0 and must be Y/Yf-tiled,
517 * the CCS will be plane index 1.
518 *
519 * Each CCS tile matches a 1024x512 pixel area of the main surface.
520 * To match certain aspects of the 3D hardware the CCS is
521 * considered to be made up of normal 128Bx32 Y tiles, Thus
522 * the CCS pitch must be specified in multiples of 128 bytes.
523 *
524 * In reality the CCS tile appears to be a 64Bx64 Y tile, composed
525 * of QWORD (8 bytes) chunks instead of OWORD (16 bytes) chunks.
526 * But that fact is not relevant unless the memory is accessed
527 * directly.
528 */
529 #define I915_FORMAT_MOD_Y_TILED_CCS fourcc_mod_code(INTEL, 4)
530 #define I915_FORMAT_MOD_Yf_TILED_CCS fourcc_mod_code(INTEL, 5)
531
532 /*
533 * Intel color control surfaces (CCS) for Gen-12 render compression.
534 *
535 * The main surface is Y-tiled and at plane index 0, the CCS is linear and
536 * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
537 * main surface. In other words, 4 bits in CCS map to a main surface cache
538 * line pair. The main surface pitch is required to be a multiple of four
539 * Y-tile widths.
540 */
541 #define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS fourcc_mod_code(INTEL, 6)
542
543 /*
544 * Intel color control surfaces (CCS) for Gen-12 media compression
545 *
546 * The main surface is Y-tiled and at plane index 0, the CCS is linear and
547 * at index 1. A 64B CCS cache line corresponds to an area of 4x1 tiles in
548 * main surface. In other words, 4 bits in CCS map to a main surface cache
549 * line pair. The main surface pitch is required to be a multiple of four
550 * Y-tile widths. For semi-planar formats like NV12, CCS planes follow the
551 * Y and UV planes i.e., planes 0 and 1 are used for Y and UV surfaces,
552 * planes 2 and 3 for the respective CCS.
553 */
554 #define I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS fourcc_mod_code(INTEL, 7)
555
556 /*
557 * Intel Color Control Surface with Clear Color (CCS) for Gen-12 render
558 * compression.
559 *
560 * The main surface is Y-tiled and is at plane index 0 whereas CCS is linear
561 * and at index 1. The clear color is stored at index 2, and the pitch should
562 * be ignored. The clear color structure is 256 bits. The first 128 bits
563 * represents Raw Clear Color Red, Green, Blue and Alpha color each represented
564 * by 32 bits. The raw clear color is consumed by the 3d engine and generates
565 * the converted clear color of size 64 bits. The first 32 bits store the Lower
566 * Converted Clear Color value and the next 32 bits store the Higher Converted
567 * Clear Color value when applicable. The Converted Clear Color values are
568 * consumed by the DE. The last 64 bits are used to store Color Discard Enable
569 * and Depth Clear Value Valid which are ignored by the DE. A CCS cache line
570 * corresponds to an area of 4x1 tiles in the main surface. The main surface
571 * pitch is required to be a multiple of 4 tile widths.
572 */
573 #define I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC fourcc_mod_code(INTEL, 8)
574
575 /*
576 * Intel Tile 4 layout
577 *
578 * This is a tiled layout using 4KB tiles in a row-major layout. It has the same
579 * shape as Tile Y at two granularities: 4KB (128B x 32) and 64B (16B x 4). It
580 * only differs from Tile Y at the 256B granularity in between. At this
581 * granularity, Tile Y has a shape of 16B x 32 rows, but this tiling has a shape
582 * of 64B x 8 rows.
583 */
584 #define I915_FORMAT_MOD_4_TILED fourcc_mod_code(INTEL, 9)
585
586 /*
587 * Intel color control surfaces (CCS) for DG2 render compression.
588 *
589 * The main surface is Tile 4 and at plane index 0. The CCS data is stored
590 * outside of the GEM object in a reserved memory area dedicated for the
591 * storage of the CCS data for all RC/RC_CC/MC compressible GEM objects. The
592 * main surface pitch is required to be a multiple of four Tile 4 widths.
593 */
594 #define I915_FORMAT_MOD_4_TILED_DG2_RC_CCS fourcc_mod_code(INTEL, 10)
595
596 /*
597 * Intel color control surfaces (CCS) for DG2 media compression.
598 *
599 * The main surface is Tile 4 and at plane index 0. For semi-planar formats
600 * like NV12, the Y and UV planes are Tile 4 and are located at plane indices
601 * 0 and 1, respectively. The CCS for all planes are stored outside of the
602 * GEM object in a reserved memory area dedicated for the storage of the
603 * CCS data for all RC/RC_CC/MC compressible GEM objects. The main surface
604 * pitch is required to be a multiple of four Tile 4 widths.
605 */
606 #define I915_FORMAT_MOD_4_TILED_DG2_MC_CCS fourcc_mod_code(INTEL, 11)
607
608 /*
609 * Intel Color Control Surface with Clear Color (CCS) for DG2 render compression.
610 *
611 * The main surface is Tile 4 and at plane index 0. The CCS data is stored
612 * outside of the GEM object in a reserved memory area dedicated for the
613 * storage of the CCS data for all RC/RC_CC/MC compressible GEM objects. The
614 * main surface pitch is required to be a multiple of four Tile 4 widths. The
615 * clear color is stored at plane index 1 and the pitch should be ignored. The
616 * format of the 256 bits of clear color data matches the one used for the
617 * I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC modifier, see its description
618 * for details.
619 */
620 #define I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC fourcc_mod_code(INTEL, 12)
621
622 /*
623 * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
624 *
625 * Macroblocks are laid in a Z-shape, and each pixel data is following the
626 * standard NV12 style.
627 * As for NV12, an image is the result of two frame buffers: one for Y,
628 * one for the interleaved Cb/Cr components (1/2 the height of the Y buffer).
629 * Alignment requirements are (for each buffer):
630 * - multiple of 128 pixels for the width
631 * - multiple of 32 pixels for the height
632 *
633 * For more information: see https://linuxtv.org/downloads/v4l-dvb-apis/re32.html
634 */
635 #define DRM_FORMAT_MOD_SAMSUNG_64_32_TILE fourcc_mod_code(SAMSUNG, 1)
636
637 /*
638 * Tiled, 16 (pixels) x 16 (lines) - sized macroblocks
639 *
640 * This is a simple tiled layout using tiles of 16x16 pixels in a row-major
641 * layout. For YCbCr formats Cb/Cr components are taken in such a way that
642 * they correspond to their 16x16 luma block.
643 */
644 #define DRM_FORMAT_MOD_SAMSUNG_16_16_TILE fourcc_mod_code(SAMSUNG, 2)
645
646 /*
647 * Qualcomm Compressed Format
648 *
649 * Refers to a compressed variant of the base format that is compressed.
650 * Implementation may be platform and base-format specific.
651 *
652 * Each macrotile consists of m x n (mostly 4 x 4) tiles.
653 * Pixel data pitch/stride is aligned with macrotile width.
654 * Pixel data height is aligned with macrotile height.
655 * Entire pixel data buffer is aligned with 4k(bytes).
656 */
657 #define DRM_FORMAT_MOD_QCOM_COMPRESSED fourcc_mod_code(QCOM, 1)
658
659 /*
660 * Qualcomm Tiled Format
661 *
662 * Similar to DRM_FORMAT_MOD_QCOM_COMPRESSED but not compressed.
663 * Implementation may be platform and base-format specific.
664 *
665 * Each macrotile consists of m x n (mostly 4 x 4) tiles.
666 * Pixel data pitch/stride is aligned with macrotile width.
667 * Pixel data height is aligned with macrotile height.
668 * Entire pixel data buffer is aligned with 4k(bytes).
669 */
670 #define DRM_FORMAT_MOD_QCOM_TILED3 fourcc_mod_code(QCOM, 3)
671
672 /*
673 * Qualcomm Alternate Tiled Format
674 *
675 * Alternate tiled format typically only used within GMEM.
676 * Implementation may be platform and base-format specific.
677 */
678 #define DRM_FORMAT_MOD_QCOM_TILED2 fourcc_mod_code(QCOM, 2)
679
680
681 /* Vivante framebuffer modifiers */
682
683 /*
684 * Vivante 4x4 tiling layout
685 *
686 * This is a simple tiled layout using tiles of 4x4 pixels in a row-major
687 * layout.
688 */
689 #define DRM_FORMAT_MOD_VIVANTE_TILED fourcc_mod_code(VIVANTE, 1)
690
691 /*
692 * Vivante 64x64 super-tiling layout
693 *
694 * This is a tiled layout using 64x64 pixel super-tiles, where each super-tile
695 * contains 8x4 groups of 2x4 tiles of 4x4 pixels (like above) each, all in row-
696 * major layout.
697 *
698 * For more information: see
699 * https://github.com/etnaviv/etna_viv/blob/master/doc/hardware.md#texture-tiling
700 */
701 #define DRM_FORMAT_MOD_VIVANTE_SUPER_TILED fourcc_mod_code(VIVANTE, 2)
702
703 /*
704 * Vivante 4x4 tiling layout for dual-pipe
705 *
706 * Same as the 4x4 tiling layout, except every second 4x4 pixel tile starts at a
707 * different base address. Offsets from the base addresses are therefore halved
708 * compared to the non-split tiled layout.
709 */
710 #define DRM_FORMAT_MOD_VIVANTE_SPLIT_TILED fourcc_mod_code(VIVANTE, 3)
711
712 /*
713 * Vivante 64x64 super-tiling layout for dual-pipe
714 *
715 * Same as the 64x64 super-tiling layout, except every second 4x4 pixel tile
716 * starts at a different base address. Offsets from the base addresses are
717 * therefore halved compared to the non-split super-tiled layout.
718 */
719 #define DRM_FORMAT_MOD_VIVANTE_SPLIT_SUPER_TILED fourcc_mod_code(VIVANTE, 4)
720
721 /* NVIDIA frame buffer modifiers */
722
723 /*
724 * Tegra Tiled Layout, used by Tegra 2, 3 and 4.
725 *
726 * Pixels are arranged in simple tiles of 16 x 16 bytes.
727 */
728 #define DRM_FORMAT_MOD_NVIDIA_TEGRA_TILED fourcc_mod_code(NVIDIA, 1)
729
730 /*
731 * Generalized Block Linear layout, used by desktop GPUs starting with NV50/G80,
732 * and Tegra GPUs starting with Tegra K1.
733 *
734 * Pixels are arranged in Groups of Bytes (GOBs). GOB size and layout varies
735 * based on the architecture generation. GOBs themselves are then arranged in
736 * 3D blocks, with the block dimensions (in terms of GOBs) always being a power
737 * of two, and hence expressible as their log2 equivalent (E.g., "2" represents
738 * a block depth or height of "4").
739 *
740 * Chapter 20 "Pixel Memory Formats" of the Tegra X1 TRM describes this format
741 * in full detail.
742 *
743 * Macro
744 * Bits Param Description
745 * ---- ----- -----------------------------------------------------------------
746 *
747 * 3:0 h log2(height) of each block, in GOBs. Placed here for
748 * compatibility with the existing
749 * DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK()-based modifiers.
750 *
751 * 4:4 - Must be 1, to indicate block-linear layout. Necessary for
752 * compatibility with the existing
753 * DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK()-based modifiers.
754 *
755 * 8:5 - Reserved (To support 3D-surfaces with variable log2(depth) block
756 * size). Must be zero.
757 *
758 * Note there is no log2(width) parameter. Some portions of the
759 * hardware support a block width of two gobs, but it is impractical
760 * to use due to lack of support elsewhere, and has no known
761 * benefits.
762 *
763 * 11:9 - Reserved (To support 2D-array textures with variable array stride
764 * in blocks, specified via log2(tile width in blocks)). Must be
765 * zero.
766 *
767 * 19:12 k Page Kind. This value directly maps to a field in the page
768 * tables of all GPUs >= NV50. It affects the exact layout of bits
769 * in memory and can be derived from the tuple
770 *
771 * (format, GPU model, compression type, samples per pixel)
772 *
773 * Where compression type is defined below. If GPU model were
774 * implied by the format modifier, format, or memory buffer, page
775 * kind would not need to be included in the modifier itself, but
776 * since the modifier should define the layout of the associated
777 * memory buffer independent from any device or other context, it
778 * must be included here.
779 *
780 * 21:20 g GOB Height and Page Kind Generation. The height of a GOB changed
781 * starting with Fermi GPUs. Additionally, the mapping between page
782 * kind and bit layout has changed at various points.
783 *
784 * 0 = Gob Height 8, Fermi - Volta, Tegra K1+ Page Kind mapping
785 * 1 = Gob Height 4, G80 - GT2XX Page Kind mapping
786 * 2 = Gob Height 8, Turing+ Page Kind mapping
787 * 3 = Reserved for future use.
788 *
789 * 22:22 s Sector layout. On Tegra GPUs prior to Xavier, there is a further
790 * bit remapping step that occurs at an even lower level than the
791 * page kind and block linear swizzles. This causes the layout of
792 * surfaces mapped in those SOC's GPUs to be incompatible with the
793 * equivalent mapping on other GPUs in the same system.
794 *
795 * 0 = Tegra K1 - Tegra Parker/TX2 Layout.
796 * 1 = Desktop GPU and Tegra Xavier+ Layout
797 *
798 * 25:23 c Lossless Framebuffer Compression type.
799 *
800 * 0 = none
801 * 1 = ROP/3D, layout 1, exact compression format implied by Page
802 * Kind field
803 * 2 = ROP/3D, layout 2, exact compression format implied by Page
804 * Kind field
805 * 3 = CDE horizontal
806 * 4 = CDE vertical
807 * 5 = Reserved for future use
808 * 6 = Reserved for future use
809 * 7 = Reserved for future use
810 *
811 * 55:25 - Reserved for future use. Must be zero.
812 */
813 #define DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(c, s, g, k, h) \
814 fourcc_mod_code(NVIDIA, (0x10 | \
815 ((h) & 0xf) | \
816 (((k) & 0xff) << 12) | \
817 (((g) & 0x3) << 20) | \
818 (((s) & 0x1) << 22) | \
819 (((c) & 0x7) << 23)))
820
821 /* To grandfather in prior block linear format modifiers to the above layout,
822 * the page kind "0", which corresponds to "pitch/linear" and hence is unusable
823 * with block-linear layouts, is remapped within drivers to the value 0xfe,
824 * which corresponds to the "generic" kind used for simple single-sample
825 * uncompressed color formats on Fermi - Volta GPUs.
826 */
827 static inline __u64
drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier)828 drm_fourcc_canonicalize_nvidia_format_mod(__u64 modifier)
829 {
830 if (!(modifier & 0x10) || (modifier & (0xff << 12)))
831 return modifier;
832 else
833 return modifier | (0xfe << 12);
834 }
835
836 /*
837 * 16Bx2 Block Linear layout, used by Tegra K1 and later
838 *
839 * Pixels are arranged in 64x8 Groups Of Bytes (GOBs). GOBs are then stacked
840 * vertically by a power of 2 (1 to 32 GOBs) to form a block.
841 *
842 * Within a GOB, data is ordered as 16B x 2 lines sectors laid in Z-shape.
843 *
844 * Parameter 'v' is the log2 encoding of the number of GOBs stacked vertically.
845 * Valid values are:
846 *
847 * 0 == ONE_GOB
848 * 1 == TWO_GOBS
849 * 2 == FOUR_GOBS
850 * 3 == EIGHT_GOBS
851 * 4 == SIXTEEN_GOBS
852 * 5 == THIRTYTWO_GOBS
853 *
854 * Chapter 20 "Pixel Memory Formats" of the Tegra X1 TRM describes this format
855 * in full detail.
856 */
857 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(v) \
858 DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D(0, 0, 0, 0, (v))
859
860 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_ONE_GOB \
861 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(0)
862 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_TWO_GOB \
863 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(1)
864 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_FOUR_GOB \
865 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(2)
866 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_EIGHT_GOB \
867 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(3)
868 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_SIXTEEN_GOB \
869 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(4)
870 #define DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK_THIRTYTWO_GOB \
871 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(5)
872
873 /*
874 * Some Broadcom modifiers take parameters, for example the number of
875 * vertical lines in the image. Reserve the lower 32 bits for modifier
876 * type, and the next 24 bits for parameters. Top 8 bits are the
877 * vendor code.
878 */
879 #define __fourcc_mod_broadcom_param_shift 8
880 #define __fourcc_mod_broadcom_param_bits 48
881 #define fourcc_mod_broadcom_code(val, params) \
882 fourcc_mod_code(BROADCOM, ((((__u64)params) << __fourcc_mod_broadcom_param_shift) | val))
883 #define fourcc_mod_broadcom_param(m) \
884 ((int)(((m) >> __fourcc_mod_broadcom_param_shift) & \
885 ((1ULL << __fourcc_mod_broadcom_param_bits) - 1)))
886 #define fourcc_mod_broadcom_mod(m) \
887 ((m) & ~(((1ULL << __fourcc_mod_broadcom_param_bits) - 1) << \
888 __fourcc_mod_broadcom_param_shift))
889
890 /*
891 * Broadcom VC4 "T" format
892 *
893 * This is the primary layout that the V3D GPU can texture from (it
894 * can't do linear). The T format has:
895 *
896 * - 64b utiles of pixels in a raster-order grid according to cpp. It's 4x4
897 * pixels at 32 bit depth.
898 *
899 * - 1k subtiles made of a 4x4 raster-order grid of 64b utiles (so usually
900 * 16x16 pixels).
901 *
902 * - 4k tiles made of a 2x2 grid of 1k subtiles (so usually 32x32 pixels). On
903 * even 4k tile rows, they're arranged as (BL, TL, TR, BR), and on odd rows
904 * they're (TR, BR, BL, TL), where bottom left is start of memory.
905 *
906 * - an image made of 4k tiles in rows either left-to-right (even rows of 4k
907 * tiles) or right-to-left (odd rows of 4k tiles).
908 */
909 #define DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED fourcc_mod_code(BROADCOM, 1)
910
911 /*
912 * Broadcom SAND format
913 *
914 * This is the native format that the H.264 codec block uses. For VC4
915 * HVS, it is only valid for H.264 (NV12/21) and RGBA modes.
916 *
917 * The image can be considered to be split into columns, and the
918 * columns are placed consecutively into memory. The width of those
919 * columns can be either 32, 64, 128, or 256 pixels, but in practice
920 * only 128 pixel columns are used.
921 *
922 * The pitch between the start of each column is set to optimally
923 * switch between SDRAM banks. This is passed as the number of lines
924 * of column width in the modifier (we can't use the stride value due
925 * to various core checks that look at it , so you should set the
926 * stride to width*cpp).
927 *
928 * Note that the column height for this format modifier is the same
929 * for all of the planes, assuming that each column contains both Y
930 * and UV. Some SAND-using hardware stores UV in a separate tiled
931 * image from Y to reduce the column height, which is not supported
932 * with these modifiers.
933 *
934 * The DRM_FORMAT_MOD_BROADCOM_SAND128_COL_HEIGHT modifier is also
935 * supported for DRM_FORMAT_P030 where the columns remain as 128 bytes
936 * wide, but as this is a 10 bpp format that translates to 96 pixels.
937 */
938
939 #define DRM_FORMAT_MOD_BROADCOM_SAND32_COL_HEIGHT(v) \
940 fourcc_mod_broadcom_code(2, v)
941 #define DRM_FORMAT_MOD_BROADCOM_SAND64_COL_HEIGHT(v) \
942 fourcc_mod_broadcom_code(3, v)
943 #define DRM_FORMAT_MOD_BROADCOM_SAND128_COL_HEIGHT(v) \
944 fourcc_mod_broadcom_code(4, v)
945 #define DRM_FORMAT_MOD_BROADCOM_SAND256_COL_HEIGHT(v) \
946 fourcc_mod_broadcom_code(5, v)
947
948 #define DRM_FORMAT_MOD_BROADCOM_SAND32 \
949 DRM_FORMAT_MOD_BROADCOM_SAND32_COL_HEIGHT(0)
950 #define DRM_FORMAT_MOD_BROADCOM_SAND64 \
951 DRM_FORMAT_MOD_BROADCOM_SAND64_COL_HEIGHT(0)
952 #define DRM_FORMAT_MOD_BROADCOM_SAND128 \
953 DRM_FORMAT_MOD_BROADCOM_SAND128_COL_HEIGHT(0)
954 #define DRM_FORMAT_MOD_BROADCOM_SAND256 \
955 DRM_FORMAT_MOD_BROADCOM_SAND256_COL_HEIGHT(0)
956
957 /* Broadcom UIF format
958 *
959 * This is the common format for the current Broadcom multimedia
960 * blocks, including V3D 3.x and newer, newer video codecs, and
961 * displays.
962 *
963 * The image consists of utiles (64b blocks), UIF blocks (2x2 utiles),
964 * and macroblocks (4x4 UIF blocks). Those 4x4 UIF block groups are
965 * stored in columns, with padding between the columns to ensure that
966 * moving from one column to the next doesn't hit the same SDRAM page
967 * bank.
968 *
969 * To calculate the padding, it is assumed that each hardware block
970 * and the software driving it knows the platform's SDRAM page size,
971 * number of banks, and XOR address, and that it's identical between
972 * all blocks using the format. This tiling modifier will use XOR as
973 * necessary to reduce the padding. If a hardware block can't do XOR,
974 * the assumption is that a no-XOR tiling modifier will be created.
975 */
976 #define DRM_FORMAT_MOD_BROADCOM_UIF fourcc_mod_code(BROADCOM, 6)
977
978 /*
979 * Arm Framebuffer Compression (AFBC) modifiers
980 *
981 * AFBC is a proprietary lossless image compression protocol and format.
982 * It provides fine-grained random access and minimizes the amount of data
983 * transferred between IP blocks.
984 *
985 * AFBC has several features which may be supported and/or used, which are
986 * represented using bits in the modifier. Not all combinations are valid,
987 * and different devices or use-cases may support different combinations.
988 *
989 * Further information on the use of AFBC modifiers can be found in
990 * Documentation/gpu/afbc.rst
991 */
992
993 /*
994 * The top 4 bits (out of the 56 bits alloted for specifying vendor specific
995 * modifiers) denote the category for modifiers. Currently we have three
996 * categories of modifiers ie AFBC, MISC and AFRC. We can have a maximum of
997 * sixteen different categories.
998 */
999 #define DRM_FORMAT_MOD_ARM_CODE(__type, __val) \
1000 fourcc_mod_code(ARM, ((__u64)(__type) << 52) | ((__val) & 0x000fffffffffffffULL))
1001
1002 #define DRM_FORMAT_MOD_ARM_TYPE_AFBC 0x00
1003 #define DRM_FORMAT_MOD_ARM_TYPE_MISC 0x01
1004
1005 #define DRM_FORMAT_MOD_ARM_AFBC(__afbc_mode) \
1006 DRM_FORMAT_MOD_ARM_CODE(DRM_FORMAT_MOD_ARM_TYPE_AFBC, __afbc_mode)
1007
1008 /*
1009 * AFBC superblock size
1010 *
1011 * Indicates the superblock size(s) used for the AFBC buffer. The buffer
1012 * size (in pixels) must be aligned to a multiple of the superblock size.
1013 * Four lowest significant bits(LSBs) are reserved for block size.
1014 *
1015 * Where one superblock size is specified, it applies to all planes of the
1016 * buffer (e.g. 16x16, 32x8). When multiple superblock sizes are specified,
1017 * the first applies to the Luma plane and the second applies to the Chroma
1018 * plane(s). e.g. (32x8_64x4 means 32x8 Luma, with 64x4 Chroma).
1019 * Multiple superblock sizes are only valid for multi-plane YCbCr formats.
1020 */
1021 #define AFBC_FORMAT_MOD_BLOCK_SIZE_MASK 0xf
1022 #define AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 (1ULL)
1023 #define AFBC_FORMAT_MOD_BLOCK_SIZE_32x8 (2ULL)
1024 #define AFBC_FORMAT_MOD_BLOCK_SIZE_64x4 (3ULL)
1025 #define AFBC_FORMAT_MOD_BLOCK_SIZE_32x8_64x4 (4ULL)
1026
1027 /*
1028 * AFBC lossless colorspace transform
1029 *
1030 * Indicates that the buffer makes use of the AFBC lossless colorspace
1031 * transform.
1032 */
1033 #define AFBC_FORMAT_MOD_YTR (1ULL << 4)
1034
1035 /*
1036 * AFBC block-split
1037 *
1038 * Indicates that the payload of each superblock is split. The second
1039 * half of the payload is positioned at a predefined offset from the start
1040 * of the superblock payload.
1041 */
1042 #define AFBC_FORMAT_MOD_SPLIT (1ULL << 5)
1043
1044 /*
1045 * AFBC sparse layout
1046 *
1047 * This flag indicates that the payload of each superblock must be stored at a
1048 * predefined position relative to the other superblocks in the same AFBC
1049 * buffer. This order is the same order used by the header buffer. In this mode
1050 * each superblock is given the same amount of space as an uncompressed
1051 * superblock of the particular format would require, rounding up to the next
1052 * multiple of 128 bytes in size.
1053 */
1054 #define AFBC_FORMAT_MOD_SPARSE (1ULL << 6)
1055
1056 /*
1057 * AFBC copy-block restrict
1058 *
1059 * Buffers with this flag must obey the copy-block restriction. The restriction
1060 * is such that there are no copy-blocks referring across the border of 8x8
1061 * blocks. For the subsampled data the 8x8 limitation is also subsampled.
1062 */
1063 #define AFBC_FORMAT_MOD_CBR (1ULL << 7)
1064
1065 /*
1066 * AFBC tiled layout
1067 *
1068 * The tiled layout groups superblocks in 8x8 or 4x4 tiles, where all
1069 * superblocks inside a tile are stored together in memory. 8x8 tiles are used
1070 * for pixel formats up to and including 32 bpp while 4x4 tiles are used for
1071 * larger bpp formats. The order between the tiles is scan line.
1072 * When the tiled layout is used, the buffer size (in pixels) must be aligned
1073 * to the tile size.
1074 */
1075 #define AFBC_FORMAT_MOD_TILED (1ULL << 8)
1076
1077 /*
1078 * AFBC solid color blocks
1079 *
1080 * Indicates that the buffer makes use of solid-color blocks, whereby bandwidth
1081 * can be reduced if a whole superblock is a single color.
1082 */
1083 #define AFBC_FORMAT_MOD_SC (1ULL << 9)
1084
1085 /*
1086 * AFBC double-buffer
1087 *
1088 * Indicates that the buffer is allocated in a layout safe for front-buffer
1089 * rendering.
1090 */
1091 #define AFBC_FORMAT_MOD_DB (1ULL << 10)
1092
1093 /*
1094 * AFBC buffer content hints
1095 *
1096 * Indicates that the buffer includes per-superblock content hints.
1097 */
1098 #define AFBC_FORMAT_MOD_BCH (1ULL << 11)
1099
1100 /* AFBC uncompressed storage mode
1101 *
1102 * Indicates that the buffer is using AFBC uncompressed storage mode.
1103 * In this mode all superblock payloads in the buffer use the uncompressed
1104 * storage mode, which is usually only used for data which cannot be compressed.
1105 * The buffer layout is the same as for AFBC buffers without USM set, this only
1106 * affects the storage mode of the individual superblocks. Note that even a
1107 * buffer without USM set may use uncompressed storage mode for some or all
1108 * superblocks, USM just guarantees it for all.
1109 */
1110 #define AFBC_FORMAT_MOD_USM (1ULL << 12)
1111
1112 /*
1113 * Arm Fixed-Rate Compression (AFRC) modifiers
1114 *
1115 * AFRC is a proprietary fixed rate image compression protocol and format,
1116 * designed to provide guaranteed bandwidth and memory footprint
1117 * reductions in graphics and media use-cases.
1118 *
1119 * AFRC buffers consist of one or more planes, with the same components
1120 * and meaning as an uncompressed buffer using the same pixel format.
1121 *
1122 * Within each plane, the pixel/luma/chroma values are grouped into
1123 * "coding unit" blocks which are individually compressed to a
1124 * fixed size (in bytes). All coding units within a given plane of a buffer
1125 * store the same number of values, and have the same compressed size.
1126 *
1127 * The coding unit size is configurable, allowing different rates of compression.
1128 *
1129 * The start of each AFRC buffer plane must be aligned to an alignment granule which
1130 * depends on the coding unit size.
1131 *
1132 * Coding Unit Size Plane Alignment
1133 * ---------------- ---------------
1134 * 16 bytes 1024 bytes
1135 * 24 bytes 512 bytes
1136 * 32 bytes 2048 bytes
1137 *
1138 * Coding units are grouped into paging tiles. AFRC buffer dimensions must be aligned
1139 * to a multiple of the paging tile dimensions.
1140 * The dimensions of each paging tile depend on whether the buffer is optimised for
1141 * scanline (SCAN layout) or rotated (ROT layout) access.
1142 *
1143 * Layout Paging Tile Width Paging Tile Height
1144 * ------ ----------------- ------------------
1145 * SCAN 16 coding units 4 coding units
1146 * ROT 8 coding units 8 coding units
1147 *
1148 * The dimensions of each coding unit depend on the number of components
1149 * in the compressed plane and whether the buffer is optimised for
1150 * scanline (SCAN layout) or rotated (ROT layout) access.
1151 *
1152 * Number of Components in Plane Layout Coding Unit Width Coding Unit Height
1153 * ----------------------------- --------- ----------------- ------------------
1154 * 1 SCAN 16 samples 4 samples
1155 * Example: 16x4 luma samples in a 'Y' plane
1156 * 16x4 chroma 'V' values, in the 'V' plane of a fully-planar YUV buffer
1157 * ----------------------------- --------- ----------------- ------------------
1158 * 1 ROT 8 samples 8 samples
1159 * Example: 8x8 luma samples in a 'Y' plane
1160 * 8x8 chroma 'V' values, in the 'V' plane of a fully-planar YUV buffer
1161 * ----------------------------- --------- ----------------- ------------------
1162 * 2 DONT CARE 8 samples 4 samples
1163 * Example: 8x4 chroma pairs in the 'UV' plane of a semi-planar YUV buffer
1164 * ----------------------------- --------- ----------------- ------------------
1165 * 3 DONT CARE 4 samples 4 samples
1166 * Example: 4x4 pixels in an RGB buffer without alpha
1167 * ----------------------------- --------- ----------------- ------------------
1168 * 4 DONT CARE 4 samples 4 samples
1169 * Example: 4x4 pixels in an RGB buffer with alpha
1170 */
1171
1172 #define DRM_FORMAT_MOD_ARM_TYPE_AFRC 0x02
1173
1174 #define DRM_FORMAT_MOD_ARM_AFRC(__afrc_mode) \
1175 DRM_FORMAT_MOD_ARM_CODE(DRM_FORMAT_MOD_ARM_TYPE_AFRC, __afrc_mode)
1176
1177 /*
1178 * AFRC coding unit size modifier.
1179 *
1180 * Indicates the number of bytes used to store each compressed coding unit for
1181 * one or more planes in an AFRC encoded buffer. The coding unit size for chrominance
1182 * is the same for both Cb and Cr, which may be stored in separate planes.
1183 *
1184 * AFRC_FORMAT_MOD_CU_SIZE_P0 indicates the number of bytes used to store
1185 * each compressed coding unit in the first plane of the buffer. For RGBA buffers
1186 * this is the only plane, while for semi-planar and fully-planar YUV buffers,
1187 * this corresponds to the luma plane.
1188 *
1189 * AFRC_FORMAT_MOD_CU_SIZE_P12 indicates the number of bytes used to store
1190 * each compressed coding unit in the second and third planes in the buffer.
1191 * For semi-planar and fully-planar YUV buffers, this corresponds to the chroma plane(s).
1192 *
1193 * For single-plane buffers, AFRC_FORMAT_MOD_CU_SIZE_P0 must be specified
1194 * and AFRC_FORMAT_MOD_CU_SIZE_P12 must be zero.
1195 * For semi-planar and fully-planar buffers, both AFRC_FORMAT_MOD_CU_SIZE_P0 and
1196 * AFRC_FORMAT_MOD_CU_SIZE_P12 must be specified.
1197 */
1198 #define AFRC_FORMAT_MOD_CU_SIZE_MASK 0xf
1199 #define AFRC_FORMAT_MOD_CU_SIZE_16 (1ULL)
1200 #define AFRC_FORMAT_MOD_CU_SIZE_24 (2ULL)
1201 #define AFRC_FORMAT_MOD_CU_SIZE_32 (3ULL)
1202
1203 #define AFRC_FORMAT_MOD_CU_SIZE_P0(__afrc_cu_size) (__afrc_cu_size)
1204 #define AFRC_FORMAT_MOD_CU_SIZE_P12(__afrc_cu_size) ((__afrc_cu_size) << 4)
1205
1206 /*
1207 * AFRC scanline memory layout.
1208 *
1209 * Indicates if the buffer uses the scanline-optimised layout
1210 * for an AFRC encoded buffer, otherwise, it uses the rotation-optimised layout.
1211 * The memory layout is the same for all planes.
1212 */
1213 #define AFRC_FORMAT_MOD_LAYOUT_SCAN (1ULL << 8)
1214
1215 /*
1216 * Arm 16x16 Block U-Interleaved modifier
1217 *
1218 * This is used by Arm Mali Utgard and Midgard GPUs. It divides the image
1219 * into 16x16 pixel blocks. Blocks are stored linearly in order, but pixels
1220 * in the block are reordered.
1221 */
1222 #define DRM_FORMAT_MOD_ARM_16X16_BLOCK_U_INTERLEAVED \
1223 DRM_FORMAT_MOD_ARM_CODE(DRM_FORMAT_MOD_ARM_TYPE_MISC, 1ULL)
1224
1225 /*
1226 * Allwinner tiled modifier
1227 *
1228 * This tiling mode is implemented by the VPU found on all Allwinner platforms,
1229 * codenamed sunxi. It is associated with a YUV format that uses either 2 or 3
1230 * planes.
1231 *
1232 * With this tiling, the luminance samples are disposed in tiles representing
1233 * 32x32 pixels and the chrominance samples in tiles representing 32x64 pixels.
1234 * The pixel order in each tile is linear and the tiles are disposed linearly,
1235 * both in row-major order.
1236 */
1237 #define DRM_FORMAT_MOD_ALLWINNER_TILED fourcc_mod_code(ALLWINNER, 1)
1238
1239 /*
1240 * Amlogic Video Framebuffer Compression modifiers
1241 *
1242 * Amlogic uses a proprietary lossless image compression protocol and format
1243 * for their hardware video codec accelerators, either video decoders or
1244 * video input encoders.
1245 *
1246 * It considerably reduces memory bandwidth while writing and reading
1247 * frames in memory.
1248 *
1249 * The underlying storage is considered to be 3 components, 8bit or 10-bit
1250 * per component YCbCr 420, single plane :
1251 * - DRM_FORMAT_YUV420_8BIT
1252 * - DRM_FORMAT_YUV420_10BIT
1253 *
1254 * The first 8 bits of the mode defines the layout, then the following 8 bits
1255 * defines the options changing the layout.
1256 *
1257 * Not all combinations are valid, and different SoCs may support different
1258 * combinations of layout and options.
1259 */
1260 #define __fourcc_mod_amlogic_layout_mask 0xff
1261 #define __fourcc_mod_amlogic_options_shift 8
1262 #define __fourcc_mod_amlogic_options_mask 0xff
1263
1264 #define DRM_FORMAT_MOD_AMLOGIC_FBC(__layout, __options) \
1265 fourcc_mod_code(AMLOGIC, \
1266 ((__layout) & __fourcc_mod_amlogic_layout_mask) | \
1267 (((__options) & __fourcc_mod_amlogic_options_mask) \
1268 << __fourcc_mod_amlogic_options_shift))
1269
1270 /* Amlogic FBC Layouts */
1271
1272 /*
1273 * Amlogic FBC Basic Layout
1274 *
1275 * The basic layout is composed of:
1276 * - a body content organized in 64x32 superblocks with 4096 bytes per
1277 * superblock in default mode.
1278 * - a 32 bytes per 128x64 header block
1279 *
1280 * This layout is transferrable between Amlogic SoCs supporting this modifier.
1281 */
1282 #define AMLOGIC_FBC_LAYOUT_BASIC (1ULL)
1283
1284 /*
1285 * Amlogic FBC Scatter Memory layout
1286 *
1287 * Indicates the header contains IOMMU references to the compressed
1288 * frames content to optimize memory access and layout.
1289 *
1290 * In this mode, only the header memory address is needed, thus the
1291 * content memory organization is tied to the current producer
1292 * execution and cannot be saved/dumped neither transferrable between
1293 * Amlogic SoCs supporting this modifier.
1294 *
1295 * Due to the nature of the layout, these buffers are not expected to
1296 * be accessible by the user-space clients, but only accessible by the
1297 * hardware producers and consumers.
1298 *
1299 * The user-space clients should expect a failure while trying to mmap
1300 * the DMA-BUF handle returned by the producer.
1301 */
1302 #define AMLOGIC_FBC_LAYOUT_SCATTER (2ULL)
1303
1304 /* Amlogic FBC Layout Options Bit Mask */
1305
1306 /*
1307 * Amlogic FBC Memory Saving mode
1308 *
1309 * Indicates the storage is packed when pixel size is multiple of word
1310 * boudaries, i.e. 8bit should be stored in this mode to save allocation
1311 * memory.
1312 *
1313 * This mode reduces body layout to 3072 bytes per 64x32 superblock with
1314 * the basic layout and 3200 bytes per 64x32 superblock combined with
1315 * the scatter layout.
1316 */
1317 #define AMLOGIC_FBC_OPTION_MEM_SAVING (1ULL << 0)
1318
1319 /*
1320 * AMD modifiers
1321 *
1322 * Memory layout:
1323 *
1324 * without DCC:
1325 * - main surface
1326 *
1327 * with DCC & without DCC_RETILE:
1328 * - main surface in plane 0
1329 * - DCC surface in plane 1 (RB-aligned, pipe-aligned if DCC_PIPE_ALIGN is set)
1330 *
1331 * with DCC & DCC_RETILE:
1332 * - main surface in plane 0
1333 * - displayable DCC surface in plane 1 (not RB-aligned & not pipe-aligned)
1334 * - pipe-aligned DCC surface in plane 2 (RB-aligned & pipe-aligned)
1335 *
1336 * For multi-plane formats the above surfaces get merged into one plane for
1337 * each format plane, based on the required alignment only.
1338 *
1339 * Bits Parameter Notes
1340 * ----- ------------------------ ---------------------------------------------
1341 *
1342 * 7:0 TILE_VERSION Values are AMD_FMT_MOD_TILE_VER_*
1343 * 12:8 TILE Values are AMD_FMT_MOD_TILE_<version>_*
1344 * 13 DCC
1345 * 14 DCC_RETILE
1346 * 15 DCC_PIPE_ALIGN
1347 * 16 DCC_INDEPENDENT_64B
1348 * 17 DCC_INDEPENDENT_128B
1349 * 19:18 DCC_MAX_COMPRESSED_BLOCK Values are AMD_FMT_MOD_DCC_BLOCK_*
1350 * 20 DCC_CONSTANT_ENCODE
1351 * 23:21 PIPE_XOR_BITS Only for some chips
1352 * 26:24 BANK_XOR_BITS Only for some chips
1353 * 29:27 PACKERS Only for some chips
1354 * 32:30 RB Only for some chips
1355 * 35:33 PIPE Only for some chips
1356 * 55:36 - Reserved for future use, must be zero
1357 */
1358 #define AMD_FMT_MOD fourcc_mod_code(AMD, 0)
1359
1360 #define IS_AMD_FMT_MOD(val) (((val) >> 56) == DRM_FORMAT_MOD_VENDOR_AMD)
1361
1362 /* Reserve 0 for GFX8 and older */
1363 #define AMD_FMT_MOD_TILE_VER_GFX9 1
1364 #define AMD_FMT_MOD_TILE_VER_GFX10 2
1365 #define AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS 3
1366
1367 /*
1368 * 64K_S is the same for GFX9/GFX10/GFX10_RBPLUS and hence has GFX9 as canonical
1369 * version.
1370 */
1371 #define AMD_FMT_MOD_TILE_GFX9_64K_S 9
1372
1373 /*
1374 * 64K_D for non-32 bpp is the same for GFX9/GFX10/GFX10_RBPLUS and hence has
1375 * GFX9 as canonical version.
1376 */
1377 #define AMD_FMT_MOD_TILE_GFX9_64K_D 10
1378 #define AMD_FMT_MOD_TILE_GFX9_64K_S_X 25
1379 #define AMD_FMT_MOD_TILE_GFX9_64K_D_X 26
1380 #define AMD_FMT_MOD_TILE_GFX9_64K_R_X 27
1381
1382 #define AMD_FMT_MOD_DCC_BLOCK_64B 0
1383 #define AMD_FMT_MOD_DCC_BLOCK_128B 1
1384 #define AMD_FMT_MOD_DCC_BLOCK_256B 2
1385
1386 #define AMD_FMT_MOD_TILE_VERSION_SHIFT 0
1387 #define AMD_FMT_MOD_TILE_VERSION_MASK 0xFF
1388 #define AMD_FMT_MOD_TILE_SHIFT 8
1389 #define AMD_FMT_MOD_TILE_MASK 0x1F
1390
1391 /* Whether DCC compression is enabled. */
1392 #define AMD_FMT_MOD_DCC_SHIFT 13
1393 #define AMD_FMT_MOD_DCC_MASK 0x1
1394
1395 /*
1396 * Whether to include two DCC surfaces, one which is rb & pipe aligned, and
1397 * one which is not-aligned.
1398 */
1399 #define AMD_FMT_MOD_DCC_RETILE_SHIFT 14
1400 #define AMD_FMT_MOD_DCC_RETILE_MASK 0x1
1401
1402 /* Only set if DCC_RETILE = false */
1403 #define AMD_FMT_MOD_DCC_PIPE_ALIGN_SHIFT 15
1404 #define AMD_FMT_MOD_DCC_PIPE_ALIGN_MASK 0x1
1405
1406 #define AMD_FMT_MOD_DCC_INDEPENDENT_64B_SHIFT 16
1407 #define AMD_FMT_MOD_DCC_INDEPENDENT_64B_MASK 0x1
1408 #define AMD_FMT_MOD_DCC_INDEPENDENT_128B_SHIFT 17
1409 #define AMD_FMT_MOD_DCC_INDEPENDENT_128B_MASK 0x1
1410 #define AMD_FMT_MOD_DCC_MAX_COMPRESSED_BLOCK_SHIFT 18
1411 #define AMD_FMT_MOD_DCC_MAX_COMPRESSED_BLOCK_MASK 0x3
1412
1413 /*
1414 * DCC supports embedding some clear colors directly in the DCC surface.
1415 * However, on older GPUs the rendering HW ignores the embedded clear color
1416 * and prefers the driver provided color. This necessitates doing a fastclear
1417 * eliminate operation before a process transfers control.
1418 *
1419 * If this bit is set that means the fastclear eliminate is not needed for these
1420 * embeddable colors.
1421 */
1422 #define AMD_FMT_MOD_DCC_CONSTANT_ENCODE_SHIFT 20
1423 #define AMD_FMT_MOD_DCC_CONSTANT_ENCODE_MASK 0x1
1424
1425 /*
1426 * The below fields are for accounting for per GPU differences. These are only
1427 * relevant for GFX9 and later and if the tile field is *_X/_T.
1428 *
1429 * PIPE_XOR_BITS = always needed
1430 * BANK_XOR_BITS = only for TILE_VER_GFX9
1431 * PACKERS = only for TILE_VER_GFX10_RBPLUS
1432 * RB = only for TILE_VER_GFX9 & DCC
1433 * PIPE = only for TILE_VER_GFX9 & DCC & (DCC_RETILE | DCC_PIPE_ALIGN)
1434 */
1435 #define AMD_FMT_MOD_PIPE_XOR_BITS_SHIFT 21
1436 #define AMD_FMT_MOD_PIPE_XOR_BITS_MASK 0x7
1437 #define AMD_FMT_MOD_BANK_XOR_BITS_SHIFT 24
1438 #define AMD_FMT_MOD_BANK_XOR_BITS_MASK 0x7
1439 #define AMD_FMT_MOD_PACKERS_SHIFT 27
1440 #define AMD_FMT_MOD_PACKERS_MASK 0x7
1441 #define AMD_FMT_MOD_RB_SHIFT 30
1442 #define AMD_FMT_MOD_RB_MASK 0x7
1443 #define AMD_FMT_MOD_PIPE_SHIFT 33
1444 #define AMD_FMT_MOD_PIPE_MASK 0x7
1445
1446 #define AMD_FMT_MOD_SET(field, value) \
1447 ((__u64)(value) << AMD_FMT_MOD_##field##_SHIFT)
1448 #define AMD_FMT_MOD_GET(field, value) \
1449 (((value) >> AMD_FMT_MOD_##field##_SHIFT) & AMD_FMT_MOD_##field##_MASK)
1450 #define AMD_FMT_MOD_CLEAR(field) \
1451 (~((__u64)AMD_FMT_MOD_##field##_MASK << AMD_FMT_MOD_##field##_SHIFT))
1452
1453 #if defined(__cplusplus)
1454 }
1455 #endif
1456
1457 #endif /* DRM_FOURCC_H */
1458