1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * Copyright © 2000-2010 David Woodhouse <dwmw2@infradead.org>
4 * Steven J. Hill <sjhill@realitydiluted.com>
5 * Thomas Gleixner <tglx@linutronix.de>
6 *
7 * Info:
8 * Contains standard defines and IDs for NAND flash devices
9 *
10 * Changelog:
11 * See git changelog.
12 */
13 #ifndef __LINUX_MTD_RAWNAND_H
14 #define __LINUX_MTD_RAWNAND_H
15
16 #include <linux/mtd/mtd.h>
17 #include <linux/mtd/nand.h>
18 #include <linux/mtd/flashchip.h>
19 #include <linux/mtd/bbm.h>
20 #include <linux/mtd/jedec.h>
21 #include <linux/mtd/onfi.h>
22 #include <linux/mutex.h>
23 #include <linux/of.h>
24 #include <linux/types.h>
25
26 struct nand_chip;
27 struct gpio_desc;
28
29 /* The maximum number of NAND chips in an array */
30 #define NAND_MAX_CHIPS 8
31
32 /*
33 * Constants for hardware specific CLE/ALE/NCE function
34 *
35 * These are bits which can be or'ed to set/clear multiple
36 * bits in one go.
37 */
38 /* Select the chip by setting nCE to low */
39 #define NAND_NCE 0x01
40 /* Select the command latch by setting CLE to high */
41 #define NAND_CLE 0x02
42 /* Select the address latch by setting ALE to high */
43 #define NAND_ALE 0x04
44
45 #define NAND_CTRL_CLE (NAND_NCE | NAND_CLE)
46 #define NAND_CTRL_ALE (NAND_NCE | NAND_ALE)
47 #define NAND_CTRL_CHANGE 0x80
48
49 /*
50 * Standard NAND flash commands
51 */
52 #define NAND_CMD_READ0 0
53 #define NAND_CMD_READ1 1
54 #define NAND_CMD_RNDOUT 5
55 #define NAND_CMD_PAGEPROG 0x10
56 #define NAND_CMD_READOOB 0x50
57 #define NAND_CMD_ERASE1 0x60
58 #define NAND_CMD_STATUS 0x70
59 #define NAND_CMD_SEQIN 0x80
60 #define NAND_CMD_RNDIN 0x85
61 #define NAND_CMD_READID 0x90
62 #define NAND_CMD_ERASE2 0xd0
63 #define NAND_CMD_PARAM 0xec
64 #define NAND_CMD_GET_FEATURES 0xee
65 #define NAND_CMD_SET_FEATURES 0xef
66 #define NAND_CMD_RESET 0xff
67
68 /* Extended commands for large page devices */
69 #define NAND_CMD_READSTART 0x30
70 #define NAND_CMD_RNDOUTSTART 0xE0
71 #define NAND_CMD_CACHEDPROG 0x15
72
73 #define NAND_CMD_NONE -1
74
75 /* Status bits */
76 #define NAND_STATUS_FAIL 0x01
77 #define NAND_STATUS_FAIL_N1 0x02
78 #define NAND_STATUS_TRUE_READY 0x20
79 #define NAND_STATUS_READY 0x40
80 #define NAND_STATUS_WP 0x80
81
82 #define NAND_DATA_IFACE_CHECK_ONLY -1
83
84 /*
85 * Constants for Hardware ECC
86 */
87 /* Reset Hardware ECC for read */
88 #define NAND_ECC_READ 0
89 /* Reset Hardware ECC for write */
90 #define NAND_ECC_WRITE 1
91 /* Enable Hardware ECC before syndrome is read back from flash */
92 #define NAND_ECC_READSYN 2
93
94 /*
95 * Enable generic NAND 'page erased' check. This check is only done when
96 * ecc.correct() returns -EBADMSG.
97 * Set this flag if your implementation does not fix bitflips in erased
98 * pages and you want to rely on the default implementation.
99 */
100 #define NAND_ECC_GENERIC_ERASED_CHECK BIT(0)
101
102 /*
103 * Option constants for bizarre disfunctionality and real
104 * features.
105 */
106
107 /* Buswidth is 16 bit */
108 #define NAND_BUSWIDTH_16 BIT(1)
109
110 /*
111 * When using software implementation of Hamming, we can specify which byte
112 * ordering should be used.
113 */
114 #define NAND_ECC_SOFT_HAMMING_SM_ORDER BIT(2)
115
116 /* Chip has cache program function */
117 #define NAND_CACHEPRG BIT(3)
118 /* Options valid for Samsung large page devices */
119 #define NAND_SAMSUNG_LP_OPTIONS NAND_CACHEPRG
120
121 /*
122 * Chip requires ready check on read (for auto-incremented sequential read).
123 * True only for small page devices; large page devices do not support
124 * autoincrement.
125 */
126 #define NAND_NEED_READRDY BIT(8)
127
128 /* Chip does not allow subpage writes */
129 #define NAND_NO_SUBPAGE_WRITE BIT(9)
130
131 /* Device is one of 'new' xD cards that expose fake nand command set */
132 #define NAND_BROKEN_XD BIT(10)
133
134 /* Device behaves just like nand, but is readonly */
135 #define NAND_ROM BIT(11)
136
137 /* Device supports subpage reads */
138 #define NAND_SUBPAGE_READ BIT(12)
139 /* Macros to identify the above */
140 #define NAND_HAS_SUBPAGE_READ(chip) ((chip->options & NAND_SUBPAGE_READ))
141
142 /*
143 * Some MLC NANDs need data scrambling to limit bitflips caused by repeated
144 * patterns.
145 */
146 #define NAND_NEED_SCRAMBLING BIT(13)
147
148 /* Device needs 3rd row address cycle */
149 #define NAND_ROW_ADDR_3 BIT(14)
150
151 /* Non chip related options */
152 /* This option skips the bbt scan during initialization. */
153 #define NAND_SKIP_BBTSCAN BIT(16)
154 /* Chip may not exist, so silence any errors in scan */
155 #define NAND_SCAN_SILENT_NODEV BIT(18)
156
157 /*
158 * Autodetect nand buswidth with readid/onfi.
159 * This suppose the driver will configure the hardware in 8 bits mode
160 * when calling nand_scan_ident, and update its configuration
161 * before calling nand_scan_tail.
162 */
163 #define NAND_BUSWIDTH_AUTO BIT(19)
164
165 /*
166 * This option could be defined by controller drivers to protect against
167 * kmap'ed, vmalloc'ed highmem buffers being passed from upper layers
168 */
169 #define NAND_USES_DMA BIT(20)
170
171 /*
172 * In case your controller is implementing ->legacy.cmd_ctrl() and is relying
173 * on the default ->cmdfunc() implementation, you may want to let the core
174 * handle the tCCS delay which is required when a column change (RNDIN or
175 * RNDOUT) is requested.
176 * If your controller already takes care of this delay, you don't need to set
177 * this flag.
178 */
179 #define NAND_WAIT_TCCS BIT(21)
180
181 /*
182 * Whether the NAND chip is a boot medium. Drivers might use this information
183 * to select ECC algorithms supported by the boot ROM or similar restrictions.
184 */
185 #define NAND_IS_BOOT_MEDIUM BIT(22)
186
187 /*
188 * Do not try to tweak the timings at runtime. This is needed when the
189 * controller initializes the timings on itself or when it relies on
190 * configuration done by the bootloader.
191 */
192 #define NAND_KEEP_TIMINGS BIT(23)
193
194 /*
195 * There are different places where the manufacturer stores the factory bad
196 * block markers.
197 *
198 * Position within the block: Each of these pages needs to be checked for a
199 * bad block marking pattern.
200 */
201 #define NAND_BBM_FIRSTPAGE BIT(24)
202 #define NAND_BBM_SECONDPAGE BIT(25)
203 #define NAND_BBM_LASTPAGE BIT(26)
204
205 /*
206 * Some controllers with pipelined ECC engines override the BBM marker with
207 * data or ECC bytes, thus making bad block detection through bad block marker
208 * impossible. Let's flag those chips so the core knows it shouldn't check the
209 * BBM and consider all blocks good.
210 */
211 #define NAND_NO_BBM_QUIRK BIT(27)
212
213 /* Cell info constants */
214 #define NAND_CI_CHIPNR_MSK 0x03
215 #define NAND_CI_CELLTYPE_MSK 0x0C
216 #define NAND_CI_CELLTYPE_SHIFT 2
217
218 /* Position within the OOB data of the page */
219 #define NAND_BBM_POS_SMALL 5
220 #define NAND_BBM_POS_LARGE 0
221
222 /**
223 * struct nand_parameters - NAND generic parameters from the parameter page
224 * @model: Model name
225 * @supports_set_get_features: The NAND chip supports setting/getting features
226 * @set_feature_list: Bitmap of features that can be set
227 * @get_feature_list: Bitmap of features that can be get
228 * @onfi: ONFI specific parameters
229 */
230 struct nand_parameters {
231 /* Generic parameters */
232 const char *model;
233 bool supports_set_get_features;
234 DECLARE_BITMAP(set_feature_list, ONFI_FEATURE_NUMBER);
235 DECLARE_BITMAP(get_feature_list, ONFI_FEATURE_NUMBER);
236
237 /* ONFI parameters */
238 struct onfi_params *onfi;
239 };
240
241 /* The maximum expected count of bytes in the NAND ID sequence */
242 #define NAND_MAX_ID_LEN 8
243
244 /**
245 * struct nand_id - NAND id structure
246 * @data: buffer containing the id bytes.
247 * @len: ID length.
248 */
249 struct nand_id {
250 u8 data[NAND_MAX_ID_LEN];
251 int len;
252 };
253
254 /**
255 * struct nand_ecc_step_info - ECC step information of ECC engine
256 * @stepsize: data bytes per ECC step
257 * @strengths: array of supported strengths
258 * @nstrengths: number of supported strengths
259 */
260 struct nand_ecc_step_info {
261 int stepsize;
262 const int *strengths;
263 int nstrengths;
264 };
265
266 /**
267 * struct nand_ecc_caps - capability of ECC engine
268 * @stepinfos: array of ECC step information
269 * @nstepinfos: number of ECC step information
270 * @calc_ecc_bytes: driver's hook to calculate ECC bytes per step
271 */
272 struct nand_ecc_caps {
273 const struct nand_ecc_step_info *stepinfos;
274 int nstepinfos;
275 int (*calc_ecc_bytes)(int step_size, int strength);
276 };
277
278 /* a shorthand to generate struct nand_ecc_caps with only one ECC stepsize */
279 #define NAND_ECC_CAPS_SINGLE(__name, __calc, __step, ...) \
280 static const int __name##_strengths[] = { __VA_ARGS__ }; \
281 static const struct nand_ecc_step_info __name##_stepinfo = { \
282 .stepsize = __step, \
283 .strengths = __name##_strengths, \
284 .nstrengths = ARRAY_SIZE(__name##_strengths), \
285 }; \
286 static const struct nand_ecc_caps __name = { \
287 .stepinfos = &__name##_stepinfo, \
288 .nstepinfos = 1, \
289 .calc_ecc_bytes = __calc, \
290 }
291
292 /**
293 * struct nand_ecc_ctrl - Control structure for ECC
294 * @engine_type: ECC engine type
295 * @placement: OOB bytes placement
296 * @algo: ECC algorithm
297 * @steps: number of ECC steps per page
298 * @size: data bytes per ECC step
299 * @bytes: ECC bytes per step
300 * @strength: max number of correctible bits per ECC step
301 * @total: total number of ECC bytes per page
302 * @prepad: padding information for syndrome based ECC generators
303 * @postpad: padding information for syndrome based ECC generators
304 * @options: ECC specific options (see NAND_ECC_XXX flags defined above)
305 * @calc_buf: buffer for calculated ECC, size is oobsize.
306 * @code_buf: buffer for ECC read from flash, size is oobsize.
307 * @hwctl: function to control hardware ECC generator. Must only
308 * be provided if an hardware ECC is available
309 * @calculate: function for ECC calculation or readback from ECC hardware
310 * @correct: function for ECC correction, matching to ECC generator (sw/hw).
311 * Should return a positive number representing the number of
312 * corrected bitflips, -EBADMSG if the number of bitflips exceed
313 * ECC strength, or any other error code if the error is not
314 * directly related to correction.
315 * If -EBADMSG is returned the input buffers should be left
316 * untouched.
317 * @read_page_raw: function to read a raw page without ECC. This function
318 * should hide the specific layout used by the ECC
319 * controller and always return contiguous in-band and
320 * out-of-band data even if they're not stored
321 * contiguously on the NAND chip (e.g.
322 * NAND_ECC_PLACEMENT_INTERLEAVED interleaves in-band and
323 * out-of-band data).
324 * @write_page_raw: function to write a raw page without ECC. This function
325 * should hide the specific layout used by the ECC
326 * controller and consider the passed data as contiguous
327 * in-band and out-of-band data. ECC controller is
328 * responsible for doing the appropriate transformations
329 * to adapt to its specific layout (e.g.
330 * NAND_ECC_PLACEMENT_INTERLEAVED interleaves in-band and
331 * out-of-band data).
332 * @read_page: function to read a page according to the ECC generator
333 * requirements; returns maximum number of bitflips corrected in
334 * any single ECC step, -EIO hw error
335 * @read_subpage: function to read parts of the page covered by ECC;
336 * returns same as read_page()
337 * @write_subpage: function to write parts of the page covered by ECC.
338 * @write_page: function to write a page according to the ECC generator
339 * requirements.
340 * @write_oob_raw: function to write chip OOB data without ECC
341 * @read_oob_raw: function to read chip OOB data without ECC
342 * @read_oob: function to read chip OOB data
343 * @write_oob: function to write chip OOB data
344 */
345 struct nand_ecc_ctrl {
346 enum nand_ecc_engine_type engine_type;
347 enum nand_ecc_placement placement;
348 enum nand_ecc_algo algo;
349 int steps;
350 int size;
351 int bytes;
352 int total;
353 int strength;
354 int prepad;
355 int postpad;
356 unsigned int options;
357 u8 *calc_buf;
358 u8 *code_buf;
359 void (*hwctl)(struct nand_chip *chip, int mode);
360 int (*calculate)(struct nand_chip *chip, const uint8_t *dat,
361 uint8_t *ecc_code);
362 int (*correct)(struct nand_chip *chip, uint8_t *dat, uint8_t *read_ecc,
363 uint8_t *calc_ecc);
364 int (*read_page_raw)(struct nand_chip *chip, uint8_t *buf,
365 int oob_required, int page);
366 int (*write_page_raw)(struct nand_chip *chip, const uint8_t *buf,
367 int oob_required, int page);
368 int (*read_page)(struct nand_chip *chip, uint8_t *buf,
369 int oob_required, int page);
370 int (*read_subpage)(struct nand_chip *chip, uint32_t offs,
371 uint32_t len, uint8_t *buf, int page);
372 int (*write_subpage)(struct nand_chip *chip, uint32_t offset,
373 uint32_t data_len, const uint8_t *data_buf,
374 int oob_required, int page);
375 int (*write_page)(struct nand_chip *chip, const uint8_t *buf,
376 int oob_required, int page);
377 int (*write_oob_raw)(struct nand_chip *chip, int page);
378 int (*read_oob_raw)(struct nand_chip *chip, int page);
379 int (*read_oob)(struct nand_chip *chip, int page);
380 int (*write_oob)(struct nand_chip *chip, int page);
381 };
382
383 /**
384 * struct nand_sdr_timings - SDR NAND chip timings
385 *
386 * This struct defines the timing requirements of a SDR NAND chip.
387 * These information can be found in every NAND datasheets and the timings
388 * meaning are described in the ONFI specifications:
389 * https://media-www.micron.com/-/media/client/onfi/specs/onfi_3_1_spec.pdf
390 * (chapter 4.15 Timing Parameters)
391 *
392 * All these timings are expressed in picoseconds.
393 *
394 * @tBERS_max: Block erase time
395 * @tCCS_min: Change column setup time
396 * @tPROG_max: Page program time
397 * @tR_max: Page read time
398 * @tALH_min: ALE hold time
399 * @tADL_min: ALE to data loading time
400 * @tALS_min: ALE setup time
401 * @tAR_min: ALE to RE# delay
402 * @tCEA_max: CE# access time
403 * @tCEH_min: CE# high hold time
404 * @tCH_min: CE# hold time
405 * @tCHZ_max: CE# high to output hi-Z
406 * @tCLH_min: CLE hold time
407 * @tCLR_min: CLE to RE# delay
408 * @tCLS_min: CLE setup time
409 * @tCOH_min: CE# high to output hold
410 * @tCS_min: CE# setup time
411 * @tDH_min: Data hold time
412 * @tDS_min: Data setup time
413 * @tFEAT_max: Busy time for Set Features and Get Features
414 * @tIR_min: Output hi-Z to RE# low
415 * @tITC_max: Interface and Timing Mode Change time
416 * @tRC_min: RE# cycle time
417 * @tREA_max: RE# access time
418 * @tREH_min: RE# high hold time
419 * @tRHOH_min: RE# high to output hold
420 * @tRHW_min: RE# high to WE# low
421 * @tRHZ_max: RE# high to output hi-Z
422 * @tRLOH_min: RE# low to output hold
423 * @tRP_min: RE# pulse width
424 * @tRR_min: Ready to RE# low (data only)
425 * @tRST_max: Device reset time, measured from the falling edge of R/B# to the
426 * rising edge of R/B#.
427 * @tWB_max: WE# high to SR[6] low
428 * @tWC_min: WE# cycle time
429 * @tWH_min: WE# high hold time
430 * @tWHR_min: WE# high to RE# low
431 * @tWP_min: WE# pulse width
432 * @tWW_min: WP# transition to WE# low
433 */
434 struct nand_sdr_timings {
435 u64 tBERS_max;
436 u32 tCCS_min;
437 u64 tPROG_max;
438 u64 tR_max;
439 u32 tALH_min;
440 u32 tADL_min;
441 u32 tALS_min;
442 u32 tAR_min;
443 u32 tCEA_max;
444 u32 tCEH_min;
445 u32 tCH_min;
446 u32 tCHZ_max;
447 u32 tCLH_min;
448 u32 tCLR_min;
449 u32 tCLS_min;
450 u32 tCOH_min;
451 u32 tCS_min;
452 u32 tDH_min;
453 u32 tDS_min;
454 u32 tFEAT_max;
455 u32 tIR_min;
456 u32 tITC_max;
457 u32 tRC_min;
458 u32 tREA_max;
459 u32 tREH_min;
460 u32 tRHOH_min;
461 u32 tRHW_min;
462 u32 tRHZ_max;
463 u32 tRLOH_min;
464 u32 tRP_min;
465 u32 tRR_min;
466 u64 tRST_max;
467 u32 tWB_max;
468 u32 tWC_min;
469 u32 tWH_min;
470 u32 tWHR_min;
471 u32 tWP_min;
472 u32 tWW_min;
473 };
474
475 /**
476 * struct nand_nvddr_timings - NV-DDR NAND chip timings
477 *
478 * This struct defines the timing requirements of a NV-DDR NAND data interface.
479 * These information can be found in every NAND datasheets and the timings
480 * meaning are described in the ONFI specifications:
481 * https://media-www.micron.com/-/media/client/onfi/specs/onfi_4_1_gold.pdf
482 * (chapter 4.18.2 NV-DDR)
483 *
484 * All these timings are expressed in picoseconds.
485 *
486 * @tBERS_max: Block erase time
487 * @tCCS_min: Change column setup time
488 * @tPROG_max: Page program time
489 * @tR_max: Page read time
490 * @tAC_min: Access window of DQ[7:0] from CLK
491 * @tAC_max: Access window of DQ[7:0] from CLK
492 * @tADL_min: ALE to data loading time
493 * @tCAD_min: Command, Address, Data delay
494 * @tCAH_min: Command/Address DQ hold time
495 * @tCALH_min: W/R_n, CLE and ALE hold time
496 * @tCALS_min: W/R_n, CLE and ALE setup time
497 * @tCAS_min: Command/address DQ setup time
498 * @tCEH_min: CE# high hold time
499 * @tCH_min: CE# hold time
500 * @tCK_min: Average clock cycle time
501 * @tCS_min: CE# setup time
502 * @tDH_min: Data hold time
503 * @tDQSCK_min: Start of the access window of DQS from CLK
504 * @tDQSCK_max: End of the access window of DQS from CLK
505 * @tDQSD_min: Min W/R_n low to DQS/DQ driven by device
506 * @tDQSD_max: Max W/R_n low to DQS/DQ driven by device
507 * @tDQSHZ_max: W/R_n high to DQS/DQ tri-state by device
508 * @tDQSQ_max: DQS-DQ skew, DQS to last DQ valid, per access
509 * @tDS_min: Data setup time
510 * @tDSC_min: DQS cycle time
511 * @tFEAT_max: Busy time for Set Features and Get Features
512 * @tITC_max: Interface and Timing Mode Change time
513 * @tQHS_max: Data hold skew factor
514 * @tRHW_min: Data output cycle to command, address, or data input cycle
515 * @tRR_min: Ready to RE# low (data only)
516 * @tRST_max: Device reset time, measured from the falling edge of R/B# to the
517 * rising edge of R/B#.
518 * @tWB_max: WE# high to SR[6] low
519 * @tWHR_min: WE# high to RE# low
520 * @tWRCK_min: W/R_n low to data output cycle
521 * @tWW_min: WP# transition to WE# low
522 */
523 struct nand_nvddr_timings {
524 u64 tBERS_max;
525 u32 tCCS_min;
526 u64 tPROG_max;
527 u64 tR_max;
528 u32 tAC_min;
529 u32 tAC_max;
530 u32 tADL_min;
531 u32 tCAD_min;
532 u32 tCAH_min;
533 u32 tCALH_min;
534 u32 tCALS_min;
535 u32 tCAS_min;
536 u32 tCEH_min;
537 u32 tCH_min;
538 u32 tCK_min;
539 u32 tCS_min;
540 u32 tDH_min;
541 u32 tDQSCK_min;
542 u32 tDQSCK_max;
543 u32 tDQSD_min;
544 u32 tDQSD_max;
545 u32 tDQSHZ_max;
546 u32 tDQSQ_max;
547 u32 tDS_min;
548 u32 tDSC_min;
549 u32 tFEAT_max;
550 u32 tITC_max;
551 u32 tQHS_max;
552 u32 tRHW_min;
553 u32 tRR_min;
554 u32 tRST_max;
555 u32 tWB_max;
556 u32 tWHR_min;
557 u32 tWRCK_min;
558 u32 tWW_min;
559 };
560
561 /*
562 * While timings related to the data interface itself are mostly different
563 * between SDR and NV-DDR, timings related to the internal chip behavior are
564 * common. IOW, the following entries which describe the internal delays have
565 * the same definition and are shared in both SDR and NV-DDR timing structures:
566 * - tADL_min
567 * - tBERS_max
568 * - tCCS_min
569 * - tFEAT_max
570 * - tPROG_max
571 * - tR_max
572 * - tRR_min
573 * - tRST_max
574 * - tWB_max
575 *
576 * The below macros return the value of a given timing, no matter the interface.
577 */
578 #define NAND_COMMON_TIMING_PS(conf, timing_name) \
579 nand_interface_is_sdr(conf) ? \
580 nand_get_sdr_timings(conf)->timing_name : \
581 nand_get_nvddr_timings(conf)->timing_name
582
583 #define NAND_COMMON_TIMING_MS(conf, timing_name) \
584 PSEC_TO_MSEC(NAND_COMMON_TIMING_PS((conf), timing_name))
585
586 #define NAND_COMMON_TIMING_NS(conf, timing_name) \
587 PSEC_TO_NSEC(NAND_COMMON_TIMING_PS((conf), timing_name))
588
589 /**
590 * enum nand_interface_type - NAND interface type
591 * @NAND_SDR_IFACE: Single Data Rate interface
592 * @NAND_NVDDR_IFACE: Double Data Rate interface
593 */
594 enum nand_interface_type {
595 NAND_SDR_IFACE,
596 NAND_NVDDR_IFACE,
597 };
598
599 /**
600 * struct nand_interface_config - NAND interface timing
601 * @type: type of the timing
602 * @timings: The timing information
603 * @timings.mode: Timing mode as defined in the specification
604 * @timings.sdr: Use it when @type is %NAND_SDR_IFACE.
605 * @timings.nvddr: Use it when @type is %NAND_NVDDR_IFACE.
606 */
607 struct nand_interface_config {
608 enum nand_interface_type type;
609 struct nand_timings {
610 unsigned int mode;
611 union {
612 struct nand_sdr_timings sdr;
613 struct nand_nvddr_timings nvddr;
614 };
615 } timings;
616 };
617
618 /**
619 * nand_interface_is_sdr - get the interface type
620 * @conf: The data interface
621 */
nand_interface_is_sdr(const struct nand_interface_config * conf)622 static bool nand_interface_is_sdr(const struct nand_interface_config *conf)
623 {
624 return conf->type == NAND_SDR_IFACE;
625 }
626
627 /**
628 * nand_interface_is_nvddr - get the interface type
629 * @conf: The data interface
630 */
nand_interface_is_nvddr(const struct nand_interface_config * conf)631 static bool nand_interface_is_nvddr(const struct nand_interface_config *conf)
632 {
633 return conf->type == NAND_NVDDR_IFACE;
634 }
635
636 /**
637 * nand_get_sdr_timings - get SDR timing from data interface
638 * @conf: The data interface
639 */
640 static inline const struct nand_sdr_timings *
nand_get_sdr_timings(const struct nand_interface_config * conf)641 nand_get_sdr_timings(const struct nand_interface_config *conf)
642 {
643 if (!nand_interface_is_sdr(conf))
644 return ERR_PTR(-EINVAL);
645
646 return &conf->timings.sdr;
647 }
648
649 /**
650 * nand_get_nvddr_timings - get NV-DDR timing from data interface
651 * @conf: The data interface
652 */
653 static inline const struct nand_nvddr_timings *
nand_get_nvddr_timings(const struct nand_interface_config * conf)654 nand_get_nvddr_timings(const struct nand_interface_config *conf)
655 {
656 if (!nand_interface_is_nvddr(conf))
657 return ERR_PTR(-EINVAL);
658
659 return &conf->timings.nvddr;
660 }
661
662 /**
663 * struct nand_op_cmd_instr - Definition of a command instruction
664 * @opcode: the command to issue in one cycle
665 */
666 struct nand_op_cmd_instr {
667 u8 opcode;
668 };
669
670 /**
671 * struct nand_op_addr_instr - Definition of an address instruction
672 * @naddrs: length of the @addrs array
673 * @addrs: array containing the address cycles to issue
674 */
675 struct nand_op_addr_instr {
676 unsigned int naddrs;
677 const u8 *addrs;
678 };
679
680 /**
681 * struct nand_op_data_instr - Definition of a data instruction
682 * @len: number of data bytes to move
683 * @buf: buffer to fill
684 * @buf.in: buffer to fill when reading from the NAND chip
685 * @buf.out: buffer to read from when writing to the NAND chip
686 * @force_8bit: force 8-bit access
687 *
688 * Please note that "in" and "out" are inverted from the ONFI specification
689 * and are from the controller perspective, so a "in" is a read from the NAND
690 * chip while a "out" is a write to the NAND chip.
691 */
692 struct nand_op_data_instr {
693 unsigned int len;
694 union {
695 void *in;
696 const void *out;
697 } buf;
698 bool force_8bit;
699 };
700
701 /**
702 * struct nand_op_waitrdy_instr - Definition of a wait ready instruction
703 * @timeout_ms: maximum delay while waiting for the ready/busy pin in ms
704 */
705 struct nand_op_waitrdy_instr {
706 unsigned int timeout_ms;
707 };
708
709 /**
710 * enum nand_op_instr_type - Definition of all instruction types
711 * @NAND_OP_CMD_INSTR: command instruction
712 * @NAND_OP_ADDR_INSTR: address instruction
713 * @NAND_OP_DATA_IN_INSTR: data in instruction
714 * @NAND_OP_DATA_OUT_INSTR: data out instruction
715 * @NAND_OP_WAITRDY_INSTR: wait ready instruction
716 */
717 enum nand_op_instr_type {
718 NAND_OP_CMD_INSTR,
719 NAND_OP_ADDR_INSTR,
720 NAND_OP_DATA_IN_INSTR,
721 NAND_OP_DATA_OUT_INSTR,
722 NAND_OP_WAITRDY_INSTR,
723 };
724
725 /**
726 * struct nand_op_instr - Instruction object
727 * @type: the instruction type
728 * @ctx: extra data associated to the instruction. You'll have to use the
729 * appropriate element depending on @type
730 * @ctx.cmd: use it if @type is %NAND_OP_CMD_INSTR
731 * @ctx.addr: use it if @type is %NAND_OP_ADDR_INSTR
732 * @ctx.data: use it if @type is %NAND_OP_DATA_IN_INSTR
733 * or %NAND_OP_DATA_OUT_INSTR
734 * @ctx.waitrdy: use it if @type is %NAND_OP_WAITRDY_INSTR
735 * @delay_ns: delay the controller should apply after the instruction has been
736 * issued on the bus. Most modern controllers have internal timings
737 * control logic, and in this case, the controller driver can ignore
738 * this field.
739 */
740 struct nand_op_instr {
741 enum nand_op_instr_type type;
742 union {
743 struct nand_op_cmd_instr cmd;
744 struct nand_op_addr_instr addr;
745 struct nand_op_data_instr data;
746 struct nand_op_waitrdy_instr waitrdy;
747 } ctx;
748 unsigned int delay_ns;
749 };
750
751 /*
752 * Special handling must be done for the WAITRDY timeout parameter as it usually
753 * is either tPROG (after a prog), tR (before a read), tRST (during a reset) or
754 * tBERS (during an erase) which all of them are u64 values that cannot be
755 * divided by usual kernel macros and must be handled with the special
756 * DIV_ROUND_UP_ULL() macro.
757 *
758 * Cast to type of dividend is needed here to guarantee that the result won't
759 * be an unsigned long long when the dividend is an unsigned long (or smaller),
760 * which is what the compiler does when it sees ternary operator with 2
761 * different return types (picks the largest type to make sure there's no
762 * loss).
763 */
764 #define __DIVIDE(dividend, divisor) ({ \
765 (__typeof__(dividend))(sizeof(dividend) <= sizeof(unsigned long) ? \
766 DIV_ROUND_UP(dividend, divisor) : \
767 DIV_ROUND_UP_ULL(dividend, divisor)); \
768 })
769 #define PSEC_TO_NSEC(x) __DIVIDE(x, 1000)
770 #define PSEC_TO_MSEC(x) __DIVIDE(x, 1000000000)
771
772 #define NAND_OP_CMD(id, ns) \
773 { \
774 .type = NAND_OP_CMD_INSTR, \
775 .ctx.cmd.opcode = id, \
776 .delay_ns = ns, \
777 }
778
779 #define NAND_OP_ADDR(ncycles, cycles, ns) \
780 { \
781 .type = NAND_OP_ADDR_INSTR, \
782 .ctx.addr = { \
783 .naddrs = ncycles, \
784 .addrs = cycles, \
785 }, \
786 .delay_ns = ns, \
787 }
788
789 #define NAND_OP_DATA_IN(l, b, ns) \
790 { \
791 .type = NAND_OP_DATA_IN_INSTR, \
792 .ctx.data = { \
793 .len = l, \
794 .buf.in = b, \
795 .force_8bit = false, \
796 }, \
797 .delay_ns = ns, \
798 }
799
800 #define NAND_OP_DATA_OUT(l, b, ns) \
801 { \
802 .type = NAND_OP_DATA_OUT_INSTR, \
803 .ctx.data = { \
804 .len = l, \
805 .buf.out = b, \
806 .force_8bit = false, \
807 }, \
808 .delay_ns = ns, \
809 }
810
811 #define NAND_OP_8BIT_DATA_IN(l, b, ns) \
812 { \
813 .type = NAND_OP_DATA_IN_INSTR, \
814 .ctx.data = { \
815 .len = l, \
816 .buf.in = b, \
817 .force_8bit = true, \
818 }, \
819 .delay_ns = ns, \
820 }
821
822 #define NAND_OP_8BIT_DATA_OUT(l, b, ns) \
823 { \
824 .type = NAND_OP_DATA_OUT_INSTR, \
825 .ctx.data = { \
826 .len = l, \
827 .buf.out = b, \
828 .force_8bit = true, \
829 }, \
830 .delay_ns = ns, \
831 }
832
833 #define NAND_OP_WAIT_RDY(tout_ms, ns) \
834 { \
835 .type = NAND_OP_WAITRDY_INSTR, \
836 .ctx.waitrdy.timeout_ms = tout_ms, \
837 .delay_ns = ns, \
838 }
839
840 /**
841 * struct nand_subop - a sub operation
842 * @cs: the CS line to select for this NAND sub-operation
843 * @instrs: array of instructions
844 * @ninstrs: length of the @instrs array
845 * @first_instr_start_off: offset to start from for the first instruction
846 * of the sub-operation
847 * @last_instr_end_off: offset to end at (excluded) for the last instruction
848 * of the sub-operation
849 *
850 * Both @first_instr_start_off and @last_instr_end_off only apply to data or
851 * address instructions.
852 *
853 * When an operation cannot be handled as is by the NAND controller, it will
854 * be split by the parser into sub-operations which will be passed to the
855 * controller driver.
856 */
857 struct nand_subop {
858 unsigned int cs;
859 const struct nand_op_instr *instrs;
860 unsigned int ninstrs;
861 unsigned int first_instr_start_off;
862 unsigned int last_instr_end_off;
863 };
864
865 unsigned int nand_subop_get_addr_start_off(const struct nand_subop *subop,
866 unsigned int op_id);
867 unsigned int nand_subop_get_num_addr_cyc(const struct nand_subop *subop,
868 unsigned int op_id);
869 unsigned int nand_subop_get_data_start_off(const struct nand_subop *subop,
870 unsigned int op_id);
871 unsigned int nand_subop_get_data_len(const struct nand_subop *subop,
872 unsigned int op_id);
873
874 /**
875 * struct nand_op_parser_addr_constraints - Constraints for address instructions
876 * @maxcycles: maximum number of address cycles the controller can issue in a
877 * single step
878 */
879 struct nand_op_parser_addr_constraints {
880 unsigned int maxcycles;
881 };
882
883 /**
884 * struct nand_op_parser_data_constraints - Constraints for data instructions
885 * @maxlen: maximum data length that the controller can handle in a single step
886 */
887 struct nand_op_parser_data_constraints {
888 unsigned int maxlen;
889 };
890
891 /**
892 * struct nand_op_parser_pattern_elem - One element of a pattern
893 * @type: the instructuction type
894 * @optional: whether this element of the pattern is optional or mandatory
895 * @ctx: address or data constraint
896 * @ctx.addr: address constraint (number of cycles)
897 * @ctx.data: data constraint (data length)
898 */
899 struct nand_op_parser_pattern_elem {
900 enum nand_op_instr_type type;
901 bool optional;
902 union {
903 struct nand_op_parser_addr_constraints addr;
904 struct nand_op_parser_data_constraints data;
905 } ctx;
906 };
907
908 #define NAND_OP_PARSER_PAT_CMD_ELEM(_opt) \
909 { \
910 .type = NAND_OP_CMD_INSTR, \
911 .optional = _opt, \
912 }
913
914 #define NAND_OP_PARSER_PAT_ADDR_ELEM(_opt, _maxcycles) \
915 { \
916 .type = NAND_OP_ADDR_INSTR, \
917 .optional = _opt, \
918 .ctx.addr.maxcycles = _maxcycles, \
919 }
920
921 #define NAND_OP_PARSER_PAT_DATA_IN_ELEM(_opt, _maxlen) \
922 { \
923 .type = NAND_OP_DATA_IN_INSTR, \
924 .optional = _opt, \
925 .ctx.data.maxlen = _maxlen, \
926 }
927
928 #define NAND_OP_PARSER_PAT_DATA_OUT_ELEM(_opt, _maxlen) \
929 { \
930 .type = NAND_OP_DATA_OUT_INSTR, \
931 .optional = _opt, \
932 .ctx.data.maxlen = _maxlen, \
933 }
934
935 #define NAND_OP_PARSER_PAT_WAITRDY_ELEM(_opt) \
936 { \
937 .type = NAND_OP_WAITRDY_INSTR, \
938 .optional = _opt, \
939 }
940
941 /**
942 * struct nand_op_parser_pattern - NAND sub-operation pattern descriptor
943 * @elems: array of pattern elements
944 * @nelems: number of pattern elements in @elems array
945 * @exec: the function that will issue a sub-operation
946 *
947 * A pattern is a list of elements, each element reprensenting one instruction
948 * with its constraints. The pattern itself is used by the core to match NAND
949 * chip operation with NAND controller operations.
950 * Once a match between a NAND controller operation pattern and a NAND chip
951 * operation (or a sub-set of a NAND operation) is found, the pattern ->exec()
952 * hook is called so that the controller driver can issue the operation on the
953 * bus.
954 *
955 * Controller drivers should declare as many patterns as they support and pass
956 * this list of patterns (created with the help of the following macro) to
957 * the nand_op_parser_exec_op() helper.
958 */
959 struct nand_op_parser_pattern {
960 const struct nand_op_parser_pattern_elem *elems;
961 unsigned int nelems;
962 int (*exec)(struct nand_chip *chip, const struct nand_subop *subop);
963 };
964
965 #define NAND_OP_PARSER_PATTERN(_exec, ...) \
966 { \
967 .exec = _exec, \
968 .elems = (const struct nand_op_parser_pattern_elem[]) { __VA_ARGS__ }, \
969 .nelems = sizeof((struct nand_op_parser_pattern_elem[]) { __VA_ARGS__ }) / \
970 sizeof(struct nand_op_parser_pattern_elem), \
971 }
972
973 /**
974 * struct nand_op_parser - NAND controller operation parser descriptor
975 * @patterns: array of supported patterns
976 * @npatterns: length of the @patterns array
977 *
978 * The parser descriptor is just an array of supported patterns which will be
979 * iterated by nand_op_parser_exec_op() everytime it tries to execute an
980 * NAND operation (or tries to determine if a specific operation is supported).
981 *
982 * It is worth mentioning that patterns will be tested in their declaration
983 * order, and the first match will be taken, so it's important to order patterns
984 * appropriately so that simple/inefficient patterns are placed at the end of
985 * the list. Usually, this is where you put single instruction patterns.
986 */
987 struct nand_op_parser {
988 const struct nand_op_parser_pattern *patterns;
989 unsigned int npatterns;
990 };
991
992 #define NAND_OP_PARSER(...) \
993 { \
994 .patterns = (const struct nand_op_parser_pattern[]) { __VA_ARGS__ }, \
995 .npatterns = sizeof((struct nand_op_parser_pattern[]) { __VA_ARGS__ }) / \
996 sizeof(struct nand_op_parser_pattern), \
997 }
998
999 /**
1000 * struct nand_operation - NAND operation descriptor
1001 * @cs: the CS line to select for this NAND operation
1002 * @instrs: array of instructions to execute
1003 * @ninstrs: length of the @instrs array
1004 *
1005 * The actual operation structure that will be passed to chip->exec_op().
1006 */
1007 struct nand_operation {
1008 unsigned int cs;
1009 const struct nand_op_instr *instrs;
1010 unsigned int ninstrs;
1011 };
1012
1013 #define NAND_OPERATION(_cs, _instrs) \
1014 { \
1015 .cs = _cs, \
1016 .instrs = _instrs, \
1017 .ninstrs = ARRAY_SIZE(_instrs), \
1018 }
1019
1020 int nand_op_parser_exec_op(struct nand_chip *chip,
1021 const struct nand_op_parser *parser,
1022 const struct nand_operation *op, bool check_only);
1023
nand_op_trace(const char * prefix,const struct nand_op_instr * instr)1024 static inline void nand_op_trace(const char *prefix,
1025 const struct nand_op_instr *instr)
1026 {
1027 #if IS_ENABLED(CONFIG_DYNAMIC_DEBUG) || defined(DEBUG)
1028 switch (instr->type) {
1029 case NAND_OP_CMD_INSTR:
1030 pr_debug("%sCMD [0x%02x]\n", prefix,
1031 instr->ctx.cmd.opcode);
1032 break;
1033 case NAND_OP_ADDR_INSTR:
1034 pr_debug("%sADDR [%d cyc: %*ph]\n", prefix,
1035 instr->ctx.addr.naddrs,
1036 instr->ctx.addr.naddrs < 64 ?
1037 instr->ctx.addr.naddrs : 64,
1038 instr->ctx.addr.addrs);
1039 break;
1040 case NAND_OP_DATA_IN_INSTR:
1041 pr_debug("%sDATA_IN [%d B%s]\n", prefix,
1042 instr->ctx.data.len,
1043 instr->ctx.data.force_8bit ?
1044 ", force 8-bit" : "");
1045 break;
1046 case NAND_OP_DATA_OUT_INSTR:
1047 pr_debug("%sDATA_OUT [%d B%s]\n", prefix,
1048 instr->ctx.data.len,
1049 instr->ctx.data.force_8bit ?
1050 ", force 8-bit" : "");
1051 break;
1052 case NAND_OP_WAITRDY_INSTR:
1053 pr_debug("%sWAITRDY [max %d ms]\n", prefix,
1054 instr->ctx.waitrdy.timeout_ms);
1055 break;
1056 }
1057 #endif
1058 }
1059
1060 /**
1061 * struct nand_controller_ops - Controller operations
1062 *
1063 * @attach_chip: this method is called after the NAND detection phase after
1064 * flash ID and MTD fields such as erase size, page size and OOB
1065 * size have been set up. ECC requirements are available if
1066 * provided by the NAND chip or device tree. Typically used to
1067 * choose the appropriate ECC configuration and allocate
1068 * associated resources.
1069 * This hook is optional.
1070 * @detach_chip: free all resources allocated/claimed in
1071 * nand_controller_ops->attach_chip().
1072 * This hook is optional.
1073 * @exec_op: controller specific method to execute NAND operations.
1074 * This method replaces chip->legacy.cmdfunc(),
1075 * chip->legacy.{read,write}_{buf,byte,word}(),
1076 * chip->legacy.dev_ready() and chip->legacy.waifunc().
1077 * @setup_interface: setup the data interface and timing. If chipnr is set to
1078 * %NAND_DATA_IFACE_CHECK_ONLY this means the configuration
1079 * should not be applied but only checked.
1080 * This hook is optional.
1081 */
1082 struct nand_controller_ops {
1083 int (*attach_chip)(struct nand_chip *chip);
1084 void (*detach_chip)(struct nand_chip *chip);
1085 int (*exec_op)(struct nand_chip *chip,
1086 const struct nand_operation *op,
1087 bool check_only);
1088 int (*setup_interface)(struct nand_chip *chip, int chipnr,
1089 const struct nand_interface_config *conf);
1090 };
1091
1092 /**
1093 * struct nand_controller - Structure used to describe a NAND controller
1094 *
1095 * @lock: lock used to serialize accesses to the NAND controller
1096 * @ops: NAND controller operations.
1097 */
1098 struct nand_controller {
1099 struct mutex lock;
1100 const struct nand_controller_ops *ops;
1101 };
1102
nand_controller_init(struct nand_controller * nfc)1103 static inline void nand_controller_init(struct nand_controller *nfc)
1104 {
1105 mutex_init(&nfc->lock);
1106 }
1107
1108 /**
1109 * struct nand_legacy - NAND chip legacy fields/hooks
1110 * @IO_ADDR_R: address to read the 8 I/O lines of the flash device
1111 * @IO_ADDR_W: address to write the 8 I/O lines of the flash device
1112 * @select_chip: select/deselect a specific target/die
1113 * @read_byte: read one byte from the chip
1114 * @write_byte: write a single byte to the chip on the low 8 I/O lines
1115 * @write_buf: write data from the buffer to the chip
1116 * @read_buf: read data from the chip into the buffer
1117 * @cmd_ctrl: hardware specific function for controlling ALE/CLE/nCE. Also used
1118 * to write command and address
1119 * @cmdfunc: hardware specific function for writing commands to the chip.
1120 * @dev_ready: hardware specific function for accessing device ready/busy line.
1121 * If set to NULL no access to ready/busy is available and the
1122 * ready/busy information is read from the chip status register.
1123 * @waitfunc: hardware specific function for wait on ready.
1124 * @block_bad: check if a block is bad, using OOB markers
1125 * @block_markbad: mark a block bad
1126 * @set_features: set the NAND chip features
1127 * @get_features: get the NAND chip features
1128 * @chip_delay: chip dependent delay for transferring data from array to read
1129 * regs (tR).
1130 * @dummy_controller: dummy controller implementation for drivers that can
1131 * only control a single chip
1132 *
1133 * If you look at this structure you're already wrong. These fields/hooks are
1134 * all deprecated.
1135 */
1136 struct nand_legacy {
1137 void __iomem *IO_ADDR_R;
1138 void __iomem *IO_ADDR_W;
1139 void (*select_chip)(struct nand_chip *chip, int cs);
1140 u8 (*read_byte)(struct nand_chip *chip);
1141 void (*write_byte)(struct nand_chip *chip, u8 byte);
1142 void (*write_buf)(struct nand_chip *chip, const u8 *buf, int len);
1143 void (*read_buf)(struct nand_chip *chip, u8 *buf, int len);
1144 void (*cmd_ctrl)(struct nand_chip *chip, int dat, unsigned int ctrl);
1145 void (*cmdfunc)(struct nand_chip *chip, unsigned command, int column,
1146 int page_addr);
1147 int (*dev_ready)(struct nand_chip *chip);
1148 int (*waitfunc)(struct nand_chip *chip);
1149 int (*block_bad)(struct nand_chip *chip, loff_t ofs);
1150 int (*block_markbad)(struct nand_chip *chip, loff_t ofs);
1151 int (*set_features)(struct nand_chip *chip, int feature_addr,
1152 u8 *subfeature_para);
1153 int (*get_features)(struct nand_chip *chip, int feature_addr,
1154 u8 *subfeature_para);
1155 int chip_delay;
1156 struct nand_controller dummy_controller;
1157 };
1158
1159 /**
1160 * struct nand_chip_ops - NAND chip operations
1161 * @suspend: Suspend operation
1162 * @resume: Resume operation
1163 * @lock_area: Lock operation
1164 * @unlock_area: Unlock operation
1165 * @setup_read_retry: Set the read-retry mode (mostly needed for MLC NANDs)
1166 * @choose_interface_config: Choose the best interface configuration
1167 */
1168 struct nand_chip_ops {
1169 int (*suspend)(struct nand_chip *chip);
1170 void (*resume)(struct nand_chip *chip);
1171 int (*lock_area)(struct nand_chip *chip, loff_t ofs, uint64_t len);
1172 int (*unlock_area)(struct nand_chip *chip, loff_t ofs, uint64_t len);
1173 int (*setup_read_retry)(struct nand_chip *chip, int retry_mode);
1174 int (*choose_interface_config)(struct nand_chip *chip,
1175 struct nand_interface_config *iface);
1176 };
1177
1178 /**
1179 * struct nand_manufacturer - NAND manufacturer structure
1180 * @desc: The manufacturer description
1181 * @priv: Private information for the manufacturer driver
1182 */
1183 struct nand_manufacturer {
1184 const struct nand_manufacturer_desc *desc;
1185 void *priv;
1186 };
1187
1188 /**
1189 * struct nand_secure_region - NAND secure region structure
1190 * @offset: Offset of the start of the secure region
1191 * @size: Size of the secure region
1192 */
1193 struct nand_secure_region {
1194 u64 offset;
1195 u64 size;
1196 };
1197
1198 /**
1199 * struct nand_chip - NAND Private Flash Chip Data
1200 * @base: Inherit from the generic NAND device
1201 * @id: Holds NAND ID
1202 * @parameters: Holds generic parameters under an easily readable form
1203 * @manufacturer: Manufacturer information
1204 * @ops: NAND chip operations
1205 * @legacy: All legacy fields/hooks. If you develop a new driver, don't even try
1206 * to use any of these fields/hooks, and if you're modifying an
1207 * existing driver that is using those fields/hooks, you should
1208 * consider reworking the driver and avoid using them.
1209 * @options: Various chip options. They can partly be set to inform nand_scan
1210 * about special functionality. See the defines for further
1211 * explanation.
1212 * @current_interface_config: The currently used NAND interface configuration
1213 * @best_interface_config: The best NAND interface configuration which fits both
1214 * the NAND chip and NAND controller constraints. If
1215 * unset, the default reset interface configuration must
1216 * be used.
1217 * @bbt_erase_shift: Number of address bits in a bbt entry
1218 * @bbt_options: Bad block table specific options. All options used here must
1219 * come from bbm.h. By default, these options will be copied to
1220 * the appropriate nand_bbt_descr's.
1221 * @badblockpos: Bad block marker position in the oob area
1222 * @badblockbits: Minimum number of set bits in a good block's bad block marker
1223 * position; i.e., BBM = 11110111b is good when badblockbits = 7
1224 * @bbt_td: Bad block table descriptor for flash lookup
1225 * @bbt_md: Bad block table mirror descriptor
1226 * @badblock_pattern: Bad block scan pattern used for initial bad block scan
1227 * @bbt: Bad block table pointer
1228 * @page_shift: Number of address bits in a page (column address bits)
1229 * @phys_erase_shift: Number of address bits in a physical eraseblock
1230 * @chip_shift: Number of address bits in one chip
1231 * @pagemask: Page number mask = number of (pages / chip) - 1
1232 * @subpagesize: Holds the subpagesize
1233 * @data_buf: Buffer for data, size is (page size + oobsize)
1234 * @oob_poi: pointer on the OOB area covered by data_buf
1235 * @pagecache: Structure containing page cache related fields
1236 * @pagecache.bitflips: Number of bitflips of the cached page
1237 * @pagecache.page: Page number currently in the cache. -1 means no page is
1238 * currently cached
1239 * @buf_align: Minimum buffer alignment required by a platform
1240 * @lock: Lock protecting the suspended field. Also used to serialize accesses
1241 * to the NAND device
1242 * @suspended: Set to 1 when the device is suspended, 0 when it's not
1243 * @resume_wq: wait queue to sleep if rawnand is in suspended state.
1244 * @cur_cs: Currently selected target. -1 means no target selected, otherwise we
1245 * should always have cur_cs >= 0 && cur_cs < nanddev_ntargets().
1246 * NAND Controller drivers should not modify this value, but they're
1247 * allowed to read it.
1248 * @read_retries: The number of read retry modes supported
1249 * @secure_regions: Structure containing the secure regions info
1250 * @nr_secure_regions: Number of secure regions
1251 * @controller: The hardware controller structure which is shared among multiple
1252 * independent devices
1253 * @ecc: The ECC controller structure
1254 * @priv: Chip private data
1255 */
1256 struct nand_chip {
1257 struct nand_device base;
1258 struct nand_id id;
1259 struct nand_parameters parameters;
1260 struct nand_manufacturer manufacturer;
1261 struct nand_chip_ops ops;
1262 struct nand_legacy legacy;
1263 unsigned int options;
1264
1265 /* Data interface */
1266 const struct nand_interface_config *current_interface_config;
1267 struct nand_interface_config *best_interface_config;
1268
1269 /* Bad block information */
1270 unsigned int bbt_erase_shift;
1271 unsigned int bbt_options;
1272 unsigned int badblockpos;
1273 unsigned int badblockbits;
1274 struct nand_bbt_descr *bbt_td;
1275 struct nand_bbt_descr *bbt_md;
1276 struct nand_bbt_descr *badblock_pattern;
1277 u8 *bbt;
1278
1279 /* Device internal layout */
1280 unsigned int page_shift;
1281 unsigned int phys_erase_shift;
1282 unsigned int chip_shift;
1283 unsigned int pagemask;
1284 unsigned int subpagesize;
1285
1286 /* Buffers */
1287 u8 *data_buf;
1288 u8 *oob_poi;
1289 struct {
1290 unsigned int bitflips;
1291 int page;
1292 } pagecache;
1293 unsigned long buf_align;
1294
1295 /* Internals */
1296 struct mutex lock;
1297 unsigned int suspended : 1;
1298 wait_queue_head_t resume_wq;
1299 int cur_cs;
1300 int read_retries;
1301 struct nand_secure_region *secure_regions;
1302 u8 nr_secure_regions;
1303
1304 /* Externals */
1305 struct nand_controller *controller;
1306 struct nand_ecc_ctrl ecc;
1307 void *priv;
1308 };
1309
mtd_to_nand(struct mtd_info * mtd)1310 static inline struct nand_chip *mtd_to_nand(struct mtd_info *mtd)
1311 {
1312 return container_of(mtd, struct nand_chip, base.mtd);
1313 }
1314
nand_to_mtd(struct nand_chip * chip)1315 static inline struct mtd_info *nand_to_mtd(struct nand_chip *chip)
1316 {
1317 return &chip->base.mtd;
1318 }
1319
nand_get_controller_data(struct nand_chip * chip)1320 static inline void *nand_get_controller_data(struct nand_chip *chip)
1321 {
1322 return chip->priv;
1323 }
1324
nand_set_controller_data(struct nand_chip * chip,void * priv)1325 static inline void nand_set_controller_data(struct nand_chip *chip, void *priv)
1326 {
1327 chip->priv = priv;
1328 }
1329
nand_set_manufacturer_data(struct nand_chip * chip,void * priv)1330 static inline void nand_set_manufacturer_data(struct nand_chip *chip,
1331 void *priv)
1332 {
1333 chip->manufacturer.priv = priv;
1334 }
1335
nand_get_manufacturer_data(struct nand_chip * chip)1336 static inline void *nand_get_manufacturer_data(struct nand_chip *chip)
1337 {
1338 return chip->manufacturer.priv;
1339 }
1340
nand_set_flash_node(struct nand_chip * chip,struct device_node * np)1341 static inline void nand_set_flash_node(struct nand_chip *chip,
1342 struct device_node *np)
1343 {
1344 mtd_set_of_node(nand_to_mtd(chip), np);
1345 }
1346
nand_get_flash_node(struct nand_chip * chip)1347 static inline struct device_node *nand_get_flash_node(struct nand_chip *chip)
1348 {
1349 return mtd_get_of_node(nand_to_mtd(chip));
1350 }
1351
1352 /**
1353 * nand_get_interface_config - Retrieve the current interface configuration
1354 * of a NAND chip
1355 * @chip: The NAND chip
1356 */
1357 static inline const struct nand_interface_config *
nand_get_interface_config(struct nand_chip * chip)1358 nand_get_interface_config(struct nand_chip *chip)
1359 {
1360 return chip->current_interface_config;
1361 }
1362
1363 /*
1364 * A helper for defining older NAND chips where the second ID byte fully
1365 * defined the chip, including the geometry (chip size, eraseblock size, page
1366 * size). All these chips have 512 bytes NAND page size.
1367 */
1368 #define LEGACY_ID_NAND(nm, devid, chipsz, erasesz, opts) \
1369 { .name = (nm), {{ .dev_id = (devid) }}, .pagesize = 512, \
1370 .chipsize = (chipsz), .erasesize = (erasesz), .options = (opts) }
1371
1372 /*
1373 * A helper for defining newer chips which report their page size and
1374 * eraseblock size via the extended ID bytes.
1375 *
1376 * The real difference between LEGACY_ID_NAND and EXTENDED_ID_NAND is that with
1377 * EXTENDED_ID_NAND, manufacturers overloaded the same device ID so that the
1378 * device ID now only represented a particular total chip size (and voltage,
1379 * buswidth), and the page size, eraseblock size, and OOB size could vary while
1380 * using the same device ID.
1381 */
1382 #define EXTENDED_ID_NAND(nm, devid, chipsz, opts) \
1383 { .name = (nm), {{ .dev_id = (devid) }}, .chipsize = (chipsz), \
1384 .options = (opts) }
1385
1386 #define NAND_ECC_INFO(_strength, _step) \
1387 { .strength_ds = (_strength), .step_ds = (_step) }
1388 #define NAND_ECC_STRENGTH(type) ((type)->ecc.strength_ds)
1389 #define NAND_ECC_STEP(type) ((type)->ecc.step_ds)
1390
1391 /**
1392 * struct nand_flash_dev - NAND Flash Device ID Structure
1393 * @name: a human-readable name of the NAND chip
1394 * @dev_id: the device ID (the second byte of the full chip ID array)
1395 * @mfr_id: manufacturer ID part of the full chip ID array (refers the same
1396 * memory address as ``id[0]``)
1397 * @dev_id: device ID part of the full chip ID array (refers the same memory
1398 * address as ``id[1]``)
1399 * @id: full device ID array
1400 * @pagesize: size of the NAND page in bytes; if 0, then the real page size (as
1401 * well as the eraseblock size) is determined from the extended NAND
1402 * chip ID array)
1403 * @chipsize: total chip size in MiB
1404 * @erasesize: eraseblock size in bytes (determined from the extended ID if 0)
1405 * @options: stores various chip bit options
1406 * @id_len: The valid length of the @id.
1407 * @oobsize: OOB size
1408 * @ecc: ECC correctability and step information from the datasheet.
1409 * @ecc.strength_ds: The ECC correctability from the datasheet, same as the
1410 * @ecc_strength_ds in nand_chip{}.
1411 * @ecc.step_ds: The ECC step required by the @ecc.strength_ds, same as the
1412 * @ecc_step_ds in nand_chip{}, also from the datasheet.
1413 * For example, the "4bit ECC for each 512Byte" can be set with
1414 * NAND_ECC_INFO(4, 512).
1415 */
1416 struct nand_flash_dev {
1417 char *name;
1418 union {
1419 struct {
1420 uint8_t mfr_id;
1421 uint8_t dev_id;
1422 };
1423 uint8_t id[NAND_MAX_ID_LEN];
1424 };
1425 unsigned int pagesize;
1426 unsigned int chipsize;
1427 unsigned int erasesize;
1428 unsigned int options;
1429 uint16_t id_len;
1430 uint16_t oobsize;
1431 struct {
1432 uint16_t strength_ds;
1433 uint16_t step_ds;
1434 } ecc;
1435 };
1436
1437 int nand_create_bbt(struct nand_chip *chip);
1438
1439 /*
1440 * Check if it is a SLC nand.
1441 * The !nand_is_slc() can be used to check the MLC/TLC nand chips.
1442 * We do not distinguish the MLC and TLC now.
1443 */
nand_is_slc(struct nand_chip * chip)1444 static inline bool nand_is_slc(struct nand_chip *chip)
1445 {
1446 WARN(nanddev_bits_per_cell(&chip->base) == 0,
1447 "chip->bits_per_cell is used uninitialized\n");
1448 return nanddev_bits_per_cell(&chip->base) == 1;
1449 }
1450
1451 /**
1452 * nand_opcode_8bits - Check if the opcode's address should be sent only on the
1453 * lower 8 bits
1454 * @command: opcode to check
1455 */
nand_opcode_8bits(unsigned int command)1456 static inline int nand_opcode_8bits(unsigned int command)
1457 {
1458 switch (command) {
1459 case NAND_CMD_READID:
1460 case NAND_CMD_PARAM:
1461 case NAND_CMD_GET_FEATURES:
1462 case NAND_CMD_SET_FEATURES:
1463 return 1;
1464 default:
1465 break;
1466 }
1467 return 0;
1468 }
1469
1470 int rawnand_sw_hamming_init(struct nand_chip *chip);
1471 int rawnand_sw_hamming_calculate(struct nand_chip *chip,
1472 const unsigned char *buf,
1473 unsigned char *code);
1474 int rawnand_sw_hamming_correct(struct nand_chip *chip,
1475 unsigned char *buf,
1476 unsigned char *read_ecc,
1477 unsigned char *calc_ecc);
1478 void rawnand_sw_hamming_cleanup(struct nand_chip *chip);
1479 int rawnand_sw_bch_init(struct nand_chip *chip);
1480 int rawnand_sw_bch_correct(struct nand_chip *chip, unsigned char *buf,
1481 unsigned char *read_ecc, unsigned char *calc_ecc);
1482 void rawnand_sw_bch_cleanup(struct nand_chip *chip);
1483
1484 int nand_check_erased_ecc_chunk(void *data, int datalen,
1485 void *ecc, int ecclen,
1486 void *extraoob, int extraooblen,
1487 int threshold);
1488
1489 int nand_ecc_choose_conf(struct nand_chip *chip,
1490 const struct nand_ecc_caps *caps, int oobavail);
1491
1492 /* Default write_oob implementation */
1493 int nand_write_oob_std(struct nand_chip *chip, int page);
1494
1495 /* Default read_oob implementation */
1496 int nand_read_oob_std(struct nand_chip *chip, int page);
1497
1498 /* Stub used by drivers that do not support GET/SET FEATURES operations */
1499 int nand_get_set_features_notsupp(struct nand_chip *chip, int addr,
1500 u8 *subfeature_param);
1501
1502 /* read_page_raw implementations */
1503 int nand_read_page_raw(struct nand_chip *chip, uint8_t *buf, int oob_required,
1504 int page);
1505 int nand_monolithic_read_page_raw(struct nand_chip *chip, uint8_t *buf,
1506 int oob_required, int page);
1507
1508 /* write_page_raw implementations */
1509 int nand_write_page_raw(struct nand_chip *chip, const uint8_t *buf,
1510 int oob_required, int page);
1511 int nand_monolithic_write_page_raw(struct nand_chip *chip, const uint8_t *buf,
1512 int oob_required, int page);
1513
1514 /* Reset and initialize a NAND device */
1515 int nand_reset(struct nand_chip *chip, int chipnr);
1516
1517 /* NAND operation helpers */
1518 int nand_reset_op(struct nand_chip *chip);
1519 int nand_readid_op(struct nand_chip *chip, u8 addr, void *buf,
1520 unsigned int len);
1521 int nand_status_op(struct nand_chip *chip, u8 *status);
1522 int nand_erase_op(struct nand_chip *chip, unsigned int eraseblock);
1523 int nand_read_page_op(struct nand_chip *chip, unsigned int page,
1524 unsigned int offset_in_page, void *buf, unsigned int len);
1525 int nand_change_read_column_op(struct nand_chip *chip,
1526 unsigned int offset_in_page, void *buf,
1527 unsigned int len, bool force_8bit);
1528 int nand_read_oob_op(struct nand_chip *chip, unsigned int page,
1529 unsigned int offset_in_page, void *buf, unsigned int len);
1530 int nand_prog_page_begin_op(struct nand_chip *chip, unsigned int page,
1531 unsigned int offset_in_page, const void *buf,
1532 unsigned int len);
1533 int nand_prog_page_end_op(struct nand_chip *chip);
1534 int nand_prog_page_op(struct nand_chip *chip, unsigned int page,
1535 unsigned int offset_in_page, const void *buf,
1536 unsigned int len);
1537 int nand_change_write_column_op(struct nand_chip *chip,
1538 unsigned int offset_in_page, const void *buf,
1539 unsigned int len, bool force_8bit);
1540 int nand_read_data_op(struct nand_chip *chip, void *buf, unsigned int len,
1541 bool force_8bit, bool check_only);
1542 int nand_write_data_op(struct nand_chip *chip, const void *buf,
1543 unsigned int len, bool force_8bit);
1544 int nand_read_page_hwecc_oob_first(struct nand_chip *chip, uint8_t *buf,
1545 int oob_required, int page);
1546
1547 /* Scan and identify a NAND device */
1548 int nand_scan_with_ids(struct nand_chip *chip, unsigned int max_chips,
1549 struct nand_flash_dev *ids);
1550
nand_scan(struct nand_chip * chip,unsigned int max_chips)1551 static inline int nand_scan(struct nand_chip *chip, unsigned int max_chips)
1552 {
1553 return nand_scan_with_ids(chip, max_chips, NULL);
1554 }
1555
1556 /* Internal helper for board drivers which need to override command function */
1557 void nand_wait_ready(struct nand_chip *chip);
1558
1559 /*
1560 * Free resources held by the NAND device, must be called on error after a
1561 * sucessful nand_scan().
1562 */
1563 void nand_cleanup(struct nand_chip *chip);
1564
1565 /*
1566 * External helper for controller drivers that have to implement the WAITRDY
1567 * instruction and have no physical pin to check it.
1568 */
1569 int nand_soft_waitrdy(struct nand_chip *chip, unsigned long timeout_ms);
1570 int nand_gpio_waitrdy(struct nand_chip *chip, struct gpio_desc *gpiod,
1571 unsigned long timeout_ms);
1572
1573 /* Select/deselect a NAND target. */
1574 void nand_select_target(struct nand_chip *chip, unsigned int cs);
1575 void nand_deselect_target(struct nand_chip *chip);
1576
1577 /* Bitops */
1578 void nand_extract_bits(u8 *dst, unsigned int dst_off, const u8 *src,
1579 unsigned int src_off, unsigned int nbits);
1580
1581 /**
1582 * nand_get_data_buf() - Get the internal page buffer
1583 * @chip: NAND chip object
1584 *
1585 * Returns the pre-allocated page buffer after invalidating the cache. This
1586 * function should be used by drivers that do not want to allocate their own
1587 * bounce buffer and still need such a buffer for specific operations (most
1588 * commonly when reading OOB data only).
1589 *
1590 * Be careful to never call this function in the write/write_oob path, because
1591 * the core may have placed the data to be written out in this buffer.
1592 *
1593 * Return: pointer to the page cache buffer
1594 */
nand_get_data_buf(struct nand_chip * chip)1595 static inline void *nand_get_data_buf(struct nand_chip *chip)
1596 {
1597 chip->pagecache.page = -1;
1598
1599 return chip->data_buf;
1600 }
1601
1602 /* Parse the gpio-cs property */
1603 int rawnand_dt_parse_gpio_cs(struct device *dev, struct gpio_desc ***cs_array,
1604 unsigned int *ncs_array);
1605
1606 #endif /* __LINUX_MTD_RAWNAND_H */
1607