1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3  * Copyright(c) 2004 - 2006 Intel Corporation. All rights reserved.
4  */
5 #ifndef LINUX_DMAENGINE_H
6 #define LINUX_DMAENGINE_H
7 
8 #include <linux/device.h>
9 #include <linux/err.h>
10 #include <linux/uio.h>
11 #include <linux/bug.h>
12 #include <linux/scatterlist.h>
13 #include <linux/bitmap.h>
14 #include <linux/types.h>
15 #include <asm/page.h>
16 
17 /**
18  * typedef dma_cookie_t - an opaque DMA cookie
19  *
20  * if dma_cookie_t is >0 it's a DMA request cookie, <0 it's an error code
21  */
22 typedef s32 dma_cookie_t;
23 #define DMA_MIN_COOKIE	1
24 
dma_submit_error(dma_cookie_t cookie)25 static inline int dma_submit_error(dma_cookie_t cookie)
26 {
27 	return cookie < 0 ? cookie : 0;
28 }
29 
30 /**
31  * enum dma_status - DMA transaction status
32  * @DMA_COMPLETE: transaction completed
33  * @DMA_IN_PROGRESS: transaction not yet processed
34  * @DMA_PAUSED: transaction is paused
35  * @DMA_ERROR: transaction failed
36  */
37 enum dma_status {
38 	DMA_COMPLETE,
39 	DMA_IN_PROGRESS,
40 	DMA_PAUSED,
41 	DMA_ERROR,
42 	DMA_OUT_OF_ORDER,
43 };
44 
45 /**
46  * enum dma_transaction_type - DMA transaction types/indexes
47  *
48  * Note: The DMA_ASYNC_TX capability is not to be set by drivers.  It is
49  * automatically set as dma devices are registered.
50  */
51 enum dma_transaction_type {
52 	DMA_MEMCPY,
53 	DMA_MEMCPY_SG,
54 	DMA_XOR,
55 	DMA_PQ,
56 	DMA_XOR_VAL,
57 	DMA_PQ_VAL,
58 	DMA_MEMSET,
59 	DMA_MEMSET_SG,
60 	DMA_INTERRUPT,
61 	DMA_PRIVATE,
62 	DMA_ASYNC_TX,
63 	DMA_SLAVE,
64 	DMA_CYCLIC,
65 	DMA_INTERLEAVE,
66 	DMA_COMPLETION_NO_ORDER,
67 	DMA_REPEAT,
68 	DMA_LOAD_EOT,
69 /* last transaction type for creation of the capabilities mask */
70 	DMA_TX_TYPE_END,
71 };
72 
73 /**
74  * enum dma_transfer_direction - dma transfer mode and direction indicator
75  * @DMA_MEM_TO_MEM: Async/Memcpy mode
76  * @DMA_MEM_TO_DEV: Slave mode & From Memory to Device
77  * @DMA_DEV_TO_MEM: Slave mode & From Device to Memory
78  * @DMA_DEV_TO_DEV: Slave mode & From Device to Device
79  */
80 enum dma_transfer_direction {
81 	DMA_MEM_TO_MEM,
82 	DMA_MEM_TO_DEV,
83 	DMA_DEV_TO_MEM,
84 	DMA_DEV_TO_DEV,
85 	DMA_TRANS_NONE,
86 };
87 
88 /**
89  * Interleaved Transfer Request
90  * ----------------------------
91  * A chunk is collection of contiguous bytes to be transferred.
92  * The gap(in bytes) between two chunks is called inter-chunk-gap(ICG).
93  * ICGs may or may not change between chunks.
94  * A FRAME is the smallest series of contiguous {chunk,icg} pairs,
95  *  that when repeated an integral number of times, specifies the transfer.
96  * A transfer template is specification of a Frame, the number of times
97  *  it is to be repeated and other per-transfer attributes.
98  *
99  * Practically, a client driver would have ready a template for each
100  *  type of transfer it is going to need during its lifetime and
101  *  set only 'src_start' and 'dst_start' before submitting the requests.
102  *
103  *
104  *  |      Frame-1        |       Frame-2       | ~ |       Frame-'numf'  |
105  *  |====....==.===...=...|====....==.===...=...| ~ |====....==.===...=...|
106  *
107  *    ==  Chunk size
108  *    ... ICG
109  */
110 
111 /**
112  * struct data_chunk - Element of scatter-gather list that makes a frame.
113  * @size: Number of bytes to read from source.
114  *	  size_dst := fn(op, size_src), so doesn't mean much for destination.
115  * @icg: Number of bytes to jump after last src/dst address of this
116  *	 chunk and before first src/dst address for next chunk.
117  *	 Ignored for dst(assumed 0), if dst_inc is true and dst_sgl is false.
118  *	 Ignored for src(assumed 0), if src_inc is true and src_sgl is false.
119  * @dst_icg: Number of bytes to jump after last dst address of this
120  *	 chunk and before the first dst address for next chunk.
121  *	 Ignored if dst_inc is true and dst_sgl is false.
122  * @src_icg: Number of bytes to jump after last src address of this
123  *	 chunk and before the first src address for next chunk.
124  *	 Ignored if src_inc is true and src_sgl is false.
125  */
126 struct data_chunk {
127 	size_t size;
128 	size_t icg;
129 	size_t dst_icg;
130 	size_t src_icg;
131 };
132 
133 /**
134  * struct dma_interleaved_template - Template to convey DMAC the transfer pattern
135  *	 and attributes.
136  * @src_start: Bus address of source for the first chunk.
137  * @dst_start: Bus address of destination for the first chunk.
138  * @dir: Specifies the type of Source and Destination.
139  * @src_inc: If the source address increments after reading from it.
140  * @dst_inc: If the destination address increments after writing to it.
141  * @src_sgl: If the 'icg' of sgl[] applies to Source (scattered read).
142  *		Otherwise, source is read contiguously (icg ignored).
143  *		Ignored if src_inc is false.
144  * @dst_sgl: If the 'icg' of sgl[] applies to Destination (scattered write).
145  *		Otherwise, destination is filled contiguously (icg ignored).
146  *		Ignored if dst_inc is false.
147  * @numf: Number of frames in this template.
148  * @frame_size: Number of chunks in a frame i.e, size of sgl[].
149  * @sgl: Array of {chunk,icg} pairs that make up a frame.
150  */
151 struct dma_interleaved_template {
152 	dma_addr_t src_start;
153 	dma_addr_t dst_start;
154 	enum dma_transfer_direction dir;
155 	bool src_inc;
156 	bool dst_inc;
157 	bool src_sgl;
158 	bool dst_sgl;
159 	size_t numf;
160 	size_t frame_size;
161 	struct data_chunk sgl[];
162 };
163 
164 /**
165  * enum dma_ctrl_flags - DMA flags to augment operation preparation,
166  *  control completion, and communicate status.
167  * @DMA_PREP_INTERRUPT - trigger an interrupt (callback) upon completion of
168  *  this transaction
169  * @DMA_CTRL_ACK - if clear, the descriptor cannot be reused until the client
170  *  acknowledges receipt, i.e. has a chance to establish any dependency
171  *  chains
172  * @DMA_PREP_PQ_DISABLE_P - prevent generation of P while generating Q
173  * @DMA_PREP_PQ_DISABLE_Q - prevent generation of Q while generating P
174  * @DMA_PREP_CONTINUE - indicate to a driver that it is reusing buffers as
175  *  sources that were the result of a previous operation, in the case of a PQ
176  *  operation it continues the calculation with new sources
177  * @DMA_PREP_FENCE - tell the driver that subsequent operations depend
178  *  on the result of this operation
179  * @DMA_CTRL_REUSE: client can reuse the descriptor and submit again till
180  *  cleared or freed
181  * @DMA_PREP_CMD: tell the driver that the data passed to DMA API is command
182  *  data and the descriptor should be in different format from normal
183  *  data descriptors.
184  * @DMA_PREP_REPEAT: tell the driver that the transaction shall be automatically
185  *  repeated when it ends until a transaction is issued on the same channel
186  *  with the DMA_PREP_LOAD_EOT flag set. This flag is only applicable to
187  *  interleaved transactions and is ignored for all other transaction types.
188  * @DMA_PREP_LOAD_EOT: tell the driver that the transaction shall replace any
189  *  active repeated (as indicated by DMA_PREP_REPEAT) transaction when the
190  *  repeated transaction ends. Not setting this flag when the previously queued
191  *  transaction is marked with DMA_PREP_REPEAT will cause the new transaction
192  *  to never be processed and stay in the issued queue forever. The flag is
193  *  ignored if the previous transaction is not a repeated transaction.
194  */
195 enum dma_ctrl_flags {
196 	DMA_PREP_INTERRUPT = (1 << 0),
197 	DMA_CTRL_ACK = (1 << 1),
198 	DMA_PREP_PQ_DISABLE_P = (1 << 2),
199 	DMA_PREP_PQ_DISABLE_Q = (1 << 3),
200 	DMA_PREP_CONTINUE = (1 << 4),
201 	DMA_PREP_FENCE = (1 << 5),
202 	DMA_CTRL_REUSE = (1 << 6),
203 	DMA_PREP_CMD = (1 << 7),
204 	DMA_PREP_REPEAT = (1 << 8),
205 	DMA_PREP_LOAD_EOT = (1 << 9),
206 };
207 
208 /**
209  * enum sum_check_bits - bit position of pq_check_flags
210  */
211 enum sum_check_bits {
212 	SUM_CHECK_P = 0,
213 	SUM_CHECK_Q = 1,
214 };
215 
216 /**
217  * enum pq_check_flags - result of async_{xor,pq}_zero_sum operations
218  * @SUM_CHECK_P_RESULT - 1 if xor zero sum error, 0 otherwise
219  * @SUM_CHECK_Q_RESULT - 1 if reed-solomon zero sum error, 0 otherwise
220  */
221 enum sum_check_flags {
222 	SUM_CHECK_P_RESULT = (1 << SUM_CHECK_P),
223 	SUM_CHECK_Q_RESULT = (1 << SUM_CHECK_Q),
224 };
225 
226 
227 /**
228  * dma_cap_mask_t - capabilities bitmap modeled after cpumask_t.
229  * See linux/cpumask.h
230  */
231 typedef struct { DECLARE_BITMAP(bits, DMA_TX_TYPE_END); } dma_cap_mask_t;
232 
233 /**
234  * enum dma_desc_metadata_mode - per descriptor metadata mode types supported
235  * @DESC_METADATA_CLIENT - the metadata buffer is allocated/provided by the
236  *  client driver and it is attached (via the dmaengine_desc_attach_metadata()
237  *  helper) to the descriptor.
238  *
239  * Client drivers interested to use this mode can follow:
240  * - DMA_MEM_TO_DEV / DEV_MEM_TO_MEM:
241  *   1. prepare the descriptor (dmaengine_prep_*)
242  *	construct the metadata in the client's buffer
243  *   2. use dmaengine_desc_attach_metadata() to attach the buffer to the
244  *	descriptor
245  *   3. submit the transfer
246  * - DMA_DEV_TO_MEM:
247  *   1. prepare the descriptor (dmaengine_prep_*)
248  *   2. use dmaengine_desc_attach_metadata() to attach the buffer to the
249  *	descriptor
250  *   3. submit the transfer
251  *   4. when the transfer is completed, the metadata should be available in the
252  *	attached buffer
253  *
254  * @DESC_METADATA_ENGINE - the metadata buffer is allocated/managed by the DMA
255  *  driver. The client driver can ask for the pointer, maximum size and the
256  *  currently used size of the metadata and can directly update or read it.
257  *  dmaengine_desc_get_metadata_ptr() and dmaengine_desc_set_metadata_len() is
258  *  provided as helper functions.
259  *
260  *  Note: the metadata area for the descriptor is no longer valid after the
261  *  transfer has been completed (valid up to the point when the completion
262  *  callback returns if used).
263  *
264  * Client drivers interested to use this mode can follow:
265  * - DMA_MEM_TO_DEV / DEV_MEM_TO_MEM:
266  *   1. prepare the descriptor (dmaengine_prep_*)
267  *   2. use dmaengine_desc_get_metadata_ptr() to get the pointer to the engine's
268  *	metadata area
269  *   3. update the metadata at the pointer
270  *   4. use dmaengine_desc_set_metadata_len()  to tell the DMA engine the amount
271  *	of data the client has placed into the metadata buffer
272  *   5. submit the transfer
273  * - DMA_DEV_TO_MEM:
274  *   1. prepare the descriptor (dmaengine_prep_*)
275  *   2. submit the transfer
276  *   3. on transfer completion, use dmaengine_desc_get_metadata_ptr() to get the
277  *	pointer to the engine's metadata area
278  *   4. Read out the metadata from the pointer
279  *
280  * Note: the two mode is not compatible and clients must use one mode for a
281  * descriptor.
282  */
283 enum dma_desc_metadata_mode {
284 	DESC_METADATA_NONE = 0,
285 	DESC_METADATA_CLIENT = BIT(0),
286 	DESC_METADATA_ENGINE = BIT(1),
287 };
288 
289 /**
290  * struct dma_chan_percpu - the per-CPU part of struct dma_chan
291  * @memcpy_count: transaction counter
292  * @bytes_transferred: byte counter
293  */
294 struct dma_chan_percpu {
295 	/* stats */
296 	unsigned long memcpy_count;
297 	unsigned long bytes_transferred;
298 };
299 
300 /**
301  * struct dma_router - DMA router structure
302  * @dev: pointer to the DMA router device
303  * @route_free: function to be called when the route can be disconnected
304  */
305 struct dma_router {
306 	struct device *dev;
307 	void (*route_free)(struct device *dev, void *route_data);
308 };
309 
310 /**
311  * struct dma_chan - devices supply DMA channels, clients use them
312  * @device: ptr to the dma device who supplies this channel, always !%NULL
313  * @slave: ptr to the device using this channel
314  * @cookie: last cookie value returned to client
315  * @completed_cookie: last completed cookie for this channel
316  * @chan_id: channel ID for sysfs
317  * @dev: class device for sysfs
318  * @name: backlink name for sysfs
319  * @dbg_client_name: slave name for debugfs in format:
320  *	dev_name(requester's dev):channel name, for example: "2b00000.mcasp:tx"
321  * @device_node: used to add this to the device chan list
322  * @local: per-cpu pointer to a struct dma_chan_percpu
323  * @client_count: how many clients are using this channel
324  * @table_count: number of appearances in the mem-to-mem allocation table
325  * @router: pointer to the DMA router structure
326  * @route_data: channel specific data for the router
327  * @private: private data for certain client-channel associations
328  */
329 struct dma_chan {
330 	struct dma_device *device;
331 	struct device *slave;
332 	dma_cookie_t cookie;
333 	dma_cookie_t completed_cookie;
334 
335 	/* sysfs */
336 	int chan_id;
337 	struct dma_chan_dev *dev;
338 	const char *name;
339 #ifdef CONFIG_DEBUG_FS
340 	char *dbg_client_name;
341 #endif
342 
343 	struct list_head device_node;
344 	struct dma_chan_percpu __percpu *local;
345 	int client_count;
346 	int table_count;
347 
348 	/* DMA router */
349 	struct dma_router *router;
350 	void *route_data;
351 
352 	void *private;
353 };
354 
355 /**
356  * struct dma_chan_dev - relate sysfs device node to backing channel device
357  * @chan: driver channel device
358  * @device: sysfs device
359  * @dev_id: parent dma_device dev_id
360  * @chan_dma_dev: The channel is using custom/different dma-mapping
361  * compared to the parent dma_device
362  */
363 struct dma_chan_dev {
364 	struct dma_chan *chan;
365 	struct device device;
366 	int dev_id;
367 	bool chan_dma_dev;
368 };
369 
370 /**
371  * enum dma_slave_buswidth - defines bus width of the DMA slave
372  * device, source or target buses
373  */
374 enum dma_slave_buswidth {
375 	DMA_SLAVE_BUSWIDTH_UNDEFINED = 0,
376 	DMA_SLAVE_BUSWIDTH_1_BYTE = 1,
377 	DMA_SLAVE_BUSWIDTH_2_BYTES = 2,
378 	DMA_SLAVE_BUSWIDTH_3_BYTES = 3,
379 	DMA_SLAVE_BUSWIDTH_4_BYTES = 4,
380 	DMA_SLAVE_BUSWIDTH_8_BYTES = 8,
381 	DMA_SLAVE_BUSWIDTH_16_BYTES = 16,
382 	DMA_SLAVE_BUSWIDTH_32_BYTES = 32,
383 	DMA_SLAVE_BUSWIDTH_64_BYTES = 64,
384 	DMA_SLAVE_BUSWIDTH_128_BYTES = 128,
385 };
386 
387 /**
388  * struct dma_slave_config - dma slave channel runtime config
389  * @direction: whether the data shall go in or out on this slave
390  * channel, right now. DMA_MEM_TO_DEV and DMA_DEV_TO_MEM are
391  * legal values. DEPRECATED, drivers should use the direction argument
392  * to the device_prep_slave_sg and device_prep_dma_cyclic functions or
393  * the dir field in the dma_interleaved_template structure.
394  * @src_addr: this is the physical address where DMA slave data
395  * should be read (RX), if the source is memory this argument is
396  * ignored.
397  * @dst_addr: this is the physical address where DMA slave data
398  * should be written (TX), if the source is memory this argument
399  * is ignored.
400  * @src_addr_width: this is the width in bytes of the source (RX)
401  * register where DMA data shall be read. If the source
402  * is memory this may be ignored depending on architecture.
403  * Legal values: 1, 2, 3, 4, 8, 16, 32, 64, 128.
404  * @dst_addr_width: same as src_addr_width but for destination
405  * target (TX) mutatis mutandis.
406  * @src_maxburst: the maximum number of words (note: words, as in
407  * units of the src_addr_width member, not bytes) that can be sent
408  * in one burst to the device. Typically something like half the
409  * FIFO depth on I/O peripherals so you don't overflow it. This
410  * may or may not be applicable on memory sources.
411  * @dst_maxburst: same as src_maxburst but for destination target
412  * mutatis mutandis.
413  * @src_port_window_size: The length of the register area in words the data need
414  * to be accessed on the device side. It is only used for devices which is using
415  * an area instead of a single register to receive the data. Typically the DMA
416  * loops in this area in order to transfer the data.
417  * @dst_port_window_size: same as src_port_window_size but for the destination
418  * port.
419  * @device_fc: Flow Controller Settings. Only valid for slave channels. Fill
420  * with 'true' if peripheral should be flow controller. Direction will be
421  * selected at Runtime.
422  * @peripheral_config: peripheral configuration for programming peripheral
423  * for dmaengine transfer
424  * @peripheral_size: peripheral configuration buffer size
425  *
426  * This struct is passed in as configuration data to a DMA engine
427  * in order to set up a certain channel for DMA transport at runtime.
428  * The DMA device/engine has to provide support for an additional
429  * callback in the dma_device structure, device_config and this struct
430  * will then be passed in as an argument to the function.
431  *
432  * The rationale for adding configuration information to this struct is as
433  * follows: if it is likely that more than one DMA slave controllers in
434  * the world will support the configuration option, then make it generic.
435  * If not: if it is fixed so that it be sent in static from the platform
436  * data, then prefer to do that.
437  */
438 struct dma_slave_config {
439 	enum dma_transfer_direction direction;
440 	phys_addr_t src_addr;
441 	phys_addr_t dst_addr;
442 	enum dma_slave_buswidth src_addr_width;
443 	enum dma_slave_buswidth dst_addr_width;
444 	u32 src_maxburst;
445 	u32 dst_maxburst;
446 	u32 src_port_window_size;
447 	u32 dst_port_window_size;
448 	bool device_fc;
449 	void *peripheral_config;
450 	size_t peripheral_size;
451 };
452 
453 /**
454  * enum dma_residue_granularity - Granularity of the reported transfer residue
455  * @DMA_RESIDUE_GRANULARITY_DESCRIPTOR: Residue reporting is not support. The
456  *  DMA channel is only able to tell whether a descriptor has been completed or
457  *  not, which means residue reporting is not supported by this channel. The
458  *  residue field of the dma_tx_state field will always be 0.
459  * @DMA_RESIDUE_GRANULARITY_SEGMENT: Residue is updated after each successfully
460  *  completed segment of the transfer (For cyclic transfers this is after each
461  *  period). This is typically implemented by having the hardware generate an
462  *  interrupt after each transferred segment and then the drivers updates the
463  *  outstanding residue by the size of the segment. Another possibility is if
464  *  the hardware supports scatter-gather and the segment descriptor has a field
465  *  which gets set after the segment has been completed. The driver then counts
466  *  the number of segments without the flag set to compute the residue.
467  * @DMA_RESIDUE_GRANULARITY_BURST: Residue is updated after each transferred
468  *  burst. This is typically only supported if the hardware has a progress
469  *  register of some sort (E.g. a register with the current read/write address
470  *  or a register with the amount of bursts/beats/bytes that have been
471  *  transferred or still need to be transferred).
472  */
473 enum dma_residue_granularity {
474 	DMA_RESIDUE_GRANULARITY_DESCRIPTOR = 0,
475 	DMA_RESIDUE_GRANULARITY_SEGMENT = 1,
476 	DMA_RESIDUE_GRANULARITY_BURST = 2,
477 };
478 
479 /**
480  * struct dma_slave_caps - expose capabilities of a slave channel only
481  * @src_addr_widths: bit mask of src addr widths the channel supports.
482  *	Width is specified in bytes, e.g. for a channel supporting
483  *	a width of 4 the mask should have BIT(4) set.
484  * @dst_addr_widths: bit mask of dst addr widths the channel supports
485  * @directions: bit mask of slave directions the channel supports.
486  *	Since the enum dma_transfer_direction is not defined as bit flag for
487  *	each type, the dma controller should set BIT(<TYPE>) and same
488  *	should be checked by controller as well
489  * @min_burst: min burst capability per-transfer
490  * @max_burst: max burst capability per-transfer
491  * @max_sg_burst: max number of SG list entries executed in a single burst
492  *	DMA tansaction with no software intervention for reinitialization.
493  *	Zero value means unlimited number of entries.
494  * @cmd_pause: true, if pause is supported (i.e. for reading residue or
495  *	       for resume later)
496  * @cmd_resume: true, if resume is supported
497  * @cmd_terminate: true, if terminate cmd is supported
498  * @residue_granularity: granularity of the reported transfer residue
499  * @descriptor_reuse: if a descriptor can be reused by client and
500  * resubmitted multiple times
501  */
502 struct dma_slave_caps {
503 	u32 src_addr_widths;
504 	u32 dst_addr_widths;
505 	u32 directions;
506 	u32 min_burst;
507 	u32 max_burst;
508 	u32 max_sg_burst;
509 	bool cmd_pause;
510 	bool cmd_resume;
511 	bool cmd_terminate;
512 	enum dma_residue_granularity residue_granularity;
513 	bool descriptor_reuse;
514 };
515 
dma_chan_name(struct dma_chan * chan)516 static inline const char *dma_chan_name(struct dma_chan *chan)
517 {
518 	return dev_name(&chan->dev->device);
519 }
520 
521 void dma_chan_cleanup(struct kref *kref);
522 
523 /**
524  * typedef dma_filter_fn - callback filter for dma_request_channel
525  * @chan: channel to be reviewed
526  * @filter_param: opaque parameter passed through dma_request_channel
527  *
528  * When this optional parameter is specified in a call to dma_request_channel a
529  * suitable channel is passed to this routine for further dispositioning before
530  * being returned.  Where 'suitable' indicates a non-busy channel that
531  * satisfies the given capability mask.  It returns 'true' to indicate that the
532  * channel is suitable.
533  */
534 typedef bool (*dma_filter_fn)(struct dma_chan *chan, void *filter_param);
535 
536 typedef void (*dma_async_tx_callback)(void *dma_async_param);
537 
538 enum dmaengine_tx_result {
539 	DMA_TRANS_NOERROR = 0,		/* SUCCESS */
540 	DMA_TRANS_READ_FAILED,		/* Source DMA read failed */
541 	DMA_TRANS_WRITE_FAILED,		/* Destination DMA write failed */
542 	DMA_TRANS_ABORTED,		/* Op never submitted / aborted */
543 };
544 
545 struct dmaengine_result {
546 	enum dmaengine_tx_result result;
547 	u32 residue;
548 };
549 
550 typedef void (*dma_async_tx_callback_result)(void *dma_async_param,
551 				const struct dmaengine_result *result);
552 
553 struct dmaengine_unmap_data {
554 #if IS_ENABLED(CONFIG_DMA_ENGINE_RAID)
555 	u16 map_cnt;
556 #else
557 	u8 map_cnt;
558 #endif
559 	u8 to_cnt;
560 	u8 from_cnt;
561 	u8 bidi_cnt;
562 	struct device *dev;
563 	struct kref kref;
564 	size_t len;
565 	dma_addr_t addr[];
566 };
567 
568 struct dma_async_tx_descriptor;
569 
570 struct dma_descriptor_metadata_ops {
571 	int (*attach)(struct dma_async_tx_descriptor *desc, void *data,
572 		      size_t len);
573 
574 	void *(*get_ptr)(struct dma_async_tx_descriptor *desc,
575 			 size_t *payload_len, size_t *max_len);
576 	int (*set_len)(struct dma_async_tx_descriptor *desc,
577 		       size_t payload_len);
578 };
579 
580 /**
581  * struct dma_async_tx_descriptor - async transaction descriptor
582  * ---dma generic offload fields---
583  * @cookie: tracking cookie for this transaction, set to -EBUSY if
584  *	this tx is sitting on a dependency list
585  * @flags: flags to augment operation preparation, control completion, and
586  *	communicate status
587  * @phys: physical address of the descriptor
588  * @chan: target channel for this operation
589  * @tx_submit: accept the descriptor, assign ordered cookie and mark the
590  * descriptor pending. To be pushed on .issue_pending() call
591  * @callback: routine to call after this operation is complete
592  * @callback_param: general parameter to pass to the callback routine
593  * @desc_metadata_mode: core managed metadata mode to protect mixed use of
594  *	DESC_METADATA_CLIENT or DESC_METADATA_ENGINE. Otherwise
595  *	DESC_METADATA_NONE
596  * @metadata_ops: DMA driver provided metadata mode ops, need to be set by the
597  *	DMA driver if metadata mode is supported with the descriptor
598  * ---async_tx api specific fields---
599  * @next: at completion submit this descriptor
600  * @parent: pointer to the next level up in the dependency chain
601  * @lock: protect the parent and next pointers
602  */
603 struct dma_async_tx_descriptor {
604 	dma_cookie_t cookie;
605 	enum dma_ctrl_flags flags; /* not a 'long' to pack with cookie */
606 	dma_addr_t phys;
607 	struct dma_chan *chan;
608 	dma_cookie_t (*tx_submit)(struct dma_async_tx_descriptor *tx);
609 	int (*desc_free)(struct dma_async_tx_descriptor *tx);
610 	dma_async_tx_callback callback;
611 	dma_async_tx_callback_result callback_result;
612 	void *callback_param;
613 	struct dmaengine_unmap_data *unmap;
614 	enum dma_desc_metadata_mode desc_metadata_mode;
615 	struct dma_descriptor_metadata_ops *metadata_ops;
616 #ifdef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH
617 	struct dma_async_tx_descriptor *next;
618 	struct dma_async_tx_descriptor *parent;
619 	spinlock_t lock;
620 #endif
621 };
622 
623 #ifdef CONFIG_DMA_ENGINE
dma_set_unmap(struct dma_async_tx_descriptor * tx,struct dmaengine_unmap_data * unmap)624 static inline void dma_set_unmap(struct dma_async_tx_descriptor *tx,
625 				 struct dmaengine_unmap_data *unmap)
626 {
627 	kref_get(&unmap->kref);
628 	tx->unmap = unmap;
629 }
630 
631 struct dmaengine_unmap_data *
632 dmaengine_get_unmap_data(struct device *dev, int nr, gfp_t flags);
633 void dmaengine_unmap_put(struct dmaengine_unmap_data *unmap);
634 #else
dma_set_unmap(struct dma_async_tx_descriptor * tx,struct dmaengine_unmap_data * unmap)635 static inline void dma_set_unmap(struct dma_async_tx_descriptor *tx,
636 				 struct dmaengine_unmap_data *unmap)
637 {
638 }
639 static inline struct dmaengine_unmap_data *
dmaengine_get_unmap_data(struct device * dev,int nr,gfp_t flags)640 dmaengine_get_unmap_data(struct device *dev, int nr, gfp_t flags)
641 {
642 	return NULL;
643 }
dmaengine_unmap_put(struct dmaengine_unmap_data * unmap)644 static inline void dmaengine_unmap_put(struct dmaengine_unmap_data *unmap)
645 {
646 }
647 #endif
648 
dma_descriptor_unmap(struct dma_async_tx_descriptor * tx)649 static inline void dma_descriptor_unmap(struct dma_async_tx_descriptor *tx)
650 {
651 	if (!tx->unmap)
652 		return;
653 
654 	dmaengine_unmap_put(tx->unmap);
655 	tx->unmap = NULL;
656 }
657 
658 #ifndef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH
txd_lock(struct dma_async_tx_descriptor * txd)659 static inline void txd_lock(struct dma_async_tx_descriptor *txd)
660 {
661 }
txd_unlock(struct dma_async_tx_descriptor * txd)662 static inline void txd_unlock(struct dma_async_tx_descriptor *txd)
663 {
664 }
txd_chain(struct dma_async_tx_descriptor * txd,struct dma_async_tx_descriptor * next)665 static inline void txd_chain(struct dma_async_tx_descriptor *txd, struct dma_async_tx_descriptor *next)
666 {
667 	BUG();
668 }
txd_clear_parent(struct dma_async_tx_descriptor * txd)669 static inline void txd_clear_parent(struct dma_async_tx_descriptor *txd)
670 {
671 }
txd_clear_next(struct dma_async_tx_descriptor * txd)672 static inline void txd_clear_next(struct dma_async_tx_descriptor *txd)
673 {
674 }
txd_next(struct dma_async_tx_descriptor * txd)675 static inline struct dma_async_tx_descriptor *txd_next(struct dma_async_tx_descriptor *txd)
676 {
677 	return NULL;
678 }
txd_parent(struct dma_async_tx_descriptor * txd)679 static inline struct dma_async_tx_descriptor *txd_parent(struct dma_async_tx_descriptor *txd)
680 {
681 	return NULL;
682 }
683 
684 #else
txd_lock(struct dma_async_tx_descriptor * txd)685 static inline void txd_lock(struct dma_async_tx_descriptor *txd)
686 {
687 	spin_lock_bh(&txd->lock);
688 }
txd_unlock(struct dma_async_tx_descriptor * txd)689 static inline void txd_unlock(struct dma_async_tx_descriptor *txd)
690 {
691 	spin_unlock_bh(&txd->lock);
692 }
txd_chain(struct dma_async_tx_descriptor * txd,struct dma_async_tx_descriptor * next)693 static inline void txd_chain(struct dma_async_tx_descriptor *txd, struct dma_async_tx_descriptor *next)
694 {
695 	txd->next = next;
696 	next->parent = txd;
697 }
txd_clear_parent(struct dma_async_tx_descriptor * txd)698 static inline void txd_clear_parent(struct dma_async_tx_descriptor *txd)
699 {
700 	txd->parent = NULL;
701 }
txd_clear_next(struct dma_async_tx_descriptor * txd)702 static inline void txd_clear_next(struct dma_async_tx_descriptor *txd)
703 {
704 	txd->next = NULL;
705 }
txd_parent(struct dma_async_tx_descriptor * txd)706 static inline struct dma_async_tx_descriptor *txd_parent(struct dma_async_tx_descriptor *txd)
707 {
708 	return txd->parent;
709 }
txd_next(struct dma_async_tx_descriptor * txd)710 static inline struct dma_async_tx_descriptor *txd_next(struct dma_async_tx_descriptor *txd)
711 {
712 	return txd->next;
713 }
714 #endif
715 
716 /**
717  * struct dma_tx_state - filled in to report the status of
718  * a transfer.
719  * @last: last completed DMA cookie
720  * @used: last issued DMA cookie (i.e. the one in progress)
721  * @residue: the remaining number of bytes left to transmit
722  *	on the selected transfer for states DMA_IN_PROGRESS and
723  *	DMA_PAUSED if this is implemented in the driver, else 0
724  * @in_flight_bytes: amount of data in bytes cached by the DMA.
725  */
726 struct dma_tx_state {
727 	dma_cookie_t last;
728 	dma_cookie_t used;
729 	u32 residue;
730 	u32 in_flight_bytes;
731 };
732 
733 /**
734  * enum dmaengine_alignment - defines alignment of the DMA async tx
735  * buffers
736  */
737 enum dmaengine_alignment {
738 	DMAENGINE_ALIGN_1_BYTE = 0,
739 	DMAENGINE_ALIGN_2_BYTES = 1,
740 	DMAENGINE_ALIGN_4_BYTES = 2,
741 	DMAENGINE_ALIGN_8_BYTES = 3,
742 	DMAENGINE_ALIGN_16_BYTES = 4,
743 	DMAENGINE_ALIGN_32_BYTES = 5,
744 	DMAENGINE_ALIGN_64_BYTES = 6,
745 	DMAENGINE_ALIGN_128_BYTES = 7,
746 	DMAENGINE_ALIGN_256_BYTES = 8,
747 };
748 
749 /**
750  * struct dma_slave_map - associates slave device and it's slave channel with
751  * parameter to be used by a filter function
752  * @devname: name of the device
753  * @slave: slave channel name
754  * @param: opaque parameter to pass to struct dma_filter.fn
755  */
756 struct dma_slave_map {
757 	const char *devname;
758 	const char *slave;
759 	void *param;
760 };
761 
762 /**
763  * struct dma_filter - information for slave device/channel to filter_fn/param
764  * mapping
765  * @fn: filter function callback
766  * @mapcnt: number of slave device/channel in the map
767  * @map: array of channel to filter mapping data
768  */
769 struct dma_filter {
770 	dma_filter_fn fn;
771 	int mapcnt;
772 	const struct dma_slave_map *map;
773 };
774 
775 /**
776  * struct dma_device - info on the entity supplying DMA services
777  * @chancnt: how many DMA channels are supported
778  * @privatecnt: how many DMA channels are requested by dma_request_channel
779  * @channels: the list of struct dma_chan
780  * @global_node: list_head for global dma_device_list
781  * @filter: information for device/slave to filter function/param mapping
782  * @cap_mask: one or more dma_capability flags
783  * @desc_metadata_modes: supported metadata modes by the DMA device
784  * @max_xor: maximum number of xor sources, 0 if no capability
785  * @max_pq: maximum number of PQ sources and PQ-continue capability
786  * @copy_align: alignment shift for memcpy operations
787  * @xor_align: alignment shift for xor operations
788  * @pq_align: alignment shift for pq operations
789  * @fill_align: alignment shift for memset operations
790  * @dev_id: unique device ID
791  * @dev: struct device reference for dma mapping api
792  * @owner: owner module (automatically set based on the provided dev)
793  * @src_addr_widths: bit mask of src addr widths the device supports
794  *	Width is specified in bytes, e.g. for a device supporting
795  *	a width of 4 the mask should have BIT(4) set.
796  * @dst_addr_widths: bit mask of dst addr widths the device supports
797  * @directions: bit mask of slave directions the device supports.
798  *	Since the enum dma_transfer_direction is not defined as bit flag for
799  *	each type, the dma controller should set BIT(<TYPE>) and same
800  *	should be checked by controller as well
801  * @min_burst: min burst capability per-transfer
802  * @max_burst: max burst capability per-transfer
803  * @max_sg_burst: max number of SG list entries executed in a single burst
804  *	DMA tansaction with no software intervention for reinitialization.
805  *	Zero value means unlimited number of entries.
806  * @residue_granularity: granularity of the transfer residue reported
807  *	by tx_status
808  * @device_alloc_chan_resources: allocate resources and return the
809  *	number of allocated descriptors
810  * @device_router_config: optional callback for DMA router configuration
811  * @device_free_chan_resources: release DMA channel's resources
812  * @device_prep_dma_memcpy: prepares a memcpy operation
813  * @device_prep_dma_xor: prepares a xor operation
814  * @device_prep_dma_xor_val: prepares a xor validation operation
815  * @device_prep_dma_pq: prepares a pq operation
816  * @device_prep_dma_pq_val: prepares a pqzero_sum operation
817  * @device_prep_dma_memset: prepares a memset operation
818  * @device_prep_dma_memset_sg: prepares a memset operation over a scatter list
819  * @device_prep_dma_interrupt: prepares an end of chain interrupt operation
820  * @device_prep_slave_sg: prepares a slave dma operation
821  * @device_prep_dma_cyclic: prepare a cyclic dma operation suitable for audio.
822  *	The function takes a buffer of size buf_len. The callback function will
823  *	be called after period_len bytes have been transferred.
824  * @device_prep_interleaved_dma: Transfer expression in a generic way.
825  * @device_prep_dma_imm_data: DMA's 8 byte immediate data to the dst address
826  * @device_caps: May be used to override the generic DMA slave capabilities
827  *	with per-channel specific ones
828  * @device_config: Pushes a new configuration to a channel, return 0 or an error
829  *	code
830  * @device_pause: Pauses any transfer happening on a channel. Returns
831  *	0 or an error code
832  * @device_resume: Resumes any transfer on a channel previously
833  *	paused. Returns 0 or an error code
834  * @device_terminate_all: Aborts all transfers on a channel. Returns 0
835  *	or an error code
836  * @device_synchronize: Synchronizes the termination of a transfers to the
837  *  current context.
838  * @device_tx_status: poll for transaction completion, the optional
839  *	txstate parameter can be supplied with a pointer to get a
840  *	struct with auxiliary transfer status information, otherwise the call
841  *	will just return a simple status code
842  * @device_issue_pending: push pending transactions to hardware
843  * @descriptor_reuse: a submitted transfer can be resubmitted after completion
844  * @device_release: called sometime atfer dma_async_device_unregister() is
845  *     called and there are no further references to this structure. This
846  *     must be implemented to free resources however many existing drivers
847  *     do not and are therefore not safe to unbind while in use.
848  * @dbg_summary_show: optional routine to show contents in debugfs; default code
849  *     will be used when this is omitted, but custom code can show extra,
850  *     controller specific information.
851  */
852 struct dma_device {
853 	struct kref ref;
854 	unsigned int chancnt;
855 	unsigned int privatecnt;
856 	struct list_head channels;
857 	struct list_head global_node;
858 	struct dma_filter filter;
859 	dma_cap_mask_t  cap_mask;
860 	enum dma_desc_metadata_mode desc_metadata_modes;
861 	unsigned short max_xor;
862 	unsigned short max_pq;
863 	enum dmaengine_alignment copy_align;
864 	enum dmaengine_alignment xor_align;
865 	enum dmaengine_alignment pq_align;
866 	enum dmaengine_alignment fill_align;
867 	#define DMA_HAS_PQ_CONTINUE (1 << 15)
868 
869 	int dev_id;
870 	struct device *dev;
871 	struct module *owner;
872 	struct ida chan_ida;
873 
874 	u32 src_addr_widths;
875 	u32 dst_addr_widths;
876 	u32 directions;
877 	u32 min_burst;
878 	u32 max_burst;
879 	u32 max_sg_burst;
880 	bool descriptor_reuse;
881 	enum dma_residue_granularity residue_granularity;
882 
883 	int (*device_alloc_chan_resources)(struct dma_chan *chan);
884 	int (*device_router_config)(struct dma_chan *chan);
885 	void (*device_free_chan_resources)(struct dma_chan *chan);
886 
887 	struct dma_async_tx_descriptor *(*device_prep_dma_memcpy)(
888 		struct dma_chan *chan, dma_addr_t dst, dma_addr_t src,
889 		size_t len, unsigned long flags);
890 	struct dma_async_tx_descriptor *(*device_prep_dma_memcpy_sg)(
891 		struct dma_chan *chan,
892 		struct scatterlist *dst_sg, unsigned int dst_nents,
893 		struct scatterlist *src_sg, unsigned int src_nents,
894 		unsigned long flags);
895 	struct dma_async_tx_descriptor *(*device_prep_dma_xor)(
896 		struct dma_chan *chan, dma_addr_t dst, dma_addr_t *src,
897 		unsigned int src_cnt, size_t len, unsigned long flags);
898 	struct dma_async_tx_descriptor *(*device_prep_dma_xor_val)(
899 		struct dma_chan *chan, dma_addr_t *src,	unsigned int src_cnt,
900 		size_t len, enum sum_check_flags *result, unsigned long flags);
901 	struct dma_async_tx_descriptor *(*device_prep_dma_pq)(
902 		struct dma_chan *chan, dma_addr_t *dst, dma_addr_t *src,
903 		unsigned int src_cnt, const unsigned char *scf,
904 		size_t len, unsigned long flags);
905 	struct dma_async_tx_descriptor *(*device_prep_dma_pq_val)(
906 		struct dma_chan *chan, dma_addr_t *pq, dma_addr_t *src,
907 		unsigned int src_cnt, const unsigned char *scf, size_t len,
908 		enum sum_check_flags *pqres, unsigned long flags);
909 	struct dma_async_tx_descriptor *(*device_prep_dma_memset)(
910 		struct dma_chan *chan, dma_addr_t dest, int value, size_t len,
911 		unsigned long flags);
912 	struct dma_async_tx_descriptor *(*device_prep_dma_memset_sg)(
913 		struct dma_chan *chan, struct scatterlist *sg,
914 		unsigned int nents, int value, unsigned long flags);
915 	struct dma_async_tx_descriptor *(*device_prep_dma_interrupt)(
916 		struct dma_chan *chan, unsigned long flags);
917 
918 	struct dma_async_tx_descriptor *(*device_prep_slave_sg)(
919 		struct dma_chan *chan, struct scatterlist *sgl,
920 		unsigned int sg_len, enum dma_transfer_direction direction,
921 		unsigned long flags, void *context);
922 	struct dma_async_tx_descriptor *(*device_prep_dma_cyclic)(
923 		struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
924 		size_t period_len, enum dma_transfer_direction direction,
925 		unsigned long flags);
926 	struct dma_async_tx_descriptor *(*device_prep_interleaved_dma)(
927 		struct dma_chan *chan, struct dma_interleaved_template *xt,
928 		unsigned long flags);
929 	struct dma_async_tx_descriptor *(*device_prep_dma_imm_data)(
930 		struct dma_chan *chan, dma_addr_t dst, u64 data,
931 		unsigned long flags);
932 
933 	void (*device_caps)(struct dma_chan *chan,
934 			    struct dma_slave_caps *caps);
935 	int (*device_config)(struct dma_chan *chan,
936 			     struct dma_slave_config *config);
937 	int (*device_pause)(struct dma_chan *chan);
938 	int (*device_resume)(struct dma_chan *chan);
939 	int (*device_terminate_all)(struct dma_chan *chan);
940 	void (*device_synchronize)(struct dma_chan *chan);
941 
942 	enum dma_status (*device_tx_status)(struct dma_chan *chan,
943 					    dma_cookie_t cookie,
944 					    struct dma_tx_state *txstate);
945 	void (*device_issue_pending)(struct dma_chan *chan);
946 	void (*device_release)(struct dma_device *dev);
947 	/* debugfs support */
948 	void (*dbg_summary_show)(struct seq_file *s, struct dma_device *dev);
949 	struct dentry *dbg_dev_root;
950 };
951 
dmaengine_slave_config(struct dma_chan * chan,struct dma_slave_config * config)952 static inline int dmaengine_slave_config(struct dma_chan *chan,
953 					  struct dma_slave_config *config)
954 {
955 	if (chan->device->device_config)
956 		return chan->device->device_config(chan, config);
957 
958 	return -ENOSYS;
959 }
960 
is_slave_direction(enum dma_transfer_direction direction)961 static inline bool is_slave_direction(enum dma_transfer_direction direction)
962 {
963 	return (direction == DMA_MEM_TO_DEV) || (direction == DMA_DEV_TO_MEM);
964 }
965 
dmaengine_prep_slave_single(struct dma_chan * chan,dma_addr_t buf,size_t len,enum dma_transfer_direction dir,unsigned long flags)966 static inline struct dma_async_tx_descriptor *dmaengine_prep_slave_single(
967 	struct dma_chan *chan, dma_addr_t buf, size_t len,
968 	enum dma_transfer_direction dir, unsigned long flags)
969 {
970 	struct scatterlist sg;
971 	sg_init_table(&sg, 1);
972 	sg_dma_address(&sg) = buf;
973 	sg_dma_len(&sg) = len;
974 
975 	if (!chan || !chan->device || !chan->device->device_prep_slave_sg)
976 		return NULL;
977 
978 	return chan->device->device_prep_slave_sg(chan, &sg, 1,
979 						  dir, flags, NULL);
980 }
981 
dmaengine_prep_slave_sg(struct dma_chan * chan,struct scatterlist * sgl,unsigned int sg_len,enum dma_transfer_direction dir,unsigned long flags)982 static inline struct dma_async_tx_descriptor *dmaengine_prep_slave_sg(
983 	struct dma_chan *chan, struct scatterlist *sgl,	unsigned int sg_len,
984 	enum dma_transfer_direction dir, unsigned long flags)
985 {
986 	if (!chan || !chan->device || !chan->device->device_prep_slave_sg)
987 		return NULL;
988 
989 	return chan->device->device_prep_slave_sg(chan, sgl, sg_len,
990 						  dir, flags, NULL);
991 }
992 
993 #ifdef CONFIG_RAPIDIO_DMA_ENGINE
994 struct rio_dma_ext;
dmaengine_prep_rio_sg(struct dma_chan * chan,struct scatterlist * sgl,unsigned int sg_len,enum dma_transfer_direction dir,unsigned long flags,struct rio_dma_ext * rio_ext)995 static inline struct dma_async_tx_descriptor *dmaengine_prep_rio_sg(
996 	struct dma_chan *chan, struct scatterlist *sgl,	unsigned int sg_len,
997 	enum dma_transfer_direction dir, unsigned long flags,
998 	struct rio_dma_ext *rio_ext)
999 {
1000 	if (!chan || !chan->device || !chan->device->device_prep_slave_sg)
1001 		return NULL;
1002 
1003 	return chan->device->device_prep_slave_sg(chan, sgl, sg_len,
1004 						  dir, flags, rio_ext);
1005 }
1006 #endif
1007 
dmaengine_prep_dma_cyclic(struct dma_chan * chan,dma_addr_t buf_addr,size_t buf_len,size_t period_len,enum dma_transfer_direction dir,unsigned long flags)1008 static inline struct dma_async_tx_descriptor *dmaengine_prep_dma_cyclic(
1009 		struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
1010 		size_t period_len, enum dma_transfer_direction dir,
1011 		unsigned long flags)
1012 {
1013 	if (!chan || !chan->device || !chan->device->device_prep_dma_cyclic)
1014 		return NULL;
1015 
1016 	return chan->device->device_prep_dma_cyclic(chan, buf_addr, buf_len,
1017 						period_len, dir, flags);
1018 }
1019 
dmaengine_prep_interleaved_dma(struct dma_chan * chan,struct dma_interleaved_template * xt,unsigned long flags)1020 static inline struct dma_async_tx_descriptor *dmaengine_prep_interleaved_dma(
1021 		struct dma_chan *chan, struct dma_interleaved_template *xt,
1022 		unsigned long flags)
1023 {
1024 	if (!chan || !chan->device || !chan->device->device_prep_interleaved_dma)
1025 		return NULL;
1026 	if (flags & DMA_PREP_REPEAT &&
1027 	    !test_bit(DMA_REPEAT, chan->device->cap_mask.bits))
1028 		return NULL;
1029 
1030 	return chan->device->device_prep_interleaved_dma(chan, xt, flags);
1031 }
1032 
1033 /**
1034  * dmaengine_prep_dma_memset() - Prepare a DMA memset descriptor.
1035  * @chan: The channel to be used for this descriptor
1036  * @dest: Address of buffer to be set
1037  * @value: Treated as a single byte value that fills the destination buffer
1038  * @len: The total size of dest
1039  * @flags: DMA engine flags
1040  */
dmaengine_prep_dma_memset(struct dma_chan * chan,dma_addr_t dest,int value,size_t len,unsigned long flags)1041 static inline struct dma_async_tx_descriptor *dmaengine_prep_dma_memset(
1042 		struct dma_chan *chan, dma_addr_t dest, int value, size_t len,
1043 		unsigned long flags)
1044 {
1045 	if (!chan || !chan->device || !chan->device->device_prep_dma_memset)
1046 		return NULL;
1047 
1048 	return chan->device->device_prep_dma_memset(chan, dest, value,
1049 						    len, flags);
1050 }
1051 
dmaengine_prep_dma_memcpy(struct dma_chan * chan,dma_addr_t dest,dma_addr_t src,size_t len,unsigned long flags)1052 static inline struct dma_async_tx_descriptor *dmaengine_prep_dma_memcpy(
1053 		struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
1054 		size_t len, unsigned long flags)
1055 {
1056 	if (!chan || !chan->device || !chan->device->device_prep_dma_memcpy)
1057 		return NULL;
1058 
1059 	return chan->device->device_prep_dma_memcpy(chan, dest, src,
1060 						    len, flags);
1061 }
1062 
dmaengine_prep_dma_memcpy_sg(struct dma_chan * chan,struct scatterlist * dst_sg,unsigned int dst_nents,struct scatterlist * src_sg,unsigned int src_nents,unsigned long flags)1063 static inline struct dma_async_tx_descriptor *dmaengine_prep_dma_memcpy_sg(
1064 		struct dma_chan *chan,
1065 		struct scatterlist *dst_sg, unsigned int dst_nents,
1066 		struct scatterlist *src_sg, unsigned int src_nents,
1067 		unsigned long flags)
1068 {
1069 	if (!chan || !chan->device || !chan->device->device_prep_dma_memcpy_sg)
1070 		return NULL;
1071 
1072 	return chan->device->device_prep_dma_memcpy_sg(chan, dst_sg, dst_nents,
1073 						       src_sg, src_nents,
1074 						       flags);
1075 }
1076 
dmaengine_is_metadata_mode_supported(struct dma_chan * chan,enum dma_desc_metadata_mode mode)1077 static inline bool dmaengine_is_metadata_mode_supported(struct dma_chan *chan,
1078 		enum dma_desc_metadata_mode mode)
1079 {
1080 	if (!chan)
1081 		return false;
1082 
1083 	return !!(chan->device->desc_metadata_modes & mode);
1084 }
1085 
1086 #ifdef CONFIG_DMA_ENGINE
1087 int dmaengine_desc_attach_metadata(struct dma_async_tx_descriptor *desc,
1088 				   void *data, size_t len);
1089 void *dmaengine_desc_get_metadata_ptr(struct dma_async_tx_descriptor *desc,
1090 				      size_t *payload_len, size_t *max_len);
1091 int dmaengine_desc_set_metadata_len(struct dma_async_tx_descriptor *desc,
1092 				    size_t payload_len);
1093 #else /* CONFIG_DMA_ENGINE */
dmaengine_desc_attach_metadata(struct dma_async_tx_descriptor * desc,void * data,size_t len)1094 static inline int dmaengine_desc_attach_metadata(
1095 		struct dma_async_tx_descriptor *desc, void *data, size_t len)
1096 {
1097 	return -EINVAL;
1098 }
dmaengine_desc_get_metadata_ptr(struct dma_async_tx_descriptor * desc,size_t * payload_len,size_t * max_len)1099 static inline void *dmaengine_desc_get_metadata_ptr(
1100 		struct dma_async_tx_descriptor *desc, size_t *payload_len,
1101 		size_t *max_len)
1102 {
1103 	return NULL;
1104 }
dmaengine_desc_set_metadata_len(struct dma_async_tx_descriptor * desc,size_t payload_len)1105 static inline int dmaengine_desc_set_metadata_len(
1106 		struct dma_async_tx_descriptor *desc, size_t payload_len)
1107 {
1108 	return -EINVAL;
1109 }
1110 #endif /* CONFIG_DMA_ENGINE */
1111 
1112 /**
1113  * dmaengine_terminate_all() - Terminate all active DMA transfers
1114  * @chan: The channel for which to terminate the transfers
1115  *
1116  * This function is DEPRECATED use either dmaengine_terminate_sync() or
1117  * dmaengine_terminate_async() instead.
1118  */
dmaengine_terminate_all(struct dma_chan * chan)1119 static inline int dmaengine_terminate_all(struct dma_chan *chan)
1120 {
1121 	if (chan->device->device_terminate_all)
1122 		return chan->device->device_terminate_all(chan);
1123 
1124 	return -ENOSYS;
1125 }
1126 
1127 /**
1128  * dmaengine_terminate_async() - Terminate all active DMA transfers
1129  * @chan: The channel for which to terminate the transfers
1130  *
1131  * Calling this function will terminate all active and pending descriptors
1132  * that have previously been submitted to the channel. It is not guaranteed
1133  * though that the transfer for the active descriptor has stopped when the
1134  * function returns. Furthermore it is possible the complete callback of a
1135  * submitted transfer is still running when this function returns.
1136  *
1137  * dmaengine_synchronize() needs to be called before it is safe to free
1138  * any memory that is accessed by previously submitted descriptors or before
1139  * freeing any resources accessed from within the completion callback of any
1140  * previously submitted descriptors.
1141  *
1142  * This function can be called from atomic context as well as from within a
1143  * complete callback of a descriptor submitted on the same channel.
1144  *
1145  * If none of the two conditions above apply consider using
1146  * dmaengine_terminate_sync() instead.
1147  */
dmaengine_terminate_async(struct dma_chan * chan)1148 static inline int dmaengine_terminate_async(struct dma_chan *chan)
1149 {
1150 	if (chan->device->device_terminate_all)
1151 		return chan->device->device_terminate_all(chan);
1152 
1153 	return -EINVAL;
1154 }
1155 
1156 /**
1157  * dmaengine_synchronize() - Synchronize DMA channel termination
1158  * @chan: The channel to synchronize
1159  *
1160  * Synchronizes to the DMA channel termination to the current context. When this
1161  * function returns it is guaranteed that all transfers for previously issued
1162  * descriptors have stopped and it is safe to free the memory associated
1163  * with them. Furthermore it is guaranteed that all complete callback functions
1164  * for a previously submitted descriptor have finished running and it is safe to
1165  * free resources accessed from within the complete callbacks.
1166  *
1167  * The behavior of this function is undefined if dma_async_issue_pending() has
1168  * been called between dmaengine_terminate_async() and this function.
1169  *
1170  * This function must only be called from non-atomic context and must not be
1171  * called from within a complete callback of a descriptor submitted on the same
1172  * channel.
1173  */
dmaengine_synchronize(struct dma_chan * chan)1174 static inline void dmaengine_synchronize(struct dma_chan *chan)
1175 {
1176 	might_sleep();
1177 
1178 	if (chan->device->device_synchronize)
1179 		chan->device->device_synchronize(chan);
1180 }
1181 
1182 /**
1183  * dmaengine_terminate_sync() - Terminate all active DMA transfers
1184  * @chan: The channel for which to terminate the transfers
1185  *
1186  * Calling this function will terminate all active and pending transfers
1187  * that have previously been submitted to the channel. It is similar to
1188  * dmaengine_terminate_async() but guarantees that the DMA transfer has actually
1189  * stopped and that all complete callbacks have finished running when the
1190  * function returns.
1191  *
1192  * This function must only be called from non-atomic context and must not be
1193  * called from within a complete callback of a descriptor submitted on the same
1194  * channel.
1195  */
dmaengine_terminate_sync(struct dma_chan * chan)1196 static inline int dmaengine_terminate_sync(struct dma_chan *chan)
1197 {
1198 	int ret;
1199 
1200 	ret = dmaengine_terminate_async(chan);
1201 	if (ret)
1202 		return ret;
1203 
1204 	dmaengine_synchronize(chan);
1205 
1206 	return 0;
1207 }
1208 
dmaengine_pause(struct dma_chan * chan)1209 static inline int dmaengine_pause(struct dma_chan *chan)
1210 {
1211 	if (chan->device->device_pause)
1212 		return chan->device->device_pause(chan);
1213 
1214 	return -ENOSYS;
1215 }
1216 
dmaengine_resume(struct dma_chan * chan)1217 static inline int dmaengine_resume(struct dma_chan *chan)
1218 {
1219 	if (chan->device->device_resume)
1220 		return chan->device->device_resume(chan);
1221 
1222 	return -ENOSYS;
1223 }
1224 
dmaengine_tx_status(struct dma_chan * chan,dma_cookie_t cookie,struct dma_tx_state * state)1225 static inline enum dma_status dmaengine_tx_status(struct dma_chan *chan,
1226 	dma_cookie_t cookie, struct dma_tx_state *state)
1227 {
1228 	return chan->device->device_tx_status(chan, cookie, state);
1229 }
1230 
dmaengine_submit(struct dma_async_tx_descriptor * desc)1231 static inline dma_cookie_t dmaengine_submit(struct dma_async_tx_descriptor *desc)
1232 {
1233 	return desc->tx_submit(desc);
1234 }
1235 
dmaengine_check_align(enum dmaengine_alignment align,size_t off1,size_t off2,size_t len)1236 static inline bool dmaengine_check_align(enum dmaengine_alignment align,
1237 					 size_t off1, size_t off2, size_t len)
1238 {
1239 	return !(((1 << align) - 1) & (off1 | off2 | len));
1240 }
1241 
is_dma_copy_aligned(struct dma_device * dev,size_t off1,size_t off2,size_t len)1242 static inline bool is_dma_copy_aligned(struct dma_device *dev, size_t off1,
1243 				       size_t off2, size_t len)
1244 {
1245 	return dmaengine_check_align(dev->copy_align, off1, off2, len);
1246 }
1247 
is_dma_xor_aligned(struct dma_device * dev,size_t off1,size_t off2,size_t len)1248 static inline bool is_dma_xor_aligned(struct dma_device *dev, size_t off1,
1249 				      size_t off2, size_t len)
1250 {
1251 	return dmaengine_check_align(dev->xor_align, off1, off2, len);
1252 }
1253 
is_dma_pq_aligned(struct dma_device * dev,size_t off1,size_t off2,size_t len)1254 static inline bool is_dma_pq_aligned(struct dma_device *dev, size_t off1,
1255 				     size_t off2, size_t len)
1256 {
1257 	return dmaengine_check_align(dev->pq_align, off1, off2, len);
1258 }
1259 
is_dma_fill_aligned(struct dma_device * dev,size_t off1,size_t off2,size_t len)1260 static inline bool is_dma_fill_aligned(struct dma_device *dev, size_t off1,
1261 				       size_t off2, size_t len)
1262 {
1263 	return dmaengine_check_align(dev->fill_align, off1, off2, len);
1264 }
1265 
1266 static inline void
dma_set_maxpq(struct dma_device * dma,int maxpq,int has_pq_continue)1267 dma_set_maxpq(struct dma_device *dma, int maxpq, int has_pq_continue)
1268 {
1269 	dma->max_pq = maxpq;
1270 	if (has_pq_continue)
1271 		dma->max_pq |= DMA_HAS_PQ_CONTINUE;
1272 }
1273 
dmaf_continue(enum dma_ctrl_flags flags)1274 static inline bool dmaf_continue(enum dma_ctrl_flags flags)
1275 {
1276 	return (flags & DMA_PREP_CONTINUE) == DMA_PREP_CONTINUE;
1277 }
1278 
dmaf_p_disabled_continue(enum dma_ctrl_flags flags)1279 static inline bool dmaf_p_disabled_continue(enum dma_ctrl_flags flags)
1280 {
1281 	enum dma_ctrl_flags mask = DMA_PREP_CONTINUE | DMA_PREP_PQ_DISABLE_P;
1282 
1283 	return (flags & mask) == mask;
1284 }
1285 
dma_dev_has_pq_continue(struct dma_device * dma)1286 static inline bool dma_dev_has_pq_continue(struct dma_device *dma)
1287 {
1288 	return (dma->max_pq & DMA_HAS_PQ_CONTINUE) == DMA_HAS_PQ_CONTINUE;
1289 }
1290 
dma_dev_to_maxpq(struct dma_device * dma)1291 static inline unsigned short dma_dev_to_maxpq(struct dma_device *dma)
1292 {
1293 	return dma->max_pq & ~DMA_HAS_PQ_CONTINUE;
1294 }
1295 
1296 /* dma_maxpq - reduce maxpq in the face of continued operations
1297  * @dma - dma device with PQ capability
1298  * @flags - to check if DMA_PREP_CONTINUE and DMA_PREP_PQ_DISABLE_P are set
1299  *
1300  * When an engine does not support native continuation we need 3 extra
1301  * source slots to reuse P and Q with the following coefficients:
1302  * 1/ {00} * P : remove P from Q', but use it as a source for P'
1303  * 2/ {01} * Q : use Q to continue Q' calculation
1304  * 3/ {00} * Q : subtract Q from P' to cancel (2)
1305  *
1306  * In the case where P is disabled we only need 1 extra source:
1307  * 1/ {01} * Q : use Q to continue Q' calculation
1308  */
dma_maxpq(struct dma_device * dma,enum dma_ctrl_flags flags)1309 static inline int dma_maxpq(struct dma_device *dma, enum dma_ctrl_flags flags)
1310 {
1311 	if (dma_dev_has_pq_continue(dma) || !dmaf_continue(flags))
1312 		return dma_dev_to_maxpq(dma);
1313 	if (dmaf_p_disabled_continue(flags))
1314 		return dma_dev_to_maxpq(dma) - 1;
1315 	if (dmaf_continue(flags))
1316 		return dma_dev_to_maxpq(dma) - 3;
1317 	BUG();
1318 }
1319 
dmaengine_get_icg(bool inc,bool sgl,size_t icg,size_t dir_icg)1320 static inline size_t dmaengine_get_icg(bool inc, bool sgl, size_t icg,
1321 				      size_t dir_icg)
1322 {
1323 	if (inc) {
1324 		if (dir_icg)
1325 			return dir_icg;
1326 		if (sgl)
1327 			return icg;
1328 	}
1329 
1330 	return 0;
1331 }
1332 
dmaengine_get_dst_icg(struct dma_interleaved_template * xt,struct data_chunk * chunk)1333 static inline size_t dmaengine_get_dst_icg(struct dma_interleaved_template *xt,
1334 					   struct data_chunk *chunk)
1335 {
1336 	return dmaengine_get_icg(xt->dst_inc, xt->dst_sgl,
1337 				 chunk->icg, chunk->dst_icg);
1338 }
1339 
dmaengine_get_src_icg(struct dma_interleaved_template * xt,struct data_chunk * chunk)1340 static inline size_t dmaengine_get_src_icg(struct dma_interleaved_template *xt,
1341 					   struct data_chunk *chunk)
1342 {
1343 	return dmaengine_get_icg(xt->src_inc, xt->src_sgl,
1344 				 chunk->icg, chunk->src_icg);
1345 }
1346 
1347 /* --- public DMA engine API --- */
1348 
1349 #ifdef CONFIG_DMA_ENGINE
1350 void dmaengine_get(void);
1351 void dmaengine_put(void);
1352 #else
dmaengine_get(void)1353 static inline void dmaengine_get(void)
1354 {
1355 }
dmaengine_put(void)1356 static inline void dmaengine_put(void)
1357 {
1358 }
1359 #endif
1360 
1361 #ifdef CONFIG_ASYNC_TX_DMA
1362 #define async_dmaengine_get()	dmaengine_get()
1363 #define async_dmaengine_put()	dmaengine_put()
1364 #ifndef CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH
1365 #define async_dma_find_channel(type) dma_find_channel(DMA_ASYNC_TX)
1366 #else
1367 #define async_dma_find_channel(type) dma_find_channel(type)
1368 #endif /* CONFIG_ASYNC_TX_ENABLE_CHANNEL_SWITCH */
1369 #else
async_dmaengine_get(void)1370 static inline void async_dmaengine_get(void)
1371 {
1372 }
async_dmaengine_put(void)1373 static inline void async_dmaengine_put(void)
1374 {
1375 }
1376 static inline struct dma_chan *
async_dma_find_channel(enum dma_transaction_type type)1377 async_dma_find_channel(enum dma_transaction_type type)
1378 {
1379 	return NULL;
1380 }
1381 #endif /* CONFIG_ASYNC_TX_DMA */
1382 void dma_async_tx_descriptor_init(struct dma_async_tx_descriptor *tx,
1383 				  struct dma_chan *chan);
1384 
async_tx_ack(struct dma_async_tx_descriptor * tx)1385 static inline void async_tx_ack(struct dma_async_tx_descriptor *tx)
1386 {
1387 	tx->flags |= DMA_CTRL_ACK;
1388 }
1389 
async_tx_clear_ack(struct dma_async_tx_descriptor * tx)1390 static inline void async_tx_clear_ack(struct dma_async_tx_descriptor *tx)
1391 {
1392 	tx->flags &= ~DMA_CTRL_ACK;
1393 }
1394 
async_tx_test_ack(struct dma_async_tx_descriptor * tx)1395 static inline bool async_tx_test_ack(struct dma_async_tx_descriptor *tx)
1396 {
1397 	return (tx->flags & DMA_CTRL_ACK) == DMA_CTRL_ACK;
1398 }
1399 
1400 #define dma_cap_set(tx, mask) __dma_cap_set((tx), &(mask))
1401 static inline void
__dma_cap_set(enum dma_transaction_type tx_type,dma_cap_mask_t * dstp)1402 __dma_cap_set(enum dma_transaction_type tx_type, dma_cap_mask_t *dstp)
1403 {
1404 	set_bit(tx_type, dstp->bits);
1405 }
1406 
1407 #define dma_cap_clear(tx, mask) __dma_cap_clear((tx), &(mask))
1408 static inline void
__dma_cap_clear(enum dma_transaction_type tx_type,dma_cap_mask_t * dstp)1409 __dma_cap_clear(enum dma_transaction_type tx_type, dma_cap_mask_t *dstp)
1410 {
1411 	clear_bit(tx_type, dstp->bits);
1412 }
1413 
1414 #define dma_cap_zero(mask) __dma_cap_zero(&(mask))
__dma_cap_zero(dma_cap_mask_t * dstp)1415 static inline void __dma_cap_zero(dma_cap_mask_t *dstp)
1416 {
1417 	bitmap_zero(dstp->bits, DMA_TX_TYPE_END);
1418 }
1419 
1420 #define dma_has_cap(tx, mask) __dma_has_cap((tx), &(mask))
1421 static inline int
__dma_has_cap(enum dma_transaction_type tx_type,dma_cap_mask_t * srcp)1422 __dma_has_cap(enum dma_transaction_type tx_type, dma_cap_mask_t *srcp)
1423 {
1424 	return test_bit(tx_type, srcp->bits);
1425 }
1426 
1427 #define for_each_dma_cap_mask(cap, mask) \
1428 	for_each_set_bit(cap, mask.bits, DMA_TX_TYPE_END)
1429 
1430 /**
1431  * dma_async_issue_pending - flush pending transactions to HW
1432  * @chan: target DMA channel
1433  *
1434  * This allows drivers to push copies to HW in batches,
1435  * reducing MMIO writes where possible.
1436  */
dma_async_issue_pending(struct dma_chan * chan)1437 static inline void dma_async_issue_pending(struct dma_chan *chan)
1438 {
1439 	chan->device->device_issue_pending(chan);
1440 }
1441 
1442 /**
1443  * dma_async_is_tx_complete - poll for transaction completion
1444  * @chan: DMA channel
1445  * @cookie: transaction identifier to check status of
1446  * @last: returns last completed cookie, can be NULL
1447  * @used: returns last issued cookie, can be NULL
1448  *
1449  * If @last and @used are passed in, upon return they reflect the driver
1450  * internal state and can be used with dma_async_is_complete() to check
1451  * the status of multiple cookies without re-checking hardware state.
1452  */
dma_async_is_tx_complete(struct dma_chan * chan,dma_cookie_t cookie,dma_cookie_t * last,dma_cookie_t * used)1453 static inline enum dma_status dma_async_is_tx_complete(struct dma_chan *chan,
1454 	dma_cookie_t cookie, dma_cookie_t *last, dma_cookie_t *used)
1455 {
1456 	struct dma_tx_state state;
1457 	enum dma_status status;
1458 
1459 	status = chan->device->device_tx_status(chan, cookie, &state);
1460 	if (last)
1461 		*last = state.last;
1462 	if (used)
1463 		*used = state.used;
1464 	return status;
1465 }
1466 
1467 /**
1468  * dma_async_is_complete - test a cookie against chan state
1469  * @cookie: transaction identifier to test status of
1470  * @last_complete: last know completed transaction
1471  * @last_used: last cookie value handed out
1472  *
1473  * dma_async_is_complete() is used in dma_async_is_tx_complete()
1474  * the test logic is separated for lightweight testing of multiple cookies
1475  */
dma_async_is_complete(dma_cookie_t cookie,dma_cookie_t last_complete,dma_cookie_t last_used)1476 static inline enum dma_status dma_async_is_complete(dma_cookie_t cookie,
1477 			dma_cookie_t last_complete, dma_cookie_t last_used)
1478 {
1479 	if (last_complete <= last_used) {
1480 		if ((cookie <= last_complete) || (cookie > last_used))
1481 			return DMA_COMPLETE;
1482 	} else {
1483 		if ((cookie <= last_complete) && (cookie > last_used))
1484 			return DMA_COMPLETE;
1485 	}
1486 	return DMA_IN_PROGRESS;
1487 }
1488 
1489 static inline void
dma_set_tx_state(struct dma_tx_state * st,dma_cookie_t last,dma_cookie_t used,u32 residue)1490 dma_set_tx_state(struct dma_tx_state *st, dma_cookie_t last, dma_cookie_t used, u32 residue)
1491 {
1492 	if (!st)
1493 		return;
1494 
1495 	st->last = last;
1496 	st->used = used;
1497 	st->residue = residue;
1498 }
1499 
1500 #ifdef CONFIG_DMA_ENGINE
1501 struct dma_chan *dma_find_channel(enum dma_transaction_type tx_type);
1502 enum dma_status dma_sync_wait(struct dma_chan *chan, dma_cookie_t cookie);
1503 enum dma_status dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx);
1504 void dma_issue_pending_all(void);
1505 struct dma_chan *__dma_request_channel(const dma_cap_mask_t *mask,
1506 				       dma_filter_fn fn, void *fn_param,
1507 				       struct device_node *np);
1508 
1509 struct dma_chan *dma_request_chan(struct device *dev, const char *name);
1510 struct dma_chan *dma_request_chan_by_mask(const dma_cap_mask_t *mask);
1511 
1512 void dma_release_channel(struct dma_chan *chan);
1513 int dma_get_slave_caps(struct dma_chan *chan, struct dma_slave_caps *caps);
1514 #else
dma_find_channel(enum dma_transaction_type tx_type)1515 static inline struct dma_chan *dma_find_channel(enum dma_transaction_type tx_type)
1516 {
1517 	return NULL;
1518 }
dma_sync_wait(struct dma_chan * chan,dma_cookie_t cookie)1519 static inline enum dma_status dma_sync_wait(struct dma_chan *chan, dma_cookie_t cookie)
1520 {
1521 	return DMA_COMPLETE;
1522 }
dma_wait_for_async_tx(struct dma_async_tx_descriptor * tx)1523 static inline enum dma_status dma_wait_for_async_tx(struct dma_async_tx_descriptor *tx)
1524 {
1525 	return DMA_COMPLETE;
1526 }
dma_issue_pending_all(void)1527 static inline void dma_issue_pending_all(void)
1528 {
1529 }
__dma_request_channel(const dma_cap_mask_t * mask,dma_filter_fn fn,void * fn_param,struct device_node * np)1530 static inline struct dma_chan *__dma_request_channel(const dma_cap_mask_t *mask,
1531 						     dma_filter_fn fn,
1532 						     void *fn_param,
1533 						     struct device_node *np)
1534 {
1535 	return NULL;
1536 }
dma_request_chan(struct device * dev,const char * name)1537 static inline struct dma_chan *dma_request_chan(struct device *dev,
1538 						const char *name)
1539 {
1540 	return ERR_PTR(-ENODEV);
1541 }
dma_request_chan_by_mask(const dma_cap_mask_t * mask)1542 static inline struct dma_chan *dma_request_chan_by_mask(
1543 						const dma_cap_mask_t *mask)
1544 {
1545 	return ERR_PTR(-ENODEV);
1546 }
dma_release_channel(struct dma_chan * chan)1547 static inline void dma_release_channel(struct dma_chan *chan)
1548 {
1549 }
dma_get_slave_caps(struct dma_chan * chan,struct dma_slave_caps * caps)1550 static inline int dma_get_slave_caps(struct dma_chan *chan,
1551 				     struct dma_slave_caps *caps)
1552 {
1553 	return -ENXIO;
1554 }
1555 #endif
1556 
dmaengine_desc_set_reuse(struct dma_async_tx_descriptor * tx)1557 static inline int dmaengine_desc_set_reuse(struct dma_async_tx_descriptor *tx)
1558 {
1559 	struct dma_slave_caps caps;
1560 	int ret;
1561 
1562 	ret = dma_get_slave_caps(tx->chan, &caps);
1563 	if (ret)
1564 		return ret;
1565 
1566 	if (!caps.descriptor_reuse)
1567 		return -EPERM;
1568 
1569 	tx->flags |= DMA_CTRL_REUSE;
1570 	return 0;
1571 }
1572 
dmaengine_desc_clear_reuse(struct dma_async_tx_descriptor * tx)1573 static inline void dmaengine_desc_clear_reuse(struct dma_async_tx_descriptor *tx)
1574 {
1575 	tx->flags &= ~DMA_CTRL_REUSE;
1576 }
1577 
dmaengine_desc_test_reuse(struct dma_async_tx_descriptor * tx)1578 static inline bool dmaengine_desc_test_reuse(struct dma_async_tx_descriptor *tx)
1579 {
1580 	return (tx->flags & DMA_CTRL_REUSE) == DMA_CTRL_REUSE;
1581 }
1582 
dmaengine_desc_free(struct dma_async_tx_descriptor * desc)1583 static inline int dmaengine_desc_free(struct dma_async_tx_descriptor *desc)
1584 {
1585 	/* this is supported for reusable desc, so check that */
1586 	if (!dmaengine_desc_test_reuse(desc))
1587 		return -EPERM;
1588 
1589 	return desc->desc_free(desc);
1590 }
1591 
1592 /* --- DMA device --- */
1593 
1594 int dma_async_device_register(struct dma_device *device);
1595 int dmaenginem_async_device_register(struct dma_device *device);
1596 void dma_async_device_unregister(struct dma_device *device);
1597 int dma_async_device_channel_register(struct dma_device *device,
1598 				      struct dma_chan *chan);
1599 void dma_async_device_channel_unregister(struct dma_device *device,
1600 					 struct dma_chan *chan);
1601 void dma_run_dependencies(struct dma_async_tx_descriptor *tx);
1602 #define dma_request_channel(mask, x, y) \
1603 	__dma_request_channel(&(mask), x, y, NULL)
1604 
1605 /* Deprecated, please use dma_request_chan() directly */
1606 static inline struct dma_chan * __deprecated
dma_request_slave_channel(struct device * dev,const char * name)1607 dma_request_slave_channel(struct device *dev, const char *name)
1608 {
1609 	struct dma_chan *ch = dma_request_chan(dev, name);
1610 
1611 	return IS_ERR(ch) ? NULL : ch;
1612 }
1613 
1614 static inline struct dma_chan
dma_request_slave_channel_compat(const dma_cap_mask_t mask,dma_filter_fn fn,void * fn_param,struct device * dev,const char * name)1615 *dma_request_slave_channel_compat(const dma_cap_mask_t mask,
1616 				  dma_filter_fn fn, void *fn_param,
1617 				  struct device *dev, const char *name)
1618 {
1619 	struct dma_chan *chan;
1620 
1621 	chan = dma_request_slave_channel(dev, name);
1622 	if (chan)
1623 		return chan;
1624 
1625 	if (!fn || !fn_param)
1626 		return NULL;
1627 
1628 	return __dma_request_channel(&mask, fn, fn_param, NULL);
1629 }
1630 
1631 static inline char *
dmaengine_get_direction_text(enum dma_transfer_direction dir)1632 dmaengine_get_direction_text(enum dma_transfer_direction dir)
1633 {
1634 	switch (dir) {
1635 	case DMA_DEV_TO_MEM:
1636 		return "DEV_TO_MEM";
1637 	case DMA_MEM_TO_DEV:
1638 		return "MEM_TO_DEV";
1639 	case DMA_MEM_TO_MEM:
1640 		return "MEM_TO_MEM";
1641 	case DMA_DEV_TO_DEV:
1642 		return "DEV_TO_DEV";
1643 	default:
1644 		return "invalid";
1645 	}
1646 }
1647 
dmaengine_get_dma_device(struct dma_chan * chan)1648 static inline struct device *dmaengine_get_dma_device(struct dma_chan *chan)
1649 {
1650 	if (chan->dev->chan_dma_dev)
1651 		return &chan->dev->device;
1652 
1653 	return chan->device->dev;
1654 }
1655 
1656 #endif /* DMAENGINE_H */
1657