1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3  * Copyright (c) 2012, The Linux Foundation. All rights reserved.
4  */
5 
6 #ifndef _LINUX_CORESIGHT_H
7 #define _LINUX_CORESIGHT_H
8 
9 #include <linux/device.h>
10 #include <linux/io.h>
11 #include <linux/perf_event.h>
12 #include <linux/sched.h>
13 
14 /* Peripheral id registers (0xFD0-0xFEC) */
15 #define CORESIGHT_PERIPHIDR4	0xfd0
16 #define CORESIGHT_PERIPHIDR5	0xfd4
17 #define CORESIGHT_PERIPHIDR6	0xfd8
18 #define CORESIGHT_PERIPHIDR7	0xfdC
19 #define CORESIGHT_PERIPHIDR0	0xfe0
20 #define CORESIGHT_PERIPHIDR1	0xfe4
21 #define CORESIGHT_PERIPHIDR2	0xfe8
22 #define CORESIGHT_PERIPHIDR3	0xfeC
23 /* Component id registers (0xFF0-0xFFC) */
24 #define CORESIGHT_COMPIDR0	0xff0
25 #define CORESIGHT_COMPIDR1	0xff4
26 #define CORESIGHT_COMPIDR2	0xff8
27 #define CORESIGHT_COMPIDR3	0xffC
28 
29 #define ETM_ARCH_V3_3		0x23
30 #define ETM_ARCH_V3_5		0x25
31 #define PFT_ARCH_V1_0		0x30
32 #define PFT_ARCH_V1_1		0x31
33 
34 #define CORESIGHT_UNLOCK	0xc5acce55
35 
36 extern struct bus_type coresight_bustype;
37 
38 enum coresight_dev_type {
39 	CORESIGHT_DEV_TYPE_SINK,
40 	CORESIGHT_DEV_TYPE_LINK,
41 	CORESIGHT_DEV_TYPE_LINKSINK,
42 	CORESIGHT_DEV_TYPE_SOURCE,
43 	CORESIGHT_DEV_TYPE_HELPER,
44 	CORESIGHT_DEV_TYPE_ECT,
45 };
46 
47 enum coresight_dev_subtype_sink {
48 	CORESIGHT_DEV_SUBTYPE_SINK_PORT,
49 	CORESIGHT_DEV_SUBTYPE_SINK_BUFFER,
50 	CORESIGHT_DEV_SUBTYPE_SINK_SYSMEM,
51 	CORESIGHT_DEV_SUBTYPE_SINK_PERCPU_SYSMEM,
52 };
53 
54 enum coresight_dev_subtype_link {
55 	CORESIGHT_DEV_SUBTYPE_LINK_MERG,
56 	CORESIGHT_DEV_SUBTYPE_LINK_SPLIT,
57 	CORESIGHT_DEV_SUBTYPE_LINK_FIFO,
58 };
59 
60 enum coresight_dev_subtype_source {
61 	CORESIGHT_DEV_SUBTYPE_SOURCE_PROC,
62 	CORESIGHT_DEV_SUBTYPE_SOURCE_BUS,
63 	CORESIGHT_DEV_SUBTYPE_SOURCE_SOFTWARE,
64 };
65 
66 enum coresight_dev_subtype_helper {
67 	CORESIGHT_DEV_SUBTYPE_HELPER_CATU,
68 };
69 
70 /* Embedded Cross Trigger (ECT) sub-types */
71 enum coresight_dev_subtype_ect {
72 	CORESIGHT_DEV_SUBTYPE_ECT_NONE,
73 	CORESIGHT_DEV_SUBTYPE_ECT_CTI,
74 };
75 
76 /**
77  * union coresight_dev_subtype - further characterisation of a type
78  * @sink_subtype:	type of sink this component is, as defined
79  *			by @coresight_dev_subtype_sink.
80  * @link_subtype:	type of link this component is, as defined
81  *			by @coresight_dev_subtype_link.
82  * @source_subtype:	type of source this component is, as defined
83  *			by @coresight_dev_subtype_source.
84  * @helper_subtype:	type of helper this component is, as defined
85  *			by @coresight_dev_subtype_helper.
86  * @ect_subtype:        type of cross trigger this component is, as
87  *			defined by @coresight_dev_subtype_ect
88  */
89 union coresight_dev_subtype {
90 	/* We have some devices which acts as LINK and SINK */
91 	struct {
92 		enum coresight_dev_subtype_sink sink_subtype;
93 		enum coresight_dev_subtype_link link_subtype;
94 	};
95 	enum coresight_dev_subtype_source source_subtype;
96 	enum coresight_dev_subtype_helper helper_subtype;
97 	enum coresight_dev_subtype_ect ect_subtype;
98 };
99 
100 /**
101  * struct coresight_platform_data - data harvested from the firmware
102  * specification.
103  *
104  * @nr_inport:	Number of elements for the input connections.
105  * @nr_outport:	Number of elements for the output connections.
106  * @conns:	Sparse array of nr_outport connections from this component.
107  */
108 struct coresight_platform_data {
109 	int nr_inport;
110 	int nr_outport;
111 	struct coresight_connection *conns;
112 };
113 
114 /**
115  * struct csdev_access - Abstraction of a CoreSight device access.
116  *
117  * @io_mem	: True if the device has memory mapped I/O
118  * @base	: When io_mem == true, base address of the component
119  * @read	: Read from the given "offset" of the given instance.
120  * @write	: Write "val" to the given "offset".
121  */
122 struct csdev_access {
123 	bool io_mem;
124 	union {
125 		void __iomem *base;
126 		struct {
127 			u64 (*read)(u32 offset, bool relaxed, bool _64bit);
128 			void (*write)(u64 val, u32 offset, bool relaxed,
129 				      bool _64bit);
130 		};
131 	};
132 };
133 
134 #define CSDEV_ACCESS_IOMEM(_addr)		\
135 	((struct csdev_access)	{		\
136 		.io_mem		= true,		\
137 		.base		= (_addr),	\
138 	})
139 
140 /**
141  * struct coresight_desc - description of a component required from drivers
142  * @type:	as defined by @coresight_dev_type.
143  * @subtype:	as defined by @coresight_dev_subtype.
144  * @ops:	generic operations for this component, as defined
145  *		by @coresight_ops.
146  * @pdata:	platform data collected from DT.
147  * @dev:	The device entity associated to this component.
148  * @groups:	operations specific to this component. These will end up
149  *		in the component's sysfs sub-directory.
150  * @name:	name for the coresight device, also shown under sysfs.
151  * @access:	Describe access to the device
152  */
153 struct coresight_desc {
154 	enum coresight_dev_type type;
155 	union coresight_dev_subtype subtype;
156 	const struct coresight_ops *ops;
157 	struct coresight_platform_data *pdata;
158 	struct device *dev;
159 	const struct attribute_group **groups;
160 	const char *name;
161 	struct csdev_access access;
162 };
163 
164 /**
165  * struct coresight_connection - representation of a single connection
166  * @outport:	a connection's output port number.
167  * @child_port:	remote component's port number @output is connected to.
168  * @chid_fwnode: remote component's fwnode handle.
169  * @child_dev:	a @coresight_device representation of the component
170 		connected to @outport.
171  * @link: Representation of the connection as a sysfs link.
172  */
173 struct coresight_connection {
174 	int outport;
175 	int child_port;
176 	struct fwnode_handle *child_fwnode;
177 	struct coresight_device *child_dev;
178 	struct coresight_sysfs_link *link;
179 };
180 
181 /**
182  * struct coresight_sysfs_link - representation of a connection in sysfs.
183  * @orig:		Originating (master) coresight device for the link.
184  * @orig_name:		Name to use for the link orig->target.
185  * @target:		Target (slave) coresight device for the link.
186  * @target_name:	Name to use for the link target->orig.
187  */
188 struct coresight_sysfs_link {
189 	struct coresight_device *orig;
190 	const char *orig_name;
191 	struct coresight_device *target;
192 	const char *target_name;
193 };
194 
195 /**
196  * struct coresight_device - representation of a device as used by the framework
197  * @pdata:	Platform data with device connections associated to this device.
198  * @type:	as defined by @coresight_dev_type.
199  * @subtype:	as defined by @coresight_dev_subtype.
200  * @ops:	generic operations for this component, as defined
201  *		by @coresight_ops.
202  * @access:	Device i/o access abstraction for this device.
203  * @dev:	The device entity associated to this component.
204  * @refcnt:	keep track of what is in use.
205  * @orphan:	true if the component has connections that haven't been linked.
206  * @enable:	'true' if component is currently part of an active path.
207  * @activated:	'true' only if a _sink_ has been activated.  A sink can be
208  *		activated but not yet enabled.  Enabling for a _sink_
209  *		happens when a source has been selected and a path is enabled
210  *		from source to that sink.
211  * @ea:		Device attribute for sink representation under PMU directory.
212  * @def_sink:	cached reference to default sink found for this device.
213  * @ect_dev:	Associated cross trigger device. Not part of the trace data
214  *		path or connections.
215  * @nr_links:   number of sysfs links created to other components from this
216  *		device. These will appear in the "connections" group.
217  * @has_conns_grp: Have added a "connections" group for sysfs links.
218  * @feature_csdev_list: List of complex feature programming added to the device.
219  * @config_csdev_list:  List of system configurations added to the device.
220  * @cscfg_csdev_lock:	Protect the lists of configurations and features.
221  * @active_cscfg_ctxt:  Context information for current active system configuration.
222  */
223 struct coresight_device {
224 	struct coresight_platform_data *pdata;
225 	enum coresight_dev_type type;
226 	union coresight_dev_subtype subtype;
227 	const struct coresight_ops *ops;
228 	struct csdev_access access;
229 	struct device dev;
230 	atomic_t *refcnt;
231 	bool orphan;
232 	bool enable;	/* true only if configured as part of a path */
233 	/* sink specific fields */
234 	bool activated;	/* true only if a sink is part of a path */
235 	struct dev_ext_attribute *ea;
236 	struct coresight_device *def_sink;
237 	/* cross trigger handling */
238 	struct coresight_device *ect_dev;
239 	/* sysfs links between components */
240 	int nr_links;
241 	bool has_conns_grp;
242 	bool ect_enabled; /* true only if associated ect device is enabled */
243 	/* system configuration and feature lists */
244 	struct list_head feature_csdev_list;
245 	struct list_head config_csdev_list;
246 	spinlock_t cscfg_csdev_lock;
247 	void *active_cscfg_ctxt;
248 };
249 
250 /*
251  * coresight_dev_list - Mapping for devices to "name" index for device
252  * names.
253  *
254  * @nr_idx:		Number of entries already allocated.
255  * @pfx:		Prefix pattern for device name.
256  * @fwnode_list:	Array of fwnode_handles associated with each allocated
257  *			index, upto nr_idx entries.
258  */
259 struct coresight_dev_list {
260 	int			nr_idx;
261 	const char		*pfx;
262 	struct fwnode_handle	**fwnode_list;
263 };
264 
265 #define DEFINE_CORESIGHT_DEVLIST(var, dev_pfx)				\
266 static struct coresight_dev_list (var) = {				\
267 						.pfx = dev_pfx,		\
268 						.nr_idx = 0,		\
269 						.fwnode_list = NULL,	\
270 }
271 
272 #define to_coresight_device(d) container_of(d, struct coresight_device, dev)
273 
274 #define source_ops(csdev)	csdev->ops->source_ops
275 #define sink_ops(csdev)		csdev->ops->sink_ops
276 #define link_ops(csdev)		csdev->ops->link_ops
277 #define helper_ops(csdev)	csdev->ops->helper_ops
278 #define ect_ops(csdev)		csdev->ops->ect_ops
279 
280 /**
281  * struct coresight_ops_sink - basic operations for a sink
282  * Operations available for sinks
283  * @enable:		enables the sink.
284  * @disable:		disables the sink.
285  * @alloc_buffer:	initialises perf's ring buffer for trace collection.
286  * @free_buffer:	release memory allocated in @get_config.
287  * @update_buffer:	update buffer pointers after a trace session.
288  */
289 struct coresight_ops_sink {
290 	int (*enable)(struct coresight_device *csdev, u32 mode, void *data);
291 	int (*disable)(struct coresight_device *csdev);
292 	void *(*alloc_buffer)(struct coresight_device *csdev,
293 			      struct perf_event *event, void **pages,
294 			      int nr_pages, bool overwrite);
295 	void (*free_buffer)(void *config);
296 	unsigned long (*update_buffer)(struct coresight_device *csdev,
297 			      struct perf_output_handle *handle,
298 			      void *sink_config);
299 };
300 
301 /**
302  * struct coresight_ops_link - basic operations for a link
303  * Operations available for links.
304  * @enable:	enables flow between iport and oport.
305  * @disable:	disables flow between iport and oport.
306  */
307 struct coresight_ops_link {
308 	int (*enable)(struct coresight_device *csdev, int iport, int oport);
309 	void (*disable)(struct coresight_device *csdev, int iport, int oport);
310 };
311 
312 /**
313  * struct coresight_ops_source - basic operations for a source
314  * Operations available for sources.
315  * @cpu_id:	returns the value of the CPU number this component
316  *		is associated to.
317  * @trace_id:	returns the value of the component's trace ID as known
318  *		to the HW.
319  * @enable:	enables tracing for a source.
320  * @disable:	disables tracing for a source.
321  */
322 struct coresight_ops_source {
323 	int (*cpu_id)(struct coresight_device *csdev);
324 	int (*trace_id)(struct coresight_device *csdev);
325 	int (*enable)(struct coresight_device *csdev,
326 		      struct perf_event *event,  u32 mode);
327 	void (*disable)(struct coresight_device *csdev,
328 			struct perf_event *event);
329 };
330 
331 /**
332  * struct coresight_ops_helper - Operations for a helper device.
333  *
334  * All operations could pass in a device specific data, which could
335  * help the helper device to determine what to do.
336  *
337  * @enable	: Enable the device
338  * @disable	: Disable the device
339  */
340 struct coresight_ops_helper {
341 	int (*enable)(struct coresight_device *csdev, void *data);
342 	int (*disable)(struct coresight_device *csdev, void *data);
343 };
344 
345 /**
346  * struct coresight_ops_ect - Ops for an embedded cross trigger device
347  *
348  * @enable	: Enable the device
349  * @disable	: Disable the device
350  */
351 struct coresight_ops_ect {
352 	int (*enable)(struct coresight_device *csdev);
353 	int (*disable)(struct coresight_device *csdev);
354 };
355 
356 struct coresight_ops {
357 	const struct coresight_ops_sink *sink_ops;
358 	const struct coresight_ops_link *link_ops;
359 	const struct coresight_ops_source *source_ops;
360 	const struct coresight_ops_helper *helper_ops;
361 	const struct coresight_ops_ect *ect_ops;
362 };
363 
364 #if IS_ENABLED(CONFIG_CORESIGHT)
365 
csdev_access_relaxed_read32(struct csdev_access * csa,u32 offset)366 static inline u32 csdev_access_relaxed_read32(struct csdev_access *csa,
367 					      u32 offset)
368 {
369 	if (likely(csa->io_mem))
370 		return readl_relaxed(csa->base + offset);
371 
372 	return csa->read(offset, true, false);
373 }
374 
csdev_access_read32(struct csdev_access * csa,u32 offset)375 static inline u32 csdev_access_read32(struct csdev_access *csa, u32 offset)
376 {
377 	if (likely(csa->io_mem))
378 		return readl(csa->base + offset);
379 
380 	return csa->read(offset, false, false);
381 }
382 
csdev_access_relaxed_write32(struct csdev_access * csa,u32 val,u32 offset)383 static inline void csdev_access_relaxed_write32(struct csdev_access *csa,
384 						u32 val, u32 offset)
385 {
386 	if (likely(csa->io_mem))
387 		writel_relaxed(val, csa->base + offset);
388 	else
389 		csa->write(val, offset, true, false);
390 }
391 
csdev_access_write32(struct csdev_access * csa,u32 val,u32 offset)392 static inline void csdev_access_write32(struct csdev_access *csa, u32 val, u32 offset)
393 {
394 	if (likely(csa->io_mem))
395 		writel(val, csa->base + offset);
396 	else
397 		csa->write(val, offset, false, false);
398 }
399 
400 #ifdef CONFIG_64BIT
401 
csdev_access_relaxed_read64(struct csdev_access * csa,u32 offset)402 static inline u64 csdev_access_relaxed_read64(struct csdev_access *csa,
403 					      u32 offset)
404 {
405 	if (likely(csa->io_mem))
406 		return readq_relaxed(csa->base + offset);
407 
408 	return csa->read(offset, true, true);
409 }
410 
csdev_access_read64(struct csdev_access * csa,u32 offset)411 static inline u64 csdev_access_read64(struct csdev_access *csa, u32 offset)
412 {
413 	if (likely(csa->io_mem))
414 		return readq(csa->base + offset);
415 
416 	return csa->read(offset, false, true);
417 }
418 
csdev_access_relaxed_write64(struct csdev_access * csa,u64 val,u32 offset)419 static inline void csdev_access_relaxed_write64(struct csdev_access *csa,
420 						u64 val, u32 offset)
421 {
422 	if (likely(csa->io_mem))
423 		writeq_relaxed(val, csa->base + offset);
424 	else
425 		csa->write(val, offset, true, true);
426 }
427 
csdev_access_write64(struct csdev_access * csa,u64 val,u32 offset)428 static inline void csdev_access_write64(struct csdev_access *csa, u64 val, u32 offset)
429 {
430 	if (likely(csa->io_mem))
431 		writeq(val, csa->base + offset);
432 	else
433 		csa->write(val, offset, false, true);
434 }
435 
436 #else	/* !CONFIG_64BIT */
437 
csdev_access_relaxed_read64(struct csdev_access * csa,u32 offset)438 static inline u64 csdev_access_relaxed_read64(struct csdev_access *csa,
439 					      u32 offset)
440 {
441 	WARN_ON(1);
442 	return 0;
443 }
444 
csdev_access_read64(struct csdev_access * csa,u32 offset)445 static inline u64 csdev_access_read64(struct csdev_access *csa, u32 offset)
446 {
447 	WARN_ON(1);
448 	return 0;
449 }
450 
csdev_access_relaxed_write64(struct csdev_access * csa,u64 val,u32 offset)451 static inline void csdev_access_relaxed_write64(struct csdev_access *csa,
452 						u64 val, u32 offset)
453 {
454 	WARN_ON(1);
455 }
456 
csdev_access_write64(struct csdev_access * csa,u64 val,u32 offset)457 static inline void csdev_access_write64(struct csdev_access *csa, u64 val, u32 offset)
458 {
459 	WARN_ON(1);
460 }
461 #endif	/* CONFIG_64BIT */
462 
coresight_is_percpu_source(struct coresight_device * csdev)463 static inline bool coresight_is_percpu_source(struct coresight_device *csdev)
464 {
465 	return csdev && (csdev->type == CORESIGHT_DEV_TYPE_SOURCE) &&
466 	       (csdev->subtype.source_subtype == CORESIGHT_DEV_SUBTYPE_SOURCE_PROC);
467 }
468 
coresight_is_percpu_sink(struct coresight_device * csdev)469 static inline bool coresight_is_percpu_sink(struct coresight_device *csdev)
470 {
471 	return csdev && (csdev->type == CORESIGHT_DEV_TYPE_SINK) &&
472 	       (csdev->subtype.sink_subtype == CORESIGHT_DEV_SUBTYPE_SINK_PERCPU_SYSMEM);
473 }
474 
475 extern struct coresight_device *
476 coresight_register(struct coresight_desc *desc);
477 extern void coresight_unregister(struct coresight_device *csdev);
478 extern int coresight_enable(struct coresight_device *csdev);
479 extern void coresight_disable(struct coresight_device *csdev);
480 extern int coresight_timeout(struct csdev_access *csa, u32 offset,
481 			     int position, int value);
482 
483 extern int coresight_claim_device(struct coresight_device *csdev);
484 extern int coresight_claim_device_unlocked(struct coresight_device *csdev);
485 
486 extern void coresight_disclaim_device(struct coresight_device *csdev);
487 extern void coresight_disclaim_device_unlocked(struct coresight_device *csdev);
488 extern char *coresight_alloc_device_name(struct coresight_dev_list *devs,
489 					 struct device *dev);
490 
491 extern bool coresight_loses_context_with_cpu(struct device *dev);
492 
493 u32 coresight_relaxed_read32(struct coresight_device *csdev, u32 offset);
494 u32 coresight_read32(struct coresight_device *csdev, u32 offset);
495 void coresight_write32(struct coresight_device *csdev, u32 val, u32 offset);
496 void coresight_relaxed_write32(struct coresight_device *csdev,
497 			       u32 val, u32 offset);
498 u64 coresight_relaxed_read64(struct coresight_device *csdev, u32 offset);
499 u64 coresight_read64(struct coresight_device *csdev, u32 offset);
500 void coresight_relaxed_write64(struct coresight_device *csdev,
501 			       u64 val, u32 offset);
502 void coresight_write64(struct coresight_device *csdev, u64 val, u32 offset);
503 
504 #else
505 static inline struct coresight_device *
coresight_register(struct coresight_desc * desc)506 coresight_register(struct coresight_desc *desc) { return NULL; }
coresight_unregister(struct coresight_device * csdev)507 static inline void coresight_unregister(struct coresight_device *csdev) {}
508 static inline int
coresight_enable(struct coresight_device * csdev)509 coresight_enable(struct coresight_device *csdev) { return -ENOSYS; }
coresight_disable(struct coresight_device * csdev)510 static inline void coresight_disable(struct coresight_device *csdev) {}
511 
coresight_timeout(struct csdev_access * csa,u32 offset,int position,int value)512 static inline int coresight_timeout(struct csdev_access *csa, u32 offset,
513 				    int position, int value)
514 {
515 	return 1;
516 }
517 
coresight_claim_device_unlocked(struct coresight_device * csdev)518 static inline int coresight_claim_device_unlocked(struct coresight_device *csdev)
519 {
520 	return -EINVAL;
521 }
522 
coresight_claim_device(struct coresight_device * csdev)523 static inline int coresight_claim_device(struct coresight_device *csdev)
524 {
525 	return -EINVAL;
526 }
527 
coresight_disclaim_device(struct coresight_device * csdev)528 static inline void coresight_disclaim_device(struct coresight_device *csdev) {}
coresight_disclaim_device_unlocked(struct coresight_device * csdev)529 static inline void coresight_disclaim_device_unlocked(struct coresight_device *csdev) {}
530 
coresight_loses_context_with_cpu(struct device * dev)531 static inline bool coresight_loses_context_with_cpu(struct device *dev)
532 {
533 	return false;
534 }
535 
coresight_relaxed_read32(struct coresight_device * csdev,u32 offset)536 static inline u32 coresight_relaxed_read32(struct coresight_device *csdev, u32 offset)
537 {
538 	WARN_ON_ONCE(1);
539 	return 0;
540 }
541 
coresight_read32(struct coresight_device * csdev,u32 offset)542 static inline u32 coresight_read32(struct coresight_device *csdev, u32 offset)
543 {
544 	WARN_ON_ONCE(1);
545 	return 0;
546 }
547 
coresight_write32(struct coresight_device * csdev,u32 val,u32 offset)548 static inline void coresight_write32(struct coresight_device *csdev, u32 val, u32 offset)
549 {
550 }
551 
coresight_relaxed_write32(struct coresight_device * csdev,u32 val,u32 offset)552 static inline void coresight_relaxed_write32(struct coresight_device *csdev,
553 					     u32 val, u32 offset)
554 {
555 }
556 
coresight_relaxed_read64(struct coresight_device * csdev,u32 offset)557 static inline u64 coresight_relaxed_read64(struct coresight_device *csdev,
558 					   u32 offset)
559 {
560 	WARN_ON_ONCE(1);
561 	return 0;
562 }
563 
coresight_read64(struct coresight_device * csdev,u32 offset)564 static inline u64 coresight_read64(struct coresight_device *csdev, u32 offset)
565 {
566 	WARN_ON_ONCE(1);
567 	return 0;
568 }
569 
coresight_relaxed_write64(struct coresight_device * csdev,u64 val,u32 offset)570 static inline void coresight_relaxed_write64(struct coresight_device *csdev,
571 					     u64 val, u32 offset)
572 {
573 }
574 
coresight_write64(struct coresight_device * csdev,u64 val,u32 offset)575 static inline void coresight_write64(struct coresight_device *csdev, u64 val, u32 offset)
576 {
577 }
578 
579 #endif		/* IS_ENABLED(CONFIG_CORESIGHT) */
580 
581 extern int coresight_get_cpu(struct device *dev);
582 
583 struct coresight_platform_data *coresight_get_platform_data(struct device *dev);
584 
585 #endif		/* _LINUX_COREISGHT_H */
586