1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2 /*
3  * core.c - DesignWare HS OTG Controller common routines
4  *
5  * Copyright (C) 2004-2013 Synopsys, Inc.
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions
9  * are met:
10  * 1. Redistributions of source code must retain the above copyright
11  *    notice, this list of conditions, and the following disclaimer,
12  *    without modification.
13  * 2. Redistributions in binary form must reproduce the above copyright
14  *    notice, this list of conditions and the following disclaimer in the
15  *    documentation and/or other materials provided with the distribution.
16  * 3. The names of the above-listed copyright holders may not be used
17  *    to endorse or promote products derived from this software without
18  *    specific prior written permission.
19  *
20  * ALTERNATIVELY, this software may be distributed under the terms of the
21  * GNU General Public License ("GPL") as published by the Free Software
22  * Foundation; either version 2 of the License, or (at your option) any
23  * later version.
24  *
25  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
26  * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
27  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
28  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
29  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
30  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
31  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
32  * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
33  * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
34  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
35  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36  */
37 
38 /*
39  * The Core code provides basic services for accessing and managing the
40  * DWC_otg hardware. These services are used by both the Host Controller
41  * Driver and the Peripheral Controller Driver.
42  */
43 #include <linux/kernel.h>
44 #include <linux/module.h>
45 #include <linux/moduleparam.h>
46 #include <linux/spinlock.h>
47 #include <linux/interrupt.h>
48 #include <linux/dma-mapping.h>
49 #include <linux/delay.h>
50 #include <linux/io.h>
51 #include <linux/slab.h>
52 #include <linux/usb.h>
53 
54 #include <linux/usb/hcd.h>
55 #include <linux/usb/ch11.h>
56 
57 #include "core.h"
58 #include "hcd.h"
59 
60 /**
61  * dwc2_backup_global_registers() - Backup global controller registers.
62  * When suspending usb bus, registers needs to be backuped
63  * if controller power is disabled once suspended.
64  *
65  * @hsotg: Programming view of the DWC_otg controller
66  */
dwc2_backup_global_registers(struct dwc2_hsotg * hsotg)67 int dwc2_backup_global_registers(struct dwc2_hsotg *hsotg)
68 {
69 	struct dwc2_gregs_backup *gr;
70 
71 	dev_dbg(hsotg->dev, "%s\n", __func__);
72 
73 	/* Backup global regs */
74 	gr = &hsotg->gr_backup;
75 
76 	gr->gotgctl = dwc2_readl(hsotg, GOTGCTL);
77 	gr->gintmsk = dwc2_readl(hsotg, GINTMSK);
78 	gr->gahbcfg = dwc2_readl(hsotg, GAHBCFG);
79 	gr->gusbcfg = dwc2_readl(hsotg, GUSBCFG);
80 	gr->grxfsiz = dwc2_readl(hsotg, GRXFSIZ);
81 	gr->gnptxfsiz = dwc2_readl(hsotg, GNPTXFSIZ);
82 	gr->gdfifocfg = dwc2_readl(hsotg, GDFIFOCFG);
83 	gr->pcgcctl1 = dwc2_readl(hsotg, PCGCCTL1);
84 	gr->glpmcfg = dwc2_readl(hsotg, GLPMCFG);
85 	gr->gi2cctl = dwc2_readl(hsotg, GI2CCTL);
86 	gr->pcgcctl = dwc2_readl(hsotg, PCGCTL);
87 
88 	gr->valid = true;
89 	return 0;
90 }
91 
92 /**
93  * dwc2_restore_global_registers() - Restore controller global registers.
94  * When resuming usb bus, device registers needs to be restored
95  * if controller power were disabled.
96  *
97  * @hsotg: Programming view of the DWC_otg controller
98  */
dwc2_restore_global_registers(struct dwc2_hsotg * hsotg)99 int dwc2_restore_global_registers(struct dwc2_hsotg *hsotg)
100 {
101 	struct dwc2_gregs_backup *gr;
102 
103 	dev_dbg(hsotg->dev, "%s\n", __func__);
104 
105 	/* Restore global regs */
106 	gr = &hsotg->gr_backup;
107 	if (!gr->valid) {
108 		dev_err(hsotg->dev, "%s: no global registers to restore\n",
109 			__func__);
110 		return -EINVAL;
111 	}
112 	gr->valid = false;
113 
114 	dwc2_writel(hsotg, 0xffffffff, GINTSTS);
115 	dwc2_writel(hsotg, gr->gotgctl, GOTGCTL);
116 	dwc2_writel(hsotg, gr->gintmsk, GINTMSK);
117 	dwc2_writel(hsotg, gr->gusbcfg, GUSBCFG);
118 	dwc2_writel(hsotg, gr->gahbcfg, GAHBCFG);
119 	dwc2_writel(hsotg, gr->grxfsiz, GRXFSIZ);
120 	dwc2_writel(hsotg, gr->gnptxfsiz, GNPTXFSIZ);
121 	dwc2_writel(hsotg, gr->gdfifocfg, GDFIFOCFG);
122 	dwc2_writel(hsotg, gr->pcgcctl1, PCGCCTL1);
123 	dwc2_writel(hsotg, gr->glpmcfg, GLPMCFG);
124 	dwc2_writel(hsotg, gr->pcgcctl, PCGCTL);
125 	dwc2_writel(hsotg, gr->gi2cctl, GI2CCTL);
126 
127 	return 0;
128 }
129 
130 /**
131  * dwc2_exit_partial_power_down() - Exit controller from Partial Power Down.
132  *
133  * @hsotg: Programming view of the DWC_otg controller
134  * @rem_wakeup: indicates whether resume is initiated by Reset.
135  * @restore: Controller registers need to be restored
136  */
dwc2_exit_partial_power_down(struct dwc2_hsotg * hsotg,int rem_wakeup,bool restore)137 int dwc2_exit_partial_power_down(struct dwc2_hsotg *hsotg, int rem_wakeup,
138 				 bool restore)
139 {
140 	struct dwc2_gregs_backup *gr;
141 
142 	gr = &hsotg->gr_backup;
143 
144 	/*
145 	 * Restore host or device regisers with the same mode core enterted
146 	 * to partial power down by checking "GOTGCTL_CURMODE_HOST" backup
147 	 * value of the "gotgctl" register.
148 	 */
149 	if (gr->gotgctl & GOTGCTL_CURMODE_HOST)
150 		return dwc2_host_exit_partial_power_down(hsotg, rem_wakeup,
151 							 restore);
152 	else
153 		return dwc2_gadget_exit_partial_power_down(hsotg, restore);
154 }
155 
156 /**
157  * dwc2_enter_partial_power_down() - Put controller in Partial Power Down.
158  *
159  * @hsotg: Programming view of the DWC_otg controller
160  */
dwc2_enter_partial_power_down(struct dwc2_hsotg * hsotg)161 int dwc2_enter_partial_power_down(struct dwc2_hsotg *hsotg)
162 {
163 	if (dwc2_is_host_mode(hsotg))
164 		return dwc2_host_enter_partial_power_down(hsotg);
165 	else
166 		return dwc2_gadget_enter_partial_power_down(hsotg);
167 }
168 
169 /**
170  * dwc2_restore_essential_regs() - Restore essiential regs of core.
171  *
172  * @hsotg: Programming view of the DWC_otg controller
173  * @rmode: Restore mode, enabled in case of remote-wakeup.
174  * @is_host: Host or device mode.
175  */
dwc2_restore_essential_regs(struct dwc2_hsotg * hsotg,int rmode,int is_host)176 static void dwc2_restore_essential_regs(struct dwc2_hsotg *hsotg, int rmode,
177 					int is_host)
178 {
179 	u32 pcgcctl;
180 	struct dwc2_gregs_backup *gr;
181 	struct dwc2_dregs_backup *dr;
182 	struct dwc2_hregs_backup *hr;
183 
184 	gr = &hsotg->gr_backup;
185 	dr = &hsotg->dr_backup;
186 	hr = &hsotg->hr_backup;
187 
188 	dev_dbg(hsotg->dev, "%s: restoring essential regs\n", __func__);
189 
190 	/* Load restore values for [31:14] bits */
191 	pcgcctl = (gr->pcgcctl & 0xffffc000);
192 	/* If High Speed */
193 	if (is_host) {
194 		if (!(pcgcctl & PCGCTL_P2HD_PRT_SPD_MASK))
195 			pcgcctl |= BIT(17);
196 	} else {
197 		if (!(pcgcctl & PCGCTL_P2HD_DEV_ENUM_SPD_MASK))
198 			pcgcctl |= BIT(17);
199 	}
200 	dwc2_writel(hsotg, pcgcctl, PCGCTL);
201 
202 	/* Umnask global Interrupt in GAHBCFG and restore it */
203 	dwc2_writel(hsotg, gr->gahbcfg | GAHBCFG_GLBL_INTR_EN, GAHBCFG);
204 
205 	/* Clear all pending interupts */
206 	dwc2_writel(hsotg, 0xffffffff, GINTSTS);
207 
208 	/* Unmask restore done interrupt */
209 	dwc2_writel(hsotg, GINTSTS_RESTOREDONE, GINTMSK);
210 
211 	/* Restore GUSBCFG and HCFG/DCFG */
212 	dwc2_writel(hsotg, gr->gusbcfg, GUSBCFG);
213 
214 	if (is_host) {
215 		dwc2_writel(hsotg, hr->hcfg, HCFG);
216 		if (rmode)
217 			pcgcctl |= PCGCTL_RESTOREMODE;
218 		dwc2_writel(hsotg, pcgcctl, PCGCTL);
219 		udelay(10);
220 
221 		pcgcctl |= PCGCTL_ESS_REG_RESTORED;
222 		dwc2_writel(hsotg, pcgcctl, PCGCTL);
223 		udelay(10);
224 	} else {
225 		dwc2_writel(hsotg, dr->dcfg, DCFG);
226 		if (!rmode)
227 			pcgcctl |= PCGCTL_RESTOREMODE | PCGCTL_RSTPDWNMODULE;
228 		dwc2_writel(hsotg, pcgcctl, PCGCTL);
229 		udelay(10);
230 
231 		pcgcctl |= PCGCTL_ESS_REG_RESTORED;
232 		dwc2_writel(hsotg, pcgcctl, PCGCTL);
233 		udelay(10);
234 	}
235 }
236 
237 /**
238  * dwc2_hib_restore_common() - Common part of restore routine.
239  *
240  * @hsotg: Programming view of the DWC_otg controller
241  * @rem_wakeup: Remote-wakeup, enabled in case of remote-wakeup.
242  * @is_host: Host or device mode.
243  */
dwc2_hib_restore_common(struct dwc2_hsotg * hsotg,int rem_wakeup,int is_host)244 void dwc2_hib_restore_common(struct dwc2_hsotg *hsotg, int rem_wakeup,
245 			     int is_host)
246 {
247 	u32 gpwrdn;
248 
249 	/* Switch-on voltage to the core */
250 	gpwrdn = dwc2_readl(hsotg, GPWRDN);
251 	gpwrdn &= ~GPWRDN_PWRDNSWTCH;
252 	dwc2_writel(hsotg, gpwrdn, GPWRDN);
253 	udelay(10);
254 
255 	/* Reset core */
256 	gpwrdn = dwc2_readl(hsotg, GPWRDN);
257 	gpwrdn &= ~GPWRDN_PWRDNRSTN;
258 	dwc2_writel(hsotg, gpwrdn, GPWRDN);
259 	udelay(10);
260 
261 	/* Enable restore from PMU */
262 	gpwrdn = dwc2_readl(hsotg, GPWRDN);
263 	gpwrdn |= GPWRDN_RESTORE;
264 	dwc2_writel(hsotg, gpwrdn, GPWRDN);
265 	udelay(10);
266 
267 	/* Disable Power Down Clamp */
268 	gpwrdn = dwc2_readl(hsotg, GPWRDN);
269 	gpwrdn &= ~GPWRDN_PWRDNCLMP;
270 	dwc2_writel(hsotg, gpwrdn, GPWRDN);
271 	udelay(50);
272 
273 	if (!is_host && rem_wakeup)
274 		udelay(70);
275 
276 	/* Deassert reset core */
277 	gpwrdn = dwc2_readl(hsotg, GPWRDN);
278 	gpwrdn |= GPWRDN_PWRDNRSTN;
279 	dwc2_writel(hsotg, gpwrdn, GPWRDN);
280 	udelay(10);
281 
282 	/* Disable PMU interrupt */
283 	gpwrdn = dwc2_readl(hsotg, GPWRDN);
284 	gpwrdn &= ~GPWRDN_PMUINTSEL;
285 	dwc2_writel(hsotg, gpwrdn, GPWRDN);
286 	udelay(10);
287 
288 	/* Set Restore Essential Regs bit in PCGCCTL register */
289 	dwc2_restore_essential_regs(hsotg, rem_wakeup, is_host);
290 
291 	/*
292 	 * Wait For Restore_done Interrupt. This mechanism of polling the
293 	 * interrupt is introduced to avoid any possible race conditions
294 	 */
295 	if (dwc2_hsotg_wait_bit_set(hsotg, GINTSTS, GINTSTS_RESTOREDONE,
296 				    20000)) {
297 		dev_dbg(hsotg->dev,
298 			"%s: Restore Done wasn't generated here\n",
299 			__func__);
300 	} else {
301 		dev_dbg(hsotg->dev, "restore done  generated here\n");
302 
303 		/*
304 		 * To avoid restore done interrupt storm after restore is
305 		 * generated clear GINTSTS_RESTOREDONE bit.
306 		 */
307 		dwc2_writel(hsotg, GINTSTS_RESTOREDONE, GINTSTS);
308 	}
309 }
310 
311 /**
312  * dwc2_wait_for_mode() - Waits for the controller mode.
313  * @hsotg:	Programming view of the DWC_otg controller.
314  * @host_mode:	If true, waits for host mode, otherwise device mode.
315  */
dwc2_wait_for_mode(struct dwc2_hsotg * hsotg,bool host_mode)316 static void dwc2_wait_for_mode(struct dwc2_hsotg *hsotg,
317 			       bool host_mode)
318 {
319 	ktime_t start;
320 	ktime_t end;
321 	unsigned int timeout = 110;
322 
323 	dev_vdbg(hsotg->dev, "Waiting for %s mode\n",
324 		 host_mode ? "host" : "device");
325 
326 	start = ktime_get();
327 
328 	while (1) {
329 		s64 ms;
330 
331 		if (dwc2_is_host_mode(hsotg) == host_mode) {
332 			dev_vdbg(hsotg->dev, "%s mode set\n",
333 				 host_mode ? "Host" : "Device");
334 			break;
335 		}
336 
337 		end = ktime_get();
338 		ms = ktime_to_ms(ktime_sub(end, start));
339 
340 		if (ms >= (s64)timeout) {
341 			dev_warn(hsotg->dev, "%s: Couldn't set %s mode\n",
342 				 __func__, host_mode ? "host" : "device");
343 			break;
344 		}
345 
346 		usleep_range(1000, 2000);
347 	}
348 }
349 
350 /**
351  * dwc2_iddig_filter_enabled() - Returns true if the IDDIG debounce
352  * filter is enabled.
353  *
354  * @hsotg: Programming view of DWC_otg controller
355  */
dwc2_iddig_filter_enabled(struct dwc2_hsotg * hsotg)356 static bool dwc2_iddig_filter_enabled(struct dwc2_hsotg *hsotg)
357 {
358 	u32 gsnpsid;
359 	u32 ghwcfg4;
360 
361 	if (!dwc2_hw_is_otg(hsotg))
362 		return false;
363 
364 	/* Check if core configuration includes the IDDIG filter. */
365 	ghwcfg4 = dwc2_readl(hsotg, GHWCFG4);
366 	if (!(ghwcfg4 & GHWCFG4_IDDIG_FILT_EN))
367 		return false;
368 
369 	/*
370 	 * Check if the IDDIG debounce filter is bypassed. Available
371 	 * in core version >= 3.10a.
372 	 */
373 	gsnpsid = dwc2_readl(hsotg, GSNPSID);
374 	if (gsnpsid >= DWC2_CORE_REV_3_10a) {
375 		u32 gotgctl = dwc2_readl(hsotg, GOTGCTL);
376 
377 		if (gotgctl & GOTGCTL_DBNCE_FLTR_BYPASS)
378 			return false;
379 	}
380 
381 	return true;
382 }
383 
384 /*
385  * dwc2_enter_hibernation() - Common function to enter hibernation.
386  *
387  * @hsotg: Programming view of the DWC_otg controller
388  * @is_host: True if core is in host mode.
389  *
390  * Return: 0 if successful, negative error code otherwise
391  */
dwc2_enter_hibernation(struct dwc2_hsotg * hsotg,int is_host)392 int dwc2_enter_hibernation(struct dwc2_hsotg *hsotg, int is_host)
393 {
394 	if (is_host)
395 		return dwc2_host_enter_hibernation(hsotg);
396 	else
397 		return dwc2_gadget_enter_hibernation(hsotg);
398 }
399 
400 /*
401  * dwc2_exit_hibernation() - Common function to exit from hibernation.
402  *
403  * @hsotg: Programming view of the DWC_otg controller
404  * @rem_wakeup: Remote-wakeup, enabled in case of remote-wakeup.
405  * @reset: Enabled in case of restore with reset.
406  * @is_host: True if core is in host mode.
407  *
408  * Return: 0 if successful, negative error code otherwise
409  */
dwc2_exit_hibernation(struct dwc2_hsotg * hsotg,int rem_wakeup,int reset,int is_host)410 int dwc2_exit_hibernation(struct dwc2_hsotg *hsotg, int rem_wakeup,
411 			  int reset, int is_host)
412 {
413 	if (is_host)
414 		return dwc2_host_exit_hibernation(hsotg, rem_wakeup, reset);
415 	else
416 		return dwc2_gadget_exit_hibernation(hsotg, rem_wakeup, reset);
417 }
418 
419 /*
420  * Do core a soft reset of the core.  Be careful with this because it
421  * resets all the internal state machines of the core.
422  */
dwc2_core_reset(struct dwc2_hsotg * hsotg,bool skip_wait)423 int dwc2_core_reset(struct dwc2_hsotg *hsotg, bool skip_wait)
424 {
425 	u32 greset;
426 	bool wait_for_host_mode = false;
427 
428 	dev_vdbg(hsotg->dev, "%s()\n", __func__);
429 
430 	/*
431 	 * If the current mode is host, either due to the force mode
432 	 * bit being set (which persists after core reset) or the
433 	 * connector id pin, a core soft reset will temporarily reset
434 	 * the mode to device. A delay from the IDDIG debounce filter
435 	 * will occur before going back to host mode.
436 	 *
437 	 * Determine whether we will go back into host mode after a
438 	 * reset and account for this delay after the reset.
439 	 */
440 	if (dwc2_iddig_filter_enabled(hsotg)) {
441 		u32 gotgctl = dwc2_readl(hsotg, GOTGCTL);
442 		u32 gusbcfg = dwc2_readl(hsotg, GUSBCFG);
443 
444 		if (!(gotgctl & GOTGCTL_CONID_B) ||
445 		    (gusbcfg & GUSBCFG_FORCEHOSTMODE)) {
446 			wait_for_host_mode = true;
447 		}
448 	}
449 
450 	/* Core Soft Reset */
451 	greset = dwc2_readl(hsotg, GRSTCTL);
452 	greset |= GRSTCTL_CSFTRST;
453 	dwc2_writel(hsotg, greset, GRSTCTL);
454 
455 	if ((hsotg->hw_params.snpsid & DWC2_CORE_REV_MASK) <
456 		(DWC2_CORE_REV_4_20a & DWC2_CORE_REV_MASK)) {
457 		if (dwc2_hsotg_wait_bit_clear(hsotg, GRSTCTL,
458 					      GRSTCTL_CSFTRST, 10000)) {
459 			dev_warn(hsotg->dev, "%s: HANG! Soft Reset timeout GRSTCTL_CSFTRST\n",
460 				 __func__);
461 			return -EBUSY;
462 		}
463 	} else {
464 		if (dwc2_hsotg_wait_bit_set(hsotg, GRSTCTL,
465 					    GRSTCTL_CSFTRST_DONE, 10000)) {
466 			dev_warn(hsotg->dev, "%s: HANG! Soft Reset timeout GRSTCTL_CSFTRST_DONE\n",
467 				 __func__);
468 			return -EBUSY;
469 		}
470 		greset = dwc2_readl(hsotg, GRSTCTL);
471 		greset &= ~GRSTCTL_CSFTRST;
472 		greset |= GRSTCTL_CSFTRST_DONE;
473 		dwc2_writel(hsotg, greset, GRSTCTL);
474 	}
475 
476 	/*
477 	 * Switching from device mode to host mode by disconnecting
478 	 * device cable core enters and exits form hibernation.
479 	 * However, the fifo map remains not cleared. It results
480 	 * to a WARNING (WARNING: CPU: 5 PID: 0 at drivers/usb/dwc2/
481 	 * gadget.c:307 dwc2_hsotg_init_fifo+0x12/0x152 [dwc2])
482 	 * if in host mode we disconnect the micro a to b host
483 	 * cable. Because core reset occurs.
484 	 * To avoid the WARNING, fifo_map should be cleared
485 	 * in dwc2_core_reset() function by taking into account configs.
486 	 * fifo_map must be cleared only if driver is configured in
487 	 * "CONFIG_USB_DWC2_PERIPHERAL" or "CONFIG_USB_DWC2_DUAL_ROLE"
488 	 * mode.
489 	 */
490 	dwc2_clear_fifo_map(hsotg);
491 
492 	/* Wait for AHB master IDLE state */
493 	if (dwc2_hsotg_wait_bit_set(hsotg, GRSTCTL, GRSTCTL_AHBIDLE, 10000)) {
494 		dev_warn(hsotg->dev, "%s: HANG! AHB Idle timeout GRSTCTL GRSTCTL_AHBIDLE\n",
495 			 __func__);
496 		return -EBUSY;
497 	}
498 
499 	if (wait_for_host_mode && !skip_wait)
500 		dwc2_wait_for_mode(hsotg, true);
501 
502 	return 0;
503 }
504 
505 /**
506  * dwc2_force_mode() - Force the mode of the controller.
507  *
508  * Forcing the mode is needed for two cases:
509  *
510  * 1) If the dr_mode is set to either HOST or PERIPHERAL we force the
511  * controller to stay in a particular mode regardless of ID pin
512  * changes. We do this once during probe.
513  *
514  * 2) During probe we want to read reset values of the hw
515  * configuration registers that are only available in either host or
516  * device mode. We may need to force the mode if the current mode does
517  * not allow us to access the register in the mode that we want.
518  *
519  * In either case it only makes sense to force the mode if the
520  * controller hardware is OTG capable.
521  *
522  * Checks are done in this function to determine whether doing a force
523  * would be valid or not.
524  *
525  * If a force is done, it requires a IDDIG debounce filter delay if
526  * the filter is configured and enabled. We poll the current mode of
527  * the controller to account for this delay.
528  *
529  * @hsotg: Programming view of DWC_otg controller
530  * @host: Host mode flag
531  */
dwc2_force_mode(struct dwc2_hsotg * hsotg,bool host)532 void dwc2_force_mode(struct dwc2_hsotg *hsotg, bool host)
533 {
534 	u32 gusbcfg;
535 	u32 set;
536 	u32 clear;
537 
538 	dev_dbg(hsotg->dev, "Forcing mode to %s\n", host ? "host" : "device");
539 
540 	/*
541 	 * Force mode has no effect if the hardware is not OTG.
542 	 */
543 	if (!dwc2_hw_is_otg(hsotg))
544 		return;
545 
546 	/*
547 	 * If dr_mode is either peripheral or host only, there is no
548 	 * need to ever force the mode to the opposite mode.
549 	 */
550 	if (WARN_ON(host && hsotg->dr_mode == USB_DR_MODE_PERIPHERAL))
551 		return;
552 
553 	if (WARN_ON(!host && hsotg->dr_mode == USB_DR_MODE_HOST))
554 		return;
555 
556 	gusbcfg = dwc2_readl(hsotg, GUSBCFG);
557 
558 	set = host ? GUSBCFG_FORCEHOSTMODE : GUSBCFG_FORCEDEVMODE;
559 	clear = host ? GUSBCFG_FORCEDEVMODE : GUSBCFG_FORCEHOSTMODE;
560 
561 	gusbcfg &= ~clear;
562 	gusbcfg |= set;
563 	dwc2_writel(hsotg, gusbcfg, GUSBCFG);
564 
565 	dwc2_wait_for_mode(hsotg, host);
566 	return;
567 }
568 
569 /**
570  * dwc2_clear_force_mode() - Clears the force mode bits.
571  *
572  * After clearing the bits, wait up to 100 ms to account for any
573  * potential IDDIG filter delay. We can't know if we expect this delay
574  * or not because the value of the connector ID status is affected by
575  * the force mode. We only need to call this once during probe if
576  * dr_mode == OTG.
577  *
578  * @hsotg: Programming view of DWC_otg controller
579  */
dwc2_clear_force_mode(struct dwc2_hsotg * hsotg)580 static void dwc2_clear_force_mode(struct dwc2_hsotg *hsotg)
581 {
582 	u32 gusbcfg;
583 
584 	if (!dwc2_hw_is_otg(hsotg))
585 		return;
586 
587 	dev_dbg(hsotg->dev, "Clearing force mode bits\n");
588 
589 	gusbcfg = dwc2_readl(hsotg, GUSBCFG);
590 	gusbcfg &= ~GUSBCFG_FORCEHOSTMODE;
591 	gusbcfg &= ~GUSBCFG_FORCEDEVMODE;
592 	dwc2_writel(hsotg, gusbcfg, GUSBCFG);
593 
594 	if (dwc2_iddig_filter_enabled(hsotg))
595 		msleep(100);
596 }
597 
598 /*
599  * Sets or clears force mode based on the dr_mode parameter.
600  */
dwc2_force_dr_mode(struct dwc2_hsotg * hsotg)601 void dwc2_force_dr_mode(struct dwc2_hsotg *hsotg)
602 {
603 	switch (hsotg->dr_mode) {
604 	case USB_DR_MODE_HOST:
605 		/*
606 		 * NOTE: This is required for some rockchip soc based
607 		 * platforms on their host-only dwc2.
608 		 */
609 		if (!dwc2_hw_is_otg(hsotg))
610 			msleep(50);
611 
612 		break;
613 	case USB_DR_MODE_PERIPHERAL:
614 		dwc2_force_mode(hsotg, false);
615 		break;
616 	case USB_DR_MODE_OTG:
617 		dwc2_clear_force_mode(hsotg);
618 		break;
619 	default:
620 		dev_warn(hsotg->dev, "%s() Invalid dr_mode=%d\n",
621 			 __func__, hsotg->dr_mode);
622 		break;
623 	}
624 }
625 
626 /*
627  * dwc2_enable_acg - enable active clock gating feature
628  */
dwc2_enable_acg(struct dwc2_hsotg * hsotg)629 void dwc2_enable_acg(struct dwc2_hsotg *hsotg)
630 {
631 	if (hsotg->params.acg_enable) {
632 		u32 pcgcctl1 = dwc2_readl(hsotg, PCGCCTL1);
633 
634 		dev_dbg(hsotg->dev, "Enabling Active Clock Gating\n");
635 		pcgcctl1 |= PCGCCTL1_GATEEN;
636 		dwc2_writel(hsotg, pcgcctl1, PCGCCTL1);
637 	}
638 }
639 
640 /**
641  * dwc2_dump_host_registers() - Prints the host registers
642  *
643  * @hsotg: Programming view of DWC_otg controller
644  *
645  * NOTE: This function will be removed once the peripheral controller code
646  * is integrated and the driver is stable
647  */
dwc2_dump_host_registers(struct dwc2_hsotg * hsotg)648 void dwc2_dump_host_registers(struct dwc2_hsotg *hsotg)
649 {
650 #ifdef DEBUG
651 	u32 __iomem *addr;
652 	int i;
653 
654 	dev_dbg(hsotg->dev, "Host Global Registers\n");
655 	addr = hsotg->regs + HCFG;
656 	dev_dbg(hsotg->dev, "HCFG	 @0x%08lX : 0x%08X\n",
657 		(unsigned long)addr, dwc2_readl(hsotg, HCFG));
658 	addr = hsotg->regs + HFIR;
659 	dev_dbg(hsotg->dev, "HFIR	 @0x%08lX : 0x%08X\n",
660 		(unsigned long)addr, dwc2_readl(hsotg, HFIR));
661 	addr = hsotg->regs + HFNUM;
662 	dev_dbg(hsotg->dev, "HFNUM	 @0x%08lX : 0x%08X\n",
663 		(unsigned long)addr, dwc2_readl(hsotg, HFNUM));
664 	addr = hsotg->regs + HPTXSTS;
665 	dev_dbg(hsotg->dev, "HPTXSTS	 @0x%08lX : 0x%08X\n",
666 		(unsigned long)addr, dwc2_readl(hsotg, HPTXSTS));
667 	addr = hsotg->regs + HAINT;
668 	dev_dbg(hsotg->dev, "HAINT	 @0x%08lX : 0x%08X\n",
669 		(unsigned long)addr, dwc2_readl(hsotg, HAINT));
670 	addr = hsotg->regs + HAINTMSK;
671 	dev_dbg(hsotg->dev, "HAINTMSK	 @0x%08lX : 0x%08X\n",
672 		(unsigned long)addr, dwc2_readl(hsotg, HAINTMSK));
673 	if (hsotg->params.dma_desc_enable) {
674 		addr = hsotg->regs + HFLBADDR;
675 		dev_dbg(hsotg->dev, "HFLBADDR @0x%08lX : 0x%08X\n",
676 			(unsigned long)addr, dwc2_readl(hsotg, HFLBADDR));
677 	}
678 
679 	addr = hsotg->regs + HPRT0;
680 	dev_dbg(hsotg->dev, "HPRT0	 @0x%08lX : 0x%08X\n",
681 		(unsigned long)addr, dwc2_readl(hsotg, HPRT0));
682 
683 	for (i = 0; i < hsotg->params.host_channels; i++) {
684 		dev_dbg(hsotg->dev, "Host Channel %d Specific Registers\n", i);
685 		addr = hsotg->regs + HCCHAR(i);
686 		dev_dbg(hsotg->dev, "HCCHAR	 @0x%08lX : 0x%08X\n",
687 			(unsigned long)addr, dwc2_readl(hsotg, HCCHAR(i)));
688 		addr = hsotg->regs + HCSPLT(i);
689 		dev_dbg(hsotg->dev, "HCSPLT	 @0x%08lX : 0x%08X\n",
690 			(unsigned long)addr, dwc2_readl(hsotg, HCSPLT(i)));
691 		addr = hsotg->regs + HCINT(i);
692 		dev_dbg(hsotg->dev, "HCINT	 @0x%08lX : 0x%08X\n",
693 			(unsigned long)addr, dwc2_readl(hsotg, HCINT(i)));
694 		addr = hsotg->regs + HCINTMSK(i);
695 		dev_dbg(hsotg->dev, "HCINTMSK	 @0x%08lX : 0x%08X\n",
696 			(unsigned long)addr, dwc2_readl(hsotg, HCINTMSK(i)));
697 		addr = hsotg->regs + HCTSIZ(i);
698 		dev_dbg(hsotg->dev, "HCTSIZ	 @0x%08lX : 0x%08X\n",
699 			(unsigned long)addr, dwc2_readl(hsotg, HCTSIZ(i)));
700 		addr = hsotg->regs + HCDMA(i);
701 		dev_dbg(hsotg->dev, "HCDMA	 @0x%08lX : 0x%08X\n",
702 			(unsigned long)addr, dwc2_readl(hsotg, HCDMA(i)));
703 		if (hsotg->params.dma_desc_enable) {
704 			addr = hsotg->regs + HCDMAB(i);
705 			dev_dbg(hsotg->dev, "HCDMAB	 @0x%08lX : 0x%08X\n",
706 				(unsigned long)addr, dwc2_readl(hsotg,
707 								HCDMAB(i)));
708 		}
709 	}
710 #endif
711 }
712 
713 /**
714  * dwc2_dump_global_registers() - Prints the core global registers
715  *
716  * @hsotg: Programming view of DWC_otg controller
717  *
718  * NOTE: This function will be removed once the peripheral controller code
719  * is integrated and the driver is stable
720  */
dwc2_dump_global_registers(struct dwc2_hsotg * hsotg)721 void dwc2_dump_global_registers(struct dwc2_hsotg *hsotg)
722 {
723 #ifdef DEBUG
724 	u32 __iomem *addr;
725 
726 	dev_dbg(hsotg->dev, "Core Global Registers\n");
727 	addr = hsotg->regs + GOTGCTL;
728 	dev_dbg(hsotg->dev, "GOTGCTL	 @0x%08lX : 0x%08X\n",
729 		(unsigned long)addr, dwc2_readl(hsotg, GOTGCTL));
730 	addr = hsotg->regs + GOTGINT;
731 	dev_dbg(hsotg->dev, "GOTGINT	 @0x%08lX : 0x%08X\n",
732 		(unsigned long)addr, dwc2_readl(hsotg, GOTGINT));
733 	addr = hsotg->regs + GAHBCFG;
734 	dev_dbg(hsotg->dev, "GAHBCFG	 @0x%08lX : 0x%08X\n",
735 		(unsigned long)addr, dwc2_readl(hsotg, GAHBCFG));
736 	addr = hsotg->regs + GUSBCFG;
737 	dev_dbg(hsotg->dev, "GUSBCFG	 @0x%08lX : 0x%08X\n",
738 		(unsigned long)addr, dwc2_readl(hsotg, GUSBCFG));
739 	addr = hsotg->regs + GRSTCTL;
740 	dev_dbg(hsotg->dev, "GRSTCTL	 @0x%08lX : 0x%08X\n",
741 		(unsigned long)addr, dwc2_readl(hsotg, GRSTCTL));
742 	addr = hsotg->regs + GINTSTS;
743 	dev_dbg(hsotg->dev, "GINTSTS	 @0x%08lX : 0x%08X\n",
744 		(unsigned long)addr, dwc2_readl(hsotg, GINTSTS));
745 	addr = hsotg->regs + GINTMSK;
746 	dev_dbg(hsotg->dev, "GINTMSK	 @0x%08lX : 0x%08X\n",
747 		(unsigned long)addr, dwc2_readl(hsotg, GINTMSK));
748 	addr = hsotg->regs + GRXSTSR;
749 	dev_dbg(hsotg->dev, "GRXSTSR	 @0x%08lX : 0x%08X\n",
750 		(unsigned long)addr, dwc2_readl(hsotg, GRXSTSR));
751 	addr = hsotg->regs + GRXFSIZ;
752 	dev_dbg(hsotg->dev, "GRXFSIZ	 @0x%08lX : 0x%08X\n",
753 		(unsigned long)addr, dwc2_readl(hsotg, GRXFSIZ));
754 	addr = hsotg->regs + GNPTXFSIZ;
755 	dev_dbg(hsotg->dev, "GNPTXFSIZ	 @0x%08lX : 0x%08X\n",
756 		(unsigned long)addr, dwc2_readl(hsotg, GNPTXFSIZ));
757 	addr = hsotg->regs + GNPTXSTS;
758 	dev_dbg(hsotg->dev, "GNPTXSTS	 @0x%08lX : 0x%08X\n",
759 		(unsigned long)addr, dwc2_readl(hsotg, GNPTXSTS));
760 	addr = hsotg->regs + GI2CCTL;
761 	dev_dbg(hsotg->dev, "GI2CCTL	 @0x%08lX : 0x%08X\n",
762 		(unsigned long)addr, dwc2_readl(hsotg, GI2CCTL));
763 	addr = hsotg->regs + GPVNDCTL;
764 	dev_dbg(hsotg->dev, "GPVNDCTL	 @0x%08lX : 0x%08X\n",
765 		(unsigned long)addr, dwc2_readl(hsotg, GPVNDCTL));
766 	addr = hsotg->regs + GGPIO;
767 	dev_dbg(hsotg->dev, "GGPIO	 @0x%08lX : 0x%08X\n",
768 		(unsigned long)addr, dwc2_readl(hsotg, GGPIO));
769 	addr = hsotg->regs + GUID;
770 	dev_dbg(hsotg->dev, "GUID	 @0x%08lX : 0x%08X\n",
771 		(unsigned long)addr, dwc2_readl(hsotg, GUID));
772 	addr = hsotg->regs + GSNPSID;
773 	dev_dbg(hsotg->dev, "GSNPSID	 @0x%08lX : 0x%08X\n",
774 		(unsigned long)addr, dwc2_readl(hsotg, GSNPSID));
775 	addr = hsotg->regs + GHWCFG1;
776 	dev_dbg(hsotg->dev, "GHWCFG1	 @0x%08lX : 0x%08X\n",
777 		(unsigned long)addr, dwc2_readl(hsotg, GHWCFG1));
778 	addr = hsotg->regs + GHWCFG2;
779 	dev_dbg(hsotg->dev, "GHWCFG2	 @0x%08lX : 0x%08X\n",
780 		(unsigned long)addr, dwc2_readl(hsotg, GHWCFG2));
781 	addr = hsotg->regs + GHWCFG3;
782 	dev_dbg(hsotg->dev, "GHWCFG3	 @0x%08lX : 0x%08X\n",
783 		(unsigned long)addr, dwc2_readl(hsotg, GHWCFG3));
784 	addr = hsotg->regs + GHWCFG4;
785 	dev_dbg(hsotg->dev, "GHWCFG4	 @0x%08lX : 0x%08X\n",
786 		(unsigned long)addr, dwc2_readl(hsotg, GHWCFG4));
787 	addr = hsotg->regs + GLPMCFG;
788 	dev_dbg(hsotg->dev, "GLPMCFG	 @0x%08lX : 0x%08X\n",
789 		(unsigned long)addr, dwc2_readl(hsotg, GLPMCFG));
790 	addr = hsotg->regs + GPWRDN;
791 	dev_dbg(hsotg->dev, "GPWRDN	 @0x%08lX : 0x%08X\n",
792 		(unsigned long)addr, dwc2_readl(hsotg, GPWRDN));
793 	addr = hsotg->regs + GDFIFOCFG;
794 	dev_dbg(hsotg->dev, "GDFIFOCFG	 @0x%08lX : 0x%08X\n",
795 		(unsigned long)addr, dwc2_readl(hsotg, GDFIFOCFG));
796 	addr = hsotg->regs + HPTXFSIZ;
797 	dev_dbg(hsotg->dev, "HPTXFSIZ	 @0x%08lX : 0x%08X\n",
798 		(unsigned long)addr, dwc2_readl(hsotg, HPTXFSIZ));
799 
800 	addr = hsotg->regs + PCGCTL;
801 	dev_dbg(hsotg->dev, "PCGCTL	 @0x%08lX : 0x%08X\n",
802 		(unsigned long)addr, dwc2_readl(hsotg, PCGCTL));
803 #endif
804 }
805 
806 /**
807  * dwc2_flush_tx_fifo() - Flushes a Tx FIFO
808  *
809  * @hsotg: Programming view of DWC_otg controller
810  * @num:   Tx FIFO to flush
811  */
dwc2_flush_tx_fifo(struct dwc2_hsotg * hsotg,const int num)812 void dwc2_flush_tx_fifo(struct dwc2_hsotg *hsotg, const int num)
813 {
814 	u32 greset;
815 
816 	dev_vdbg(hsotg->dev, "Flush Tx FIFO %d\n", num);
817 
818 	/* Wait for AHB master IDLE state */
819 	if (dwc2_hsotg_wait_bit_set(hsotg, GRSTCTL, GRSTCTL_AHBIDLE, 10000))
820 		dev_warn(hsotg->dev, "%s:  HANG! AHB Idle GRSCTL\n",
821 			 __func__);
822 
823 	greset = GRSTCTL_TXFFLSH;
824 	greset |= num << GRSTCTL_TXFNUM_SHIFT & GRSTCTL_TXFNUM_MASK;
825 	dwc2_writel(hsotg, greset, GRSTCTL);
826 
827 	if (dwc2_hsotg_wait_bit_clear(hsotg, GRSTCTL, GRSTCTL_TXFFLSH, 10000))
828 		dev_warn(hsotg->dev, "%s:  HANG! timeout GRSTCTL GRSTCTL_TXFFLSH\n",
829 			 __func__);
830 
831 	/* Wait for at least 3 PHY Clocks */
832 	udelay(1);
833 }
834 
835 /**
836  * dwc2_flush_rx_fifo() - Flushes the Rx FIFO
837  *
838  * @hsotg: Programming view of DWC_otg controller
839  */
dwc2_flush_rx_fifo(struct dwc2_hsotg * hsotg)840 void dwc2_flush_rx_fifo(struct dwc2_hsotg *hsotg)
841 {
842 	u32 greset;
843 
844 	dev_vdbg(hsotg->dev, "%s()\n", __func__);
845 
846 	/* Wait for AHB master IDLE state */
847 	if (dwc2_hsotg_wait_bit_set(hsotg, GRSTCTL, GRSTCTL_AHBIDLE, 10000))
848 		dev_warn(hsotg->dev, "%s:  HANG! AHB Idle GRSCTL\n",
849 			 __func__);
850 
851 	greset = GRSTCTL_RXFFLSH;
852 	dwc2_writel(hsotg, greset, GRSTCTL);
853 
854 	/* Wait for RxFIFO flush done */
855 	if (dwc2_hsotg_wait_bit_clear(hsotg, GRSTCTL, GRSTCTL_RXFFLSH, 10000))
856 		dev_warn(hsotg->dev, "%s: HANG! timeout GRSTCTL GRSTCTL_RXFFLSH\n",
857 			 __func__);
858 
859 	/* Wait for at least 3 PHY Clocks */
860 	udelay(1);
861 }
862 
dwc2_is_controller_alive(struct dwc2_hsotg * hsotg)863 bool dwc2_is_controller_alive(struct dwc2_hsotg *hsotg)
864 {
865 	if (dwc2_readl(hsotg, GSNPSID) == 0xffffffff)
866 		return false;
867 	else
868 		return true;
869 }
870 
871 /**
872  * dwc2_enable_global_interrupts() - Enables the controller's Global
873  * Interrupt in the AHB Config register
874  *
875  * @hsotg: Programming view of DWC_otg controller
876  */
dwc2_enable_global_interrupts(struct dwc2_hsotg * hsotg)877 void dwc2_enable_global_interrupts(struct dwc2_hsotg *hsotg)
878 {
879 	u32 ahbcfg = dwc2_readl(hsotg, GAHBCFG);
880 
881 	ahbcfg |= GAHBCFG_GLBL_INTR_EN;
882 	dwc2_writel(hsotg, ahbcfg, GAHBCFG);
883 }
884 
885 /**
886  * dwc2_disable_global_interrupts() - Disables the controller's Global
887  * Interrupt in the AHB Config register
888  *
889  * @hsotg: Programming view of DWC_otg controller
890  */
dwc2_disable_global_interrupts(struct dwc2_hsotg * hsotg)891 void dwc2_disable_global_interrupts(struct dwc2_hsotg *hsotg)
892 {
893 	u32 ahbcfg = dwc2_readl(hsotg, GAHBCFG);
894 
895 	ahbcfg &= ~GAHBCFG_GLBL_INTR_EN;
896 	dwc2_writel(hsotg, ahbcfg, GAHBCFG);
897 }
898 
899 /* Returns the controller's GHWCFG2.OTG_MODE. */
dwc2_op_mode(struct dwc2_hsotg * hsotg)900 unsigned int dwc2_op_mode(struct dwc2_hsotg *hsotg)
901 {
902 	u32 ghwcfg2 = dwc2_readl(hsotg, GHWCFG2);
903 
904 	return (ghwcfg2 & GHWCFG2_OP_MODE_MASK) >>
905 		GHWCFG2_OP_MODE_SHIFT;
906 }
907 
908 /* Returns true if the controller is capable of DRD. */
dwc2_hw_is_otg(struct dwc2_hsotg * hsotg)909 bool dwc2_hw_is_otg(struct dwc2_hsotg *hsotg)
910 {
911 	unsigned int op_mode = dwc2_op_mode(hsotg);
912 
913 	return (op_mode == GHWCFG2_OP_MODE_HNP_SRP_CAPABLE) ||
914 		(op_mode == GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE) ||
915 		(op_mode == GHWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE);
916 }
917 
918 /* Returns true if the controller is host-only. */
dwc2_hw_is_host(struct dwc2_hsotg * hsotg)919 bool dwc2_hw_is_host(struct dwc2_hsotg *hsotg)
920 {
921 	unsigned int op_mode = dwc2_op_mode(hsotg);
922 
923 	return (op_mode == GHWCFG2_OP_MODE_SRP_CAPABLE_HOST) ||
924 		(op_mode == GHWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST);
925 }
926 
927 /* Returns true if the controller is device-only. */
dwc2_hw_is_device(struct dwc2_hsotg * hsotg)928 bool dwc2_hw_is_device(struct dwc2_hsotg *hsotg)
929 {
930 	unsigned int op_mode = dwc2_op_mode(hsotg);
931 
932 	return (op_mode == GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE) ||
933 		(op_mode == GHWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE);
934 }
935 
936 /**
937  * dwc2_hsotg_wait_bit_set - Waits for bit to be set.
938  * @hsotg: Programming view of DWC_otg controller.
939  * @offset: Register's offset where bit/bits must be set.
940  * @mask: Mask of the bit/bits which must be set.
941  * @timeout: Timeout to wait.
942  *
943  * Return: 0 if bit/bits are set or -ETIMEDOUT in case of timeout.
944  */
dwc2_hsotg_wait_bit_set(struct dwc2_hsotg * hsotg,u32 offset,u32 mask,u32 timeout)945 int dwc2_hsotg_wait_bit_set(struct dwc2_hsotg *hsotg, u32 offset, u32 mask,
946 			    u32 timeout)
947 {
948 	u32 i;
949 
950 	for (i = 0; i < timeout; i++) {
951 		if (dwc2_readl(hsotg, offset) & mask)
952 			return 0;
953 		udelay(1);
954 	}
955 
956 	return -ETIMEDOUT;
957 }
958 
959 /**
960  * dwc2_hsotg_wait_bit_clear - Waits for bit to be clear.
961  * @hsotg: Programming view of DWC_otg controller.
962  * @offset: Register's offset where bit/bits must be set.
963  * @mask: Mask of the bit/bits which must be set.
964  * @timeout: Timeout to wait.
965  *
966  * Return: 0 if bit/bits are set or -ETIMEDOUT in case of timeout.
967  */
dwc2_hsotg_wait_bit_clear(struct dwc2_hsotg * hsotg,u32 offset,u32 mask,u32 timeout)968 int dwc2_hsotg_wait_bit_clear(struct dwc2_hsotg *hsotg, u32 offset, u32 mask,
969 			      u32 timeout)
970 {
971 	u32 i;
972 
973 	for (i = 0; i < timeout; i++) {
974 		if (!(dwc2_readl(hsotg, offset) & mask))
975 			return 0;
976 		udelay(1);
977 	}
978 
979 	return -ETIMEDOUT;
980 }
981 
982 /*
983  * Initializes the FSLSPClkSel field of the HCFG register depending on the
984  * PHY type
985  */
dwc2_init_fs_ls_pclk_sel(struct dwc2_hsotg * hsotg)986 void dwc2_init_fs_ls_pclk_sel(struct dwc2_hsotg *hsotg)
987 {
988 	u32 hcfg, val;
989 
990 	if ((hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_ULPI &&
991 	     hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED &&
992 	     hsotg->params.ulpi_fs_ls) ||
993 	    hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS) {
994 		/* Full speed PHY */
995 		val = HCFG_FSLSPCLKSEL_48_MHZ;
996 	} else {
997 		/* High speed PHY running at full speed or high speed */
998 		val = HCFG_FSLSPCLKSEL_30_60_MHZ;
999 	}
1000 
1001 	dev_dbg(hsotg->dev, "Initializing HCFG.FSLSPClkSel to %08x\n", val);
1002 	hcfg = dwc2_readl(hsotg, HCFG);
1003 	hcfg &= ~HCFG_FSLSPCLKSEL_MASK;
1004 	hcfg |= val << HCFG_FSLSPCLKSEL_SHIFT;
1005 	dwc2_writel(hsotg, hcfg, HCFG);
1006 }
1007 
dwc2_fs_phy_init(struct dwc2_hsotg * hsotg,bool select_phy)1008 static int dwc2_fs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
1009 {
1010 	u32 usbcfg, ggpio, i2cctl;
1011 	int retval = 0;
1012 
1013 	/*
1014 	 * core_init() is now called on every switch so only call the
1015 	 * following for the first time through
1016 	 */
1017 	if (select_phy) {
1018 		dev_dbg(hsotg->dev, "FS PHY selected\n");
1019 
1020 		usbcfg = dwc2_readl(hsotg, GUSBCFG);
1021 		if (!(usbcfg & GUSBCFG_PHYSEL)) {
1022 			usbcfg |= GUSBCFG_PHYSEL;
1023 			dwc2_writel(hsotg, usbcfg, GUSBCFG);
1024 
1025 			/* Reset after a PHY select */
1026 			retval = dwc2_core_reset(hsotg, false);
1027 
1028 			if (retval) {
1029 				dev_err(hsotg->dev,
1030 					"%s: Reset failed, aborting", __func__);
1031 				return retval;
1032 			}
1033 		}
1034 
1035 		if (hsotg->params.activate_stm_fs_transceiver) {
1036 			ggpio = dwc2_readl(hsotg, GGPIO);
1037 			if (!(ggpio & GGPIO_STM32_OTG_GCCFG_PWRDWN)) {
1038 				dev_dbg(hsotg->dev, "Activating transceiver\n");
1039 				/*
1040 				 * STM32F4x9 uses the GGPIO register as general
1041 				 * core configuration register.
1042 				 */
1043 				ggpio |= GGPIO_STM32_OTG_GCCFG_PWRDWN;
1044 				dwc2_writel(hsotg, ggpio, GGPIO);
1045 			}
1046 		}
1047 	}
1048 
1049 	/*
1050 	 * Program DCFG.DevSpd or HCFG.FSLSPclkSel to 48Mhz in FS. Also
1051 	 * do this on HNP Dev/Host mode switches (done in dev_init and
1052 	 * host_init).
1053 	 */
1054 	if (dwc2_is_host_mode(hsotg))
1055 		dwc2_init_fs_ls_pclk_sel(hsotg);
1056 
1057 	if (hsotg->params.i2c_enable) {
1058 		dev_dbg(hsotg->dev, "FS PHY enabling I2C\n");
1059 
1060 		/* Program GUSBCFG.OtgUtmiFsSel to I2C */
1061 		usbcfg = dwc2_readl(hsotg, GUSBCFG);
1062 		usbcfg |= GUSBCFG_OTG_UTMI_FS_SEL;
1063 		dwc2_writel(hsotg, usbcfg, GUSBCFG);
1064 
1065 		/* Program GI2CCTL.I2CEn */
1066 		i2cctl = dwc2_readl(hsotg, GI2CCTL);
1067 		i2cctl &= ~GI2CCTL_I2CDEVADDR_MASK;
1068 		i2cctl |= 1 << GI2CCTL_I2CDEVADDR_SHIFT;
1069 		i2cctl &= ~GI2CCTL_I2CEN;
1070 		dwc2_writel(hsotg, i2cctl, GI2CCTL);
1071 		i2cctl |= GI2CCTL_I2CEN;
1072 		dwc2_writel(hsotg, i2cctl, GI2CCTL);
1073 	}
1074 
1075 	return retval;
1076 }
1077 
dwc2_hs_phy_init(struct dwc2_hsotg * hsotg,bool select_phy)1078 static int dwc2_hs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
1079 {
1080 	u32 usbcfg, usbcfg_old;
1081 	int retval = 0;
1082 
1083 	if (!select_phy)
1084 		return 0;
1085 
1086 	usbcfg = dwc2_readl(hsotg, GUSBCFG);
1087 	usbcfg_old = usbcfg;
1088 
1089 	/*
1090 	 * HS PHY parameters. These parameters are preserved during soft reset
1091 	 * so only program the first time. Do a soft reset immediately after
1092 	 * setting phyif.
1093 	 */
1094 	switch (hsotg->params.phy_type) {
1095 	case DWC2_PHY_TYPE_PARAM_ULPI:
1096 		/* ULPI interface */
1097 		dev_dbg(hsotg->dev, "HS ULPI PHY selected\n");
1098 		usbcfg |= GUSBCFG_ULPI_UTMI_SEL;
1099 		usbcfg &= ~(GUSBCFG_PHYIF16 | GUSBCFG_DDRSEL);
1100 		if (hsotg->params.phy_ulpi_ddr)
1101 			usbcfg |= GUSBCFG_DDRSEL;
1102 
1103 		/* Set external VBUS indicator as needed. */
1104 		if (hsotg->params.oc_disable)
1105 			usbcfg |= (GUSBCFG_ULPI_INT_VBUS_IND |
1106 				   GUSBCFG_INDICATORPASSTHROUGH);
1107 		break;
1108 	case DWC2_PHY_TYPE_PARAM_UTMI:
1109 		/* UTMI+ interface */
1110 		dev_dbg(hsotg->dev, "HS UTMI+ PHY selected\n");
1111 		usbcfg &= ~(GUSBCFG_ULPI_UTMI_SEL | GUSBCFG_PHYIF16);
1112 		if (hsotg->params.phy_utmi_width == 16)
1113 			usbcfg |= GUSBCFG_PHYIF16;
1114 		break;
1115 	default:
1116 		dev_err(hsotg->dev, "FS PHY selected at HS!\n");
1117 		break;
1118 	}
1119 
1120 	if (usbcfg != usbcfg_old) {
1121 		dwc2_writel(hsotg, usbcfg, GUSBCFG);
1122 
1123 		/* Reset after setting the PHY parameters */
1124 		retval = dwc2_core_reset(hsotg, false);
1125 		if (retval) {
1126 			dev_err(hsotg->dev,
1127 				"%s: Reset failed, aborting", __func__);
1128 			return retval;
1129 		}
1130 	}
1131 
1132 	return retval;
1133 }
1134 
dwc2_set_turnaround_time(struct dwc2_hsotg * hsotg)1135 static void dwc2_set_turnaround_time(struct dwc2_hsotg *hsotg)
1136 {
1137 	u32 usbcfg;
1138 
1139 	if (hsotg->params.phy_type != DWC2_PHY_TYPE_PARAM_UTMI)
1140 		return;
1141 
1142 	usbcfg = dwc2_readl(hsotg, GUSBCFG);
1143 
1144 	usbcfg &= ~GUSBCFG_USBTRDTIM_MASK;
1145 	if (hsotg->params.phy_utmi_width == 16)
1146 		usbcfg |= 5 << GUSBCFG_USBTRDTIM_SHIFT;
1147 	else
1148 		usbcfg |= 9 << GUSBCFG_USBTRDTIM_SHIFT;
1149 
1150 	dwc2_writel(hsotg, usbcfg, GUSBCFG);
1151 }
1152 
dwc2_phy_init(struct dwc2_hsotg * hsotg,bool select_phy)1153 int dwc2_phy_init(struct dwc2_hsotg *hsotg, bool select_phy)
1154 {
1155 	u32 usbcfg;
1156 	u32 otgctl;
1157 	int retval = 0;
1158 
1159 	if ((hsotg->params.speed == DWC2_SPEED_PARAM_FULL ||
1160 	     hsotg->params.speed == DWC2_SPEED_PARAM_LOW) &&
1161 	    hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS) {
1162 		/* If FS/LS mode with FS/LS PHY */
1163 		retval = dwc2_fs_phy_init(hsotg, select_phy);
1164 		if (retval)
1165 			return retval;
1166 	} else {
1167 		/* High speed PHY */
1168 		retval = dwc2_hs_phy_init(hsotg, select_phy);
1169 		if (retval)
1170 			return retval;
1171 
1172 		if (dwc2_is_device_mode(hsotg))
1173 			dwc2_set_turnaround_time(hsotg);
1174 	}
1175 
1176 	if (hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_ULPI &&
1177 	    hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED &&
1178 	    hsotg->params.ulpi_fs_ls) {
1179 		dev_dbg(hsotg->dev, "Setting ULPI FSLS\n");
1180 		usbcfg = dwc2_readl(hsotg, GUSBCFG);
1181 		usbcfg |= GUSBCFG_ULPI_FS_LS;
1182 		usbcfg |= GUSBCFG_ULPI_CLK_SUSP_M;
1183 		dwc2_writel(hsotg, usbcfg, GUSBCFG);
1184 	} else {
1185 		usbcfg = dwc2_readl(hsotg, GUSBCFG);
1186 		usbcfg &= ~GUSBCFG_ULPI_FS_LS;
1187 		usbcfg &= ~GUSBCFG_ULPI_CLK_SUSP_M;
1188 		dwc2_writel(hsotg, usbcfg, GUSBCFG);
1189 	}
1190 
1191 	if (!hsotg->params.activate_ingenic_overcurrent_detection) {
1192 		if (dwc2_is_host_mode(hsotg)) {
1193 			otgctl = readl(hsotg->regs + GOTGCTL);
1194 			otgctl |= GOTGCTL_VBVALOEN | GOTGCTL_VBVALOVAL;
1195 			writel(otgctl, hsotg->regs + GOTGCTL);
1196 		}
1197 	}
1198 
1199 	return retval;
1200 }
1201 
1202 MODULE_DESCRIPTION("DESIGNWARE HS OTG Core");
1203 MODULE_AUTHOR("Synopsys, Inc.");
1204 MODULE_LICENSE("Dual BSD/GPL");
1205