1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * UFS Host Controller driver for Exynos specific extensions
4 *
5 * Copyright (C) 2014-2015 Samsung Electronics Co., Ltd.
6 * Author: Seungwon Jeon <essuuj@gmail.com>
7 * Author: Alim Akhtar <alim.akhtar@samsung.com>
8 *
9 */
10
11 #include <linux/clk.h>
12 #include <linux/delay.h>
13 #include <linux/module.h>
14 #include <linux/of.h>
15 #include <linux/of_address.h>
16 #include <linux/mfd/syscon.h>
17 #include <linux/phy/phy.h>
18 #include <linux/platform_device.h>
19 #include <linux/regmap.h>
20
21 #include <ufs/ufshcd.h>
22 #include "ufshcd-pltfrm.h"
23 #include <ufs/ufshci.h>
24 #include <ufs/unipro.h>
25
26 #include "ufs-exynos.h"
27
28 /*
29 * Exynos's Vendor specific registers for UFSHCI
30 */
31 #define HCI_TXPRDT_ENTRY_SIZE 0x00
32 #define PRDT_PREFECT_EN BIT(31)
33 #define PRDT_SET_SIZE(x) ((x) & 0x1F)
34 #define HCI_RXPRDT_ENTRY_SIZE 0x04
35 #define HCI_1US_TO_CNT_VAL 0x0C
36 #define CNT_VAL_1US_MASK 0x3FF
37 #define HCI_UTRL_NEXUS_TYPE 0x40
38 #define HCI_UTMRL_NEXUS_TYPE 0x44
39 #define HCI_SW_RST 0x50
40 #define UFS_LINK_SW_RST BIT(0)
41 #define UFS_UNIPRO_SW_RST BIT(1)
42 #define UFS_SW_RST_MASK (UFS_UNIPRO_SW_RST | UFS_LINK_SW_RST)
43 #define HCI_DATA_REORDER 0x60
44 #define HCI_UNIPRO_APB_CLK_CTRL 0x68
45 #define UNIPRO_APB_CLK(v, x) (((v) & ~0xF) | ((x) & 0xF))
46 #define HCI_AXIDMA_RWDATA_BURST_LEN 0x6C
47 #define HCI_GPIO_OUT 0x70
48 #define HCI_ERR_EN_PA_LAYER 0x78
49 #define HCI_ERR_EN_DL_LAYER 0x7C
50 #define HCI_ERR_EN_N_LAYER 0x80
51 #define HCI_ERR_EN_T_LAYER 0x84
52 #define HCI_ERR_EN_DME_LAYER 0x88
53 #define HCI_CLKSTOP_CTRL 0xB0
54 #define REFCLKOUT_STOP BIT(4)
55 #define REFCLK_STOP BIT(2)
56 #define UNIPRO_MCLK_STOP BIT(1)
57 #define UNIPRO_PCLK_STOP BIT(0)
58 #define CLK_STOP_MASK (REFCLKOUT_STOP | REFCLK_STOP |\
59 UNIPRO_MCLK_STOP |\
60 UNIPRO_PCLK_STOP)
61 #define HCI_MISC 0xB4
62 #define REFCLK_CTRL_EN BIT(7)
63 #define UNIPRO_PCLK_CTRL_EN BIT(6)
64 #define UNIPRO_MCLK_CTRL_EN BIT(5)
65 #define HCI_CORECLK_CTRL_EN BIT(4)
66 #define CLK_CTRL_EN_MASK (REFCLK_CTRL_EN |\
67 UNIPRO_PCLK_CTRL_EN |\
68 UNIPRO_MCLK_CTRL_EN)
69 /* Device fatal error */
70 #define DFES_ERR_EN BIT(31)
71 #define DFES_DEF_L2_ERRS (UIC_DATA_LINK_LAYER_ERROR_RX_BUF_OF |\
72 UIC_DATA_LINK_LAYER_ERROR_PA_INIT)
73 #define DFES_DEF_L3_ERRS (UIC_NETWORK_UNSUPPORTED_HEADER_TYPE |\
74 UIC_NETWORK_BAD_DEVICEID_ENC |\
75 UIC_NETWORK_LHDR_TRAP_PACKET_DROPPING)
76 #define DFES_DEF_L4_ERRS (UIC_TRANSPORT_UNSUPPORTED_HEADER_TYPE |\
77 UIC_TRANSPORT_UNKNOWN_CPORTID |\
78 UIC_TRANSPORT_NO_CONNECTION_RX |\
79 UIC_TRANSPORT_BAD_TC)
80
81 /* FSYS UFS Shareability */
82 #define UFS_WR_SHARABLE BIT(2)
83 #define UFS_RD_SHARABLE BIT(1)
84 #define UFS_SHARABLE (UFS_WR_SHARABLE | UFS_RD_SHARABLE)
85 #define UFS_SHAREABILITY_OFFSET 0x710
86
87 /* Multi-host registers */
88 #define MHCTRL 0xC4
89 #define MHCTRL_EN_VH_MASK (0xE)
90 #define MHCTRL_EN_VH(vh) (vh << 1)
91 #define PH2VH_MBOX 0xD8
92
93 #define MH_MSG_MASK (0xFF)
94
95 #define MH_MSG(id, msg) ((id << 8) | (msg & 0xFF))
96 #define MH_MSG_PH_READY 0x1
97 #define MH_MSG_VH_READY 0x2
98
99 #define ALLOW_INQUIRY BIT(25)
100 #define ALLOW_MODE_SELECT BIT(24)
101 #define ALLOW_MODE_SENSE BIT(23)
102 #define ALLOW_PRE_FETCH GENMASK(22, 21)
103 #define ALLOW_READ_CMD_ALL GENMASK(20, 18) /* read_6/10/16 */
104 #define ALLOW_READ_BUFFER BIT(17)
105 #define ALLOW_READ_CAPACITY GENMASK(16, 15)
106 #define ALLOW_REPORT_LUNS BIT(14)
107 #define ALLOW_REQUEST_SENSE BIT(13)
108 #define ALLOW_SYNCHRONIZE_CACHE GENMASK(8, 7)
109 #define ALLOW_TEST_UNIT_READY BIT(6)
110 #define ALLOW_UNMAP BIT(5)
111 #define ALLOW_VERIFY BIT(4)
112 #define ALLOW_WRITE_CMD_ALL GENMASK(3, 1) /* write_6/10/16 */
113
114 #define ALLOW_TRANS_VH_DEFAULT (ALLOW_INQUIRY | ALLOW_MODE_SELECT | \
115 ALLOW_MODE_SENSE | ALLOW_PRE_FETCH | \
116 ALLOW_READ_CMD_ALL | ALLOW_READ_BUFFER | \
117 ALLOW_READ_CAPACITY | ALLOW_REPORT_LUNS | \
118 ALLOW_REQUEST_SENSE | ALLOW_SYNCHRONIZE_CACHE | \
119 ALLOW_TEST_UNIT_READY | ALLOW_UNMAP | \
120 ALLOW_VERIFY | ALLOW_WRITE_CMD_ALL)
121
122 #define HCI_MH_ALLOWABLE_TRAN_OF_VH 0x30C
123 #define HCI_MH_IID_IN_TASK_TAG 0X308
124
125 #define PH_READY_TIMEOUT_MS (5 * MSEC_PER_SEC)
126
127 enum {
128 UNIPRO_L1_5 = 0,/* PHY Adapter */
129 UNIPRO_L2, /* Data Link */
130 UNIPRO_L3, /* Network */
131 UNIPRO_L4, /* Transport */
132 UNIPRO_DME, /* DME */
133 };
134
135 /*
136 * UNIPRO registers
137 */
138 #define UNIPRO_COMP_VERSION 0x000
139 #define UNIPRO_DME_PWR_REQ 0x090
140 #define UNIPRO_DME_PWR_REQ_POWERMODE 0x094
141 #define UNIPRO_DME_PWR_REQ_LOCALL2TIMER0 0x098
142 #define UNIPRO_DME_PWR_REQ_LOCALL2TIMER1 0x09C
143 #define UNIPRO_DME_PWR_REQ_LOCALL2TIMER2 0x0A0
144 #define UNIPRO_DME_PWR_REQ_REMOTEL2TIMER0 0x0A4
145 #define UNIPRO_DME_PWR_REQ_REMOTEL2TIMER1 0x0A8
146 #define UNIPRO_DME_PWR_REQ_REMOTEL2TIMER2 0x0AC
147
148 /*
149 * UFS Protector registers
150 */
151 #define UFSPRSECURITY 0x010
152 #define NSSMU BIT(14)
153 #define UFSPSBEGIN0 0x200
154 #define UFSPSEND0 0x204
155 #define UFSPSLUN0 0x208
156 #define UFSPSCTRL0 0x20C
157
158 #define CNTR_DIV_VAL 40
159
160 static struct exynos_ufs_drv_data exynos_ufs_drvs;
161 static void exynos_ufs_auto_ctrl_hcc(struct exynos_ufs *ufs, bool en);
162 static void exynos_ufs_ctrl_clkstop(struct exynos_ufs *ufs, bool en);
163
exynos_ufs_enable_auto_ctrl_hcc(struct exynos_ufs * ufs)164 static inline void exynos_ufs_enable_auto_ctrl_hcc(struct exynos_ufs *ufs)
165 {
166 exynos_ufs_auto_ctrl_hcc(ufs, true);
167 }
168
exynos_ufs_disable_auto_ctrl_hcc(struct exynos_ufs * ufs)169 static inline void exynos_ufs_disable_auto_ctrl_hcc(struct exynos_ufs *ufs)
170 {
171 exynos_ufs_auto_ctrl_hcc(ufs, false);
172 }
173
exynos_ufs_disable_auto_ctrl_hcc_save(struct exynos_ufs * ufs,u32 * val)174 static inline void exynos_ufs_disable_auto_ctrl_hcc_save(
175 struct exynos_ufs *ufs, u32 *val)
176 {
177 *val = hci_readl(ufs, HCI_MISC);
178 exynos_ufs_auto_ctrl_hcc(ufs, false);
179 }
180
exynos_ufs_auto_ctrl_hcc_restore(struct exynos_ufs * ufs,u32 * val)181 static inline void exynos_ufs_auto_ctrl_hcc_restore(
182 struct exynos_ufs *ufs, u32 *val)
183 {
184 hci_writel(ufs, *val, HCI_MISC);
185 }
186
exynos_ufs_gate_clks(struct exynos_ufs * ufs)187 static inline void exynos_ufs_gate_clks(struct exynos_ufs *ufs)
188 {
189 exynos_ufs_ctrl_clkstop(ufs, true);
190 }
191
exynos_ufs_ungate_clks(struct exynos_ufs * ufs)192 static inline void exynos_ufs_ungate_clks(struct exynos_ufs *ufs)
193 {
194 exynos_ufs_ctrl_clkstop(ufs, false);
195 }
196
exynos7_ufs_drv_init(struct device * dev,struct exynos_ufs * ufs)197 static int exynos7_ufs_drv_init(struct device *dev, struct exynos_ufs *ufs)
198 {
199 return 0;
200 }
201
exynosauto_ufs_drv_init(struct device * dev,struct exynos_ufs * ufs)202 static int exynosauto_ufs_drv_init(struct device *dev, struct exynos_ufs *ufs)
203 {
204 struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr;
205
206 /* IO Coherency setting */
207 if (ufs->sysreg) {
208 return regmap_update_bits(ufs->sysreg,
209 ufs->shareability_reg_offset,
210 UFS_SHARABLE, UFS_SHARABLE);
211 }
212
213 attr->tx_dif_p_nsec = 3200000;
214
215 return 0;
216 }
217
exynosauto_ufs_post_hce_enable(struct exynos_ufs * ufs)218 static int exynosauto_ufs_post_hce_enable(struct exynos_ufs *ufs)
219 {
220 struct ufs_hba *hba = ufs->hba;
221
222 /* Enable Virtual Host #1 */
223 ufshcd_rmwl(hba, MHCTRL_EN_VH_MASK, MHCTRL_EN_VH(1), MHCTRL);
224 /* Default VH Transfer permissions */
225 hci_writel(ufs, ALLOW_TRANS_VH_DEFAULT, HCI_MH_ALLOWABLE_TRAN_OF_VH);
226 /* IID information is replaced in TASKTAG[7:5] instead of IID in UCD */
227 hci_writel(ufs, 0x1, HCI_MH_IID_IN_TASK_TAG);
228
229 return 0;
230 }
231
exynosauto_ufs_pre_link(struct exynos_ufs * ufs)232 static int exynosauto_ufs_pre_link(struct exynos_ufs *ufs)
233 {
234 struct ufs_hba *hba = ufs->hba;
235 int i;
236 u32 tx_line_reset_period, rx_line_reset_period;
237
238 rx_line_reset_period = (RX_LINE_RESET_TIME * ufs->mclk_rate) / NSEC_PER_MSEC;
239 tx_line_reset_period = (TX_LINE_RESET_TIME * ufs->mclk_rate) / NSEC_PER_MSEC;
240
241 ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x40);
242 for_each_ufs_rx_lane(ufs, i) {
243 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_CLK_PRD, i),
244 DIV_ROUND_UP(NSEC_PER_SEC, ufs->mclk_rate));
245 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_CLK_PRD_EN, i), 0x0);
246
247 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_LINERESET_VALUE2, i),
248 (rx_line_reset_period >> 16) & 0xFF);
249 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_LINERESET_VALUE1, i),
250 (rx_line_reset_period >> 8) & 0xFF);
251 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_LINERESET_VALUE0, i),
252 (rx_line_reset_period) & 0xFF);
253
254 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x2f, i), 0x79);
255 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x84, i), 0x1);
256 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x25, i), 0xf6);
257 }
258
259 for_each_ufs_tx_lane(ufs, i) {
260 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_CLK_PRD, i),
261 DIV_ROUND_UP(NSEC_PER_SEC, ufs->mclk_rate));
262 /* Not to affect VND_TX_LINERESET_PVALUE to VND_TX_CLK_PRD */
263 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_CLK_PRD_EN, i),
264 0x02);
265
266 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_LINERESET_PVALUE2, i),
267 (tx_line_reset_period >> 16) & 0xFF);
268 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_LINERESET_PVALUE1, i),
269 (tx_line_reset_period >> 8) & 0xFF);
270 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_LINERESET_PVALUE0, i),
271 (tx_line_reset_period) & 0xFF);
272
273 /* TX PWM Gear Capability / PWM_G1_ONLY */
274 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x04, i), 0x1);
275 }
276
277 ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x0);
278
279 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_LOCAL_TX_LCC_ENABLE), 0x0);
280
281 ufshcd_dme_set(hba, UIC_ARG_MIB(0xa011), 0x8000);
282
283 return 0;
284 }
285
exynosauto_ufs_pre_pwr_change(struct exynos_ufs * ufs,struct ufs_pa_layer_attr * pwr)286 static int exynosauto_ufs_pre_pwr_change(struct exynos_ufs *ufs,
287 struct ufs_pa_layer_attr *pwr)
288 {
289 struct ufs_hba *hba = ufs->hba;
290
291 /* PACP_PWR_req and delivered to the remote DME */
292 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA0), 12000);
293 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA1), 32000);
294 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA2), 16000);
295
296 return 0;
297 }
298
exynosauto_ufs_post_pwr_change(struct exynos_ufs * ufs,struct ufs_pa_layer_attr * pwr)299 static int exynosauto_ufs_post_pwr_change(struct exynos_ufs *ufs,
300 struct ufs_pa_layer_attr *pwr)
301 {
302 struct ufs_hba *hba = ufs->hba;
303 u32 enabled_vh;
304
305 enabled_vh = ufshcd_readl(hba, MHCTRL) & MHCTRL_EN_VH_MASK;
306
307 /* Send physical host ready message to virtual hosts */
308 ufshcd_writel(hba, MH_MSG(enabled_vh, MH_MSG_PH_READY), PH2VH_MBOX);
309
310 return 0;
311 }
312
exynos7_ufs_pre_link(struct exynos_ufs * ufs)313 static int exynos7_ufs_pre_link(struct exynos_ufs *ufs)
314 {
315 struct ufs_hba *hba = ufs->hba;
316 u32 val = ufs->drv_data->uic_attr->pa_dbg_option_suite;
317 int i;
318
319 exynos_ufs_enable_ov_tm(hba);
320 for_each_ufs_tx_lane(ufs, i)
321 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x297, i), 0x17);
322 for_each_ufs_rx_lane(ufs, i) {
323 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x362, i), 0xff);
324 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x363, i), 0x00);
325 }
326 exynos_ufs_disable_ov_tm(hba);
327
328 for_each_ufs_tx_lane(ufs, i)
329 ufshcd_dme_set(hba,
330 UIC_ARG_MIB_SEL(TX_HIBERN8_CONTROL, i), 0x0);
331 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_TXPHY_CFGUPDT), 0x1);
332 udelay(1);
333 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_OPTION_SUITE), val | (1 << 12));
334 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_SKIP_RESET_PHY), 0x1);
335 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_SKIP_LINE_RESET), 0x1);
336 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_LINE_RESET_REQ), 0x1);
337 udelay(1600);
338 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_OPTION_SUITE), val);
339
340 return 0;
341 }
342
exynos7_ufs_post_link(struct exynos_ufs * ufs)343 static int exynos7_ufs_post_link(struct exynos_ufs *ufs)
344 {
345 struct ufs_hba *hba = ufs->hba;
346 int i;
347
348 exynos_ufs_enable_ov_tm(hba);
349 for_each_ufs_tx_lane(ufs, i) {
350 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x28b, i), 0x83);
351 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x29a, i), 0x07);
352 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x277, i),
353 TX_LINERESET_N(exynos_ufs_calc_time_cntr(ufs, 200000)));
354 }
355 exynos_ufs_disable_ov_tm(hba);
356
357 exynos_ufs_enable_dbg_mode(hba);
358 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_SAVECONFIGTIME), 0xbb8);
359 exynos_ufs_disable_dbg_mode(hba);
360
361 return 0;
362 }
363
exynos7_ufs_pre_pwr_change(struct exynos_ufs * ufs,struct ufs_pa_layer_attr * pwr)364 static int exynos7_ufs_pre_pwr_change(struct exynos_ufs *ufs,
365 struct ufs_pa_layer_attr *pwr)
366 {
367 unipro_writel(ufs, 0x22, UNIPRO_DBG_FORCE_DME_CTRL_STATE);
368
369 return 0;
370 }
371
exynos7_ufs_post_pwr_change(struct exynos_ufs * ufs,struct ufs_pa_layer_attr * pwr)372 static int exynos7_ufs_post_pwr_change(struct exynos_ufs *ufs,
373 struct ufs_pa_layer_attr *pwr)
374 {
375 struct ufs_hba *hba = ufs->hba;
376 int lanes = max_t(u32, pwr->lane_rx, pwr->lane_tx);
377
378 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_RXPHY_CFGUPDT), 0x1);
379
380 if (lanes == 1) {
381 exynos_ufs_enable_dbg_mode(hba);
382 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_CONNECTEDTXDATALANES), 0x1);
383 exynos_ufs_disable_dbg_mode(hba);
384 }
385
386 return 0;
387 }
388
389 /*
390 * exynos_ufs_auto_ctrl_hcc - HCI core clock control by h/w
391 * Control should be disabled in the below cases
392 * - Before host controller S/W reset
393 * - Access to UFS protector's register
394 */
exynos_ufs_auto_ctrl_hcc(struct exynos_ufs * ufs,bool en)395 static void exynos_ufs_auto_ctrl_hcc(struct exynos_ufs *ufs, bool en)
396 {
397 u32 misc = hci_readl(ufs, HCI_MISC);
398
399 if (en)
400 hci_writel(ufs, misc | HCI_CORECLK_CTRL_EN, HCI_MISC);
401 else
402 hci_writel(ufs, misc & ~HCI_CORECLK_CTRL_EN, HCI_MISC);
403 }
404
exynos_ufs_ctrl_clkstop(struct exynos_ufs * ufs,bool en)405 static void exynos_ufs_ctrl_clkstop(struct exynos_ufs *ufs, bool en)
406 {
407 u32 ctrl = hci_readl(ufs, HCI_CLKSTOP_CTRL);
408 u32 misc = hci_readl(ufs, HCI_MISC);
409
410 if (en) {
411 hci_writel(ufs, misc | CLK_CTRL_EN_MASK, HCI_MISC);
412 hci_writel(ufs, ctrl | CLK_STOP_MASK, HCI_CLKSTOP_CTRL);
413 } else {
414 hci_writel(ufs, ctrl & ~CLK_STOP_MASK, HCI_CLKSTOP_CTRL);
415 hci_writel(ufs, misc & ~CLK_CTRL_EN_MASK, HCI_MISC);
416 }
417 }
418
exynos_ufs_get_clk_info(struct exynos_ufs * ufs)419 static int exynos_ufs_get_clk_info(struct exynos_ufs *ufs)
420 {
421 struct ufs_hba *hba = ufs->hba;
422 struct list_head *head = &hba->clk_list_head;
423 struct ufs_clk_info *clki;
424 unsigned long pclk_rate;
425 u32 f_min, f_max;
426 u8 div = 0;
427 int ret = 0;
428
429 if (list_empty(head))
430 goto out;
431
432 list_for_each_entry(clki, head, list) {
433 if (!IS_ERR(clki->clk)) {
434 if (!strcmp(clki->name, "core_clk"))
435 ufs->clk_hci_core = clki->clk;
436 else if (!strcmp(clki->name, "sclk_unipro_main"))
437 ufs->clk_unipro_main = clki->clk;
438 }
439 }
440
441 if (!ufs->clk_hci_core || !ufs->clk_unipro_main) {
442 dev_err(hba->dev, "failed to get clk info\n");
443 ret = -EINVAL;
444 goto out;
445 }
446
447 ufs->mclk_rate = clk_get_rate(ufs->clk_unipro_main);
448 pclk_rate = clk_get_rate(ufs->clk_hci_core);
449 f_min = ufs->pclk_avail_min;
450 f_max = ufs->pclk_avail_max;
451
452 if (ufs->opts & EXYNOS_UFS_OPT_HAS_APB_CLK_CTRL) {
453 do {
454 pclk_rate /= (div + 1);
455
456 if (pclk_rate <= f_max)
457 break;
458 div++;
459 } while (pclk_rate >= f_min);
460 }
461
462 if (unlikely(pclk_rate < f_min || pclk_rate > f_max)) {
463 dev_err(hba->dev, "not available pclk range %lu\n", pclk_rate);
464 ret = -EINVAL;
465 goto out;
466 }
467
468 ufs->pclk_rate = pclk_rate;
469 ufs->pclk_div = div;
470
471 out:
472 return ret;
473 }
474
exynos_ufs_set_unipro_pclk_div(struct exynos_ufs * ufs)475 static void exynos_ufs_set_unipro_pclk_div(struct exynos_ufs *ufs)
476 {
477 if (ufs->opts & EXYNOS_UFS_OPT_HAS_APB_CLK_CTRL) {
478 u32 val;
479
480 val = hci_readl(ufs, HCI_UNIPRO_APB_CLK_CTRL);
481 hci_writel(ufs, UNIPRO_APB_CLK(val, ufs->pclk_div),
482 HCI_UNIPRO_APB_CLK_CTRL);
483 }
484 }
485
exynos_ufs_set_pwm_clk_div(struct exynos_ufs * ufs)486 static void exynos_ufs_set_pwm_clk_div(struct exynos_ufs *ufs)
487 {
488 struct ufs_hba *hba = ufs->hba;
489 struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr;
490
491 ufshcd_dme_set(hba,
492 UIC_ARG_MIB(CMN_PWM_CLK_CTRL), attr->cmn_pwm_clk_ctrl);
493 }
494
exynos_ufs_calc_pwm_clk_div(struct exynos_ufs * ufs)495 static void exynos_ufs_calc_pwm_clk_div(struct exynos_ufs *ufs)
496 {
497 struct ufs_hba *hba = ufs->hba;
498 struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr;
499 const unsigned int div = 30, mult = 20;
500 const unsigned long pwm_min = 3 * 1000 * 1000;
501 const unsigned long pwm_max = 9 * 1000 * 1000;
502 const int divs[] = {32, 16, 8, 4};
503 unsigned long clk = 0, _clk, clk_period;
504 int i = 0, clk_idx = -1;
505
506 clk_period = UNIPRO_PCLK_PERIOD(ufs);
507 for (i = 0; i < ARRAY_SIZE(divs); i++) {
508 _clk = NSEC_PER_SEC * mult / (clk_period * divs[i] * div);
509 if (_clk >= pwm_min && _clk <= pwm_max) {
510 if (_clk > clk) {
511 clk_idx = i;
512 clk = _clk;
513 }
514 }
515 }
516
517 if (clk_idx == -1) {
518 ufshcd_dme_get(hba, UIC_ARG_MIB(CMN_PWM_CLK_CTRL), &clk_idx);
519 dev_err(hba->dev,
520 "failed to decide pwm clock divider, will not change\n");
521 }
522
523 attr->cmn_pwm_clk_ctrl = clk_idx & PWM_CLK_CTRL_MASK;
524 }
525
exynos_ufs_calc_time_cntr(struct exynos_ufs * ufs,long period)526 long exynos_ufs_calc_time_cntr(struct exynos_ufs *ufs, long period)
527 {
528 const int precise = 10;
529 long pclk_rate = ufs->pclk_rate;
530 long clk_period, fraction;
531
532 clk_period = UNIPRO_PCLK_PERIOD(ufs);
533 fraction = ((NSEC_PER_SEC % pclk_rate) * precise) / pclk_rate;
534
535 return (period * precise) / ((clk_period * precise) + fraction);
536 }
537
exynos_ufs_specify_phy_time_attr(struct exynos_ufs * ufs)538 static void exynos_ufs_specify_phy_time_attr(struct exynos_ufs *ufs)
539 {
540 struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr;
541 struct ufs_phy_time_cfg *t_cfg = &ufs->t_cfg;
542
543 t_cfg->tx_linereset_p =
544 exynos_ufs_calc_time_cntr(ufs, attr->tx_dif_p_nsec);
545 t_cfg->tx_linereset_n =
546 exynos_ufs_calc_time_cntr(ufs, attr->tx_dif_n_nsec);
547 t_cfg->tx_high_z_cnt =
548 exynos_ufs_calc_time_cntr(ufs, attr->tx_high_z_cnt_nsec);
549 t_cfg->tx_base_n_val =
550 exynos_ufs_calc_time_cntr(ufs, attr->tx_base_unit_nsec);
551 t_cfg->tx_gran_n_val =
552 exynos_ufs_calc_time_cntr(ufs, attr->tx_gran_unit_nsec);
553 t_cfg->tx_sleep_cnt =
554 exynos_ufs_calc_time_cntr(ufs, attr->tx_sleep_cnt);
555
556 t_cfg->rx_linereset =
557 exynos_ufs_calc_time_cntr(ufs, attr->rx_dif_p_nsec);
558 t_cfg->rx_hibern8_wait =
559 exynos_ufs_calc_time_cntr(ufs, attr->rx_hibern8_wait_nsec);
560 t_cfg->rx_base_n_val =
561 exynos_ufs_calc_time_cntr(ufs, attr->rx_base_unit_nsec);
562 t_cfg->rx_gran_n_val =
563 exynos_ufs_calc_time_cntr(ufs, attr->rx_gran_unit_nsec);
564 t_cfg->rx_sleep_cnt =
565 exynos_ufs_calc_time_cntr(ufs, attr->rx_sleep_cnt);
566 t_cfg->rx_stall_cnt =
567 exynos_ufs_calc_time_cntr(ufs, attr->rx_stall_cnt);
568 }
569
exynos_ufs_config_phy_time_attr(struct exynos_ufs * ufs)570 static void exynos_ufs_config_phy_time_attr(struct exynos_ufs *ufs)
571 {
572 struct ufs_hba *hba = ufs->hba;
573 struct ufs_phy_time_cfg *t_cfg = &ufs->t_cfg;
574 int i;
575
576 exynos_ufs_set_pwm_clk_div(ufs);
577
578 exynos_ufs_enable_ov_tm(hba);
579
580 for_each_ufs_rx_lane(ufs, i) {
581 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_FILLER_ENABLE, i),
582 ufs->drv_data->uic_attr->rx_filler_enable);
583 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_LINERESET_VAL, i),
584 RX_LINERESET(t_cfg->rx_linereset));
585 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_BASE_NVAL_07_00, i),
586 RX_BASE_NVAL_L(t_cfg->rx_base_n_val));
587 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_BASE_NVAL_15_08, i),
588 RX_BASE_NVAL_H(t_cfg->rx_base_n_val));
589 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_GRAN_NVAL_07_00, i),
590 RX_GRAN_NVAL_L(t_cfg->rx_gran_n_val));
591 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_GRAN_NVAL_10_08, i),
592 RX_GRAN_NVAL_H(t_cfg->rx_gran_n_val));
593 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_OV_SLEEP_CNT_TIMER, i),
594 RX_OV_SLEEP_CNT(t_cfg->rx_sleep_cnt));
595 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(RX_OV_STALL_CNT_TIMER, i),
596 RX_OV_STALL_CNT(t_cfg->rx_stall_cnt));
597 }
598
599 for_each_ufs_tx_lane(ufs, i) {
600 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_LINERESET_P_VAL, i),
601 TX_LINERESET_P(t_cfg->tx_linereset_p));
602 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_HIGH_Z_CNT_07_00, i),
603 TX_HIGH_Z_CNT_L(t_cfg->tx_high_z_cnt));
604 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_HIGH_Z_CNT_11_08, i),
605 TX_HIGH_Z_CNT_H(t_cfg->tx_high_z_cnt));
606 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_BASE_NVAL_07_00, i),
607 TX_BASE_NVAL_L(t_cfg->tx_base_n_val));
608 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_BASE_NVAL_15_08, i),
609 TX_BASE_NVAL_H(t_cfg->tx_base_n_val));
610 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_GRAN_NVAL_07_00, i),
611 TX_GRAN_NVAL_L(t_cfg->tx_gran_n_val));
612 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_GRAN_NVAL_10_08, i),
613 TX_GRAN_NVAL_H(t_cfg->tx_gran_n_val));
614 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_OV_SLEEP_CNT_TIMER, i),
615 TX_OV_H8_ENTER_EN |
616 TX_OV_SLEEP_CNT(t_cfg->tx_sleep_cnt));
617 ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(TX_MIN_ACTIVATETIME, i),
618 ufs->drv_data->uic_attr->tx_min_activatetime);
619 }
620
621 exynos_ufs_disable_ov_tm(hba);
622 }
623
exynos_ufs_config_phy_cap_attr(struct exynos_ufs * ufs)624 static void exynos_ufs_config_phy_cap_attr(struct exynos_ufs *ufs)
625 {
626 struct ufs_hba *hba = ufs->hba;
627 struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr;
628 int i;
629
630 exynos_ufs_enable_ov_tm(hba);
631
632 for_each_ufs_rx_lane(ufs, i) {
633 ufshcd_dme_set(hba,
634 UIC_ARG_MIB_SEL(RX_HS_G1_SYNC_LENGTH_CAP, i),
635 attr->rx_hs_g1_sync_len_cap);
636 ufshcd_dme_set(hba,
637 UIC_ARG_MIB_SEL(RX_HS_G2_SYNC_LENGTH_CAP, i),
638 attr->rx_hs_g2_sync_len_cap);
639 ufshcd_dme_set(hba,
640 UIC_ARG_MIB_SEL(RX_HS_G3_SYNC_LENGTH_CAP, i),
641 attr->rx_hs_g3_sync_len_cap);
642 ufshcd_dme_set(hba,
643 UIC_ARG_MIB_SEL(RX_HS_G1_PREP_LENGTH_CAP, i),
644 attr->rx_hs_g1_prep_sync_len_cap);
645 ufshcd_dme_set(hba,
646 UIC_ARG_MIB_SEL(RX_HS_G2_PREP_LENGTH_CAP, i),
647 attr->rx_hs_g2_prep_sync_len_cap);
648 ufshcd_dme_set(hba,
649 UIC_ARG_MIB_SEL(RX_HS_G3_PREP_LENGTH_CAP, i),
650 attr->rx_hs_g3_prep_sync_len_cap);
651 }
652
653 if (attr->rx_adv_fine_gran_sup_en == 0) {
654 for_each_ufs_rx_lane(ufs, i) {
655 ufshcd_dme_set(hba,
656 UIC_ARG_MIB_SEL(RX_ADV_GRANULARITY_CAP, i), 0);
657
658 if (attr->rx_min_actv_time_cap)
659 ufshcd_dme_set(hba,
660 UIC_ARG_MIB_SEL(RX_MIN_ACTIVATETIME_CAP,
661 i), attr->rx_min_actv_time_cap);
662
663 if (attr->rx_hibern8_time_cap)
664 ufshcd_dme_set(hba,
665 UIC_ARG_MIB_SEL(RX_HIBERN8TIME_CAP, i),
666 attr->rx_hibern8_time_cap);
667 }
668 } else if (attr->rx_adv_fine_gran_sup_en == 1) {
669 for_each_ufs_rx_lane(ufs, i) {
670 if (attr->rx_adv_fine_gran_step)
671 ufshcd_dme_set(hba,
672 UIC_ARG_MIB_SEL(RX_ADV_GRANULARITY_CAP,
673 i), RX_ADV_FINE_GRAN_STEP(
674 attr->rx_adv_fine_gran_step));
675
676 if (attr->rx_adv_min_actv_time_cap)
677 ufshcd_dme_set(hba,
678 UIC_ARG_MIB_SEL(
679 RX_ADV_MIN_ACTIVATETIME_CAP, i),
680 attr->rx_adv_min_actv_time_cap);
681
682 if (attr->rx_adv_hibern8_time_cap)
683 ufshcd_dme_set(hba,
684 UIC_ARG_MIB_SEL(RX_ADV_HIBERN8TIME_CAP,
685 i),
686 attr->rx_adv_hibern8_time_cap);
687 }
688 }
689
690 exynos_ufs_disable_ov_tm(hba);
691 }
692
exynos_ufs_establish_connt(struct exynos_ufs * ufs)693 static void exynos_ufs_establish_connt(struct exynos_ufs *ufs)
694 {
695 struct ufs_hba *hba = ufs->hba;
696 enum {
697 DEV_ID = 0x00,
698 PEER_DEV_ID = 0x01,
699 PEER_CPORT_ID = 0x00,
700 TRAFFIC_CLASS = 0x00,
701 };
702
703 /* allow cport attributes to be set */
704 ufshcd_dme_set(hba, UIC_ARG_MIB(T_CONNECTIONSTATE), CPORT_IDLE);
705
706 /* local unipro attributes */
707 ufshcd_dme_set(hba, UIC_ARG_MIB(N_DEVICEID), DEV_ID);
708 ufshcd_dme_set(hba, UIC_ARG_MIB(N_DEVICEID_VALID), true);
709 ufshcd_dme_set(hba, UIC_ARG_MIB(T_PEERDEVICEID), PEER_DEV_ID);
710 ufshcd_dme_set(hba, UIC_ARG_MIB(T_PEERCPORTID), PEER_CPORT_ID);
711 ufshcd_dme_set(hba, UIC_ARG_MIB(T_CPORTFLAGS), CPORT_DEF_FLAGS);
712 ufshcd_dme_set(hba, UIC_ARG_MIB(T_TRAFFICCLASS), TRAFFIC_CLASS);
713 ufshcd_dme_set(hba, UIC_ARG_MIB(T_CONNECTIONSTATE), CPORT_CONNECTED);
714 }
715
exynos_ufs_config_smu(struct exynos_ufs * ufs)716 static void exynos_ufs_config_smu(struct exynos_ufs *ufs)
717 {
718 u32 reg, val;
719
720 exynos_ufs_disable_auto_ctrl_hcc_save(ufs, &val);
721
722 /* make encryption disabled by default */
723 reg = ufsp_readl(ufs, UFSPRSECURITY);
724 ufsp_writel(ufs, reg | NSSMU, UFSPRSECURITY);
725 ufsp_writel(ufs, 0x0, UFSPSBEGIN0);
726 ufsp_writel(ufs, 0xffffffff, UFSPSEND0);
727 ufsp_writel(ufs, 0xff, UFSPSLUN0);
728 ufsp_writel(ufs, 0xf1, UFSPSCTRL0);
729
730 exynos_ufs_auto_ctrl_hcc_restore(ufs, &val);
731 }
732
exynos_ufs_config_sync_pattern_mask(struct exynos_ufs * ufs,struct ufs_pa_layer_attr * pwr)733 static void exynos_ufs_config_sync_pattern_mask(struct exynos_ufs *ufs,
734 struct ufs_pa_layer_attr *pwr)
735 {
736 struct ufs_hba *hba = ufs->hba;
737 u8 g = max_t(u32, pwr->gear_rx, pwr->gear_tx);
738 u32 mask, sync_len;
739 enum {
740 SYNC_LEN_G1 = 80 * 1000, /* 80us */
741 SYNC_LEN_G2 = 40 * 1000, /* 44us */
742 SYNC_LEN_G3 = 20 * 1000, /* 20us */
743 };
744 int i;
745
746 if (g == 1)
747 sync_len = SYNC_LEN_G1;
748 else if (g == 2)
749 sync_len = SYNC_LEN_G2;
750 else if (g == 3)
751 sync_len = SYNC_LEN_G3;
752 else
753 return;
754
755 mask = exynos_ufs_calc_time_cntr(ufs, sync_len);
756 mask = (mask >> 8) & 0xff;
757
758 exynos_ufs_enable_ov_tm(hba);
759
760 for_each_ufs_rx_lane(ufs, i)
761 ufshcd_dme_set(hba,
762 UIC_ARG_MIB_SEL(RX_SYNC_MASK_LENGTH, i), mask);
763
764 exynos_ufs_disable_ov_tm(hba);
765 }
766
exynos_ufs_pre_pwr_mode(struct ufs_hba * hba,struct ufs_pa_layer_attr * dev_max_params,struct ufs_pa_layer_attr * dev_req_params)767 static int exynos_ufs_pre_pwr_mode(struct ufs_hba *hba,
768 struct ufs_pa_layer_attr *dev_max_params,
769 struct ufs_pa_layer_attr *dev_req_params)
770 {
771 struct exynos_ufs *ufs = ufshcd_get_variant(hba);
772 struct phy *generic_phy = ufs->phy;
773 struct ufs_dev_params ufs_exynos_cap;
774 int ret;
775
776 if (!dev_req_params) {
777 pr_err("%s: incoming dev_req_params is NULL\n", __func__);
778 ret = -EINVAL;
779 goto out;
780 }
781
782 ufshcd_init_pwr_dev_param(&ufs_exynos_cap);
783
784 ret = ufshcd_get_pwr_dev_param(&ufs_exynos_cap,
785 dev_max_params, dev_req_params);
786 if (ret) {
787 pr_err("%s: failed to determine capabilities\n", __func__);
788 goto out;
789 }
790
791 if (ufs->drv_data->pre_pwr_change)
792 ufs->drv_data->pre_pwr_change(ufs, dev_req_params);
793
794 if (ufshcd_is_hs_mode(dev_req_params)) {
795 exynos_ufs_config_sync_pattern_mask(ufs, dev_req_params);
796
797 switch (dev_req_params->hs_rate) {
798 case PA_HS_MODE_A:
799 case PA_HS_MODE_B:
800 phy_calibrate(generic_phy);
801 break;
802 }
803 }
804
805 /* setting for three timeout values for traffic class #0 */
806 ufshcd_dme_set(hba, UIC_ARG_MIB(DL_FC0PROTTIMEOUTVAL), 8064);
807 ufshcd_dme_set(hba, UIC_ARG_MIB(DL_TC0REPLAYTIMEOUTVAL), 28224);
808 ufshcd_dme_set(hba, UIC_ARG_MIB(DL_AFC0REQTIMEOUTVAL), 20160);
809
810 return 0;
811 out:
812 return ret;
813 }
814
815 #define PWR_MODE_STR_LEN 64
exynos_ufs_post_pwr_mode(struct ufs_hba * hba,struct ufs_pa_layer_attr * pwr_req)816 static int exynos_ufs_post_pwr_mode(struct ufs_hba *hba,
817 struct ufs_pa_layer_attr *pwr_req)
818 {
819 struct exynos_ufs *ufs = ufshcd_get_variant(hba);
820 struct phy *generic_phy = ufs->phy;
821 int gear = max_t(u32, pwr_req->gear_rx, pwr_req->gear_tx);
822 int lanes = max_t(u32, pwr_req->lane_rx, pwr_req->lane_tx);
823 char pwr_str[PWR_MODE_STR_LEN] = "";
824
825 /* let default be PWM Gear 1, Lane 1 */
826 if (!gear)
827 gear = 1;
828
829 if (!lanes)
830 lanes = 1;
831
832 if (ufs->drv_data->post_pwr_change)
833 ufs->drv_data->post_pwr_change(ufs, pwr_req);
834
835 if ((ufshcd_is_hs_mode(pwr_req))) {
836 switch (pwr_req->hs_rate) {
837 case PA_HS_MODE_A:
838 case PA_HS_MODE_B:
839 phy_calibrate(generic_phy);
840 break;
841 }
842
843 snprintf(pwr_str, PWR_MODE_STR_LEN, "%s series_%s G_%d L_%d",
844 "FAST", pwr_req->hs_rate == PA_HS_MODE_A ? "A" : "B",
845 gear, lanes);
846 } else {
847 snprintf(pwr_str, PWR_MODE_STR_LEN, "%s G_%d L_%d",
848 "SLOW", gear, lanes);
849 }
850
851 dev_info(hba->dev, "Power mode changed to : %s\n", pwr_str);
852
853 return 0;
854 }
855
exynos_ufs_specify_nexus_t_xfer_req(struct ufs_hba * hba,int tag,bool is_scsi_cmd)856 static void exynos_ufs_specify_nexus_t_xfer_req(struct ufs_hba *hba,
857 int tag, bool is_scsi_cmd)
858 {
859 struct exynos_ufs *ufs = ufshcd_get_variant(hba);
860 u32 type;
861
862 type = hci_readl(ufs, HCI_UTRL_NEXUS_TYPE);
863
864 if (is_scsi_cmd)
865 hci_writel(ufs, type | (1 << tag), HCI_UTRL_NEXUS_TYPE);
866 else
867 hci_writel(ufs, type & ~(1 << tag), HCI_UTRL_NEXUS_TYPE);
868 }
869
exynos_ufs_specify_nexus_t_tm_req(struct ufs_hba * hba,int tag,u8 func)870 static void exynos_ufs_specify_nexus_t_tm_req(struct ufs_hba *hba,
871 int tag, u8 func)
872 {
873 struct exynos_ufs *ufs = ufshcd_get_variant(hba);
874 u32 type;
875
876 type = hci_readl(ufs, HCI_UTMRL_NEXUS_TYPE);
877
878 switch (func) {
879 case UFS_ABORT_TASK:
880 case UFS_QUERY_TASK:
881 hci_writel(ufs, type | (1 << tag), HCI_UTMRL_NEXUS_TYPE);
882 break;
883 case UFS_ABORT_TASK_SET:
884 case UFS_CLEAR_TASK_SET:
885 case UFS_LOGICAL_RESET:
886 case UFS_QUERY_TASK_SET:
887 hci_writel(ufs, type & ~(1 << tag), HCI_UTMRL_NEXUS_TYPE);
888 break;
889 }
890 }
891
exynos_ufs_phy_init(struct exynos_ufs * ufs)892 static int exynos_ufs_phy_init(struct exynos_ufs *ufs)
893 {
894 struct ufs_hba *hba = ufs->hba;
895 struct phy *generic_phy = ufs->phy;
896 int ret = 0;
897
898 if (ufs->avail_ln_rx == 0 || ufs->avail_ln_tx == 0) {
899 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_AVAILRXDATALANES),
900 &ufs->avail_ln_rx);
901 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_AVAILTXDATALANES),
902 &ufs->avail_ln_tx);
903 WARN(ufs->avail_ln_rx != ufs->avail_ln_tx,
904 "available data lane is not equal(rx:%d, tx:%d)\n",
905 ufs->avail_ln_rx, ufs->avail_ln_tx);
906 }
907
908 phy_set_bus_width(generic_phy, ufs->avail_ln_rx);
909 ret = phy_init(generic_phy);
910 if (ret) {
911 dev_err(hba->dev, "%s: phy init failed, ret = %d\n",
912 __func__, ret);
913 return ret;
914 }
915
916 ret = phy_power_on(generic_phy);
917 if (ret)
918 goto out_exit_phy;
919
920 return 0;
921
922 out_exit_phy:
923 phy_exit(generic_phy);
924
925 return ret;
926 }
927
exynos_ufs_config_unipro(struct exynos_ufs * ufs)928 static void exynos_ufs_config_unipro(struct exynos_ufs *ufs)
929 {
930 struct ufs_hba *hba = ufs->hba;
931
932 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_CLK_PERIOD),
933 DIV_ROUND_UP(NSEC_PER_SEC, ufs->mclk_rate));
934 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXTRAILINGCLOCKS),
935 ufs->drv_data->uic_attr->tx_trailingclks);
936 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_DBG_OPTION_SUITE),
937 ufs->drv_data->uic_attr->pa_dbg_option_suite);
938 }
939
exynos_ufs_config_intr(struct exynos_ufs * ufs,u32 errs,u8 index)940 static void exynos_ufs_config_intr(struct exynos_ufs *ufs, u32 errs, u8 index)
941 {
942 switch (index) {
943 case UNIPRO_L1_5:
944 hci_writel(ufs, DFES_ERR_EN | errs, HCI_ERR_EN_PA_LAYER);
945 break;
946 case UNIPRO_L2:
947 hci_writel(ufs, DFES_ERR_EN | errs, HCI_ERR_EN_DL_LAYER);
948 break;
949 case UNIPRO_L3:
950 hci_writel(ufs, DFES_ERR_EN | errs, HCI_ERR_EN_N_LAYER);
951 break;
952 case UNIPRO_L4:
953 hci_writel(ufs, DFES_ERR_EN | errs, HCI_ERR_EN_T_LAYER);
954 break;
955 case UNIPRO_DME:
956 hci_writel(ufs, DFES_ERR_EN | errs, HCI_ERR_EN_DME_LAYER);
957 break;
958 }
959 }
960
exynos_ufs_setup_clocks(struct ufs_hba * hba,bool on,enum ufs_notify_change_status status)961 static int exynos_ufs_setup_clocks(struct ufs_hba *hba, bool on,
962 enum ufs_notify_change_status status)
963 {
964 struct exynos_ufs *ufs = ufshcd_get_variant(hba);
965
966 if (!ufs)
967 return 0;
968
969 if (on && status == PRE_CHANGE) {
970 if (ufs->opts & EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL)
971 exynos_ufs_disable_auto_ctrl_hcc(ufs);
972 exynos_ufs_ungate_clks(ufs);
973 } else if (!on && status == POST_CHANGE) {
974 exynos_ufs_gate_clks(ufs);
975 if (ufs->opts & EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL)
976 exynos_ufs_enable_auto_ctrl_hcc(ufs);
977 }
978
979 return 0;
980 }
981
exynos_ufs_pre_link(struct ufs_hba * hba)982 static int exynos_ufs_pre_link(struct ufs_hba *hba)
983 {
984 struct exynos_ufs *ufs = ufshcd_get_variant(hba);
985
986 /* hci */
987 exynos_ufs_config_intr(ufs, DFES_DEF_L2_ERRS, UNIPRO_L2);
988 exynos_ufs_config_intr(ufs, DFES_DEF_L3_ERRS, UNIPRO_L3);
989 exynos_ufs_config_intr(ufs, DFES_DEF_L4_ERRS, UNIPRO_L4);
990 exynos_ufs_set_unipro_pclk_div(ufs);
991
992 /* unipro */
993 exynos_ufs_config_unipro(ufs);
994
995 /* m-phy */
996 exynos_ufs_phy_init(ufs);
997 if (!(ufs->opts & EXYNOS_UFS_OPT_SKIP_CONFIG_PHY_ATTR)) {
998 exynos_ufs_config_phy_time_attr(ufs);
999 exynos_ufs_config_phy_cap_attr(ufs);
1000 }
1001
1002 exynos_ufs_setup_clocks(hba, true, PRE_CHANGE);
1003
1004 if (ufs->drv_data->pre_link)
1005 ufs->drv_data->pre_link(ufs);
1006
1007 return 0;
1008 }
1009
exynos_ufs_fit_aggr_timeout(struct exynos_ufs * ufs)1010 static void exynos_ufs_fit_aggr_timeout(struct exynos_ufs *ufs)
1011 {
1012 u32 val;
1013
1014 val = exynos_ufs_calc_time_cntr(ufs, IATOVAL_NSEC / CNTR_DIV_VAL);
1015 hci_writel(ufs, val & CNT_VAL_1US_MASK, HCI_1US_TO_CNT_VAL);
1016 }
1017
exynos_ufs_post_link(struct ufs_hba * hba)1018 static int exynos_ufs_post_link(struct ufs_hba *hba)
1019 {
1020 struct exynos_ufs *ufs = ufshcd_get_variant(hba);
1021 struct phy *generic_phy = ufs->phy;
1022 struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr;
1023
1024 exynos_ufs_establish_connt(ufs);
1025 exynos_ufs_fit_aggr_timeout(ufs);
1026
1027 hci_writel(ufs, 0xa, HCI_DATA_REORDER);
1028 hci_writel(ufs, PRDT_SET_SIZE(12), HCI_TXPRDT_ENTRY_SIZE);
1029 hci_writel(ufs, PRDT_SET_SIZE(12), HCI_RXPRDT_ENTRY_SIZE);
1030 hci_writel(ufs, (1 << hba->nutrs) - 1, HCI_UTRL_NEXUS_TYPE);
1031 hci_writel(ufs, (1 << hba->nutmrs) - 1, HCI_UTMRL_NEXUS_TYPE);
1032 hci_writel(ufs, 0xf, HCI_AXIDMA_RWDATA_BURST_LEN);
1033
1034 if (ufs->opts & EXYNOS_UFS_OPT_SKIP_CONNECTION_ESTAB)
1035 ufshcd_dme_set(hba,
1036 UIC_ARG_MIB(T_DBG_SKIP_INIT_HIBERN8_EXIT), true);
1037
1038 if (attr->pa_granularity) {
1039 exynos_ufs_enable_dbg_mode(hba);
1040 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_GRANULARITY),
1041 attr->pa_granularity);
1042 exynos_ufs_disable_dbg_mode(hba);
1043
1044 if (attr->pa_tactivate)
1045 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TACTIVATE),
1046 attr->pa_tactivate);
1047 if (attr->pa_hibern8time &&
1048 !(ufs->opts & EXYNOS_UFS_OPT_USE_SW_HIBERN8_TIMER))
1049 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HIBERN8TIME),
1050 attr->pa_hibern8time);
1051 }
1052
1053 if (ufs->opts & EXYNOS_UFS_OPT_USE_SW_HIBERN8_TIMER) {
1054 if (!attr->pa_granularity)
1055 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_GRANULARITY),
1056 &attr->pa_granularity);
1057 if (!attr->pa_hibern8time)
1058 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_HIBERN8TIME),
1059 &attr->pa_hibern8time);
1060 /*
1061 * not wait for HIBERN8 time to exit hibernation
1062 */
1063 ufshcd_dme_set(hba, UIC_ARG_MIB(PA_HIBERN8TIME), 0);
1064
1065 if (attr->pa_granularity < 1 || attr->pa_granularity > 6) {
1066 /* Valid range for granularity: 1 ~ 6 */
1067 dev_warn(hba->dev,
1068 "%s: pa_granularity %d is invalid, assuming backwards compatibility\n",
1069 __func__,
1070 attr->pa_granularity);
1071 attr->pa_granularity = 6;
1072 }
1073 }
1074
1075 phy_calibrate(generic_phy);
1076
1077 if (ufs->drv_data->post_link)
1078 ufs->drv_data->post_link(ufs);
1079
1080 return 0;
1081 }
1082
exynos_ufs_parse_dt(struct device * dev,struct exynos_ufs * ufs)1083 static int exynos_ufs_parse_dt(struct device *dev, struct exynos_ufs *ufs)
1084 {
1085 struct device_node *np = dev->of_node;
1086 struct exynos_ufs_uic_attr *attr;
1087 int ret = 0;
1088
1089 ufs->drv_data = device_get_match_data(dev);
1090
1091 if (ufs->drv_data && ufs->drv_data->uic_attr) {
1092 attr = ufs->drv_data->uic_attr;
1093 } else {
1094 dev_err(dev, "failed to get uic attributes\n");
1095 ret = -EINVAL;
1096 goto out;
1097 }
1098
1099 ufs->sysreg = syscon_regmap_lookup_by_phandle(np, "samsung,sysreg");
1100 if (IS_ERR(ufs->sysreg))
1101 ufs->sysreg = NULL;
1102 else {
1103 if (of_property_read_u32_index(np, "samsung,sysreg", 1,
1104 &ufs->shareability_reg_offset)) {
1105 dev_warn(dev, "can't get an offset from sysreg. Set to default value\n");
1106 ufs->shareability_reg_offset = UFS_SHAREABILITY_OFFSET;
1107 }
1108 }
1109
1110 ufs->pclk_avail_min = PCLK_AVAIL_MIN;
1111 ufs->pclk_avail_max = PCLK_AVAIL_MAX;
1112
1113 attr->rx_adv_fine_gran_sup_en = RX_ADV_FINE_GRAN_SUP_EN;
1114 attr->rx_adv_fine_gran_step = RX_ADV_FINE_GRAN_STEP_VAL;
1115 attr->rx_adv_min_actv_time_cap = RX_ADV_MIN_ACTV_TIME_CAP;
1116 attr->pa_granularity = PA_GRANULARITY_VAL;
1117 attr->pa_tactivate = PA_TACTIVATE_VAL;
1118 attr->pa_hibern8time = PA_HIBERN8TIME_VAL;
1119
1120 out:
1121 return ret;
1122 }
1123
exynos_ufs_priv_init(struct ufs_hba * hba,struct exynos_ufs * ufs)1124 static inline void exynos_ufs_priv_init(struct ufs_hba *hba,
1125 struct exynos_ufs *ufs)
1126 {
1127 ufs->hba = hba;
1128 ufs->opts = ufs->drv_data->opts;
1129 ufs->rx_sel_idx = PA_MAXDATALANES;
1130 if (ufs->opts & EXYNOS_UFS_OPT_BROKEN_RX_SEL_IDX)
1131 ufs->rx_sel_idx = 0;
1132 hba->priv = (void *)ufs;
1133 hba->quirks = ufs->drv_data->quirks;
1134 }
1135
exynos_ufs_init(struct ufs_hba * hba)1136 static int exynos_ufs_init(struct ufs_hba *hba)
1137 {
1138 struct device *dev = hba->dev;
1139 struct platform_device *pdev = to_platform_device(dev);
1140 struct exynos_ufs *ufs;
1141 int ret;
1142
1143 ufs = devm_kzalloc(dev, sizeof(*ufs), GFP_KERNEL);
1144 if (!ufs)
1145 return -ENOMEM;
1146
1147 /* exynos-specific hci */
1148 ufs->reg_hci = devm_platform_ioremap_resource_byname(pdev, "vs_hci");
1149 if (IS_ERR(ufs->reg_hci)) {
1150 dev_err(dev, "cannot ioremap for hci vendor register\n");
1151 return PTR_ERR(ufs->reg_hci);
1152 }
1153
1154 /* unipro */
1155 ufs->reg_unipro = devm_platform_ioremap_resource_byname(pdev, "unipro");
1156 if (IS_ERR(ufs->reg_unipro)) {
1157 dev_err(dev, "cannot ioremap for unipro register\n");
1158 return PTR_ERR(ufs->reg_unipro);
1159 }
1160
1161 /* ufs protector */
1162 ufs->reg_ufsp = devm_platform_ioremap_resource_byname(pdev, "ufsp");
1163 if (IS_ERR(ufs->reg_ufsp)) {
1164 dev_err(dev, "cannot ioremap for ufs protector register\n");
1165 return PTR_ERR(ufs->reg_ufsp);
1166 }
1167
1168 ret = exynos_ufs_parse_dt(dev, ufs);
1169 if (ret) {
1170 dev_err(dev, "failed to get dt info.\n");
1171 goto out;
1172 }
1173
1174 ufs->phy = devm_phy_get(dev, "ufs-phy");
1175 if (IS_ERR(ufs->phy)) {
1176 ret = PTR_ERR(ufs->phy);
1177 dev_err(dev, "failed to get ufs-phy\n");
1178 goto out;
1179 }
1180
1181 exynos_ufs_priv_init(hba, ufs);
1182
1183 if (ufs->drv_data->drv_init) {
1184 ret = ufs->drv_data->drv_init(dev, ufs);
1185 if (ret) {
1186 dev_err(dev, "failed to init drv-data\n");
1187 goto out;
1188 }
1189 }
1190
1191 ret = exynos_ufs_get_clk_info(ufs);
1192 if (ret)
1193 goto out;
1194 exynos_ufs_specify_phy_time_attr(ufs);
1195 exynos_ufs_config_smu(ufs);
1196 return 0;
1197
1198 out:
1199 hba->priv = NULL;
1200 return ret;
1201 }
1202
exynos_ufs_host_reset(struct ufs_hba * hba)1203 static int exynos_ufs_host_reset(struct ufs_hba *hba)
1204 {
1205 struct exynos_ufs *ufs = ufshcd_get_variant(hba);
1206 unsigned long timeout = jiffies + msecs_to_jiffies(1);
1207 u32 val;
1208 int ret = 0;
1209
1210 exynos_ufs_disable_auto_ctrl_hcc_save(ufs, &val);
1211
1212 hci_writel(ufs, UFS_SW_RST_MASK, HCI_SW_RST);
1213
1214 do {
1215 if (!(hci_readl(ufs, HCI_SW_RST) & UFS_SW_RST_MASK))
1216 goto out;
1217 } while (time_before(jiffies, timeout));
1218
1219 dev_err(hba->dev, "timeout host sw-reset\n");
1220 ret = -ETIMEDOUT;
1221
1222 out:
1223 exynos_ufs_auto_ctrl_hcc_restore(ufs, &val);
1224 return ret;
1225 }
1226
exynos_ufs_dev_hw_reset(struct ufs_hba * hba)1227 static void exynos_ufs_dev_hw_reset(struct ufs_hba *hba)
1228 {
1229 struct exynos_ufs *ufs = ufshcd_get_variant(hba);
1230
1231 hci_writel(ufs, 0 << 0, HCI_GPIO_OUT);
1232 udelay(5);
1233 hci_writel(ufs, 1 << 0, HCI_GPIO_OUT);
1234 }
1235
exynos_ufs_pre_hibern8(struct ufs_hba * hba,u8 enter)1236 static void exynos_ufs_pre_hibern8(struct ufs_hba *hba, u8 enter)
1237 {
1238 struct exynos_ufs *ufs = ufshcd_get_variant(hba);
1239 struct exynos_ufs_uic_attr *attr = ufs->drv_data->uic_attr;
1240
1241 if (!enter) {
1242 if (ufs->opts & EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL)
1243 exynos_ufs_disable_auto_ctrl_hcc(ufs);
1244 exynos_ufs_ungate_clks(ufs);
1245
1246 if (ufs->opts & EXYNOS_UFS_OPT_USE_SW_HIBERN8_TIMER) {
1247 static const unsigned int granularity_tbl[] = {
1248 1, 4, 8, 16, 32, 100
1249 };
1250 int h8_time = attr->pa_hibern8time *
1251 granularity_tbl[attr->pa_granularity - 1];
1252 unsigned long us;
1253 s64 delta;
1254
1255 do {
1256 delta = h8_time - ktime_us_delta(ktime_get(),
1257 ufs->entry_hibern8_t);
1258 if (delta <= 0)
1259 break;
1260
1261 us = min_t(s64, delta, USEC_PER_MSEC);
1262 if (us >= 10)
1263 usleep_range(us, us + 10);
1264 } while (1);
1265 }
1266 }
1267 }
1268
exynos_ufs_post_hibern8(struct ufs_hba * hba,u8 enter)1269 static void exynos_ufs_post_hibern8(struct ufs_hba *hba, u8 enter)
1270 {
1271 struct exynos_ufs *ufs = ufshcd_get_variant(hba);
1272
1273 if (!enter) {
1274 u32 cur_mode = 0;
1275 u32 pwrmode;
1276
1277 if (ufshcd_is_hs_mode(&ufs->dev_req_params))
1278 pwrmode = FAST_MODE;
1279 else
1280 pwrmode = SLOW_MODE;
1281
1282 ufshcd_dme_get(hba, UIC_ARG_MIB(PA_PWRMODE), &cur_mode);
1283 if (cur_mode != (pwrmode << 4 | pwrmode)) {
1284 dev_warn(hba->dev, "%s: power mode change\n", __func__);
1285 hba->pwr_info.pwr_rx = (cur_mode >> 4) & 0xf;
1286 hba->pwr_info.pwr_tx = cur_mode & 0xf;
1287 ufshcd_config_pwr_mode(hba, &hba->max_pwr_info.info);
1288 }
1289
1290 if (!(ufs->opts & EXYNOS_UFS_OPT_SKIP_CONNECTION_ESTAB))
1291 exynos_ufs_establish_connt(ufs);
1292 } else {
1293 ufs->entry_hibern8_t = ktime_get();
1294 exynos_ufs_gate_clks(ufs);
1295 if (ufs->opts & EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL)
1296 exynos_ufs_enable_auto_ctrl_hcc(ufs);
1297 }
1298 }
1299
exynos_ufs_hce_enable_notify(struct ufs_hba * hba,enum ufs_notify_change_status status)1300 static int exynos_ufs_hce_enable_notify(struct ufs_hba *hba,
1301 enum ufs_notify_change_status status)
1302 {
1303 struct exynos_ufs *ufs = ufshcd_get_variant(hba);
1304 int ret = 0;
1305
1306 switch (status) {
1307 case PRE_CHANGE:
1308 if (ufs->drv_data->pre_hce_enable) {
1309 ret = ufs->drv_data->pre_hce_enable(ufs);
1310 if (ret)
1311 return ret;
1312 }
1313
1314 ret = exynos_ufs_host_reset(hba);
1315 if (ret)
1316 return ret;
1317 exynos_ufs_dev_hw_reset(hba);
1318 break;
1319 case POST_CHANGE:
1320 exynos_ufs_calc_pwm_clk_div(ufs);
1321 if (!(ufs->opts & EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL))
1322 exynos_ufs_enable_auto_ctrl_hcc(ufs);
1323
1324 if (ufs->drv_data->post_hce_enable)
1325 ret = ufs->drv_data->post_hce_enable(ufs);
1326
1327 break;
1328 }
1329
1330 return ret;
1331 }
1332
exynos_ufs_link_startup_notify(struct ufs_hba * hba,enum ufs_notify_change_status status)1333 static int exynos_ufs_link_startup_notify(struct ufs_hba *hba,
1334 enum ufs_notify_change_status status)
1335 {
1336 int ret = 0;
1337
1338 switch (status) {
1339 case PRE_CHANGE:
1340 ret = exynos_ufs_pre_link(hba);
1341 break;
1342 case POST_CHANGE:
1343 ret = exynos_ufs_post_link(hba);
1344 break;
1345 }
1346
1347 return ret;
1348 }
1349
exynos_ufs_pwr_change_notify(struct ufs_hba * hba,enum ufs_notify_change_status status,struct ufs_pa_layer_attr * dev_max_params,struct ufs_pa_layer_attr * dev_req_params)1350 static int exynos_ufs_pwr_change_notify(struct ufs_hba *hba,
1351 enum ufs_notify_change_status status,
1352 struct ufs_pa_layer_attr *dev_max_params,
1353 struct ufs_pa_layer_attr *dev_req_params)
1354 {
1355 int ret = 0;
1356
1357 switch (status) {
1358 case PRE_CHANGE:
1359 ret = exynos_ufs_pre_pwr_mode(hba, dev_max_params,
1360 dev_req_params);
1361 break;
1362 case POST_CHANGE:
1363 ret = exynos_ufs_post_pwr_mode(hba, dev_req_params);
1364 break;
1365 }
1366
1367 return ret;
1368 }
1369
exynos_ufs_hibern8_notify(struct ufs_hba * hba,enum uic_cmd_dme enter,enum ufs_notify_change_status notify)1370 static void exynos_ufs_hibern8_notify(struct ufs_hba *hba,
1371 enum uic_cmd_dme enter,
1372 enum ufs_notify_change_status notify)
1373 {
1374 switch ((u8)notify) {
1375 case PRE_CHANGE:
1376 exynos_ufs_pre_hibern8(hba, enter);
1377 break;
1378 case POST_CHANGE:
1379 exynos_ufs_post_hibern8(hba, enter);
1380 break;
1381 }
1382 }
1383
exynos_ufs_suspend(struct ufs_hba * hba,enum ufs_pm_op pm_op,enum ufs_notify_change_status status)1384 static int exynos_ufs_suspend(struct ufs_hba *hba, enum ufs_pm_op pm_op,
1385 enum ufs_notify_change_status status)
1386 {
1387 struct exynos_ufs *ufs = ufshcd_get_variant(hba);
1388
1389 if (status == PRE_CHANGE)
1390 return 0;
1391
1392 if (!ufshcd_is_link_active(hba))
1393 phy_power_off(ufs->phy);
1394
1395 return 0;
1396 }
1397
exynos_ufs_resume(struct ufs_hba * hba,enum ufs_pm_op pm_op)1398 static int exynos_ufs_resume(struct ufs_hba *hba, enum ufs_pm_op pm_op)
1399 {
1400 struct exynos_ufs *ufs = ufshcd_get_variant(hba);
1401
1402 if (!ufshcd_is_link_active(hba))
1403 phy_power_on(ufs->phy);
1404
1405 exynos_ufs_config_smu(ufs);
1406
1407 return 0;
1408 }
1409
exynosauto_ufs_vh_link_startup_notify(struct ufs_hba * hba,enum ufs_notify_change_status status)1410 static int exynosauto_ufs_vh_link_startup_notify(struct ufs_hba *hba,
1411 enum ufs_notify_change_status status)
1412 {
1413 if (status == POST_CHANGE) {
1414 ufshcd_set_link_active(hba);
1415 ufshcd_set_ufs_dev_active(hba);
1416 }
1417
1418 return 0;
1419 }
1420
exynosauto_ufs_vh_wait_ph_ready(struct ufs_hba * hba)1421 static int exynosauto_ufs_vh_wait_ph_ready(struct ufs_hba *hba)
1422 {
1423 u32 mbox;
1424 ktime_t start, stop;
1425
1426 start = ktime_get();
1427 stop = ktime_add(start, ms_to_ktime(PH_READY_TIMEOUT_MS));
1428
1429 do {
1430 mbox = ufshcd_readl(hba, PH2VH_MBOX);
1431 /* TODO: Mailbox message protocols between the PH and VHs are
1432 * not implemented yet. This will be supported later
1433 */
1434 if ((mbox & MH_MSG_MASK) == MH_MSG_PH_READY)
1435 return 0;
1436
1437 usleep_range(40, 50);
1438 } while (ktime_before(ktime_get(), stop));
1439
1440 return -ETIME;
1441 }
1442
exynosauto_ufs_vh_init(struct ufs_hba * hba)1443 static int exynosauto_ufs_vh_init(struct ufs_hba *hba)
1444 {
1445 struct device *dev = hba->dev;
1446 struct platform_device *pdev = to_platform_device(dev);
1447 struct exynos_ufs *ufs;
1448 int ret;
1449
1450 ufs = devm_kzalloc(dev, sizeof(*ufs), GFP_KERNEL);
1451 if (!ufs)
1452 return -ENOMEM;
1453
1454 /* exynos-specific hci */
1455 ufs->reg_hci = devm_platform_ioremap_resource_byname(pdev, "vs_hci");
1456 if (IS_ERR(ufs->reg_hci)) {
1457 dev_err(dev, "cannot ioremap for hci vendor register\n");
1458 return PTR_ERR(ufs->reg_hci);
1459 }
1460
1461 ret = exynosauto_ufs_vh_wait_ph_ready(hba);
1462 if (ret)
1463 return ret;
1464
1465 ufs->drv_data = device_get_match_data(dev);
1466 if (!ufs->drv_data)
1467 return -ENODEV;
1468
1469 exynos_ufs_priv_init(hba, ufs);
1470
1471 return 0;
1472 }
1473
1474 static struct ufs_hba_variant_ops ufs_hba_exynos_ops = {
1475 .name = "exynos_ufs",
1476 .init = exynos_ufs_init,
1477 .hce_enable_notify = exynos_ufs_hce_enable_notify,
1478 .link_startup_notify = exynos_ufs_link_startup_notify,
1479 .pwr_change_notify = exynos_ufs_pwr_change_notify,
1480 .setup_clocks = exynos_ufs_setup_clocks,
1481 .setup_xfer_req = exynos_ufs_specify_nexus_t_xfer_req,
1482 .setup_task_mgmt = exynos_ufs_specify_nexus_t_tm_req,
1483 .hibern8_notify = exynos_ufs_hibern8_notify,
1484 .suspend = exynos_ufs_suspend,
1485 .resume = exynos_ufs_resume,
1486 };
1487
1488 static struct ufs_hba_variant_ops ufs_hba_exynosauto_vh_ops = {
1489 .name = "exynosauto_ufs_vh",
1490 .init = exynosauto_ufs_vh_init,
1491 .link_startup_notify = exynosauto_ufs_vh_link_startup_notify,
1492 };
1493
exynos_ufs_probe(struct platform_device * pdev)1494 static int exynos_ufs_probe(struct platform_device *pdev)
1495 {
1496 int err;
1497 struct device *dev = &pdev->dev;
1498 const struct ufs_hba_variant_ops *vops = &ufs_hba_exynos_ops;
1499 const struct exynos_ufs_drv_data *drv_data =
1500 device_get_match_data(dev);
1501
1502 if (drv_data && drv_data->vops)
1503 vops = drv_data->vops;
1504
1505 err = ufshcd_pltfrm_init(pdev, vops);
1506 if (err)
1507 dev_err(dev, "ufshcd_pltfrm_init() failed %d\n", err);
1508
1509 return err;
1510 }
1511
exynos_ufs_remove(struct platform_device * pdev)1512 static int exynos_ufs_remove(struct platform_device *pdev)
1513 {
1514 struct ufs_hba *hba = platform_get_drvdata(pdev);
1515 struct exynos_ufs *ufs = ufshcd_get_variant(hba);
1516
1517 pm_runtime_get_sync(&(pdev)->dev);
1518 ufshcd_remove(hba);
1519
1520 phy_power_off(ufs->phy);
1521 phy_exit(ufs->phy);
1522
1523 return 0;
1524 }
1525
1526 static struct exynos_ufs_uic_attr exynos7_uic_attr = {
1527 .tx_trailingclks = 0x10,
1528 .tx_dif_p_nsec = 3000000, /* unit: ns */
1529 .tx_dif_n_nsec = 1000000, /* unit: ns */
1530 .tx_high_z_cnt_nsec = 20000, /* unit: ns */
1531 .tx_base_unit_nsec = 100000, /* unit: ns */
1532 .tx_gran_unit_nsec = 4000, /* unit: ns */
1533 .tx_sleep_cnt = 1000, /* unit: ns */
1534 .tx_min_activatetime = 0xa,
1535 .rx_filler_enable = 0x2,
1536 .rx_dif_p_nsec = 1000000, /* unit: ns */
1537 .rx_hibern8_wait_nsec = 4000000, /* unit: ns */
1538 .rx_base_unit_nsec = 100000, /* unit: ns */
1539 .rx_gran_unit_nsec = 4000, /* unit: ns */
1540 .rx_sleep_cnt = 1280, /* unit: ns */
1541 .rx_stall_cnt = 320, /* unit: ns */
1542 .rx_hs_g1_sync_len_cap = SYNC_LEN_COARSE(0xf),
1543 .rx_hs_g2_sync_len_cap = SYNC_LEN_COARSE(0xf),
1544 .rx_hs_g3_sync_len_cap = SYNC_LEN_COARSE(0xf),
1545 .rx_hs_g1_prep_sync_len_cap = PREP_LEN(0xf),
1546 .rx_hs_g2_prep_sync_len_cap = PREP_LEN(0xf),
1547 .rx_hs_g3_prep_sync_len_cap = PREP_LEN(0xf),
1548 .pa_dbg_option_suite = 0x30103,
1549 };
1550
1551 static struct exynos_ufs_drv_data exynosauto_ufs_drvs = {
1552 .uic_attr = &exynos7_uic_attr,
1553 .quirks = UFSHCD_QUIRK_PRDT_BYTE_GRAN |
1554 UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR |
1555 UFSHCD_QUIRK_BROKEN_OCS_FATAL_ERROR |
1556 UFSHCD_QUIRK_SKIP_DEF_UNIPRO_TIMEOUT_SETTING,
1557 .opts = EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL |
1558 EXYNOS_UFS_OPT_SKIP_CONFIG_PHY_ATTR |
1559 EXYNOS_UFS_OPT_BROKEN_RX_SEL_IDX,
1560 .drv_init = exynosauto_ufs_drv_init,
1561 .post_hce_enable = exynosauto_ufs_post_hce_enable,
1562 .pre_link = exynosauto_ufs_pre_link,
1563 .pre_pwr_change = exynosauto_ufs_pre_pwr_change,
1564 .post_pwr_change = exynosauto_ufs_post_pwr_change,
1565 };
1566
1567 static struct exynos_ufs_drv_data exynosauto_ufs_vh_drvs = {
1568 .vops = &ufs_hba_exynosauto_vh_ops,
1569 .quirks = UFSHCD_QUIRK_PRDT_BYTE_GRAN |
1570 UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR |
1571 UFSHCD_QUIRK_BROKEN_OCS_FATAL_ERROR |
1572 UFSHCI_QUIRK_BROKEN_HCE |
1573 UFSHCD_QUIRK_BROKEN_UIC_CMD |
1574 UFSHCD_QUIRK_SKIP_PH_CONFIGURATION |
1575 UFSHCD_QUIRK_SKIP_DEF_UNIPRO_TIMEOUT_SETTING,
1576 .opts = EXYNOS_UFS_OPT_BROKEN_RX_SEL_IDX,
1577 };
1578
1579 static struct exynos_ufs_drv_data exynos_ufs_drvs = {
1580 .uic_attr = &exynos7_uic_attr,
1581 .quirks = UFSHCD_QUIRK_PRDT_BYTE_GRAN |
1582 UFSHCI_QUIRK_BROKEN_REQ_LIST_CLR |
1583 UFSHCI_QUIRK_BROKEN_HCE |
1584 UFSHCI_QUIRK_SKIP_RESET_INTR_AGGR |
1585 UFSHCD_QUIRK_BROKEN_OCS_FATAL_ERROR |
1586 UFSHCI_QUIRK_SKIP_MANUAL_WB_FLUSH_CTRL |
1587 UFSHCD_QUIRK_SKIP_DEF_UNIPRO_TIMEOUT_SETTING |
1588 UFSHCD_QUIRK_ALIGN_SG_WITH_PAGE_SIZE,
1589 .opts = EXYNOS_UFS_OPT_HAS_APB_CLK_CTRL |
1590 EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL |
1591 EXYNOS_UFS_OPT_BROKEN_RX_SEL_IDX |
1592 EXYNOS_UFS_OPT_SKIP_CONNECTION_ESTAB |
1593 EXYNOS_UFS_OPT_USE_SW_HIBERN8_TIMER,
1594 .drv_init = exynos7_ufs_drv_init,
1595 .pre_link = exynos7_ufs_pre_link,
1596 .post_link = exynos7_ufs_post_link,
1597 .pre_pwr_change = exynos7_ufs_pre_pwr_change,
1598 .post_pwr_change = exynos7_ufs_post_pwr_change,
1599 };
1600
1601 static const struct of_device_id exynos_ufs_of_match[] = {
1602 { .compatible = "samsung,exynos7-ufs",
1603 .data = &exynos_ufs_drvs },
1604 { .compatible = "samsung,exynosautov9-ufs",
1605 .data = &exynosauto_ufs_drvs },
1606 { .compatible = "samsung,exynosautov9-ufs-vh",
1607 .data = &exynosauto_ufs_vh_drvs },
1608 {},
1609 };
1610
1611 static const struct dev_pm_ops exynos_ufs_pm_ops = {
1612 SET_SYSTEM_SLEEP_PM_OPS(ufshcd_system_suspend, ufshcd_system_resume)
1613 SET_RUNTIME_PM_OPS(ufshcd_runtime_suspend, ufshcd_runtime_resume, NULL)
1614 .prepare = ufshcd_suspend_prepare,
1615 .complete = ufshcd_resume_complete,
1616 };
1617
1618 static struct platform_driver exynos_ufs_pltform = {
1619 .probe = exynos_ufs_probe,
1620 .remove = exynos_ufs_remove,
1621 .shutdown = ufshcd_pltfrm_shutdown,
1622 .driver = {
1623 .name = "exynos-ufshc",
1624 .pm = &exynos_ufs_pm_ops,
1625 .of_match_table = of_match_ptr(exynos_ufs_of_match),
1626 },
1627 };
1628 module_platform_driver(exynos_ufs_pltform);
1629
1630 MODULE_AUTHOR("Alim Akhtar <alim.akhtar@samsung.com>");
1631 MODULE_AUTHOR("Seungwon Jeon <essuuj@gmail.com>");
1632 MODULE_DESCRIPTION("Exynos UFS HCI Driver");
1633 MODULE_LICENSE("GPL v2");
1634